| 1 | /*************************************************************** |
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| 2 | ** |
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| 3 | ** Broadcom Corp. Confidential |
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| 4 | ** Copyright 1998-2000 Broadcom Corp. All Rights Reserved. |
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| 5 | ** |
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| 6 | ** THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED |
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| 7 | ** SOFTWARE LICENSE AGREEMENT BETWEEN THE USER AND BROADCOM. |
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| 8 | ** YOU HAVE NO RIGHT TO USE OR EXPLOIT THIS MATERIAL EXCEPT |
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| 9 | ** SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | ** |
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| 11 | ** File: bcm_mips.h |
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| 12 | ** Description: MIPS definitions. |
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| 13 | ** |
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| 14 | ****************************************************************/ |
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| 15 | #ifndef __BCM_MIPS__ |
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| 16 | #define __BCM_MIPS__ |
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| 17 | |
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| 18 | #define zero $0 /* wired zero */ |
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| 19 | #define AT $1 /* assembler temp - uppercase because of ".set at" */ |
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| 20 | #define v0 $2 /* return value */ |
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| 21 | #define v1 $3 |
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| 22 | #define a0 $4 /* argument registers */ |
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| 23 | #define a1 $5 |
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| 24 | #define a2 $6 |
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| 25 | #define a3 $7 |
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| 26 | #define t0 $8 /* caller saved */ |
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| 27 | #define t1 $9 |
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| 28 | #define t2 $10 |
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| 29 | #define t3 $11 |
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| 30 | #define t4 $12 |
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| 31 | #define t5 $13 |
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| 32 | #define t6 $14 |
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| 33 | #define t7 $15 |
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| 34 | #define s0 $16 /* callee saved */ |
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| 35 | #define s1 $17 |
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| 36 | #define s2 $18 |
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| 37 | #define s3 $19 |
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| 38 | #define s4 $20 |
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| 39 | #define s5 $21 |
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| 40 | #define s6 $22 |
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| 41 | #define s7 $23 |
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| 42 | #define t8 $24 /* caller saved */ |
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| 43 | #define t9 $25 |
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| 44 | #define jp $25 /* PIC jump register */ |
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| 45 | #define k0 $26 /* kernel scratch */ |
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| 46 | #define k1 $27 |
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| 47 | #define gp $28 /* global pointer */ |
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| 48 | #define sp $29 /* stack pointer */ |
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| 49 | #define fp $30 /* frame pointer */ |
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| 50 | #define s8 $30 /* same like fp! */ |
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| 51 | #define ra $31 /* return address */ |
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| 52 | |
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| 53 | /* |
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| 54 | * Coprocessor 0 register names |
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| 55 | */ |
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| 56 | #define CP0_INDEX $0 |
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| 57 | #define CP0_RANDOM $1 |
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| 58 | #define CP0_ENTRYLO0 $2 |
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| 59 | #define CP0_ENTRYLO1 $3 |
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| 60 | #define CP0_CONF $3 |
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| 61 | #define CP0_CONTEXT $4 |
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| 62 | #define CP0_PAGEMASK $5 |
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| 63 | #define CP0_WIRED $6 |
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| 64 | #define CP0_INFO $7 |
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| 65 | #define CP0_BADVADDR $8 |
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| 66 | #define CP0_COUNT $9 |
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| 67 | #define CP0_ENTRYHI $10 |
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| 68 | #define CP0_COMPARE $11 |
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| 69 | #define CP0_STATUS $12 |
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| 70 | #define CP0_CAUSE $13 |
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| 71 | #define CP0_EPC $14 |
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| 72 | #define CP0_PRID $15 |
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| 73 | #define CP0_CONFIG $16 |
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| 74 | #define CP0_LLADDR $17 |
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| 75 | #define CP0_WATCHLO $18 |
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| 76 | #define CP0_WATCHHI $19 |
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| 77 | #define CP0_XCONTEXT $20 |
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| 78 | #define CP0_FRAMEMASK $21 |
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| 79 | #define CP0_DIAGNOSTIC $22 |
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| 80 | #define CP0_DEBUG $23 |
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| 81 | #define CP0_DEPC $24 |
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| 82 | #define CP0_PERFORMANCE $25 |
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| 83 | #define CP0_ECC $26 |
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| 84 | #define CP0_CACHEERR $27 |
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| 85 | #define CP0_TAGLO $28 |
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| 86 | #define CP0_DATALO $28,1 |
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| 87 | #define CP0_TAGHI $29 |
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| 88 | #define CP0_ERROREPC $30 |
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| 89 | #define CP0_DESAVE $31 |
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| 90 | |
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| 91 | |
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| 92 | #define ST0_CU0 0x10000000 |
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| 93 | #define ST0_BEV 0x00400000 |
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| 94 | #define ST0_IE 0x00000001 |
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| 95 | #define ST0_EXL 0x00000002 |
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| 96 | #define ST0_ERL 0x00000004 |
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| 97 | #define ST0_KSU 0x00000018 |
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| 98 | # define KSU_USER 0x00000010 |
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| 99 | # define KSU_SUPERVISOR 0x00000008 |
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| 100 | # define KSU_KERNEL 0x00000000 |
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| 101 | #define ST0_UX 0x00000020 |
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| 102 | #define ST0_SX 0x00000040 |
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| 103 | #define ST0_KX 0x00000080 |
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| 104 | #define ST0_DE 0x00010000 |
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| 105 | #define ST0_CE 0x00020000 |
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| 106 | #define ST0_IM 0x0000ff00 |
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| 107 | #define STATUSB_IP0 8 |
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| 108 | #define STATUSF_IP0 (1UL << 8) |
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| 109 | #define STATUSB_IP1 9 |
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| 110 | #define STATUSF_IP1 (1UL << 9) |
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| 111 | #define STATUSB_IP2 10 |
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| 112 | #define STATUSF_IP2 (1UL << 10) |
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| 113 | #define STATUSB_IP3 11 |
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| 114 | #define STATUSF_IP3 (1UL << 11) |
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| 115 | #define STATUSB_IP4 12 |
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| 116 | #define STATUSF_IP4 (1UL << 12) |
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| 117 | #define STATUSB_IP5 13 |
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| 118 | #define STATUSF_IP5 (1UL << 13) |
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| 119 | #define STATUSB_IP6 14 |
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| 120 | #define STATUSF_IP6 (1UL << 14) |
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| 121 | #define STATUSB_IP7 15 |
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| 122 | #define STATUSF_IP7 (1UL << 15) |
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| 123 | |
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| 124 | |
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| 125 | #define CAUSEB_EXCCODE 2 |
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| 126 | #define CAUSEF_EXCCODE (31UL << 2) |
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| 127 | #define CAUSEB_IP 8 |
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| 128 | #define CAUSEF_IP (255UL << 8) |
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| 129 | #define CAUSEB_IP0 8 |
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| 130 | #define CAUSEF_IP0 (1UL << 8) |
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| 131 | #define CAUSEB_IP1 9 |
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| 132 | #define CAUSEF_IP1 (1UL << 9) |
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| 133 | #define CAUSEB_IP2 10 |
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| 134 | #define CAUSEF_IP2 (1UL << 10) |
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| 135 | #define CAUSEB_IP3 11 |
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| 136 | #define CAUSEF_IP3 (1UL << 11) |
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| 137 | #define CAUSEB_IP4 12 |
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| 138 | #define CAUSEF_IP4 (1UL << 12) |
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| 139 | #define CAUSEB_IP5 13 |
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| 140 | #define CAUSEF_IP5 (1UL << 13) |
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| 141 | #define CAUSEB_IP6 14 |
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| 142 | #define CAUSEF_IP6 (1UL << 14) |
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| 143 | #define CAUSEB_IP7 15 |
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| 144 | #define CAUSEF_IP7 (1UL << 15) |
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| 145 | #define CAUSEB_IV 23 |
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| 146 | #define CAUSEF_IV (1UL << 23) |
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| 147 | |
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| 148 | /* Location of pointer to the current exception handler */ |
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| 149 | |
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| 150 | #define VECTOR_START 0x8000017C |
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| 151 | |
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| 152 | /* |
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| 153 | * Some debug CP0 Register locations within saved register space |
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| 154 | */ |
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| 155 | #define ROFF_NUM_REG (48) /* Size of register space in bytes */ |
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| 156 | #define ROFF_REG_SPACE (ROFF_NUM_REG * 4) /* Size of register space in bytes */ |
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| 157 | #define ROFF_SP 29 /* word offset to sp */ |
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| 158 | #define ROFF_RA 31 /* word offset to ra */ |
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| 159 | #define ROFF_SR 32 /* word offset to CP0_STATUS */ |
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| 160 | #define ROFF_LO 33 /* word offset to LO */ |
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| 161 | #define ROFF_HI 34 /* word offset to HI */ |
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| 162 | #define ROFF_BADVA 35 /* word offset to CP0_BADVADDR */ |
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| 163 | #define ROFF_CAUSE 36 /* word offset to CP0_CAUSE */ |
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| 164 | #define ROFF_PC 37 /* word offset to CP0_EPC */ |
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| 165 | #define ROFF_START_PC 38 /* word offset to new task PC */ |
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| 166 | #define ROFF_ERROR_PC 39 /* word offset to ErrorPC */ |
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| 167 | #define ROFF_START_A0 40 /* word offset to startup a0 */ |
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| 168 | |
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| 169 | /* Macros */ |
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| 170 | #define BCM_SAVE(reg) \ |
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| 171 | sw AT, 1*4(reg) ; \ |
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| 172 | .set at ; \ |
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| 173 | sw $0, 0(reg) ; \ |
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| 174 | sw v0, 2*4(reg) ; \ |
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| 175 | sw v1, 3*4(reg) ; \ |
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| 176 | sw a0, 4*4(reg) ; \ |
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| 177 | sw a1, 5*4(reg) ; \ |
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| 178 | sw a2, 6*4(reg) ; \ |
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| 179 | sw a3, 7*4(reg) ; \ |
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| 180 | sw t0, 8*4(reg) ; \ |
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| 181 | sw t1, 9*4(reg) ; \ |
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| 182 | sw t2,10*4(reg) ; \ |
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| 183 | sw t3,11*4(reg) ; \ |
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| 184 | sw t4,12*4(reg) ; \ |
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| 185 | sw t5,13*4(reg) ; \ |
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| 186 | sw t6,14*4(reg) ; \ |
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| 187 | sw t7,15*4(reg) ; \ |
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| 188 | sw s0,16*4(reg) ; \ |
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| 189 | sw s1,17*4(reg) ; \ |
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| 190 | sw s2,18*4(reg) ; \ |
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| 191 | sw s3,19*4(reg) ; \ |
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| 192 | sw s4,20*4(reg) ; \ |
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| 193 | sw s5,21*4(reg) ; \ |
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| 194 | sw s6,22*4(reg) ; \ |
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| 195 | sw s7,23*4(reg) ; \ |
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| 196 | sw t8,24*4(reg) ; \ |
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| 197 | sw t9,25*4(reg) ; \ |
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| 198 | sw gp,28*4(reg) ; \ |
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| 199 | sw sp,29*4(reg) ; \ |
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| 200 | sw s8,30*4(reg) ; \ |
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| 201 | sw ra,31*4(reg) ; \ |
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| 202 | mfc0 t0,CP0_BADVADDR ; \ |
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| 203 | mfc0 t1,CP0_STATUS ; \ |
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| 204 | mfc0 a1,CP0_CAUSE ; \ |
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| 205 | mfc0 t2,CP0_EPC ; \ |
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| 206 | mflo t3 ; \ |
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| 207 | mfhi t4 ; \ |
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| 208 | mfc0 t5, CP0_ERROREPC; \ |
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| 209 | sw t0, ROFF_BADVA * 4(reg) ; \ |
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| 210 | sw t1, ROFF_SR * 4(reg) ; \ |
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| 211 | sw a1, ROFF_CAUSE * 4(reg) ; \ |
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| 212 | sw t2, ROFF_PC * 4(reg) ; \ |
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| 213 | sw t3, ROFF_LO * 4(reg) ; \ |
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| 214 | sw t4, ROFF_HI * 4(reg) ; \ |
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| 215 | sw t5, ROFF_ERROR_PC * 4(reg) ; |
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| 216 | |
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| 217 | |
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| 218 | #define BCM_RESTORE(reg) \ |
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| 219 | lw t0,ROFF_SR * 4(reg) ; \ |
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| 220 | mtc0 t0,CP0_STATUS ; \ |
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| 221 | lw t1,ROFF_PC * 4(reg) ; \ |
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| 222 | mtc0 t1,CP0_EPC ; \ |
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| 223 | lw t0,ROFF_LO * 4(reg) ; \ |
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| 224 | lw t1,ROFF_HI * 4(reg) ; \ |
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| 225 | mtlo t0 ; \ |
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| 226 | mthi t1 ; \ |
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| 227 | .set noat ; \ |
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| 228 | lw AT, 1*4(reg) ; \ |
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| 229 | .set at ; \ |
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| 230 | lw v0, 2*4(reg) ; \ |
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| 231 | lw v1, 3*4(reg) ; \ |
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| 232 | lw a0, 4*4(reg) ; \ |
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| 233 | lw a1, 5*4(reg) ; \ |
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| 234 | lw a2, 6*4(reg) ; \ |
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| 235 | lw a3, 7*4(reg) ; \ |
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| 236 | lw t0, 8*4(reg) ; \ |
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| 237 | lw t1, 9*4(reg) ; \ |
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| 238 | lw t2,10*4(reg) ; \ |
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| 239 | lw t3,11*4(reg) ; \ |
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| 240 | lw t4,12*4(reg) ; \ |
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| 241 | lw t5,13*4(reg) ; \ |
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| 242 | lw t6,14*4(reg) ; \ |
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| 243 | lw t7,15*4(reg) ; \ |
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| 244 | lw s0,16*4(reg) ; \ |
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| 245 | lw s1,17*4(reg) ; \ |
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| 246 | lw s2,18*4(reg) ; \ |
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| 247 | lw s3,19*4(reg) ; \ |
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| 248 | lw s4,20*4(reg) ; \ |
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| 249 | lw s5,21*4(reg) ; \ |
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| 250 | lw s6,22*4(reg) ; \ |
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| 251 | lw s7,23*4(reg) ; \ |
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| 252 | lw t8,24*4(reg) ; \ |
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| 253 | lw t9,25*4(reg) ; \ |
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| 254 | lw gp,28*4(reg) ; \ |
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| 255 | lw sp,29*4(reg) ; \ |
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| 256 | lw s8,30*4(reg) ; \ |
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| 257 | lw ra,31*4(reg) ; |
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| 258 | |
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| 259 | |
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| 260 | |
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| 261 | #define K0BASE 0x80000000 |
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| 262 | #define K1BASE 0xa0000000 |
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| 263 | |
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| 264 | #endif /* __BCM_MIPS__ */ |
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| 265 | |
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