| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2009, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_bcm3410_regs.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/1 $ |
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| 13 | * $brcm_Date: 11/16/09 2:30p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Mon Nov 16 12:43:50 2009 |
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| 23 | * MD5 Checksum 2186571576081570a005818ce2d9f39b |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/3410/bchp_bcm3410_regs.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/1 11/16/09 2:30p farshidf |
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| 36 | * SW7550-38: add the 3410 header file |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_BCM3410_REGS_H__ |
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| 41 | #define BCHP_BCM3410_REGS_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *BCM3410_regs |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_BCM3410_regs_CHIP_ID 0x00000000 /* Chip ID Register */ |
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| 47 | #define BCHP_BCM3410_regs_CHIP_REV 0x00000004 /* Chip Revision Register */ |
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| 48 | #define BCHP_BCM3410_regs_TEST 0x00000008 /* Test Register */ |
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| 49 | #define BCHP_BCM3410_regs_SERIAL_CTL 0x0000000c /* Serial Control Register */ |
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| 50 | #define BCHP_BCM3410_regs_STATUS_READ1 0x00000010 /* State Machine and Stage 1 Amplifier Read Only Register */ |
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| 51 | #define BCHP_BCM3410_regs_STATUS_READ2 0x00000014 /* State Machine and Stage 1 Amplifier Read Only Register */ |
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| 52 | #define BCHP_BCM3410_regs_STATUS_READ3 0x00000018 /* Multi-window Comparator and Chip Identification Read Only Register */ |
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| 53 | #define BCHP_BCM3410_regs_SM_BYPASS 0x0000001c /* State Machine Bypass Register */ |
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| 54 | #define BCHP_BCM3410_regs_MWC_CNTL 0x00000020 /* Multi-window Comparator Register */ |
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| 55 | #define BCHP_BCM3410_regs_MWC_PM_CNTL 0x00000024 /* Process Monitor Register and Multi-window Comparator */ |
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| 56 | #define BCHP_BCM3410_regs_LNA_ADDR 0x00000028 /* Stage 1 Amplifier Address Register */ |
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| 57 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL 0x0000002c /* Ramp Rate Register */ |
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| 58 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL 0x00000030 /* Ramp DAC Register */ |
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| 59 | #define BCHP_BCM3410_regs_LNA1_CNTL 0x00000034 /* Stage 1 Amplifier Register */ |
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| 60 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL 0x00000038 /* Bandgap, Stage 2 amplifier, Resistor Calibration Register */ |
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| 61 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL 0x0000003c /* Power Detector, OOB, and Oscillator Register */ |
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| 62 | |
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| 63 | /*************************************************************************** |
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| 64 | *CHIP_ID - Chip ID Register |
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| 65 | ***************************************************************************/ |
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| 66 | /* BCM3410_regs :: CHIP_ID :: CHIP_PART_NUMBER [31:00] */ |
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| 67 | #define BCHP_BCM3410_regs_CHIP_ID_CHIP_PART_NUMBER_MASK 0xffffffff |
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| 68 | #define BCHP_BCM3410_regs_CHIP_ID_CHIP_PART_NUMBER_SHIFT 0 |
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| 69 | |
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| 70 | /*************************************************************************** |
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| 71 | *CHIP_REV - Chip Revision Register |
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| 72 | ***************************************************************************/ |
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| 73 | /* BCM3410_regs :: CHIP_REV :: reserved0 [31:16] */ |
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| 74 | #define BCHP_BCM3410_regs_CHIP_REV_reserved0_MASK 0xffff0000 |
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| 75 | #define BCHP_BCM3410_regs_CHIP_REV_reserved0_SHIFT 16 |
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| 76 | |
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| 77 | /* BCM3410_regs :: CHIP_REV :: CHIP_REV [15:00] */ |
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| 78 | #define BCHP_BCM3410_regs_CHIP_REV_CHIP_REV_MASK 0x0000ffff |
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| 79 | #define BCHP_BCM3410_regs_CHIP_REV_CHIP_REV_SHIFT 0 |
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| 80 | |
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| 81 | /*************************************************************************** |
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| 82 | *TEST - Test Register |
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| 83 | ***************************************************************************/ |
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| 84 | /* BCM3410_regs :: TEST :: TEST_FIELD [31:00] */ |
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| 85 | #define BCHP_BCM3410_regs_TEST_TEST_FIELD_MASK 0xffffffff |
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| 86 | #define BCHP_BCM3410_regs_TEST_TEST_FIELD_SHIFT 0 |
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| 87 | |
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| 88 | /*************************************************************************** |
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| 89 | *SERIAL_CTL - Serial Control Register |
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| 90 | ***************************************************************************/ |
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| 91 | /* BCM3410_regs :: SERIAL_CTL :: reserved0 [31:08] */ |
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| 92 | #define BCHP_BCM3410_regs_SERIAL_CTL_reserved0_MASK 0xffffff00 |
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| 93 | #define BCHP_BCM3410_regs_SERIAL_CTL_reserved0_SHIFT 8 |
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| 94 | |
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| 95 | /* BCM3410_regs :: SERIAL_CTL :: reserved_for_eco1 [07:01] */ |
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| 96 | #define BCHP_BCM3410_regs_SERIAL_CTL_reserved_for_eco1_MASK 0x000000fe |
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| 97 | #define BCHP_BCM3410_regs_SERIAL_CTL_reserved_for_eco1_SHIFT 1 |
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| 98 | |
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| 99 | /* BCM3410_regs :: SERIAL_CTL :: TI2C_DELAY_DISABLE [00:00] */ |
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| 100 | #define BCHP_BCM3410_regs_SERIAL_CTL_TI2C_DELAY_DISABLE_MASK 0x00000001 |
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| 101 | #define BCHP_BCM3410_regs_SERIAL_CTL_TI2C_DELAY_DISABLE_SHIFT 0 |
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| 102 | |
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| 103 | /*************************************************************************** |
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| 104 | *STATUS_READ1 - State Machine and Stage 1 Amplifier Read Only Register |
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| 105 | ***************************************************************************/ |
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| 106 | /* BCM3410_regs :: STATUS_READ1 :: spare3_read1 [31:31] */ |
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| 107 | #define BCHP_BCM3410_regs_STATUS_READ1_spare3_read1_MASK 0x80000000 |
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| 108 | #define BCHP_BCM3410_regs_STATUS_READ1_spare3_read1_SHIFT 31 |
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| 109 | |
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| 110 | /* BCM3410_regs :: STATUS_READ1 :: FB_ON [30:30] */ |
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| 111 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_ON_MASK 0x40000000 |
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| 112 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_ON_SHIFT 30 |
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| 113 | |
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| 114 | /* BCM3410_regs :: STATUS_READ1 :: FB_CNTL_ENB [29:29] */ |
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| 115 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_CNTL_ENB_MASK 0x20000000 |
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| 116 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_CNTL_ENB_SHIFT 29 |
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| 117 | |
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| 118 | /* BCM3410_regs :: STATUS_READ1 :: FB_LAT_ENB [28:28] */ |
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| 119 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_LAT_ENB_MASK 0x10000000 |
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| 120 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_LAT_ENB_SHIFT 28 |
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| 121 | |
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| 122 | /* BCM3410_regs :: STATUS_READ1 :: FB_CNTL [27:24] */ |
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| 123 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_CNTL_MASK 0x0f000000 |
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| 124 | #define BCHP_BCM3410_regs_STATUS_READ1_FB_CNTL_SHIFT 24 |
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| 125 | |
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| 126 | /* BCM3410_regs :: STATUS_READ1 :: ON_CNTL_STG1 [23:20] */ |
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| 127 | #define BCHP_BCM3410_regs_STATUS_READ1_ON_CNTL_STG1_MASK 0x00f00000 |
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| 128 | #define BCHP_BCM3410_regs_STATUS_READ1_ON_CNTL_STG1_SHIFT 20 |
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| 129 | |
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| 130 | /* BCM3410_regs :: STATUS_READ1 :: OFF_CNTL_STG1 [19:16] */ |
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| 131 | #define BCHP_BCM3410_regs_STATUS_READ1_OFF_CNTL_STG1_MASK 0x000f0000 |
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| 132 | #define BCHP_BCM3410_regs_STATUS_READ1_OFF_CNTL_STG1_SHIFT 16 |
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| 133 | |
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| 134 | /* BCM3410_regs :: STATUS_READ1 :: spare2_read1 [15:15] */ |
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| 135 | #define BCHP_BCM3410_regs_STATUS_READ1_spare2_read1_MASK 0x00008000 |
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| 136 | #define BCHP_BCM3410_regs_STATUS_READ1_spare2_read1_SHIFT 15 |
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| 137 | |
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| 138 | /* BCM3410_regs :: STATUS_READ1 :: RAMP_DONE [14:14] */ |
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| 139 | #define BCHP_BCM3410_regs_STATUS_READ1_RAMP_DONE_MASK 0x00004000 |
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| 140 | #define BCHP_BCM3410_regs_STATUS_READ1_RAMP_DONE_SHIFT 14 |
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| 141 | |
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| 142 | /* BCM3410_regs :: STATUS_READ1 :: RAMP_RESET [13:13] */ |
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| 143 | #define BCHP_BCM3410_regs_STATUS_READ1_RAMP_RESET_MASK 0x00002000 |
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| 144 | #define BCHP_BCM3410_regs_STATUS_READ1_RAMP_RESET_SHIFT 13 |
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| 145 | |
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| 146 | /* BCM3410_regs :: STATUS_READ1 :: FAST_RAMP [12:12] */ |
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| 147 | #define BCHP_BCM3410_regs_STATUS_READ1_FAST_RAMP_MASK 0x00001000 |
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| 148 | #define BCHP_BCM3410_regs_STATUS_READ1_FAST_RAMP_SHIFT 12 |
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| 149 | |
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| 150 | /* BCM3410_regs :: STATUS_READ1 :: MWC_LAT_EN [11:11] */ |
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| 151 | #define BCHP_BCM3410_regs_STATUS_READ1_MWC_LAT_EN_MASK 0x00000800 |
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| 152 | #define BCHP_BCM3410_regs_STATUS_READ1_MWC_LAT_EN_SHIFT 11 |
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| 153 | |
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| 154 | /* BCM3410_regs :: STATUS_READ1 :: DEC_LAT_ENB_STG1 [10:10] */ |
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| 155 | #define BCHP_BCM3410_regs_STATUS_READ1_DEC_LAT_ENB_STG1_MASK 0x00000400 |
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| 156 | #define BCHP_BCM3410_regs_STATUS_READ1_DEC_LAT_ENB_STG1_SHIFT 10 |
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| 157 | |
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| 158 | /* BCM3410_regs :: STATUS_READ1 :: UP_DWNB_STG1 [09:09] */ |
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| 159 | #define BCHP_BCM3410_regs_STATUS_READ1_UP_DWNB_STG1_MASK 0x00000200 |
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| 160 | #define BCHP_BCM3410_regs_STATUS_READ1_UP_DWNB_STG1_SHIFT 9 |
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| 161 | |
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| 162 | /* BCM3410_regs :: STATUS_READ1 :: NEXT_AMP_ON_STG1 [08:08] */ |
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| 163 | #define BCHP_BCM3410_regs_STATUS_READ1_NEXT_AMP_ON_STG1_MASK 0x00000100 |
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| 164 | #define BCHP_BCM3410_regs_STATUS_READ1_NEXT_AMP_ON_STG1_SHIFT 8 |
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| 165 | |
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| 166 | /* BCM3410_regs :: STATUS_READ1 :: spare1_read1 [07:07] */ |
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| 167 | #define BCHP_BCM3410_regs_STATUS_READ1_spare1_read1_MASK 0x00000080 |
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| 168 | #define BCHP_BCM3410_regs_STATUS_READ1_spare1_read1_SHIFT 7 |
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| 169 | |
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| 170 | /* BCM3410_regs :: STATUS_READ1 :: SM_STATE [06:00] */ |
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| 171 | #define BCHP_BCM3410_regs_STATUS_READ1_SM_STATE_MASK 0x0000007f |
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| 172 | #define BCHP_BCM3410_regs_STATUS_READ1_SM_STATE_SHIFT 0 |
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| 173 | |
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| 174 | /*************************************************************************** |
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| 175 | *STATUS_READ2 - State Machine and Stage 1 Amplifier Read Only Register |
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| 176 | ***************************************************************************/ |
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| 177 | /* BCM3410_regs :: STATUS_READ2 :: spare2_read2 [31:31] */ |
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| 178 | #define BCHP_BCM3410_regs_STATUS_READ2_spare2_read2_MASK 0x80000000 |
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| 179 | #define BCHP_BCM3410_regs_STATUS_READ2_spare2_read2_SHIFT 31 |
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| 180 | |
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| 181 | /* BCM3410_regs :: STATUS_READ2 :: RAMP_DAC2 [30:24] */ |
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| 182 | #define BCHP_BCM3410_regs_STATUS_READ2_RAMP_DAC2_MASK 0x7f000000 |
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| 183 | #define BCHP_BCM3410_regs_STATUS_READ2_RAMP_DAC2_SHIFT 24 |
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| 184 | |
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| 185 | /* BCM3410_regs :: STATUS_READ2 :: spare1_read2 [23:23] */ |
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| 186 | #define BCHP_BCM3410_regs_STATUS_READ2_spare1_read2_MASK 0x00800000 |
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| 187 | #define BCHP_BCM3410_regs_STATUS_READ2_spare1_read2_SHIFT 23 |
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| 188 | |
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| 189 | /* BCM3410_regs :: STATUS_READ2 :: RAMP_DAC1 [22:16] */ |
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| 190 | #define BCHP_BCM3410_regs_STATUS_READ2_RAMP_DAC1_MASK 0x007f0000 |
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| 191 | #define BCHP_BCM3410_regs_STATUS_READ2_RAMP_DAC1_SHIFT 16 |
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| 192 | |
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| 193 | /* BCM3410_regs :: STATUS_READ2 :: spare3_read2 [15:15] */ |
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| 194 | #define BCHP_BCM3410_regs_STATUS_READ2_spare3_read2_MASK 0x00008000 |
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| 195 | #define BCHP_BCM3410_regs_STATUS_READ2_spare3_read2_SHIFT 15 |
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| 196 | |
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| 197 | /* BCM3410_regs :: STATUS_READ2 :: RAMP_RATE [14:08] */ |
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| 198 | #define BCHP_BCM3410_regs_STATUS_READ2_RAMP_RATE_MASK 0x00007f00 |
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| 199 | #define BCHP_BCM3410_regs_STATUS_READ2_RAMP_RATE_SHIFT 8 |
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| 200 | |
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| 201 | /* BCM3410_regs :: STATUS_READ2 :: AGC_LOCK [07:07] */ |
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| 202 | #define BCHP_BCM3410_regs_STATUS_READ2_AGC_LOCK_MASK 0x00000080 |
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| 203 | #define BCHP_BCM3410_regs_STATUS_READ2_AGC_LOCK_SHIFT 7 |
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| 204 | |
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| 205 | /* BCM3410_regs :: STATUS_READ2 :: COMP_OUT [06:06] */ |
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| 206 | #define BCHP_BCM3410_regs_STATUS_READ2_COMP_OUT_MASK 0x00000040 |
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| 207 | #define BCHP_BCM3410_regs_STATUS_READ2_COMP_OUT_SHIFT 6 |
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| 208 | |
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| 209 | /* BCM3410_regs :: STATUS_READ2 :: STG1_GAIN [05:00] */ |
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| 210 | #define BCHP_BCM3410_regs_STATUS_READ2_STG1_GAIN_MASK 0x0000003f |
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| 211 | #define BCHP_BCM3410_regs_STATUS_READ2_STG1_GAIN_SHIFT 0 |
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| 212 | |
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| 213 | /*************************************************************************** |
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| 214 | *STATUS_READ3 - Multi-window Comparator and Chip Identification Read Only Register |
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| 215 | ***************************************************************************/ |
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| 216 | /* BCM3410_regs :: STATUS_READ3 :: reserved0 [31:08] */ |
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| 217 | #define BCHP_BCM3410_regs_STATUS_READ3_reserved0_MASK 0xffffff00 |
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| 218 | #define BCHP_BCM3410_regs_STATUS_READ3_reserved0_SHIFT 8 |
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| 219 | |
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| 220 | /* BCM3410_regs :: STATUS_READ3 :: spare_read3 [07:05] */ |
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| 221 | #define BCHP_BCM3410_regs_STATUS_READ3_spare_read3_MASK 0x000000e0 |
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| 222 | #define BCHP_BCM3410_regs_STATUS_READ3_spare_read3_SHIFT 5 |
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| 223 | |
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| 224 | /* BCM3410_regs :: STATUS_READ3 :: MWC_STATE [04:00] */ |
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| 225 | #define BCHP_BCM3410_regs_STATUS_READ3_MWC_STATE_MASK 0x0000001f |
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| 226 | #define BCHP_BCM3410_regs_STATUS_READ3_MWC_STATE_SHIFT 0 |
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| 227 | |
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| 228 | /*************************************************************************** |
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| 229 | *SM_BYPASS - State Machine Bypass Register |
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| 230 | ***************************************************************************/ |
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| 231 | /* BCM3410_regs :: SM_BYPASS :: reserved_for_eco0 [31:31] */ |
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| 232 | #define BCHP_BCM3410_regs_SM_BYPASS_reserved_for_eco0_MASK 0x80000000 |
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| 233 | #define BCHP_BCM3410_regs_SM_BYPASS_reserved_for_eco0_SHIFT 31 |
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| 234 | |
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| 235 | /* BCM3410_regs :: SM_BYPASS :: FB_ON_I2C [30:30] */ |
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| 236 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_ON_I2C_MASK 0x40000000 |
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| 237 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_ON_I2C_SHIFT 30 |
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| 238 | |
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| 239 | /* BCM3410_regs :: SM_BYPASS :: FB_CNTL_ENB_I2C [29:29] */ |
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| 240 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_CNTL_ENB_I2C_MASK 0x20000000 |
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| 241 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_CNTL_ENB_I2C_SHIFT 29 |
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| 242 | |
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| 243 | /* BCM3410_regs :: SM_BYPASS :: FB_LAT_ENB_I2C [28:28] */ |
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| 244 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_LAT_ENB_I2C_MASK 0x10000000 |
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| 245 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_LAT_ENB_I2C_SHIFT 28 |
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| 246 | |
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| 247 | /* BCM3410_regs :: SM_BYPASS :: FB_CNTL_I2C [27:24] */ |
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| 248 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_CNTL_I2C_MASK 0x0f000000 |
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| 249 | #define BCHP_BCM3410_regs_SM_BYPASS_FB_CNTL_I2C_SHIFT 24 |
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| 250 | |
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| 251 | /* BCM3410_regs :: SM_BYPASS :: ON_CNTL_STG1_I2C [23:20] */ |
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| 252 | #define BCHP_BCM3410_regs_SM_BYPASS_ON_CNTL_STG1_I2C_MASK 0x00f00000 |
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| 253 | #define BCHP_BCM3410_regs_SM_BYPASS_ON_CNTL_STG1_I2C_SHIFT 20 |
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| 254 | |
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| 255 | /* BCM3410_regs :: SM_BYPASS :: OFF_CNTL_STG1_I2C [19:16] */ |
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| 256 | #define BCHP_BCM3410_regs_SM_BYPASS_OFF_CNTL_STG1_I2C_MASK 0x000f0000 |
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| 257 | #define BCHP_BCM3410_regs_SM_BYPASS_OFF_CNTL_STG1_I2C_SHIFT 16 |
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| 258 | |
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| 259 | /* BCM3410_regs :: SM_BYPASS :: reserved_for_eco1 [15:15] */ |
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| 260 | #define BCHP_BCM3410_regs_SM_BYPASS_reserved_for_eco1_MASK 0x00008000 |
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| 261 | #define BCHP_BCM3410_regs_SM_BYPASS_reserved_for_eco1_SHIFT 15 |
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| 262 | |
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| 263 | /* BCM3410_regs :: SM_BYPASS :: ATE [14:14] */ |
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| 264 | #define BCHP_BCM3410_regs_SM_BYPASS_ATE_MASK 0x00004000 |
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| 265 | #define BCHP_BCM3410_regs_SM_BYPASS_ATE_SHIFT 14 |
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| 266 | |
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| 267 | /* BCM3410_regs :: SM_BYPASS :: RAMP_RESET_I2C [13:13] */ |
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| 268 | #define BCHP_BCM3410_regs_SM_BYPASS_RAMP_RESET_I2C_MASK 0x00002000 |
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| 269 | #define BCHP_BCM3410_regs_SM_BYPASS_RAMP_RESET_I2C_SHIFT 13 |
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| 270 | |
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| 271 | /* BCM3410_regs :: SM_BYPASS :: FAST_RAMP_I2C [12:12] */ |
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| 272 | #define BCHP_BCM3410_regs_SM_BYPASS_FAST_RAMP_I2C_MASK 0x00001000 |
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| 273 | #define BCHP_BCM3410_regs_SM_BYPASS_FAST_RAMP_I2C_SHIFT 12 |
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| 274 | |
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| 275 | /* BCM3410_regs :: SM_BYPASS :: MWC_LAT_EN_I2C [11:11] */ |
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| 276 | #define BCHP_BCM3410_regs_SM_BYPASS_MWC_LAT_EN_I2C_MASK 0x00000800 |
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| 277 | #define BCHP_BCM3410_regs_SM_BYPASS_MWC_LAT_EN_I2C_SHIFT 11 |
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| 278 | |
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| 279 | /* BCM3410_regs :: SM_BYPASS :: DEC_LAT_ENB_STG1_I2C [10:10] */ |
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| 280 | #define BCHP_BCM3410_regs_SM_BYPASS_DEC_LAT_ENB_STG1_I2C_MASK 0x00000400 |
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| 281 | #define BCHP_BCM3410_regs_SM_BYPASS_DEC_LAT_ENB_STG1_I2C_SHIFT 10 |
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| 282 | |
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| 283 | /* BCM3410_regs :: SM_BYPASS :: UP_DWNB_STG1_I2C [09:09] */ |
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| 284 | #define BCHP_BCM3410_regs_SM_BYPASS_UP_DWNB_STG1_I2C_MASK 0x00000200 |
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| 285 | #define BCHP_BCM3410_regs_SM_BYPASS_UP_DWNB_STG1_I2C_SHIFT 9 |
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| 286 | |
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| 287 | /* BCM3410_regs :: SM_BYPASS :: NEXT_AMP_ON_STG1_I2C [08:08] */ |
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| 288 | #define BCHP_BCM3410_regs_SM_BYPASS_NEXT_AMP_ON_STG1_I2C_MASK 0x00000100 |
|---|
| 289 | #define BCHP_BCM3410_regs_SM_BYPASS_NEXT_AMP_ON_STG1_I2C_SHIFT 8 |
|---|
| 290 | |
|---|
| 291 | /* BCM3410_regs :: SM_BYPASS :: reserved_for_eco2 [07:01] */ |
|---|
| 292 | #define BCHP_BCM3410_regs_SM_BYPASS_reserved_for_eco2_MASK 0x000000fe |
|---|
| 293 | #define BCHP_BCM3410_regs_SM_BYPASS_reserved_for_eco2_SHIFT 1 |
|---|
| 294 | |
|---|
| 295 | /* BCM3410_regs :: SM_BYPASS :: I2C_RESET [00:00] */ |
|---|
| 296 | #define BCHP_BCM3410_regs_SM_BYPASS_I2C_RESET_MASK 0x00000001 |
|---|
| 297 | #define BCHP_BCM3410_regs_SM_BYPASS_I2C_RESET_SHIFT 0 |
|---|
| 298 | |
|---|
| 299 | /*************************************************************************** |
|---|
| 300 | *MWC_CNTL - Multi-window Comparator Register |
|---|
| 301 | ***************************************************************************/ |
|---|
| 302 | /* BCM3410_regs :: MWC_CNTL :: reserved_for_eco0 [31:30] */ |
|---|
| 303 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco0_MASK 0xc0000000 |
|---|
| 304 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco0_SHIFT 30 |
|---|
| 305 | |
|---|
| 306 | /* BCM3410_regs :: MWC_CNTL :: MWC_HI_FAST [29:24] */ |
|---|
| 307 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_HI_FAST_MASK 0x3f000000 |
|---|
| 308 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_HI_FAST_SHIFT 24 |
|---|
| 309 | |
|---|
| 310 | /* BCM3410_regs :: MWC_CNTL :: reserved_for_eco1 [23:22] */ |
|---|
| 311 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco1_MASK 0x00c00000 |
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| 312 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco1_SHIFT 22 |
|---|
| 313 | |
|---|
| 314 | /* BCM3410_regs :: MWC_CNTL :: MWC_HI [21:16] */ |
|---|
| 315 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_HI_MASK 0x003f0000 |
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| 316 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_HI_SHIFT 16 |
|---|
| 317 | |
|---|
| 318 | /* BCM3410_regs :: MWC_CNTL :: reserved_for_eco2 [15:15] */ |
|---|
| 319 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco2_MASK 0x00008000 |
|---|
| 320 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco2_SHIFT 15 |
|---|
| 321 | |
|---|
| 322 | /* BCM3410_regs :: MWC_CNTL :: MWC_PD [14:14] */ |
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| 323 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_PD_MASK 0x00004000 |
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| 324 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_PD_SHIFT 14 |
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| 325 | |
|---|
| 326 | /* BCM3410_regs :: MWC_CNTL :: MWC_MID [13:08] */ |
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| 327 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_MID_MASK 0x00003f00 |
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| 328 | #define BCHP_BCM3410_regs_MWC_CNTL_MWC_MID_SHIFT 8 |
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| 329 | |
|---|
| 330 | /* BCM3410_regs :: MWC_CNTL :: reserved_for_eco3 [07:01] */ |
|---|
| 331 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco3_MASK 0x000000fe |
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| 332 | #define BCHP_BCM3410_regs_MWC_CNTL_reserved_for_eco3_SHIFT 1 |
|---|
| 333 | |
|---|
| 334 | /* BCM3410_regs :: MWC_CNTL :: SM_RESET [00:00] */ |
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| 335 | #define BCHP_BCM3410_regs_MWC_CNTL_SM_RESET_MASK 0x00000001 |
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| 336 | #define BCHP_BCM3410_regs_MWC_CNTL_SM_RESET_SHIFT 0 |
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| 337 | |
|---|
| 338 | /*************************************************************************** |
|---|
| 339 | *MWC_PM_CNTL - Process Monitor Register and Multi-window Comparator |
|---|
| 340 | ***************************************************************************/ |
|---|
| 341 | /* BCM3410_regs :: MWC_PM_CNTL :: reserved_for_eco0 [31:30] */ |
|---|
| 342 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_reserved_for_eco0_MASK 0xc0000000 |
|---|
| 343 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_reserved_for_eco0_SHIFT 30 |
|---|
| 344 | |
|---|
| 345 | /* BCM3410_regs :: MWC_PM_CNTL :: MWC_LO_FAST [29:24] */ |
|---|
| 346 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_MWC_LO_FAST_MASK 0x3f000000 |
|---|
| 347 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_MWC_LO_FAST_SHIFT 24 |
|---|
| 348 | |
|---|
| 349 | /* BCM3410_regs :: MWC_PM_CNTL :: reserved_for_eco1 [23:22] */ |
|---|
| 350 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_reserved_for_eco1_MASK 0x00c00000 |
|---|
| 351 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_reserved_for_eco1_SHIFT 22 |
|---|
| 352 | |
|---|
| 353 | /* BCM3410_regs :: MWC_PM_CNTL :: MWC_LO [21:16] */ |
|---|
| 354 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_MWC_LO_MASK 0x003f0000 |
|---|
| 355 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_MWC_LO_SHIFT 16 |
|---|
| 356 | |
|---|
| 357 | /* BCM3410_regs :: MWC_PM_CNTL :: reserved_for_eco2 [15:11] */ |
|---|
| 358 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_reserved_for_eco2_MASK 0x0000f800 |
|---|
| 359 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_reserved_for_eco2_SHIFT 11 |
|---|
| 360 | |
|---|
| 361 | /* BCM3410_regs :: MWC_PM_CNTL :: PM_SEL [10:08] */ |
|---|
| 362 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_PM_SEL_MASK 0x00000700 |
|---|
| 363 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_PM_SEL_SHIFT 8 |
|---|
| 364 | |
|---|
| 365 | /* BCM3410_regs :: MWC_PM_CNTL :: PM_PD [07:07] */ |
|---|
| 366 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_PM_PD_MASK 0x00000080 |
|---|
| 367 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_PM_PD_SHIFT 7 |
|---|
| 368 | |
|---|
| 369 | /* BCM3410_regs :: MWC_PM_CNTL :: COMP_LAT_EN [06:06] */ |
|---|
| 370 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_COMP_LAT_EN_MASK 0x00000040 |
|---|
| 371 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_COMP_LAT_EN_SHIFT 6 |
|---|
| 372 | |
|---|
| 373 | /* BCM3410_regs :: MWC_PM_CNTL :: PM_VREF [05:00] */ |
|---|
| 374 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_PM_VREF_MASK 0x0000003f |
|---|
| 375 | #define BCHP_BCM3410_regs_MWC_PM_CNTL_PM_VREF_SHIFT 0 |
|---|
| 376 | |
|---|
| 377 | /*************************************************************************** |
|---|
| 378 | *LNA_ADDR - Stage 1 Amplifier Address Register |
|---|
| 379 | ***************************************************************************/ |
|---|
| 380 | /* BCM3410_regs :: LNA_ADDR :: reserved_for_eco0 [31:30] */ |
|---|
| 381 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco0_MASK 0xc0000000 |
|---|
| 382 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco0_SHIFT 30 |
|---|
| 383 | |
|---|
| 384 | /* BCM3410_regs :: LNA_ADDR :: STG1_FB_TP [29:24] */ |
|---|
| 385 | #define BCHP_BCM3410_regs_LNA_ADDR_STG1_FB_TP_MASK 0x3f000000 |
|---|
| 386 | #define BCHP_BCM3410_regs_LNA_ADDR_STG1_FB_TP_SHIFT 24 |
|---|
| 387 | |
|---|
| 388 | /* BCM3410_regs :: LNA_ADDR :: reserved_for_eco1 [23:22] */ |
|---|
| 389 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco1_MASK 0x00c00000 |
|---|
| 390 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco1_SHIFT 22 |
|---|
| 391 | |
|---|
| 392 | /* BCM3410_regs :: LNA_ADDR :: MAX_GAIN_STG1 [21:16] */ |
|---|
| 393 | #define BCHP_BCM3410_regs_LNA_ADDR_MAX_GAIN_STG1_MASK 0x003f0000 |
|---|
| 394 | #define BCHP_BCM3410_regs_LNA_ADDR_MAX_GAIN_STG1_SHIFT 16 |
|---|
| 395 | |
|---|
| 396 | /* BCM3410_regs :: LNA_ADDR :: reserved_for_eco2 [15:14] */ |
|---|
| 397 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco2_MASK 0x0000c000 |
|---|
| 398 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco2_SHIFT 14 |
|---|
| 399 | |
|---|
| 400 | /* BCM3410_regs :: LNA_ADDR :: MIN_GAIN_STG1 [13:08] */ |
|---|
| 401 | #define BCHP_BCM3410_regs_LNA_ADDR_MIN_GAIN_STG1_MASK 0x00003f00 |
|---|
| 402 | #define BCHP_BCM3410_regs_LNA_ADDR_MIN_GAIN_STG1_SHIFT 8 |
|---|
| 403 | |
|---|
| 404 | /* BCM3410_regs :: LNA_ADDR :: reserved_for_eco3 [07:06] */ |
|---|
| 405 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco3_MASK 0x000000c0 |
|---|
| 406 | #define BCHP_BCM3410_regs_LNA_ADDR_reserved_for_eco3_SHIFT 6 |
|---|
| 407 | |
|---|
| 408 | /* BCM3410_regs :: LNA_ADDR :: STG1_GAIN_I2C [05:00] */ |
|---|
| 409 | #define BCHP_BCM3410_regs_LNA_ADDR_STG1_GAIN_I2C_MASK 0x0000003f |
|---|
| 410 | #define BCHP_BCM3410_regs_LNA_ADDR_STG1_GAIN_I2C_SHIFT 0 |
|---|
| 411 | |
|---|
| 412 | /*************************************************************************** |
|---|
| 413 | *RAMP_RATE_CNTL - Ramp Rate Register |
|---|
| 414 | ***************************************************************************/ |
|---|
| 415 | /* BCM3410_regs :: RAMP_RATE_CNTL :: reserved_for_eco0 [31:31] */ |
|---|
| 416 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_reserved_for_eco0_MASK 0x80000000 |
|---|
| 417 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_reserved_for_eco0_SHIFT 31 |
|---|
| 418 | |
|---|
| 419 | /* BCM3410_regs :: RAMP_RATE_CNTL :: FAST_UP_RATE_RATE [30:24] */ |
|---|
| 420 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_FAST_UP_RATE_RATE_MASK 0x7f000000 |
|---|
| 421 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_FAST_UP_RATE_RATE_SHIFT 24 |
|---|
| 422 | |
|---|
| 423 | /* BCM3410_regs :: RAMP_RATE_CNTL :: reserved_for_eco1 [23:23] */ |
|---|
| 424 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_reserved_for_eco1_MASK 0x00800000 |
|---|
| 425 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_reserved_for_eco1_SHIFT 23 |
|---|
| 426 | |
|---|
| 427 | /* BCM3410_regs :: RAMP_RATE_CNTL :: SLOW_UP_RAMP_RATE [22:16] */ |
|---|
| 428 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_SLOW_UP_RAMP_RATE_MASK 0x007f0000 |
|---|
| 429 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_SLOW_UP_RAMP_RATE_SHIFT 16 |
|---|
| 430 | |
|---|
| 431 | /* BCM3410_regs :: RAMP_RATE_CNTL :: reserved_for_eco2 [15:15] */ |
|---|
| 432 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_reserved_for_eco2_MASK 0x00008000 |
|---|
| 433 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_reserved_for_eco2_SHIFT 15 |
|---|
| 434 | |
|---|
| 435 | /* BCM3410_regs :: RAMP_RATE_CNTL :: SLOW_DWN_RAMP_RATE [14:08] */ |
|---|
| 436 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_SLOW_DWN_RAMP_RATE_MASK 0x00007f00 |
|---|
| 437 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_SLOW_DWN_RAMP_RATE_SHIFT 8 |
|---|
| 438 | |
|---|
| 439 | /* BCM3410_regs :: RAMP_RATE_CNTL :: RAMP_PD [07:07] */ |
|---|
| 440 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_RAMP_PD_MASK 0x00000080 |
|---|
| 441 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_RAMP_PD_SHIFT 7 |
|---|
| 442 | |
|---|
| 443 | /* BCM3410_regs :: RAMP_RATE_CNTL :: FAST_DWN_RAMP_RATE [06:00] */ |
|---|
| 444 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_FAST_DWN_RAMP_RATE_MASK 0x0000007f |
|---|
| 445 | #define BCHP_BCM3410_regs_RAMP_RATE_CNTL_FAST_DWN_RAMP_RATE_SHIFT 0 |
|---|
| 446 | |
|---|
| 447 | /*************************************************************************** |
|---|
| 448 | *RAMP_DAC_CNTL - Ramp DAC Register |
|---|
| 449 | ***************************************************************************/ |
|---|
| 450 | /* BCM3410_regs :: RAMP_DAC_CNTL :: reserved_for_eco0 [31:31] */ |
|---|
| 451 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco0_MASK 0x80000000 |
|---|
| 452 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco0_SHIFT 31 |
|---|
| 453 | |
|---|
| 454 | /* BCM3410_regs :: RAMP_DAC_CNTL :: RAMP_DAC2_I2C [30:24] */ |
|---|
| 455 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_DAC2_I2C_MASK 0x7f000000 |
|---|
| 456 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_DAC2_I2C_SHIFT 24 |
|---|
| 457 | |
|---|
| 458 | /* BCM3410_regs :: RAMP_DAC_CNTL :: reserved_for_eco1 [23:23] */ |
|---|
| 459 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco1_MASK 0x00800000 |
|---|
| 460 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco1_SHIFT 23 |
|---|
| 461 | |
|---|
| 462 | /* BCM3410_regs :: RAMP_DAC_CNTL :: RAMP_DAC1_I2C [22:16] */ |
|---|
| 463 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_DAC1_I2C_MASK 0x007f0000 |
|---|
| 464 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_DAC1_I2C_SHIFT 16 |
|---|
| 465 | |
|---|
| 466 | /* BCM3410_regs :: RAMP_DAC_CNTL :: reserved_for_eco2 [15:15] */ |
|---|
| 467 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco2_MASK 0x00008000 |
|---|
| 468 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco2_SHIFT 15 |
|---|
| 469 | |
|---|
| 470 | /* BCM3410_regs :: RAMP_DAC_CNTL :: RAMP_RATE_I2C [14:08] */ |
|---|
| 471 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_RATE_I2C_MASK 0x00007f00 |
|---|
| 472 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_RATE_I2C_SHIFT 8 |
|---|
| 473 | |
|---|
| 474 | /* BCM3410_regs :: RAMP_DAC_CNTL :: reserved_for_eco3 [07:07] */ |
|---|
| 475 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco3_MASK 0x00000080 |
|---|
| 476 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_reserved_for_eco3_SHIFT 7 |
|---|
| 477 | |
|---|
| 478 | /* BCM3410_regs :: RAMP_DAC_CNTL :: RAMP_DAC_INC [06:00] */ |
|---|
| 479 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_DAC_INC_MASK 0x0000007f |
|---|
| 480 | #define BCHP_BCM3410_regs_RAMP_DAC_CNTL_RAMP_DAC_INC_SHIFT 0 |
|---|
| 481 | |
|---|
| 482 | /*************************************************************************** |
|---|
| 483 | *LNA1_CNTL - Stage 1 Amplifier Register |
|---|
| 484 | ***************************************************************************/ |
|---|
| 485 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_CSC1 [31:29] */ |
|---|
| 486 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_CSC1_MASK 0xe0000000 |
|---|
| 487 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_CSC1_SHIFT 29 |
|---|
| 488 | |
|---|
| 489 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_CSC2 [28:26] */ |
|---|
| 490 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_CSC2_MASK 0x1c000000 |
|---|
| 491 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_CSC2_SHIFT 26 |
|---|
| 492 | |
|---|
| 493 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_CSC3 [25:23] */ |
|---|
| 494 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_CSC3_MASK 0x03800000 |
|---|
| 495 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_CSC3_SHIFT 23 |
|---|
| 496 | |
|---|
| 497 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_TAIL1 [22:20] */ |
|---|
| 498 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TAIL1_MASK 0x00700000 |
|---|
| 499 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TAIL1_SHIFT 20 |
|---|
| 500 | |
|---|
| 501 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_TAIL2 [19:17] */ |
|---|
| 502 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TAIL2_MASK 0x000e0000 |
|---|
| 503 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TAIL2_SHIFT 17 |
|---|
| 504 | |
|---|
| 505 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_TAIL3 [16:14] */ |
|---|
| 506 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TAIL3_MASK 0x0001c000 |
|---|
| 507 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TAIL3_SHIFT 14 |
|---|
| 508 | |
|---|
| 509 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_FB_CURRENT [13:11] */ |
|---|
| 510 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_FB_CURRENT_MASK 0x00003800 |
|---|
| 511 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_FB_CURRENT_SHIFT 11 |
|---|
| 512 | |
|---|
| 513 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_FB_PUP [10:08] */ |
|---|
| 514 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_FB_PUP_MASK 0x00000700 |
|---|
| 515 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_FB_PUP_SHIFT 8 |
|---|
| 516 | |
|---|
| 517 | /* BCM3410_regs :: LNA1_CNTL :: reserved_for_eco0 [07:03] */ |
|---|
| 518 | #define BCHP_BCM3410_regs_LNA1_CNTL_reserved_for_eco0_MASK 0x000000f8 |
|---|
| 519 | #define BCHP_BCM3410_regs_LNA1_CNTL_reserved_for_eco0_SHIFT 3 |
|---|
| 520 | |
|---|
| 521 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_SE_IN [02:02] */ |
|---|
| 522 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_SE_IN_MASK 0x00000004 |
|---|
| 523 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_SE_IN_SHIFT 2 |
|---|
| 524 | |
|---|
| 525 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_GAIN_BOOST [01:01] */ |
|---|
| 526 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_GAIN_BOOST_MASK 0x00000002 |
|---|
| 527 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_GAIN_BOOST_SHIFT 1 |
|---|
| 528 | |
|---|
| 529 | /* BCM3410_regs :: LNA1_CNTL :: STAGE1_TILT_ON [00:00] */ |
|---|
| 530 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TILT_ON_MASK 0x00000001 |
|---|
| 531 | #define BCHP_BCM3410_regs_LNA1_CNTL_STAGE1_TILT_ON_SHIFT 0 |
|---|
| 532 | |
|---|
| 533 | /*************************************************************************** |
|---|
| 534 | *BG_LNA2_RCAL_CNTL - Bandgap, Stage 2 amplifier, Resistor Calibration Register |
|---|
| 535 | ***************************************************************************/ |
|---|
| 536 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: STAGE1_FIXCS [31:29] */ |
|---|
| 537 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE1_FIXCS_MASK 0xe0000000 |
|---|
| 538 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE1_FIXCS_SHIFT 29 |
|---|
| 539 | |
|---|
| 540 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: BG_PD [28:28] */ |
|---|
| 541 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_BG_PD_MASK 0x10000000 |
|---|
| 542 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_BG_PD_SHIFT 28 |
|---|
| 543 | |
|---|
| 544 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: CTAT_EXR_TRIM [27:24] */ |
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| 545 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_CTAT_EXR_TRIM_MASK 0x0f000000 |
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| 546 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_CTAT_EXR_TRIM_SHIFT 24 |
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| 547 | |
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| 548 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: CTAT_PH_TRIM [23:20] */ |
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| 549 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_CTAT_PH_TRIM_MASK 0x00f00000 |
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| 550 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_CTAT_PH_TRIM_SHIFT 20 |
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| 551 | |
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| 552 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: CTAT_PL_TRIM [19:16] */ |
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| 553 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_CTAT_PL_TRIM_MASK 0x000f0000 |
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| 554 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_CTAT_PL_TRIM_SHIFT 16 |
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| 555 | |
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| 556 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: reserved_for_eco0 [15:15] */ |
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| 557 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_reserved_for_eco0_MASK 0x00008000 |
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| 558 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_reserved_for_eco0_SHIFT 15 |
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| 559 | |
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| 560 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: STAGE2_PD [14:14] */ |
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| 561 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE2_PD_MASK 0x00004000 |
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| 562 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE2_PD_SHIFT 14 |
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| 563 | |
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| 564 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: STAGE2_BIAS [13:08] */ |
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| 565 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE2_BIAS_MASK 0x00003f00 |
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| 566 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE2_BIAS_SHIFT 8 |
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| 567 | |
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| 568 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: reserved_for_eco1 [07:06] */ |
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| 569 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_reserved_for_eco1_MASK 0x000000c0 |
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| 570 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_reserved_for_eco1_SHIFT 6 |
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| 571 | |
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| 572 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: STAGE1_RCAL [05:03] */ |
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| 573 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE1_RCAL_MASK 0x00000038 |
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| 574 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE1_RCAL_SHIFT 3 |
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| 575 | |
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| 576 | /* BCM3410_regs :: BG_LNA2_RCAL_CNTL :: STAGE2_RCAL [02:00] */ |
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| 577 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE2_RCAL_MASK 0x00000007 |
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| 578 | #define BCHP_BCM3410_regs_BG_LNA2_RCAL_CNTL_STAGE2_RCAL_SHIFT 0 |
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| 579 | |
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| 580 | /*************************************************************************** |
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| 581 | *PD_OOB_OSC_CNTL - Power Detector, OOB, and Oscillator Register |
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| 582 | ***************************************************************************/ |
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| 583 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: reserved_for_eco0 [31:31] */ |
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| 584 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco0_MASK 0x80000000 |
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| 585 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco0_SHIFT 31 |
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| 586 | |
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| 587 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: PD_RESET [30:30] */ |
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| 588 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_RESET_MASK 0x40000000 |
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| 589 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_RESET_SHIFT 30 |
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| 590 | |
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| 591 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: PD_BO [29:29] */ |
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| 592 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_BO_MASK 0x20000000 |
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| 593 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_BO_SHIFT 29 |
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| 594 | |
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| 595 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: PD_OD [28:28] */ |
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| 596 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_OD_MASK 0x10000000 |
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| 597 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_OD_SHIFT 28 |
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| 598 | |
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| 599 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: PD_PSET_B [27:24] */ |
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| 600 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_PSET_B_MASK 0x0f000000 |
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| 601 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_PD_PSET_B_SHIFT 24 |
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| 602 | |
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| 603 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: reserved_for_eco1 [23:23] */ |
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| 604 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco1_MASK 0x00800000 |
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| 605 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco1_SHIFT 23 |
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| 606 | |
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| 607 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: OOB_PD [22:22] */ |
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| 608 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OOB_PD_MASK 0x00400000 |
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| 609 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OOB_PD_SHIFT 22 |
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| 610 | |
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| 611 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: OOB_BIAS [21:16] */ |
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| 612 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OOB_BIAS_MASK 0x003f0000 |
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| 613 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OOB_BIAS_SHIFT 16 |
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| 614 | |
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| 615 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: reserved_for_eco2 [15:14] */ |
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| 616 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco2_MASK 0x0000c000 |
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| 617 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco2_SHIFT 14 |
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| 618 | |
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| 619 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: OSC_PD [13:13] */ |
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| 620 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OSC_PD_MASK 0x00002000 |
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| 621 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OSC_PD_SHIFT 13 |
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| 622 | |
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| 623 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: OSC_RESET [12:12] */ |
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| 624 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OSC_RESET_MASK 0x00001000 |
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| 625 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OSC_RESET_SHIFT 12 |
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| 626 | |
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| 627 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: OSC_FREQ [11:08] */ |
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| 628 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OSC_FREQ_MASK 0x00000f00 |
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| 629 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_OSC_FREQ_SHIFT 8 |
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| 630 | |
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| 631 | /* BCM3410_regs :: PD_OOB_OSC_CNTL :: reserved_for_eco3 [07:00] */ |
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| 632 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco3_MASK 0x000000ff |
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| 633 | #define BCHP_BCM3410_regs_PD_OOB_OSC_CNTL_reserved_for_eco3_SHIFT 0 |
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| 634 | |
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| 635 | #endif /* #ifndef BCHP_BCM3410_REGS_H__ */ |
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| 636 | |
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| 637 | /* End of File */ |
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