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bhab_3128_bbsi.h

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 1999-2011, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	*
7	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
8	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
9	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
10	*
11	* $brcm_Workfile: bhab_3128_bbsi.h $
12	* $brcm_Revision: Hydra_Software_Devel/1 $
13	* $brcm_Date: 2/1/11 10:45a $
14	*
15	* Module Description:
16	* DO NOT EDIT THIS FILE DIRECTLY
17	*
18	* This module was generated magically with RDB from a source description
19	* file. You must edit the source file for changes to be made to this file.
20	*
21	*
22	* Date: Generated on Mon Nov 15 20:16:05 2010
23	* MD5 Checksum b9badef1cd568ceb22e1685b6db6c7b2
24	*
25	* Compiled with: RDB Utility combo_header.pl
26	* RDB Parser 3.0
27	* unknown unknown
28	* Perl Interpreter 5.008008
29	* Operating System linux
30	*
31	* Spec Versions: CSR 1
32	* HIF 1
33	*
34	* RDB Files: /projects/BCM3128_SRC1/A0/snapshot/bcm3128_a0/design/bbsi/rdb/bbsi_blockdef.rdb
35	* /projects/BCM3128_SRC1/A0/snapshot/bcm3128_a0/design/bbsi/rdb/csr.rdb
36	* /projects/BCM3128_SRC1/A0/snapshot/bcm3128_a0/design/bbsi/rdb/hif.rdb
37	*
38	* Revision History:
39	*
40	* $brcm_Log: /magnum/basemodules/hab/3128/bhab_3128_bbsi.h $
41	*
42	* Hydra_Software_Devel/1 2/1/11 10:45a atanugul
43	* SW3128-2: Add Support for BCM3128
44	*
45	***************************************************************************/
46
47	#ifndef HOST_SERIAL_INTERFACE_H__
48	#define HOST_SERIAL_INTERFACE_H__
49
50	/**
51	* m = memory, c = core, r = register, f = field, d = data.
52	*/
53	#if !defined(GET_FIELD) && !defined(SET_FIELD)
54	#define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN
55	#define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS
56	#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK
57	#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT
58
59	#define GET_FIELD(m,c,r,f) \
60	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))
61
62	#define SET_FIELD(m,c,r,f,d) \
63	((m) = (((m) & ~BRCM_MASK(c,r,f)) \| ((((d) >> BRCM_ALIGN(c,r,f)) << \
64	BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
65	)
66
67	#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
68	#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
69	#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
70
71	#endif /* GET & SET */
72
73	/***************************************************************************
74	*CSR - BBSI Control & Status Registers
75	***************************************************************************/
76	#define CSR_SER_PROT_REV 0x00 /* Serial protocol revision ID */
77	#define CSR_CHIP_FAM0 0x01 /* Bits [15:08] of the 16-bit chip family ID */
78	#define CSR_CHIP_FAM1 0x02 /* Bits [07:00] of the 16-bit chip family ID */
79	#define CSR_CHIP_REV0 0x03 /* Bits [15:08] of the 16-bit chip revision ID */
80	#define CSR_CHIP_REV1 0x04 /* Bits [07:00] of the 16-bit chip revision ID */
81	#define CSR_STATUS 0x05 /* Status register of the serial interface */
82	#define CSR_CONFIG 0x06 /* Configuration register of the serial interface */
83	#define CSR_RBUS_ADDR0 0x08 /* Bits [31:24] of the 32-bit RBUS address */
84	#define CSR_RBUS_ADDR1 0x09 /* Bits [23:16] of the 32-bit RBUS address */
85	#define CSR_RBUS_ADDR2 0x0a /* Bits [15:08] of the 32-bit RBUS address */
86	#define CSR_RBUS_ADDR3 0x0b /* Bits [07:00] of the 32-bit RBUS address */
87	#define CSR_RBUS_DATA0 0x0c /* Bits [31:24] of the 32-bit RBUS data */
88	#define CSR_RBUS_DATA1 0x0d /* Bits [23:16] of the 32-bit RBUS data */
89	#define CSR_RBUS_DATA2 0x0e /* Bits [15:08] of the 32-bit RBUS data */
90	#define CSR_RBUS_DATA3 0x0f /* Bits [07:00] of the 32-bit RBUS data */
91
92	/***************************************************************************
93	*HIF - BBSI Host Interface Registers
94	***************************************************************************/
95	#define HIF_SFT_RST 0x40 /* Software Reset Control Register */
96	#define HIF_SFT_RST_CFG 0x41 /* Soft Reset Configuration Control Register */
97	#define HIF_PWRDN 0x42 /* Power Down Control Register */
98	#define HIF_MEM_CTRL 0x43 /* Memory Power Control Register */
99	#define HIF_OSC_LDO_CTRL 0x44 /* XTAL Oscillator LDO Control */
100	#define HIF_OSC_BIAS_CTRL 0x45 /* XTAL Oscillator Bias Control */
101	#define HIF_OSC_CML_CTRL 0x46 /* XTAL Oscillator CML Control */
102	#define HIF_OSC_MISC_CTRL 0x47 /* XTAL Oscillator Bias Control */
103	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS 0x48 /* XTAL Oscillator Stap Override Control for xcore_bias */
104	#define HIF_OSC_STRAP_OVRD_HIGHPASS 0x49 /* XTAL Oscillator Stap Override Control for highpass */
105	#define HIF_REG_PLL_RST 0x4a /* Register PLL Reset Control */
106	#define HIF_REG_PLL_PDIV 0x4b /* Register PLL PDIV Divider Control */
107	#define HIF_REG_PLL_NDIV_INT 0x4c /* Register PLL NDIV_INT Divider Control */
108	#define HIF_REG_PLL_MDIV_CLK_108 0x4d /* Register PLL 108 MHz Clock Divider Control */
109	#define HIF_REG_PLL_MDIV_CLK_054 0x4e /* Register PLL 54 MHz Clock Divider Control */
110	#define HIF_REG_PLL_MDEL_CLK_108 0x4f /* Register PLL Output Delay Control */
111	#define HIF_REG_PLL_MDEL_CLK_054 0x50 /* Register PLL Output Delay Control */
112	#define HIF_REG_PLL_MISC_CLK_108 0x51 /* Register PLL 108 MHz Clock Miscellaneous Control */
113	#define HIF_REG_PLL_MISC_CLK_054 0x52 /* Register PLL 54 MHz Clock Miscellaneous Control */
114	#define HIF_REG_PLL_GAIN_KA 0x53 /* Register PLL Ka Gain Control */
115	#define HIF_REG_PLL_GAIN_KI 0x54 /* Register PLL Ki Gain Control */
116	#define HIF_REG_PLL_GAIN_KP 0x55 /* Register PLL Kp Gain Control */
117	#define HIF_REG_PLL_DCO_BYP_EN 0x56 /* Register PLL DCO Bypass Enable Control */
118	#define HIF_REG_PLL_DCO_CTRL1 0x57 /* Register PLL DCO Control */
119	#define HIF_REG_PLL_DCO_CTRL0 0x58 /* Register PLL DCO Control */
120	#define HIF_REG_PLL_FB_EN 0x59 /* Register PLL Feedback Enable Control */
121	#define HIF_REG_PLL_FB_OFFSET1 0x5a /* Register PLL Feedback Offset Control */
122	#define HIF_REG_PLL_FB_OFFSET0 0x5b /* Register PLL Feedback Offset Control */
123	#define HIF_REG_PLL_SS_CTRL 0x5c /* System PLL Spread Spectrum Control */
124	#define HIF_REG_PLL_SS_STEP1 0x5d /* System PLL Spread Spectrum Step Size Control */
125	#define HIF_REG_PLL_SS_STEP0 0x5e /* System PLL Spread Spectrum Step Size Control */
126	#define HIF_REG_PLL_SS_LIMIT3 0x5f /* System PLL Spread Spectrum Limit Control */
127	#define HIF_REG_PLL_SS_LIMIT2 0x60 /* System PLL Spread Spectrum Limit Control */
128	#define HIF_REG_PLL_SS_LIMIT1 0x61 /* System PLL Spread Spectrum Limit Control */
129	#define HIF_REG_PLL_SS_LIMIT0 0x62 /* System PLL Spread Spectrum Limit Control */
130	#define HIF_REG_PLL_MISC_CTRL1 0x63 /* Register PLL Miscellaneous Control */
131	#define HIF_REG_PLL_MISC_CTRL0 0x64 /* Register PLL Miscellaneous Control */
132	#define HIF_REG_PLL_STAT_CTRL 0x65 /* Register PLL Status Control */
133	#define HIF_REG_PLL_STATUS2 0x66 /* Register PLL Status */
134	#define HIF_REG_PLL_STATUS1 0x67 /* Register PLL Status */
135	#define HIF_REG_PLL_STATUS0 0x68 /* Register PLL Status */
136	#define HIF_REG_CLK_EN 0x69 /* Register Clock Enable */
137	#define HIF_SYS_CLK_EN 0x6a /* System Clock Enable */
138	#define HIF_MISC_CTRL 0x6b /* Miscellaneous Control */
139	#define HIF_SPARE3 0x78 /* Spare Register */
140	#define HIF_SPARE2 0x79 /* Spare Register */
141	#define HIF_SPARE1 0x7a /* Spare Register */
142	#define HIF_SPARE0 0x7b /* Spare Register */
143	#define HIF_SFT3 0x7c /* Software Register */
144	#define HIF_SFT2 0x7d /* Software Register */
145	#define HIF_SFT1 0x7e /* Software Register */
146	#define HIF_SFT0 0x7f /* Software Register */
147
148	/***************************************************************************
149	*SER_PROT_REV - Serial protocol revision ID
150	***************************************************************************/
151	/* CSR :: SER_PROT_REV :: SER_PROT_REV [07:00] */
152	#define CSR_SER_PROT_REV_SER_PROT_REV_MASK 0xff
153	#define CSR_SER_PROT_REV_SER_PROT_REV_ALIGN 0
154	#define CSR_SER_PROT_REV_SER_PROT_REV_BITS 8
155	#define CSR_SER_PROT_REV_SER_PROT_REV_SHIFT 0
156
157	/***************************************************************************
158	*CHIP_FAM0 - Bits [15:08] of the 16-bit chip family ID
159	***************************************************************************/
160	/* CSR :: CHIP_FAM0 :: CHIP_FAMILY [07:00] */
161	#define CSR_CHIP_FAM0_CHIP_FAMILY_MASK 0xff
162	#define CSR_CHIP_FAM0_CHIP_FAMILY_ALIGN 0
163	#define CSR_CHIP_FAM0_CHIP_FAMILY_BITS 8
164	#define CSR_CHIP_FAM0_CHIP_FAMILY_SHIFT 0
165
166	/***************************************************************************
167	*CHIP_FAM1 - Bits [07:00] of the 16-bit chip family ID
168	***************************************************************************/
169	/* CSR :: CHIP_FAM1 :: CHIP_FAMILY [07:00] */
170	#define CSR_CHIP_FAM1_CHIP_FAMILY_MASK 0xff
171	#define CSR_CHIP_FAM1_CHIP_FAMILY_ALIGN 0
172	#define CSR_CHIP_FAM1_CHIP_FAMILY_BITS 8
173	#define CSR_CHIP_FAM1_CHIP_FAMILY_SHIFT 0
174
175	/***************************************************************************
176	*CHIP_REV0 - Bits [15:08] of the 16-bit chip revision ID
177	***************************************************************************/
178	/* CSR :: CHIP_REV0 :: CHIP_REV [07:00] */
179	#define CSR_CHIP_REV0_CHIP_REV_MASK 0xff
180	#define CSR_CHIP_REV0_CHIP_REV_ALIGN 0
181	#define CSR_CHIP_REV0_CHIP_REV_BITS 8
182	#define CSR_CHIP_REV0_CHIP_REV_SHIFT 0
183
184	/***************************************************************************
185	*CHIP_REV1 - Bits [07:00] of the 16-bit chip revision ID
186	***************************************************************************/
187	/* CSR :: CHIP_REV1 :: CHIP_REV [07:00] */
188	#define CSR_CHIP_REV1_CHIP_REV_MASK 0xff
189	#define CSR_CHIP_REV1_CHIP_REV_ALIGN 0
190	#define CSR_CHIP_REV1_CHIP_REV_BITS 8
191	#define CSR_CHIP_REV1_CHIP_REV_SHIFT 0
192
193	/***************************************************************************
194	*STATUS - Status register of the serial interface
195	***************************************************************************/
196	/* CSR :: STATUS :: reserved0 [07:07] */
197	#define CSR_STATUS_reserved0_MASK 0x80
198	#define CSR_STATUS_reserved0_ALIGN 0
199	#define CSR_STATUS_reserved0_BITS 1
200	#define CSR_STATUS_reserved0_SHIFT 7
201
202	/* CSR :: STATUS :: CPU_RUNNING [06:06] */
203	#define CSR_STATUS_CPU_RUNNING_MASK 0x40
204	#define CSR_STATUS_CPU_RUNNING_ALIGN 0
205	#define CSR_STATUS_CPU_RUNNING_BITS 1
206	#define CSR_STATUS_CPU_RUNNING_SHIFT 6
207
208	/* CSR :: STATUS :: HAB_REQ [05:05] */
209	#define CSR_STATUS_HAB_REQ_MASK 0x20
210	#define CSR_STATUS_HAB_REQ_ALIGN 0
211	#define CSR_STATUS_HAB_REQ_BITS 1
212	#define CSR_STATUS_HAB_REQ_SHIFT 5
213
214	/* CSR :: STATUS :: BUSY [04:04] */
215	#define CSR_STATUS_BUSY_MASK 0x10
216	#define CSR_STATUS_BUSY_ALIGN 0
217	#define CSR_STATUS_BUSY_BITS 1
218	#define CSR_STATUS_BUSY_SHIFT 4
219
220	/* CSR :: STATUS :: RBUS_UNEXP_TX [03:03] */
221	#define CSR_STATUS_RBUS_UNEXP_TX_MASK 0x08
222	#define CSR_STATUS_RBUS_UNEXP_TX_ALIGN 0
223	#define CSR_STATUS_RBUS_UNEXP_TX_BITS 1
224	#define CSR_STATUS_RBUS_UNEXP_TX_SHIFT 3
225
226	/* CSR :: STATUS :: RBUS_TIMEOUT [02:02] */
227	#define CSR_STATUS_RBUS_TIMEOUT_MASK 0x04
228	#define CSR_STATUS_RBUS_TIMEOUT_ALIGN 0
229	#define CSR_STATUS_RBUS_TIMEOUT_BITS 1
230	#define CSR_STATUS_RBUS_TIMEOUT_SHIFT 2
231
232	/* CSR :: STATUS :: RBUS_ERR_ACK [01:01] */
233	#define CSR_STATUS_RBUS_ERR_ACK_MASK 0x02
234	#define CSR_STATUS_RBUS_ERR_ACK_ALIGN 0
235	#define CSR_STATUS_RBUS_ERR_ACK_BITS 1
236	#define CSR_STATUS_RBUS_ERR_ACK_SHIFT 1
237
238	/* CSR :: STATUS :: ERROR [00:00] */
239	#define CSR_STATUS_ERROR_MASK 0x01
240	#define CSR_STATUS_ERROR_ALIGN 0
241	#define CSR_STATUS_ERROR_BITS 1
242	#define CSR_STATUS_ERROR_SHIFT 0
243
244	/***************************************************************************
245	*CONFIG - Configuration register of the serial interface
246	***************************************************************************/
247	/* CSR :: CONFIG :: reserved0 [07:05] */
248	#define CSR_CONFIG_reserved0_MASK 0xe0
249	#define CSR_CONFIG_reserved0_ALIGN 0
250	#define CSR_CONFIG_reserved0_BITS 3
251	#define CSR_CONFIG_reserved0_SHIFT 5
252
253	/* CSR :: CONFIG :: TRANSFER_MODE [04:03] */
254	#define CSR_CONFIG_TRANSFER_MODE_MASK 0x18
255	#define CSR_CONFIG_TRANSFER_MODE_8BIT 3
256	#define CSR_CONFIG_TRANSFER_MODE_16BIT 2
257	#define CSR_CONFIG_TRANSFER_MODE_24BIT 1
258	#define CSR_CONFIG_TRANSFER_MODE_32BIT 0
259	#define CSR_CONFIG_TRANSFER_MODE_ALIGN 0
260	#define CSR_CONFIG_TRANSFER_MODE_BITS 2
261	#define CSR_CONFIG_TRANSFER_MODE_SHIFT 3
262
263	/* CSR :: CONFIG :: NO_RBUS_ADDR_INC [02:02] */
264	#define CSR_CONFIG_NO_RBUS_ADDR_INC_MASK 0x04
265	#define CSR_CONFIG_NO_RBUS_ADDR_INC_ALIGN 0
266	#define CSR_CONFIG_NO_RBUS_ADDR_INC_BITS 1
267	#define CSR_CONFIG_NO_RBUS_ADDR_INC_SHIFT 2
268
269	/* CSR :: CONFIG :: SPECULATIVE_READ_EN [01:01] */
270	#define CSR_CONFIG_SPECULATIVE_READ_EN_MASK 0x02
271	#define CSR_CONFIG_SPECULATIVE_READ_EN_ALIGN 0
272	#define CSR_CONFIG_SPECULATIVE_READ_EN_BITS 1
273	#define CSR_CONFIG_SPECULATIVE_READ_EN_SHIFT 1
274
275	/* CSR :: CONFIG :: READ_RBUS [00:00] */
276	#define CSR_CONFIG_READ_RBUS_MASK 0x01
277	#define CSR_CONFIG_READ_RBUS_READ 0x01
278	#define CSR_CONFIG_READ_RBUS_WRITE 0x00
279	#define CSR_CONFIG_READ_RBUS_ALIGN 0
280	#define CSR_CONFIG_READ_RBUS_BITS 1
281	#define CSR_CONFIG_READ_RBUS_SHIFT 0
282
283	/***************************************************************************
284	*RBUS_ADDR0 - Bits [31:24] of the 32-bit RBUS address
285	***************************************************************************/
286	/* CSR :: RBUS_ADDR0 :: RBUS_ADDR0 [07:00] */
287	#define CSR_RBUS_ADDR0_RBUS_ADDR0_MASK 0xff
288	#define CSR_RBUS_ADDR0_RBUS_ADDR0_ALIGN 0
289	#define CSR_RBUS_ADDR0_RBUS_ADDR0_BITS 8
290	#define CSR_RBUS_ADDR0_RBUS_ADDR0_SHIFT 0
291
292	/***************************************************************************
293	*RBUS_ADDR1 - Bits [23:16] of the 32-bit RBUS address
294	***************************************************************************/
295	/* CSR :: RBUS_ADDR1 :: RBUS_ADDR1 [07:00] */
296	#define CSR_RBUS_ADDR1_RBUS_ADDR1_MASK 0xff
297	#define CSR_RBUS_ADDR1_RBUS_ADDR1_ALIGN 0
298	#define CSR_RBUS_ADDR1_RBUS_ADDR1_BITS 8
299	#define CSR_RBUS_ADDR1_RBUS_ADDR1_SHIFT 0
300
301	/***************************************************************************
302	*RBUS_ADDR2 - Bits [15:08] of the 32-bit RBUS address
303	***************************************************************************/
304	/* CSR :: RBUS_ADDR2 :: RBUS_ADDR2 [07:00] */
305	#define CSR_RBUS_ADDR2_RBUS_ADDR2_MASK 0xff
306	#define CSR_RBUS_ADDR2_RBUS_ADDR2_ALIGN 0
307	#define CSR_RBUS_ADDR2_RBUS_ADDR2_BITS 8
308	#define CSR_RBUS_ADDR2_RBUS_ADDR2_SHIFT 0
309
310	/***************************************************************************
311	*RBUS_ADDR3 - Bits [07:00] of the 32-bit RBUS address
312	***************************************************************************/
313	/* CSR :: RBUS_ADDR3 :: RBUS_ADDR3 [07:00] */
314	#define CSR_RBUS_ADDR3_RBUS_ADDR3_MASK 0xff
315	#define CSR_RBUS_ADDR3_RBUS_ADDR3_ALIGN 0
316	#define CSR_RBUS_ADDR3_RBUS_ADDR3_BITS 8
317	#define CSR_RBUS_ADDR3_RBUS_ADDR3_SHIFT 0
318
319	/***************************************************************************
320	*RBUS_DATA0 - Bits [31:24] of the 32-bit RBUS data
321	***************************************************************************/
322	/* CSR :: RBUS_DATA0 :: RBUS_DATA0 [07:00] */
323	#define CSR_RBUS_DATA0_RBUS_DATA0_MASK 0xff
324	#define CSR_RBUS_DATA0_RBUS_DATA0_ALIGN 0
325	#define CSR_RBUS_DATA0_RBUS_DATA0_BITS 8
326	#define CSR_RBUS_DATA0_RBUS_DATA0_SHIFT 0
327
328	/***************************************************************************
329	*RBUS_DATA1 - Bits [23:16] of the 32-bit RBUS data
330	***************************************************************************/
331	/* CSR :: RBUS_DATA1 :: RBUS_DATA1 [07:00] */
332	#define CSR_RBUS_DATA1_RBUS_DATA1_MASK 0xff
333	#define CSR_RBUS_DATA1_RBUS_DATA1_ALIGN 0
334	#define CSR_RBUS_DATA1_RBUS_DATA1_BITS 8
335	#define CSR_RBUS_DATA1_RBUS_DATA1_SHIFT 0
336
337	/***************************************************************************
338	*RBUS_DATA2 - Bits [15:08] of the 32-bit RBUS data
339	***************************************************************************/
340	/* CSR :: RBUS_DATA2 :: RBUS_DATA2 [07:00] */
341	#define CSR_RBUS_DATA2_RBUS_DATA2_MASK 0xff
342	#define CSR_RBUS_DATA2_RBUS_DATA2_ALIGN 0
343	#define CSR_RBUS_DATA2_RBUS_DATA2_BITS 8
344	#define CSR_RBUS_DATA2_RBUS_DATA2_SHIFT 0
345
346	/***************************************************************************
347	*RBUS_DATA3 - Bits [07:00] of the 32-bit RBUS data
348	***************************************************************************/
349	/* CSR :: RBUS_DATA3 :: RBUS_DATA3 [07:00] */
350	#define CSR_RBUS_DATA3_RBUS_DATA3_MASK 0xff
351	#define CSR_RBUS_DATA3_RBUS_DATA3_ALIGN 0
352	#define CSR_RBUS_DATA3_RBUS_DATA3_BITS 8
353	#define CSR_RBUS_DATA3_RBUS_DATA3_SHIFT 0
354
355	/***************************************************************************
356	*SFT_RST - Software Reset Control Register
357	***************************************************************************/
358	/* HIF :: SFT_RST :: RSVD [07:06] */
359	#define HIF_SFT_RST_RSVD_MASK 0xc0
360	#define HIF_SFT_RST_RSVD_ALIGN 0
361	#define HIF_SFT_RST_RSVD_BITS 2
362	#define HIF_SFT_RST_RSVD_SHIFT 6
363
364	/* HIF :: SFT_RST :: DS_TOPB [05:05] */
365	#define HIF_SFT_RST_DS_TOPB_MASK 0x20
366	#define HIF_SFT_RST_DS_TOPB_ALIGN 0
367	#define HIF_SFT_RST_DS_TOPB_BITS 1
368	#define HIF_SFT_RST_DS_TOPB_SHIFT 5
369
370	/* HIF :: SFT_RST :: DS_TOPA [04:04] */
371	#define HIF_SFT_RST_DS_TOPA_MASK 0x10
372	#define HIF_SFT_RST_DS_TOPA_ALIGN 0
373	#define HIF_SFT_RST_DS_TOPA_BITS 1
374	#define HIF_SFT_RST_DS_TOPA_SHIFT 4
375
376	/* HIF :: SFT_RST :: WFE [03:03] */
377	#define HIF_SFT_RST_WFE_MASK 0x08
378	#define HIF_SFT_RST_WFE_ALIGN 0
379	#define HIF_SFT_RST_WFE_BITS 1
380	#define HIF_SFT_RST_WFE_SHIFT 3
381
382	/* HIF :: SFT_RST :: CG [02:02] */
383	#define HIF_SFT_RST_CG_MASK 0x04
384	#define HIF_SFT_RST_CG_ALIGN 0
385	#define HIF_SFT_RST_CG_BITS 1
386	#define HIF_SFT_RST_CG_SHIFT 2
387
388	/* HIF :: SFT_RST :: PERIPH [01:01] */
389	#define HIF_SFT_RST_PERIPH_MASK 0x02
390	#define HIF_SFT_RST_PERIPH_ALIGN 0
391	#define HIF_SFT_RST_PERIPH_BITS 1
392	#define HIF_SFT_RST_PERIPH_SHIFT 1
393
394	/* HIF :: SFT_RST :: LEAP [00:00] */
395	#define HIF_SFT_RST_LEAP_MASK 0x01
396	#define HIF_SFT_RST_LEAP_ALIGN 0
397	#define HIF_SFT_RST_LEAP_BITS 1
398	#define HIF_SFT_RST_LEAP_SHIFT 0
399
400	/***************************************************************************
401	*SFT_RST_CFG - Soft Reset Configuration Control Register
402	***************************************************************************/
403	/* HIF :: SFT_RST_CFG :: RSVD [07:06] */
404	#define HIF_SFT_RST_CFG_RSVD_MASK 0xc0
405	#define HIF_SFT_RST_CFG_RSVD_ALIGN 0
406	#define HIF_SFT_RST_CFG_RSVD_BITS 2
407	#define HIF_SFT_RST_CFG_RSVD_SHIFT 6
408
409	/* HIF :: SFT_RST_CFG :: DS_TOPB [05:05] */
410	#define HIF_SFT_RST_CFG_DS_TOPB_MASK 0x20
411	#define HIF_SFT_RST_CFG_DS_TOPB_ALIGN 0
412	#define HIF_SFT_RST_CFG_DS_TOPB_BITS 1
413	#define HIF_SFT_RST_CFG_DS_TOPB_SHIFT 5
414
415	/* HIF :: SFT_RST_CFG :: DS_TOPA [04:04] */
416	#define HIF_SFT_RST_CFG_DS_TOPA_MASK 0x10
417	#define HIF_SFT_RST_CFG_DS_TOPA_ALIGN 0
418	#define HIF_SFT_RST_CFG_DS_TOPA_BITS 1
419	#define HIF_SFT_RST_CFG_DS_TOPA_SHIFT 4
420
421	/* HIF :: SFT_RST_CFG :: WFE [03:03] */
422	#define HIF_SFT_RST_CFG_WFE_MASK 0x08
423	#define HIF_SFT_RST_CFG_WFE_ALIGN 0
424	#define HIF_SFT_RST_CFG_WFE_BITS 1
425	#define HIF_SFT_RST_CFG_WFE_SHIFT 3
426
427	/* HIF :: SFT_RST_CFG :: CG [02:02] */
428	#define HIF_SFT_RST_CFG_CG_MASK 0x04
429	#define HIF_SFT_RST_CFG_CG_ALIGN 0
430	#define HIF_SFT_RST_CFG_CG_BITS 1
431	#define HIF_SFT_RST_CFG_CG_SHIFT 2
432
433	/* HIF :: SFT_RST_CFG :: PERIPH [01:01] */
434	#define HIF_SFT_RST_CFG_PERIPH_MASK 0x02
435	#define HIF_SFT_RST_CFG_PERIPH_ALIGN 0
436	#define HIF_SFT_RST_CFG_PERIPH_BITS 1
437	#define HIF_SFT_RST_CFG_PERIPH_SHIFT 1
438
439	/* HIF :: SFT_RST_CFG :: LEAP [00:00] */
440	#define HIF_SFT_RST_CFG_LEAP_MASK 0x01
441	#define HIF_SFT_RST_CFG_LEAP_ALIGN 0
442	#define HIF_SFT_RST_CFG_LEAP_BITS 1
443	#define HIF_SFT_RST_CFG_LEAP_SHIFT 0
444
445	/***************************************************************************
446	*PWRDN - Power Down Control Register
447	***************************************************************************/
448	/* HIF :: PWRDN :: PWRDN_07 [07:07] */
449	#define HIF_PWRDN_PWRDN_07_MASK 0x80
450	#define HIF_PWRDN_PWRDN_07_ALIGN 0
451	#define HIF_PWRDN_PWRDN_07_BITS 1
452	#define HIF_PWRDN_PWRDN_07_SHIFT 7
453
454	/* HIF :: PWRDN :: PWRDN_06 [06:06] */
455	#define HIF_PWRDN_PWRDN_06_MASK 0x40
456	#define HIF_PWRDN_PWRDN_06_ALIGN 0
457	#define HIF_PWRDN_PWRDN_06_BITS 1
458	#define HIF_PWRDN_PWRDN_06_SHIFT 6
459
460	/* HIF :: PWRDN :: PWRDN_05 [05:05] */
461	#define HIF_PWRDN_PWRDN_05_MASK 0x20
462	#define HIF_PWRDN_PWRDN_05_ALIGN 0
463	#define HIF_PWRDN_PWRDN_05_BITS 1
464	#define HIF_PWRDN_PWRDN_05_SHIFT 5
465
466	/* HIF :: PWRDN :: PWRDN_04 [04:04] */
467	#define HIF_PWRDN_PWRDN_04_MASK 0x10
468	#define HIF_PWRDN_PWRDN_04_ALIGN 0
469	#define HIF_PWRDN_PWRDN_04_BITS 1
470	#define HIF_PWRDN_PWRDN_04_SHIFT 4
471
472	/* HIF :: PWRDN :: PWRDN_03 [03:03] */
473	#define HIF_PWRDN_PWRDN_03_MASK 0x08
474	#define HIF_PWRDN_PWRDN_03_ALIGN 0
475	#define HIF_PWRDN_PWRDN_03_BITS 1
476	#define HIF_PWRDN_PWRDN_03_SHIFT 3
477
478	/* HIF :: PWRDN :: OSC_LDO [02:02] */
479	#define HIF_PWRDN_OSC_LDO_MASK 0x04
480	#define HIF_PWRDN_OSC_LDO_ALIGN 0
481	#define HIF_PWRDN_OSC_LDO_BITS 1
482	#define HIF_PWRDN_OSC_LDO_SHIFT 2
483
484	/* HIF :: PWRDN :: OSC_XTAL [01:01] */
485	#define HIF_PWRDN_OSC_XTAL_MASK 0x02
486	#define HIF_PWRDN_OSC_XTAL_ALIGN 0
487	#define HIF_PWRDN_OSC_XTAL_BITS 1
488	#define HIF_PWRDN_OSC_XTAL_SHIFT 1
489
490	/* HIF :: PWRDN :: REG_PLL [00:00] */
491	#define HIF_PWRDN_REG_PLL_MASK 0x01
492	#define HIF_PWRDN_REG_PLL_ALIGN 0
493	#define HIF_PWRDN_REG_PLL_BITS 1
494	#define HIF_PWRDN_REG_PLL_SHIFT 0
495
496	/***************************************************************************
497	*MEM_CTRL - Memory Power Control Register
498	***************************************************************************/
499	/* HIF :: MEM_CTRL :: RSVD [07:04] */
500	#define HIF_MEM_CTRL_RSVD_MASK 0xf0
501	#define HIF_MEM_CTRL_RSVD_ALIGN 0
502	#define HIF_MEM_CTRL_RSVD_BITS 4
503	#define HIF_MEM_CTRL_RSVD_SHIFT 4
504
505	/* HIF :: MEM_CTRL :: ROM_STBY_LEAP [03:03] */
506	#define HIF_MEM_CTRL_ROM_STBY_LEAP_MASK 0x08
507	#define HIF_MEM_CTRL_ROM_STBY_LEAP_ALIGN 0
508	#define HIF_MEM_CTRL_ROM_STBY_LEAP_BITS 1
509	#define HIF_MEM_CTRL_ROM_STBY_LEAP_SHIFT 3
510
511	/* HIF :: MEM_CTRL :: RAM_STBY_LEAP [02:02] */
512	#define HIF_MEM_CTRL_RAM_STBY_LEAP_MASK 0x04
513	#define HIF_MEM_CTRL_RAM_STBY_LEAP_ALIGN 0
514	#define HIF_MEM_CTRL_RAM_STBY_LEAP_BITS 1
515	#define HIF_MEM_CTRL_RAM_STBY_LEAP_SHIFT 2
516
517	/* HIF :: MEM_CTRL :: PSM_LEAP [01:00] */
518	#define HIF_MEM_CTRL_PSM_LEAP_MASK 0x03
519	#define HIF_MEM_CTRL_PSM_LEAP_ALIGN 0
520	#define HIF_MEM_CTRL_PSM_LEAP_BITS 2
521	#define HIF_MEM_CTRL_PSM_LEAP_SHIFT 0
522
523	/***************************************************************************
524	*OSC_LDO_CTRL - XTAL Oscillator LDO Control
525	***************************************************************************/
526	/* HIF :: OSC_LDO_CTRL :: RSVD [07:02] */
527	#define HIF_OSC_LDO_CTRL_RSVD_MASK 0xfc
528	#define HIF_OSC_LDO_CTRL_RSVD_ALIGN 0
529	#define HIF_OSC_LDO_CTRL_RSVD_BITS 6
530	#define HIF_OSC_LDO_CTRL_RSVD_SHIFT 2
531
532	/* HIF :: OSC_LDO_CTRL :: OUTPUT [01:00] */
533	#define HIF_OSC_LDO_CTRL_OUTPUT_MASK 0x03
534	#define HIF_OSC_LDO_CTRL_OUTPUT_ALIGN 0
535	#define HIF_OSC_LDO_CTRL_OUTPUT_BITS 2
536	#define HIF_OSC_LDO_CTRL_OUTPUT_SHIFT 0
537
538	/***************************************************************************
539	*OSC_BIAS_CTRL - XTAL Oscillator Bias Control
540	***************************************************************************/
541	/* HIF :: OSC_BIAS_CTRL :: RSVD_1 [07:07] */
542	#define HIF_OSC_BIAS_CTRL_RSVD_1_MASK 0x80
543	#define HIF_OSC_BIAS_CTRL_RSVD_1_ALIGN 0
544	#define HIF_OSC_BIAS_CTRL_RSVD_1_BITS 1
545	#define HIF_OSC_BIAS_CTRL_RSVD_1_SHIFT 7
546
547	/* HIF :: OSC_BIAS_CTRL :: D2C [06:04] */
548	#define HIF_OSC_BIAS_CTRL_D2C_MASK 0x70
549	#define HIF_OSC_BIAS_CTRL_D2C_ALIGN 0
550	#define HIF_OSC_BIAS_CTRL_D2C_BITS 3
551	#define HIF_OSC_BIAS_CTRL_D2C_SHIFT 4
552
553	/* HIF :: OSC_BIAS_CTRL :: RSVD_0 [03:03] */
554	#define HIF_OSC_BIAS_CTRL_RSVD_0_MASK 0x08
555	#define HIF_OSC_BIAS_CTRL_RSVD_0_ALIGN 0
556	#define HIF_OSC_BIAS_CTRL_RSVD_0_BITS 1
557	#define HIF_OSC_BIAS_CTRL_RSVD_0_SHIFT 3
558
559	/* HIF :: OSC_BIAS_CTRL :: MASTER [02:00] */
560	#define HIF_OSC_BIAS_CTRL_MASTER_MASK 0x07
561	#define HIF_OSC_BIAS_CTRL_MASTER_ALIGN 0
562	#define HIF_OSC_BIAS_CTRL_MASTER_BITS 3
563	#define HIF_OSC_BIAS_CTRL_MASTER_SHIFT 0
564
565	/***************************************************************************
566	*OSC_CML_CTRL - XTAL Oscillator CML Control
567	***************************************************************************/
568	/* HIF :: OSC_CML_CTRL :: RSVD_1 [07:05] */
569	#define HIF_OSC_CML_CTRL_RSVD_1_MASK 0xe0
570	#define HIF_OSC_CML_CTRL_RSVD_1_ALIGN 0
571	#define HIF_OSC_CML_CTRL_RSVD_1_BITS 3
572	#define HIF_OSC_CML_CTRL_RSVD_1_SHIFT 5
573
574	/* HIF :: OSC_CML_CTRL :: CUR [04:04] */
575	#define HIF_OSC_CML_CTRL_CUR_MASK 0x10
576	#define HIF_OSC_CML_CTRL_CUR_ALIGN 0
577	#define HIF_OSC_CML_CTRL_CUR_BITS 1
578	#define HIF_OSC_CML_CTRL_CUR_SHIFT 4
579
580	/* HIF :: OSC_CML_CTRL :: RSVD_0 [03:02] */
581	#define HIF_OSC_CML_CTRL_RSVD_0_MASK 0x0c
582	#define HIF_OSC_CML_CTRL_RSVD_0_ALIGN 0
583	#define HIF_OSC_CML_CTRL_RSVD_0_BITS 2
584	#define HIF_OSC_CML_CTRL_RSVD_0_SHIFT 2
585
586	/* HIF :: OSC_CML_CTRL :: DRIVE [01:00] */
587	#define HIF_OSC_CML_CTRL_DRIVE_MASK 0x03
588	#define HIF_OSC_CML_CTRL_DRIVE_ALIGN 0
589	#define HIF_OSC_CML_CTRL_DRIVE_BITS 2
590	#define HIF_OSC_CML_CTRL_DRIVE_SHIFT 0
591
592	/***************************************************************************
593	*OSC_MISC_CTRL - XTAL Oscillator Bias Control
594	***************************************************************************/
595	/* HIF :: OSC_MISC_CTRL :: RSVD_0 [07:01] */
596	#define HIF_OSC_MISC_CTRL_RSVD_0_MASK 0xfe
597	#define HIF_OSC_MISC_CTRL_RSVD_0_ALIGN 0
598	#define HIF_OSC_MISC_CTRL_RSVD_0_BITS 7
599	#define HIF_OSC_MISC_CTRL_RSVD_0_SHIFT 1
600
601	/* HIF :: OSC_MISC_CTRL :: LPG [00:00] */
602	#define HIF_OSC_MISC_CTRL_LPG_MASK 0x01
603	#define HIF_OSC_MISC_CTRL_LPG_ALIGN 0
604	#define HIF_OSC_MISC_CTRL_LPG_BITS 1
605	#define HIF_OSC_MISC_CTRL_LPG_SHIFT 0
606
607	/***************************************************************************
608	*OSC_STRAP_OVRD_XCORE_BIAS - XTAL Oscillator Stap Override Control for xcore_bias
609	***************************************************************************/
610	/* HIF :: OSC_STRAP_OVRD_XCORE_BIAS :: RSVD_0 [07:05] */
611	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_MASK 0xe0
612	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_ALIGN 0
613	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_BITS 3
614	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_RSVD_0_SHIFT 5
615
616	/* HIF :: OSC_STRAP_OVRD_XCORE_BIAS :: EN [04:04] */
617	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_MASK 0x10
618	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_ALIGN 0
619	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_BITS 1
620	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_EN_SHIFT 4
621
622	/* HIF :: OSC_STRAP_OVRD_XCORE_BIAS :: VAL [03:00] */
623	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_MASK 0x0f
624	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_ALIGN 0
625	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_BITS 4
626	#define HIF_OSC_STRAP_OVRD_XCORE_BIAS_VAL_SHIFT 0
627
628	/***************************************************************************
629	*OSC_STRAP_OVRD_HIGHPASS - XTAL Oscillator Stap Override Control for highpass
630	***************************************************************************/
631	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: RSVD_1 [07:05] */
632	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_MASK 0xe0
633	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_ALIGN 0
634	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_BITS 3
635	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_1_SHIFT 5
636
637	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: EN [04:04] */
638	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_MASK 0x10
639	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_ALIGN 0
640	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_BITS 1
641	#define HIF_OSC_STRAP_OVRD_HIGHPASS_EN_SHIFT 4
642
643	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: RSVD_0 [03:01] */
644	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_MASK 0x0e
645	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_ALIGN 0
646	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_BITS 3
647	#define HIF_OSC_STRAP_OVRD_HIGHPASS_RSVD_0_SHIFT 1
648
649	/* HIF :: OSC_STRAP_OVRD_HIGHPASS :: VAL [00:00] */
650	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_MASK 0x01
651	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_ALIGN 0
652	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_BITS 1
653	#define HIF_OSC_STRAP_OVRD_HIGHPASS_VAL_SHIFT 0
654
655	/***************************************************************************
656	*REG_PLL_RST - Register PLL Reset Control
657	***************************************************************************/
658	/* HIF :: REG_PLL_RST :: RSVD_0 [07:02] */
659	#define HIF_REG_PLL_RST_RSVD_0_MASK 0xfc
660	#define HIF_REG_PLL_RST_RSVD_0_ALIGN 0
661	#define HIF_REG_PLL_RST_RSVD_0_BITS 6
662	#define HIF_REG_PLL_RST_RSVD_0_SHIFT 2
663
664	/* HIF :: REG_PLL_RST :: POST [01:01] */
665	#define HIF_REG_PLL_RST_POST_MASK 0x02
666	#define HIF_REG_PLL_RST_POST_ALIGN 0
667	#define HIF_REG_PLL_RST_POST_BITS 1
668	#define HIF_REG_PLL_RST_POST_SHIFT 1
669
670	/* HIF :: REG_PLL_RST :: GLOBAL [00:00] */
671	#define HIF_REG_PLL_RST_GLOBAL_MASK 0x01
672	#define HIF_REG_PLL_RST_GLOBAL_ALIGN 0
673	#define HIF_REG_PLL_RST_GLOBAL_BITS 1
674	#define HIF_REG_PLL_RST_GLOBAL_SHIFT 0
675
676	/***************************************************************************
677	*REG_PLL_PDIV - Register PLL PDIV Divider Control
678	***************************************************************************/
679	/* HIF :: REG_PLL_PDIV :: RSVD [07:04] */
680	#define HIF_REG_PLL_PDIV_RSVD_MASK 0xf0
681	#define HIF_REG_PLL_PDIV_RSVD_ALIGN 0
682	#define HIF_REG_PLL_PDIV_RSVD_BITS 4
683	#define HIF_REG_PLL_PDIV_RSVD_SHIFT 4
684
685	/* HIF :: REG_PLL_PDIV :: DIV [03:00] */
686	#define HIF_REG_PLL_PDIV_DIV_MASK 0x0f
687	#define HIF_REG_PLL_PDIV_DIV_ALIGN 0
688	#define HIF_REG_PLL_PDIV_DIV_BITS 4
689	#define HIF_REG_PLL_PDIV_DIV_SHIFT 0
690
691	/***************************************************************************
692	*REG_PLL_NDIV_INT - Register PLL NDIV_INT Divider Control
693	***************************************************************************/
694	/* HIF :: REG_PLL_NDIV_INT :: DIV [07:00] */
695	#define HIF_REG_PLL_NDIV_INT_DIV_MASK 0xff
696	#define HIF_REG_PLL_NDIV_INT_DIV_ALIGN 0
697	#define HIF_REG_PLL_NDIV_INT_DIV_BITS 8
698	#define HIF_REG_PLL_NDIV_INT_DIV_SHIFT 0
699
700	/***************************************************************************
701	*REG_PLL_MDIV_CLK_108 - Register PLL 108 MHz Clock Divider Control
702	***************************************************************************/
703	/* HIF :: REG_PLL_MDIV_CLK_108 :: DIV [07:00] */
704	#define HIF_REG_PLL_MDIV_CLK_108_DIV_MASK 0xff
705	#define HIF_REG_PLL_MDIV_CLK_108_DIV_ALIGN 0
706	#define HIF_REG_PLL_MDIV_CLK_108_DIV_BITS 8
707	#define HIF_REG_PLL_MDIV_CLK_108_DIV_SHIFT 0
708
709	/***************************************************************************
710	*REG_PLL_MDIV_CLK_054 - Register PLL 54 MHz Clock Divider Control
711	***************************************************************************/
712	/* HIF :: REG_PLL_MDIV_CLK_054 :: DIV [07:00] */
713	#define HIF_REG_PLL_MDIV_CLK_054_DIV_MASK 0xff
714	#define HIF_REG_PLL_MDIV_CLK_054_DIV_ALIGN 0
715	#define HIF_REG_PLL_MDIV_CLK_054_DIV_BITS 8
716	#define HIF_REG_PLL_MDIV_CLK_054_DIV_SHIFT 0
717
718	/***************************************************************************
719	*REG_PLL_MDEL_CLK_108 - Register PLL Output Delay Control
720	***************************************************************************/
721	/* HIF :: REG_PLL_MDEL_CLK_108 :: RSVD [07:03] */
722	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_MASK 0xf8
723	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_ALIGN 0
724	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_BITS 5
725	#define HIF_REG_PLL_MDEL_CLK_108_RSVD_SHIFT 3
726
727	/* HIF :: REG_PLL_MDEL_CLK_108 :: DLY [02:00] */
728	#define HIF_REG_PLL_MDEL_CLK_108_DLY_MASK 0x07
729	#define HIF_REG_PLL_MDEL_CLK_108_DLY_ALIGN 0
730	#define HIF_REG_PLL_MDEL_CLK_108_DLY_BITS 3
731	#define HIF_REG_PLL_MDEL_CLK_108_DLY_SHIFT 0
732
733	/***************************************************************************
734	*REG_PLL_MDEL_CLK_054 - Register PLL Output Delay Control
735	***************************************************************************/
736	/* HIF :: REG_PLL_MDEL_CLK_054 :: RSVD [07:03] */
737	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_MASK 0xf8
738	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_ALIGN 0
739	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_BITS 5
740	#define HIF_REG_PLL_MDEL_CLK_054_RSVD_SHIFT 3
741
742	/* HIF :: REG_PLL_MDEL_CLK_054 :: DLY [02:00] */
743	#define HIF_REG_PLL_MDEL_CLK_054_DLY_MASK 0x07
744	#define HIF_REG_PLL_MDEL_CLK_054_DLY_ALIGN 0
745	#define HIF_REG_PLL_MDEL_CLK_054_DLY_BITS 3
746	#define HIF_REG_PLL_MDEL_CLK_054_DLY_SHIFT 0
747
748	/***************************************************************************
749	*REG_PLL_MISC_CLK_108 - Register PLL 108 MHz Clock Miscellaneous Control
750	***************************************************************************/
751	/* HIF :: REG_PLL_MISC_CLK_108 :: RSVD [07:03] */
752	#define HIF_REG_PLL_MISC_CLK_108_RSVD_MASK 0xf8
753	#define HIF_REG_PLL_MISC_CLK_108_RSVD_ALIGN 0
754	#define HIF_REG_PLL_MISC_CLK_108_RSVD_BITS 5
755	#define HIF_REG_PLL_MISC_CLK_108_RSVD_SHIFT 3
756
757	/* HIF :: REG_PLL_MISC_CLK_108 :: LOAD_DIS [02:02] */
758	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_MASK 0x04
759	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_ALIGN 0
760	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_BITS 1
761	#define HIF_REG_PLL_MISC_CLK_108_LOAD_DIS_SHIFT 2
762
763	/* HIF :: REG_PLL_MISC_CLK_108 :: PWRUP [01:01] */
764	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_MASK 0x02
765	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_ALIGN 0
766	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_BITS 1
767	#define HIF_REG_PLL_MISC_CLK_108_PWRUP_SHIFT 1
768
769	/* HIF :: REG_PLL_MISC_CLK_108 :: EN [00:00] */
770	#define HIF_REG_PLL_MISC_CLK_108_EN_MASK 0x01
771	#define HIF_REG_PLL_MISC_CLK_108_EN_ALIGN 0
772	#define HIF_REG_PLL_MISC_CLK_108_EN_BITS 1
773	#define HIF_REG_PLL_MISC_CLK_108_EN_SHIFT 0
774
775	/***************************************************************************
776	*REG_PLL_MISC_CLK_054 - Register PLL 54 MHz Clock Miscellaneous Control
777	***************************************************************************/
778	/* HIF :: REG_PLL_MISC_CLK_054 :: RSVD [07:03] */
779	#define HIF_REG_PLL_MISC_CLK_054_RSVD_MASK 0xf8
780	#define HIF_REG_PLL_MISC_CLK_054_RSVD_ALIGN 0
781	#define HIF_REG_PLL_MISC_CLK_054_RSVD_BITS 5
782	#define HIF_REG_PLL_MISC_CLK_054_RSVD_SHIFT 3
783
784	/* HIF :: REG_PLL_MISC_CLK_054 :: LOAD_DIS [02:02] */
785	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_MASK 0x04
786	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_ALIGN 0
787	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_BITS 1
788	#define HIF_REG_PLL_MISC_CLK_054_LOAD_DIS_SHIFT 2
789
790	/* HIF :: REG_PLL_MISC_CLK_054 :: PWRUP [01:01] */
791	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_MASK 0x02
792	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_ALIGN 0
793	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_BITS 1
794	#define HIF_REG_PLL_MISC_CLK_054_PWRUP_SHIFT 1
795
796	/* HIF :: REG_PLL_MISC_CLK_054 :: EN [00:00] */
797	#define HIF_REG_PLL_MISC_CLK_054_EN_MASK 0x01
798	#define HIF_REG_PLL_MISC_CLK_054_EN_ALIGN 0
799	#define HIF_REG_PLL_MISC_CLK_054_EN_BITS 1
800	#define HIF_REG_PLL_MISC_CLK_054_EN_SHIFT 0
801
802	/***************************************************************************
803	*REG_PLL_GAIN_KA - Register PLL Ka Gain Control
804	***************************************************************************/
805	/* HIF :: REG_PLL_GAIN_KA :: RSVD [07:03] */
806	#define HIF_REG_PLL_GAIN_KA_RSVD_MASK 0xf8
807	#define HIF_REG_PLL_GAIN_KA_RSVD_ALIGN 0
808	#define HIF_REG_PLL_GAIN_KA_RSVD_BITS 5
809	#define HIF_REG_PLL_GAIN_KA_RSVD_SHIFT 3
810
811	/* HIF :: REG_PLL_GAIN_KA :: KA [02:00] */
812	#define HIF_REG_PLL_GAIN_KA_KA_MASK 0x07
813	#define HIF_REG_PLL_GAIN_KA_KA_ALIGN 0
814	#define HIF_REG_PLL_GAIN_KA_KA_BITS 3
815	#define HIF_REG_PLL_GAIN_KA_KA_SHIFT 0
816
817	/***************************************************************************
818	*REG_PLL_GAIN_KI - Register PLL Ki Gain Control
819	***************************************************************************/
820	/* HIF :: REG_PLL_GAIN_KI :: RSVD [07:03] */
821	#define HIF_REG_PLL_GAIN_KI_RSVD_MASK 0xf8
822	#define HIF_REG_PLL_GAIN_KI_RSVD_ALIGN 0
823	#define HIF_REG_PLL_GAIN_KI_RSVD_BITS 5
824	#define HIF_REG_PLL_GAIN_KI_RSVD_SHIFT 3
825
826	/* HIF :: REG_PLL_GAIN_KI :: KI [02:00] */
827	#define HIF_REG_PLL_GAIN_KI_KI_MASK 0x07
828	#define HIF_REG_PLL_GAIN_KI_KI_ALIGN 0
829	#define HIF_REG_PLL_GAIN_KI_KI_BITS 3
830	#define HIF_REG_PLL_GAIN_KI_KI_SHIFT 0
831
832	/***************************************************************************
833	*REG_PLL_GAIN_KP - Register PLL Kp Gain Control
834	***************************************************************************/
835	/* HIF :: REG_PLL_GAIN_KP :: RSVD [07:04] */
836	#define HIF_REG_PLL_GAIN_KP_RSVD_MASK 0xf0
837	#define HIF_REG_PLL_GAIN_KP_RSVD_ALIGN 0
838	#define HIF_REG_PLL_GAIN_KP_RSVD_BITS 4
839	#define HIF_REG_PLL_GAIN_KP_RSVD_SHIFT 4
840
841	/* HIF :: REG_PLL_GAIN_KP :: KP [03:00] */
842	#define HIF_REG_PLL_GAIN_KP_KP_MASK 0x0f
843	#define HIF_REG_PLL_GAIN_KP_KP_ALIGN 0
844	#define HIF_REG_PLL_GAIN_KP_KP_BITS 4
845	#define HIF_REG_PLL_GAIN_KP_KP_SHIFT 0
846
847	/***************************************************************************
848	*REG_PLL_DCO_BYP_EN - Register PLL DCO Bypass Enable Control
849	***************************************************************************/
850	/* HIF :: REG_PLL_DCO_BYP_EN :: RSVD [07:01] */
851	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_MASK 0xfe
852	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_ALIGN 0
853	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_BITS 7
854	#define HIF_REG_PLL_DCO_BYP_EN_RSVD_SHIFT 1
855
856	/* HIF :: REG_PLL_DCO_BYP_EN :: EN [00:00] */
857	#define HIF_REG_PLL_DCO_BYP_EN_EN_MASK 0x01
858	#define HIF_REG_PLL_DCO_BYP_EN_EN_ALIGN 0
859	#define HIF_REG_PLL_DCO_BYP_EN_EN_BITS 1
860	#define HIF_REG_PLL_DCO_BYP_EN_EN_SHIFT 0
861
862	/***************************************************************************
863	*REG_PLL_DCO_CTRL1 - Register PLL DCO Control
864	***************************************************************************/
865	/* HIF :: REG_PLL_DCO_CTRL1 :: RSVD [07:04] */
866	#define HIF_REG_PLL_DCO_CTRL1_RSVD_MASK 0xf0
867	#define HIF_REG_PLL_DCO_CTRL1_RSVD_ALIGN 0
868	#define HIF_REG_PLL_DCO_CTRL1_RSVD_BITS 4
869	#define HIF_REG_PLL_DCO_CTRL1_RSVD_SHIFT 4
870
871	/* HIF :: REG_PLL_DCO_CTRL1 :: VAL [03:00] */
872	#define HIF_REG_PLL_DCO_CTRL1_VAL_MASK 0x0f
873	#define HIF_REG_PLL_DCO_CTRL1_VAL_ALIGN 0
874	#define HIF_REG_PLL_DCO_CTRL1_VAL_BITS 4
875	#define HIF_REG_PLL_DCO_CTRL1_VAL_SHIFT 0
876
877	/***************************************************************************
878	*REG_PLL_DCO_CTRL0 - Register PLL DCO Control
879	***************************************************************************/
880	/* HIF :: REG_PLL_DCO_CTRL0 :: VAL [07:00] */
881	#define HIF_REG_PLL_DCO_CTRL0_VAL_MASK 0xff
882	#define HIF_REG_PLL_DCO_CTRL0_VAL_ALIGN 0
883	#define HIF_REG_PLL_DCO_CTRL0_VAL_BITS 8
884	#define HIF_REG_PLL_DCO_CTRL0_VAL_SHIFT 0
885
886	/***************************************************************************
887	*REG_PLL_FB_EN - Register PLL Feedback Enable Control
888	***************************************************************************/
889	/* HIF :: REG_PLL_FB_EN :: RSVD [07:01] */
890	#define HIF_REG_PLL_FB_EN_RSVD_MASK 0xfe
891	#define HIF_REG_PLL_FB_EN_RSVD_ALIGN 0
892	#define HIF_REG_PLL_FB_EN_RSVD_BITS 7
893	#define HIF_REG_PLL_FB_EN_RSVD_SHIFT 1
894
895	/* HIF :: REG_PLL_FB_EN :: EN [00:00] */
896	#define HIF_REG_PLL_FB_EN_EN_MASK 0x01
897	#define HIF_REG_PLL_FB_EN_EN_ALIGN 0
898	#define HIF_REG_PLL_FB_EN_EN_BITS 1
899	#define HIF_REG_PLL_FB_EN_EN_SHIFT 0
900
901	/***************************************************************************
902	*REG_PLL_FB_OFFSET1 - Register PLL Feedback Offset Control
903	***************************************************************************/
904	/* HIF :: REG_PLL_FB_OFFSET1 :: RSVD [07:04] */
905	#define HIF_REG_PLL_FB_OFFSET1_RSVD_MASK 0xf0
906	#define HIF_REG_PLL_FB_OFFSET1_RSVD_ALIGN 0
907	#define HIF_REG_PLL_FB_OFFSET1_RSVD_BITS 4
908	#define HIF_REG_PLL_FB_OFFSET1_RSVD_SHIFT 4
909
910	/* HIF :: REG_PLL_FB_OFFSET1 :: OFFSET [03:00] */
911	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_MASK 0x0f
912	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_ALIGN 0
913	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_BITS 4
914	#define HIF_REG_PLL_FB_OFFSET1_OFFSET_SHIFT 0
915
916	/***************************************************************************
917	*REG_PLL_FB_OFFSET0 - Register PLL Feedback Offset Control
918	***************************************************************************/
919	/* HIF :: REG_PLL_FB_OFFSET0 :: OFFSET [07:00] */
920	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_MASK 0xff
921	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_ALIGN 0
922	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_BITS 8
923	#define HIF_REG_PLL_FB_OFFSET0_OFFSET_SHIFT 0
924
925	/***************************************************************************
926	*REG_PLL_SS_CTRL - System PLL Spread Spectrum Control
927	***************************************************************************/
928	/* HIF :: REG_PLL_SS_CTRL :: RSVD [07:01] */
929	#define HIF_REG_PLL_SS_CTRL_RSVD_MASK 0xfe
930	#define HIF_REG_PLL_SS_CTRL_RSVD_ALIGN 0
931	#define HIF_REG_PLL_SS_CTRL_RSVD_BITS 7
932	#define HIF_REG_PLL_SS_CTRL_RSVD_SHIFT 1
933
934	/* HIF :: REG_PLL_SS_CTRL :: EN [00:00] */
935	#define HIF_REG_PLL_SS_CTRL_EN_MASK 0x01
936	#define HIF_REG_PLL_SS_CTRL_EN_ALIGN 0
937	#define HIF_REG_PLL_SS_CTRL_EN_BITS 1
938	#define HIF_REG_PLL_SS_CTRL_EN_SHIFT 0
939
940	/***************************************************************************
941	*REG_PLL_SS_STEP1 - System PLL Spread Spectrum Step Size Control
942	***************************************************************************/
943	/* HIF :: REG_PLL_SS_STEP1 :: SIZE [07:00] */
944	#define HIF_REG_PLL_SS_STEP1_SIZE_MASK 0xff
945	#define HIF_REG_PLL_SS_STEP1_SIZE_ALIGN 0
946	#define HIF_REG_PLL_SS_STEP1_SIZE_BITS 8
947	#define HIF_REG_PLL_SS_STEP1_SIZE_SHIFT 0
948
949	/***************************************************************************
950	*REG_PLL_SS_STEP0 - System PLL Spread Spectrum Step Size Control
951	***************************************************************************/
952	/* HIF :: REG_PLL_SS_STEP0 :: SIZE [07:00] */
953	#define HIF_REG_PLL_SS_STEP0_SIZE_MASK 0xff
954	#define HIF_REG_PLL_SS_STEP0_SIZE_ALIGN 0
955	#define HIF_REG_PLL_SS_STEP0_SIZE_BITS 8
956	#define HIF_REG_PLL_SS_STEP0_SIZE_SHIFT 0
957
958	/***************************************************************************
959	*REG_PLL_SS_LIMIT3 - System PLL Spread Spectrum Limit Control
960	***************************************************************************/
961	/* HIF :: REG_PLL_SS_LIMIT3 :: RSVD [07:02] */
962	#define HIF_REG_PLL_SS_LIMIT3_RSVD_MASK 0xfc
963	#define HIF_REG_PLL_SS_LIMIT3_RSVD_ALIGN 0
964	#define HIF_REG_PLL_SS_LIMIT3_RSVD_BITS 6
965	#define HIF_REG_PLL_SS_LIMIT3_RSVD_SHIFT 2
966
967	/* HIF :: REG_PLL_SS_LIMIT3 :: LIMIT [01:00] */
968	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_MASK 0x03
969	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_ALIGN 0
970	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_BITS 2
971	#define HIF_REG_PLL_SS_LIMIT3_LIMIT_SHIFT 0
972
973	/***************************************************************************
974	*REG_PLL_SS_LIMIT2 - System PLL Spread Spectrum Limit Control
975	***************************************************************************/
976	/* HIF :: REG_PLL_SS_LIMIT2 :: LIMIT [07:00] */
977	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_MASK 0xff
978	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_ALIGN 0
979	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_BITS 8
980	#define HIF_REG_PLL_SS_LIMIT2_LIMIT_SHIFT 0
981
982	/***************************************************************************
983	*REG_PLL_SS_LIMIT1 - System PLL Spread Spectrum Limit Control
984	***************************************************************************/
985	/* HIF :: REG_PLL_SS_LIMIT1 :: LIMIT [07:00] */
986	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_MASK 0xff
987	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_ALIGN 0
988	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_BITS 8
989	#define HIF_REG_PLL_SS_LIMIT1_LIMIT_SHIFT 0
990
991	/***************************************************************************
992	*REG_PLL_SS_LIMIT0 - System PLL Spread Spectrum Limit Control
993	***************************************************************************/
994	/* HIF :: REG_PLL_SS_LIMIT0 :: LIMIT [07:00] */
995	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_MASK 0xff
996	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_ALIGN 0
997	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_BITS 8
998	#define HIF_REG_PLL_SS_LIMIT0_LIMIT_SHIFT 0
999
1000	/***************************************************************************
1001	*REG_PLL_MISC_CTRL1 - Register PLL Miscellaneous Control
1002	***************************************************************************/
1003	/* HIF :: REG_PLL_MISC_CTRL1 :: RSVD_1 [07:04] */
1004	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_MASK 0xf0
1005	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_ALIGN 0
1006	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_BITS 4
1007	#define HIF_REG_PLL_MISC_CTRL1_RSVD_1_SHIFT 4
1008
1009	/* HIF :: REG_PLL_MISC_CTRL1 :: RSVD_0 [03:02] */
1010	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_MASK 0x0c
1011	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_ALIGN 0
1012	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_BITS 2
1013	#define HIF_REG_PLL_MISC_CTRL1_RSVD_0_SHIFT 2
1014
1015	/* HIF :: REG_PLL_MISC_CTRL1 :: NDIV_RELOCK [01:01] */
1016	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_MASK 0x02
1017	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_ALIGN 0
1018	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_BITS 1
1019	#define HIF_REG_PLL_MISC_CTRL1_NDIV_RELOCK_SHIFT 1
1020
1021	/* HIF :: REG_PLL_MISC_CTRL1 :: FAST_LOCK [00:00] */
1022	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_MASK 0x01
1023	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_ALIGN 0
1024	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_BITS 1
1025	#define HIF_REG_PLL_MISC_CTRL1_FAST_LOCK_SHIFT 0
1026
1027	/***************************************************************************
1028	*REG_PLL_MISC_CTRL0 - Register PLL Miscellaneous Control
1029	***************************************************************************/
1030	/* HIF :: REG_PLL_MISC_CTRL0 :: PWM_RATE [07:06] */
1031	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_MASK 0xc0
1032	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_ALIGN 0
1033	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_BITS 2
1034	#define HIF_REG_PLL_MISC_CTRL0_PWM_RATE_SHIFT 6
1035
1036	/* HIF :: REG_PLL_MISC_CTRL0 :: VCO_DLY [05:04] */
1037	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_MASK 0x30
1038	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_ALIGN 0
1039	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_BITS 2
1040	#define HIF_REG_PLL_MISC_CTRL0_VCO_DLY_SHIFT 4
1041
1042	/* HIF :: REG_PLL_MISC_CTRL0 :: VCO_DIV2 [03:03] */
1043	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_MASK 0x08
1044	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_ALIGN 0
1045	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_BITS 1
1046	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_SHIFT 3
1047
1048	/* HIF :: REG_PLL_MISC_CTRL0 :: VCO_DIV2_POST [02:02] */
1049	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_MASK 0x04
1050	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_ALIGN 0
1051	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_BITS 1
1052	#define HIF_REG_PLL_MISC_CTRL0_VCO_DIV2_POST_SHIFT 2
1053
1054	/* HIF :: REG_PLL_MISC_CTRL0 :: AUX [01:01] */
1055	#define HIF_REG_PLL_MISC_CTRL0_AUX_MASK 0x02
1056	#define HIF_REG_PLL_MISC_CTRL0_AUX_ALIGN 0
1057	#define HIF_REG_PLL_MISC_CTRL0_AUX_BITS 1
1058	#define HIF_REG_PLL_MISC_CTRL0_AUX_SHIFT 1
1059
1060	/* HIF :: REG_PLL_MISC_CTRL0 :: EN_REF_OUT [00:00] */
1061	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_MASK 0x01
1062	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_ALIGN 0
1063	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_BITS 1
1064	#define HIF_REG_PLL_MISC_CTRL0_EN_REF_OUT_SHIFT 0
1065
1066	/***************************************************************************
1067	*REG_PLL_STAT_CTRL - Register PLL Status Control
1068	***************************************************************************/
1069	/* HIF :: REG_PLL_STAT_CTRL :: UPDATE [07:07] */
1070	#define HIF_REG_PLL_STAT_CTRL_UPDATE_MASK 0x80
1071	#define HIF_REG_PLL_STAT_CTRL_UPDATE_ALIGN 0
1072	#define HIF_REG_PLL_STAT_CTRL_UPDATE_BITS 1
1073	#define HIF_REG_PLL_STAT_CTRL_UPDATE_SHIFT 7
1074
1075	/* HIF :: REG_PLL_STAT_CTRL :: MODE [06:05] */
1076	#define HIF_REG_PLL_STAT_CTRL_MODE_MASK 0x60
1077	#define HIF_REG_PLL_STAT_CTRL_MODE_ALIGN 0
1078	#define HIF_REG_PLL_STAT_CTRL_MODE_BITS 2
1079	#define HIF_REG_PLL_STAT_CTRL_MODE_SHIFT 5
1080
1081	/* HIF :: REG_PLL_STAT_CTRL :: RST [04:04] */
1082	#define HIF_REG_PLL_STAT_CTRL_RST_MASK 0x10
1083	#define HIF_REG_PLL_STAT_CTRL_RST_ALIGN 0
1084	#define HIF_REG_PLL_STAT_CTRL_RST_BITS 1
1085	#define HIF_REG_PLL_STAT_CTRL_RST_SHIFT 4
1086
1087	/* HIF :: REG_PLL_STAT_CTRL :: RSVD [03:03] */
1088	#define HIF_REG_PLL_STAT_CTRL_RSVD_MASK 0x08
1089	#define HIF_REG_PLL_STAT_CTRL_RSVD_ALIGN 0
1090	#define HIF_REG_PLL_STAT_CTRL_RSVD_BITS 1
1091	#define HIF_REG_PLL_STAT_CTRL_RSVD_SHIFT 3
1092
1093	/* HIF :: REG_PLL_STAT_CTRL :: SEL [02:00] */
1094	#define HIF_REG_PLL_STAT_CTRL_SEL_MASK 0x07
1095	#define HIF_REG_PLL_STAT_CTRL_SEL_ALIGN 0
1096	#define HIF_REG_PLL_STAT_CTRL_SEL_BITS 3
1097	#define HIF_REG_PLL_STAT_CTRL_SEL_SHIFT 0
1098
1099	/***************************************************************************
1100	*REG_PLL_STATUS2 - Register PLL Status
1101	***************************************************************************/
1102	/* HIF :: REG_PLL_STATUS2 :: RSVD_0 [07:01] */
1103	#define HIF_REG_PLL_STATUS2_RSVD_0_MASK 0xfe
1104	#define HIF_REG_PLL_STATUS2_RSVD_0_ALIGN 0
1105	#define HIF_REG_PLL_STATUS2_RSVD_0_BITS 7
1106	#define HIF_REG_PLL_STATUS2_RSVD_0_SHIFT 1
1107
1108	/* HIF :: REG_PLL_STATUS2 :: LOCK [00:00] */
1109	#define HIF_REG_PLL_STATUS2_LOCK_MASK 0x01
1110	#define HIF_REG_PLL_STATUS2_LOCK_ALIGN 0
1111	#define HIF_REG_PLL_STATUS2_LOCK_BITS 1
1112	#define HIF_REG_PLL_STATUS2_LOCK_SHIFT 0
1113
1114	/***************************************************************************
1115	*REG_PLL_STATUS1 - Register PLL Status
1116	***************************************************************************/
1117	/* HIF :: REG_PLL_STATUS1 :: RSVD_0 [07:04] */
1118	#define HIF_REG_PLL_STATUS1_RSVD_0_MASK 0xf0
1119	#define HIF_REG_PLL_STATUS1_RSVD_0_ALIGN 0
1120	#define HIF_REG_PLL_STATUS1_RSVD_0_BITS 4
1121	#define HIF_REG_PLL_STATUS1_RSVD_0_SHIFT 4
1122
1123	/* HIF :: REG_PLL_STATUS1 :: STAT_OUT [03:00] */
1124	#define HIF_REG_PLL_STATUS1_STAT_OUT_MASK 0x0f
1125	#define HIF_REG_PLL_STATUS1_STAT_OUT_ALIGN 0
1126	#define HIF_REG_PLL_STATUS1_STAT_OUT_BITS 4
1127	#define HIF_REG_PLL_STATUS1_STAT_OUT_SHIFT 0
1128
1129	/***************************************************************************
1130	*REG_PLL_STATUS0 - Register PLL Status
1131	***************************************************************************/
1132	/* HIF :: REG_PLL_STATUS0 :: STAT_OUT [07:00] */
1133	#define HIF_REG_PLL_STATUS0_STAT_OUT_MASK 0xff
1134	#define HIF_REG_PLL_STATUS0_STAT_OUT_ALIGN 0
1135	#define HIF_REG_PLL_STATUS0_STAT_OUT_BITS 8
1136	#define HIF_REG_PLL_STATUS0_STAT_OUT_SHIFT 0
1137
1138	/***************************************************************************
1139	*REG_CLK_EN - Register Clock Enable
1140	***************************************************************************/
1141	/* HIF :: REG_CLK_EN :: RSVD [07:02] */
1142	#define HIF_REG_CLK_EN_RSVD_MASK 0xfc
1143	#define HIF_REG_CLK_EN_RSVD_ALIGN 0
1144	#define HIF_REG_CLK_EN_RSVD_BITS 6
1145	#define HIF_REG_CLK_EN_RSVD_SHIFT 2
1146
1147	/* HIF :: REG_CLK_EN :: PERIPH [01:01] */
1148	#define HIF_REG_CLK_EN_PERIPH_MASK 0x02
1149	#define HIF_REG_CLK_EN_PERIPH_ALIGN 0
1150	#define HIF_REG_CLK_EN_PERIPH_BITS 1
1151	#define HIF_REG_CLK_EN_PERIPH_SHIFT 1
1152
1153	/* HIF :: REG_CLK_EN :: LEAP [00:00] */
1154	#define HIF_REG_CLK_EN_LEAP_MASK 0x01
1155	#define HIF_REG_CLK_EN_LEAP_ALIGN 0
1156	#define HIF_REG_CLK_EN_LEAP_BITS 1
1157	#define HIF_REG_CLK_EN_LEAP_SHIFT 0
1158
1159	/***************************************************************************
1160	*SYS_CLK_EN - System Clock Enable
1161	***************************************************************************/
1162	/* HIF :: SYS_CLK_EN :: RSVD [07:01] */
1163	#define HIF_SYS_CLK_EN_RSVD_MASK 0xfe
1164	#define HIF_SYS_CLK_EN_RSVD_ALIGN 0
1165	#define HIF_SYS_CLK_EN_RSVD_BITS 7
1166	#define HIF_SYS_CLK_EN_RSVD_SHIFT 1
1167
1168	/* HIF :: SYS_CLK_EN :: LEAP [00:00] */
1169	#define HIF_SYS_CLK_EN_LEAP_MASK 0x01
1170	#define HIF_SYS_CLK_EN_LEAP_ALIGN 0
1171	#define HIF_SYS_CLK_EN_LEAP_BITS 1
1172	#define HIF_SYS_CLK_EN_LEAP_SHIFT 0
1173
1174	/***************************************************************************
1175	*MISC_CTRL - Miscellaneous Control
1176	***************************************************************************/
1177	/* HIF :: MISC_CTRL :: RSVD [07:03] */
1178	#define HIF_MISC_CTRL_RSVD_MASK 0xf8
1179	#define HIF_MISC_CTRL_RSVD_ALIGN 0
1180	#define HIF_MISC_CTRL_RSVD_BITS 5
1181	#define HIF_MISC_CTRL_RSVD_SHIFT 3
1182
1183	/* HIF :: MISC_CTRL :: OSC_CML_CTRL_SRC [02:02] */
1184	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_MASK 0x04
1185	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_ALIGN 0
1186	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_BITS 1
1187	#define HIF_MISC_CTRL_OSC_CML_CTRL_SRC_SHIFT 2
1188
1189	/* HIF :: MISC_CTRL :: RBUS_CLK_SRC [01:01] */
1190	#define HIF_MISC_CTRL_RBUS_CLK_SRC_MASK 0x02
1191	#define HIF_MISC_CTRL_RBUS_CLK_SRC_ALIGN 0
1192	#define HIF_MISC_CTRL_RBUS_CLK_SRC_BITS 1
1193	#define HIF_MISC_CTRL_RBUS_CLK_SRC_SHIFT 1
1194
1195	/* HIF :: MISC_CTRL :: REG_PLL_STAT_CTRL_SRC [00:00] */
1196	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_MASK 0x01
1197	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_ALIGN 0
1198	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_BITS 1
1199	#define HIF_MISC_CTRL_REG_PLL_STAT_CTRL_SRC_SHIFT 0
1200
1201	/***************************************************************************
1202	*SPARE3 - Spare Register
1203	***************************************************************************/
1204	/* HIF :: SPARE3 :: SPARE [07:00] */
1205	#define HIF_SPARE3_SPARE_MASK 0xff
1206	#define HIF_SPARE3_SPARE_ALIGN 0
1207	#define HIF_SPARE3_SPARE_BITS 8
1208	#define HIF_SPARE3_SPARE_SHIFT 0
1209
1210	/***************************************************************************
1211	*SPARE2 - Spare Register
1212	***************************************************************************/
1213	/* HIF :: SPARE2 :: SPARE [07:00] */
1214	#define HIF_SPARE2_SPARE_MASK 0xff
1215	#define HIF_SPARE2_SPARE_ALIGN 0
1216	#define HIF_SPARE2_SPARE_BITS 8
1217	#define HIF_SPARE2_SPARE_SHIFT 0
1218
1219	/***************************************************************************
1220	*SPARE1 - Spare Register
1221	***************************************************************************/
1222	/* HIF :: SPARE1 :: SPARE [07:00] */
1223	#define HIF_SPARE1_SPARE_MASK 0xff
1224	#define HIF_SPARE1_SPARE_ALIGN 0
1225	#define HIF_SPARE1_SPARE_BITS 8
1226	#define HIF_SPARE1_SPARE_SHIFT 0
1227
1228	/***************************************************************************
1229	*SPARE0 - Spare Register
1230	***************************************************************************/
1231	/* HIF :: SPARE0 :: SPARE [07:00] */
1232	#define HIF_SPARE0_SPARE_MASK 0xff
1233	#define HIF_SPARE0_SPARE_ALIGN 0
1234	#define HIF_SPARE0_SPARE_BITS 8
1235	#define HIF_SPARE0_SPARE_SHIFT 0
1236
1237	/***************************************************************************
1238	*SFT3 - Software Register
1239	***************************************************************************/
1240	/* HIF :: SFT3 :: SFT [07:00] */
1241	#define HIF_SFT3_SFT_MASK 0xff
1242	#define HIF_SFT3_SFT_ALIGN 0
1243	#define HIF_SFT3_SFT_BITS 8
1244	#define HIF_SFT3_SFT_SHIFT 0
1245
1246	/***************************************************************************
1247	*SFT2 - Software Register
1248	***************************************************************************/
1249	/* HIF :: SFT2 :: SFT [07:00] */
1250	#define HIF_SFT2_SFT_MASK 0xff
1251	#define HIF_SFT2_SFT_ALIGN 0
1252	#define HIF_SFT2_SFT_BITS 8
1253	#define HIF_SFT2_SFT_SHIFT 0
1254
1255	/***************************************************************************
1256	*SFT1 - Software Register
1257	***************************************************************************/
1258	/* HIF :: SFT1 :: SFT [07:00] */
1259	#define HIF_SFT1_SFT_MASK 0xff
1260	#define HIF_SFT1_SFT_ALIGN 0
1261	#define HIF_SFT1_SFT_BITS 8
1262	#define HIF_SFT1_SFT_SHIFT 0
1263
1264	/***************************************************************************
1265	*SFT0 - Software Register
1266	***************************************************************************/
1267	/* HIF :: SFT0 :: SFT [07:00] */
1268	#define HIF_SFT0_SFT_MASK 0xff
1269	#define HIF_SFT0_SFT_ALIGN 0
1270	#define HIF_SFT0_SFT_BITS 8
1271	#define HIF_SFT0_SFT_SHIFT 0
1272
1273	#endif /* #ifndef HOST_SERIAL_INTERFACE_H__ */
1274
1275	/* End of File */

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source: svn/trunk/newcon3bcm2_21bu/magnum/basemodules/hab/3128/bhab_3128_bbsi.h

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