/*************************************************************************** * Copyright (c) 2003-2012, Broadcom Corporation * All Rights Reserved * Confidential Property of Broadcom Corporation * * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. * * $brcm_Workfile: breg_mem.c $ * $brcm_Revision: Hydra_Software_Devel/86 $ * $brcm_Date: 3/14/12 5:38p $ * * Module Description: * * Revision History: * * $brcm_Log: R:/views/refsw_latest_97468/magnum/basemodules/reg/breg_mem.c $ * * Hydra_Software_Devel/86 3/14/12 5:38p jtna * SW7468-401: add 7468 atomic registers * * Hydra_Software_Devel/85 3/14/12 2:45p xhuang * SW7552-220: Add RFM atom register * * Hydra_Software_Devel/84 3/9/12 4:48p erickson * SW7231-705: add BDBG_OBJECT_ASSERT * * Hydra_Software_Devel/83 2/29/12 12:24p mward * SW7435-7: Update atomic list for 7435 * * Hydra_Software_Devel/82 2/23/12 4:47p jrubio * SW7344-104: update atomic list for 7346 * * Hydra_Software_Devel/81 2/13/12 4:14p randyjew * SW7344-104: Update atomic register list for 7344 * * Hydra_Software_Devel/80 2/2/12 5:14p jrubio * SW7344-104: add more 7346 atomic registers * * Hydra_Software_Devel/79 1/26/12 11:56a katrep * SW7429-1:fixed run time warning messages * * Hydra_Software_Devel/78 1/13/12 1:25p xhuang * SW7552-191: Add one more register to atom table * * Hydra_Software_Devel/77 12/13/11 12:01p mward * SW7125-1180: Add BCHP_SMARTCARD_PLL_SC_MACRO and * BCHP_VCXO_CTL_MISC_VC0_CTRL to the atomic update list. * * Hydra_Software_Devel/76 11/17/11 2:42p jessem * SW7425-1596: Updated atomic register check list for 7425B0. * * Hydra_Software_Devel/75 11/3/11 5:00p katrep * SW7231-317:add atmic regs for 7231B0 * * Hydra_Software_Devel/74 10/27/11 12:25p jessem * SW7425-1097: Added CLKGEN_PM_CLOCK_216_ALIVE_SEL to check atomic * register list. * * Hydra_Software_Devel/73 10/27/11 11:54a jessem * SW7425-1097: Added CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO and * CLKGEN_PM_PLL_ALIVE_SEL to check atomic register list. * * Hydra_Software_Devel/72 10/27/11 2:06p xhuang * SW7552-9: Add 7552 power management support * * Hydra_Software_Devel/71 10/20/11 3:42p bselva * SW7358-169: Changes added for power management support * * Hydra_Software_Devel/70 8/29/11 11:35a jrubio * SW7346-470: add 7346 B0 support * * Hydra_Software_Devel/69 8/24/11 3:41p jessem * SW7425-533: Added BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY and * BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY to atomic register access * list. * * Hydra_Software_Devel/68 8/16/11 3:10p jessem * SW7425-1097: Added B0 support. * * Hydra_Software_Devel/67 8/15/11 10:26a randyjew * SW7344-149: Add 7344 B0 support * * Hydra_Software_Devel/66 8/11/11 3:28p katrep * SW7231-317:add 7231B0 support * * Hydra_Software_Devel/65 7/26/11 4:28p gmohile * SW7425-533 : Add atomic access reg * * Hydra_Software_Devel/64 6/22/11 6:42p randyjew * SW7344-104:Add atomic access registers for 7344/7346 * * Hydra_Software_Devel/63 6/17/11 11:18a gmohile * SWDTV-7435 : Add atomic access registers for 35233 * * Hydra_Software_Devel/62 6/16/11 5:34p nickh * SW7425-533: Add atomic access registers * * Hydra_Software_Devel/61 6/13/11 10:28a randyjew * SW7468-6: Update Atomic update list * * Hydra_Software_Devel/60 6/2/11 1:55p gmohile * SW7231-128 : Update atomic update list * * Hydra_Software_Devel/59 5/12/11 1:39p gmohile * SW7231-128 : Update 7231 register list for atomic access * * Hydra_Software_Devel/58 4/13/11 12:09p mward * SW7125-905: Add atomic access registers. * * Hydra_Software_Devel/57 3/14/11 10:50a randyjew * SW7468-6: Update list of atomic update registers for 7468 * * Hydra_Software_Devel/56 3/11/11 5:40p jtna * SW7420-1628: add BCHP_CLK_SYS_PLL_0_PLL_3 to list * * Hydra_Software_Devel/55 3/2/11 4:35p gmohile * SW7408-190 : Update list of atomic update registers for 7408 * * Hydra_Software_Devel/54 2/17/11 5:20p nitinb * SW7572-297: Added BCHP_CLK_MISC_CLK_SEL to atomic register list of 7550 * * Hydra_Software_Devel/53 1/17/11 3:31p gmohile * SW7408-190 : Add CLK_PM_CTRL as atomic access * * Hydra_Software_Devel/52 12/6/10 4:50p gmohile * SW7408-190 : Add list of atomic reg for 7408 * * Hydra_Software_Devel/51 12/2/10 4:54p gmohile * SW7408-147 : Add atomic access registers for 7408 * * Hydra_Software_Devel/50 11/24/10 2:35p nickh * SW7422-12: Remove PFRI and STRIPE registers from atomic register list * * Hydra_Software_Devel/49 11/10/10 7:28p shyi * SW35230-1755: Added atomic access registers for 35230 * * Hydra_Software_Devel/48 11/9/10 1:35p nickh * SW7422-12: add BCHP_SUN_TOP_CTRL_SW_RESET defines back in * * Hydra_Software_Devel/47 11/9/10 1:29p nickh * SW7422-12: SW_INIT register doesn't require Atomic access * * Hydra_Software_Devel/46 8/24/10 8:33a erickson * SW3548-815: allow BREG_Read/Write to be used inside a * BREG_AtomicUpdate32 callback without warning. this avoids the need for * the app to create a second method of accessing registers. * * Hydra_Software_Devel/45 8/17/10 6:33p nickh * SW7422-12: Add support for 7422 * * Hydra_Software_Devel/44 8/17/10 5:52p mward * SW7125-237: BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6 s/b on atomic list * for >= c0, not MaxRegOffset = MaxRegOffset; #else BSTD_UNUSED(MaxRegOffset); #endif (*pRegHandle)->BaseAddr = (uint32_t)Address; (*pRegHandle)->inAtomicUpdateCallback = false; /* set default callback */ BREG_SetAtomicUpdate32Callback( *pRegHandle, NULL, NULL ); } void BREG_Close( BREG_Handle RegHandle ) { BDBG_OBJECT_ASSERT(RegHandle, BREG); BDBG_OBJECT_DESTROY(RegHandle, BREG); BKNI_Free(RegHandle); } /* compile the register access functions even for the release build */ #undef BREG_Write32 #undef BREG_Write16 #undef BREG_Write8 #undef BREG_Read32 #undef BREG_Read16 #undef BREG_Read8 #if BDBG_DEBUG_BUILD #include "bchp_sun_top_ctrl.h" /** BREG_P_CheckAtomicRegister is a development-time debug function. It's purpose is to warn the developer that a non-atomic read/modify/write is being done on a register that requires BREG_AtomicUpdate32 access. If you see a warning, you should modify the code to use BREG_AtomicUpdate32 or BREG_AtomicUpdate32_isr. See BREG_AtomicUpdate32 and BREG_SetAtomicUpdate32Callback in breg_mem.h for more information on atomic access. **/ #define BREG_P_ATOMIC_REG(reg) case reg: name=#reg;regAtomic=true;break static void BREG_P_CheckAtomicRegister(BREG_Handle regHandle, uint32_t reg, const char *function, bool atomic ) { const char *name; bool regAtomic; /* the atomic update callback can turn around and use normal BREG_Read/Write calls without having any violation. this allows the layer above to not invent a second way of doing register access. */ if (regHandle->inAtomicUpdateCallback) { return; } switch(reg) { #ifdef BCHP_SUN_TOP_CTRL_SW_RESET BREG_P_ATOMIC_REG(BCHP_SUN_TOP_CTRL_SW_RESET); #endif #if (BCHP_CHIP==7405) #include "bchp_decode_sd_0.h" #include "bchp_decode_ip_shim_0.h" #include "bchp_clk.h" #include "bchp_vcxo_ctl_misc.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2); BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_AVD_CTRL); #elif (BCHP_CHIP==7400) #include "bchp_clk.h" BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2); #elif (BCHP_CHIP==3556 || BCHP_CHIP==3548) #include "bchp_decode_sd_0.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH); #include "bchp_clkgen.h" BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_3); #include "bchp_vcxo_ctl_misc.h" BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_AVD_CTRL); #elif ( BCHP_CHIP==7335 ) #include "bchp_clk.h" #include "bchp_decode_sd_0.h" #include "bchp_decode_ip_shim_0.h" #include "bchp_vcxo_ctl_misc.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1); BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2); BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_AVD_CTRL); #elif (BCHP_CHIP==7325 ) #include "bchp_clkgen.h" #include "bchp_decode_sd_0.h" #include "bchp_decode_ip_shim_0.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_3); BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD_CTRL); #elif (BCHP_CHIP==7340 ) #include "bchp_clkgen.h" #include "bchp_decode_sd_0.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH); #if (BCHP_VER==BCHP_VER_A0) BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_216_108_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_216_108_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_MISC_CLOCKS); #endif #elif (BCHP_CHIP==7342 ) #include "bchp_clk.h" #include "bchp_decode_sd_0.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH); #elif (BCHP_CHIP==7125 ) #include "bchp_clkgen.h" #include "bchp_decode_sd_0.h" #include "bchp_decode_ip_shim_0.h" #include "bchp_vcxo_ctl_misc.h" #include "bchp_smartcard_pll.h" BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH); BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL); #if (BCHP_VER= BCHP_VER_B0) BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_LDO_POWERUP); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PAD_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY); #elif (BCHP_CHIP==7435) #include "bchp_clkgen.h" BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_LDO_POWERUP); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_PAD_CLOCK_DISABLE); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0); #if 0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY); #elif (BCHP_CHIP==7552) #include "bchp_clkgen.h" BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3); BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE); #elif (BCHP_CHIP==7344) #include "bchp_clkgen.h" BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN ); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE); #if BCHP_VER == BCHP_VER_A0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_A); #else BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY); #if BCHP_VER == BCHP_VER_A0 BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE); #else BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA); #endif BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY); #elif (BCHP_CHIP==7346) #include "bchp_clkgen.h" BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN ); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_MIPS_PLL_DIV); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY); #elif (BCHP_CHIP==7358) #include "bchp_clkgen.h" BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3); BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET); BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN); #endif default: name = ""; regAtomic = false; break; } if(regAtomic!=atomic) { if(!atomic) { BDBG_ERR(("%s: register %s(%#lx) should only be used with atomic access", function, name, (unsigned long)reg)); } else { BDBG_ERR(("%s: register %#lx shouldn't be used for atomic access", function, (unsigned long)reg)); } } } #else #define BREG_P_CheckAtomicRegister(regHandle, reg, function, atomic) #endif uint32_t BREG_Read32(BREG_Handle RegHandle, uint32_t reg) { /* BDBG_OBJECT_ASSERT(RegHandle, BREG); */ BDBG_ASSERT(reg < RegHandle->MaxRegOffset); return *((volatile uint32_t *)(RegHandle->BaseAddr+reg)); } uint16_t BREG_Read16(BREG_Handle RegHandle, uint32_t reg) { BDBG_ASSERT(reg < RegHandle->MaxRegOffset); return *((volatile uint16_t *)(RegHandle->BaseAddr+reg)); } uint8_t BREG_Read8(BREG_Handle RegHandle, uint32_t reg) { BDBG_ASSERT(reg < RegHandle->MaxRegOffset); return *((volatile uint8_t *)(RegHandle->BaseAddr+reg)); } #if BREG_CAPTURE /* BREG_CAPTURE is a hook to capture all register writes from magnum. It is used by the splashgen utility. The feature should not be enabled for a production system. */ extern void APP_BREG_Write32(BREG_Handle RegHandle, uint32_t reg, uint32_t data); #endif void BREG_Write32(BREG_Handle RegHandle, uint32_t reg, uint32_t data) { /* BDBG_OBJECT_ASSERT(RegHandle, BREG); */ BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_Write32", false); #if BREG_CAPTURE { static int warning_count = 0; if (warning_count < 5) { warning_count++; BDBG_WRN(("You are running with BREG_CAPTURE defined. This utility mode is used for running the register capture utility, not production code.")); } } APP_BREG_Write32(RegHandle, reg, data) ; #endif *((volatile uint32_t *)(RegHandle->BaseAddr+reg)) = data; } void BREG_Write16(BREG_Handle RegHandle, uint32_t reg, uint16_t data) { BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_Write16", false); *((volatile uint16_t *)(RegHandle->BaseAddr+reg)) = data; } void BREG_Write8(BREG_Handle RegHandle, uint32_t reg, uint8_t data) { BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_Write8", false); *((volatile uint8_t *)(RegHandle->BaseAddr+reg)) = data; } static void BREG_P_AtomicUpdate32_Impl_isr(void *context, uint32_t addr, uint32_t mask, uint32_t value) { uint32_t temp; BREG_Handle RegHandle = context; BDBG_OBJECT_ASSERT(RegHandle, BREG); addr = RegHandle->BaseAddr + addr; temp = *(volatile uint32_t *)addr; temp = (temp&~mask)|value; *(volatile uint32_t *)addr = temp; return; } void BREG_AtomicUpdate32_isr(BREG_Handle RegHandle, uint32_t reg, uint32_t mask, uint32_t value) { BDBG_OBJECT_ASSERT(RegHandle, BREG); BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_AtomicUpdate32_isr", true); RegHandle->inAtomicUpdateCallback = true; (*RegHandle->atomicUpdate32.callback_isr)(RegHandle->atomicUpdate32.callbackContext, reg, mask, value); RegHandle->inAtomicUpdateCallback = false; #if BREG_CAPTURE APP_BREG_Write32(RegHandle,reg,BREG_Read32(RegHandle,reg)); #endif } void BREG_AtomicUpdate32(BREG_Handle RegHandle, uint32_t reg, uint32_t mask, uint32_t value ) { BDBG_OBJECT_ASSERT(RegHandle, BREG); BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_AtomicUpdate32", true); BKNI_EnterCriticalSection(); RegHandle->inAtomicUpdateCallback = true; (*RegHandle->atomicUpdate32.callback_isr)(RegHandle->atomicUpdate32.callbackContext, reg, mask, value); RegHandle->inAtomicUpdateCallback = false; #if BREG_CAPTURE APP_BREG_Write32(RegHandle,reg,BREG_Read32(RegHandle,reg)); #endif BKNI_LeaveCriticalSection(); } static uint32_t BREG_P_CompareAndSwap32_Impl_isr(uint32_t addr, uint32_t oldValue, uint32_t newValue) { uint32_t result = *(volatile uint32_t *)addr; if(result == oldValue) { *(volatile uint32_t *)addr = newValue; } return result; } uint32_t BREG_CompareAndSwap32(BREG_Handle RegHandle, uint32_t reg, uint32_t oldValue, uint32_t newValue ) { uint32_t result; BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_CompareAndSwap32", true); BKNI_EnterCriticalSection(); result = BREG_P_CompareAndSwap32_Impl_isr(RegHandle->BaseAddr+reg, oldValue, newValue); BKNI_LeaveCriticalSection(); return result; } uint32_t BREG_CompareAndSwap32_isr(BREG_Handle RegHandle, uint32_t reg, uint32_t oldValue, uint32_t newValue ) { uint32_t result; BDBG_ASSERT(reg < RegHandle->MaxRegOffset); BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_CompareAndSwap32_isr", true); result = BREG_P_CompareAndSwap32_Impl_isr(RegHandle->BaseAddr+reg, oldValue, newValue); return result; } void BREG_SetAtomicUpdate32Callback( BREG_Handle RegHandle, BREG_AtomicUpdate32Callback callback_isr, void *callbackContext ) { BDBG_OBJECT_ASSERT(RegHandle, BREG); BKNI_EnterCriticalSection(); if (callback_isr) { RegHandle->atomicUpdate32.callback_isr = callback_isr; RegHandle->atomicUpdate32.callbackContext = callbackContext; } else { /* restore default */ RegHandle->atomicUpdate32.callback_isr = BREG_P_AtomicUpdate32_Impl_isr; RegHandle->atomicUpdate32.callbackContext = RegHandle; } BKNI_LeaveCriticalSection(); } /* End of File */