| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2005-2009, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: brdc_blockout_priv.c $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/6 $ |
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| 12 | * $brcm_Date: 6/9/09 6:21p $ |
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| 13 | * |
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| 14 | * Module Description: |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /magnum/commonutils/rdc/7038/brdc_blockout_priv.c $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/6 6/9/09 6:21p pntruong |
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| 21 | * PR55861: Added support for hw blockout and timestamp. |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/5 3/24/09 5:28p albertl |
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| 24 | * PR52513: Moved RDC debug globals into hList structure. |
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| 25 | * |
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| 26 | * Hydra_Software_Devel/4 7/9/08 10:32a jessem |
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| 27 | * PR 44647: Corrected bounds check on ulRegBlock parameter in |
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| 28 | * BRDC_P_ValidateBlockOutRegisters. |
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| 29 | * |
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| 30 | * Hydra_Software_Devel/3 3/5/08 10:53a jessem |
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| 31 | * PR 38623: Removed stdio.h and errno.h. |
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| 32 | * |
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| 33 | * Hydra_Software_Devel/2 2/28/08 5:55p jessem |
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| 34 | * PR 38623: Changed register validation to support 3563 only. |
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| 35 | * |
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| 36 | * Hydra_Software_Devel/1 2/28/08 5:46p jessem |
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| 37 | * PR 38623: Initial version |
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| 38 | * |
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| 39 | ***************************************************************************/ |
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| 40 | #include "bstd.h" |
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| 41 | #include "bdbg.h" |
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| 42 | #include "bkni.h" |
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| 43 | |
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| 44 | #include "bchp_common.h" |
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| 45 | #include "brdc.h" |
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| 46 | #include "brdc_dbg.h" |
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| 47 | #include "brdc_private.h" |
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| 48 | #include "brdc_blockout_priv.h" |
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| 49 | |
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| 50 | BDBG_MODULE(BRDC_BLOCKOUT); |
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| 51 | |
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| 52 | typedef struct |
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| 53 | { |
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| 54 | uint32_t ulOpcode; |
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| 55 | uint32_t ulReadSize; |
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| 56 | uint32_t ulWriteSize; |
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| 57 | uint32_t ulArg; |
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| 58 | uint32_t ulNumImmData; |
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| 59 | uint32_t ulSrcReg; |
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| 60 | uint32_t ulDstReg; |
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| 61 | } BRDC_RulEntry; |
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| 62 | |
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| 63 | typedef struct |
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| 64 | { |
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| 65 | uint32_t ulReg2BlockOutStart; |
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| 66 | uint32_t ulReg2BlockOutEnd; |
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| 67 | } BRDC_Reg2BlockOut; |
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| 68 | |
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| 69 | /* Checks if register block is to blocked out andif so return start and end registers that are blocked. */ |
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| 70 | static bool BRDC_P_CheckAndGetBlockOutRegs |
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| 71 | ( BRDC_Handle hRdc, |
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| 72 | uint32_t ulRegister, |
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| 73 | uint32_t ulBlockSize, |
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| 74 | BRDC_Reg2BlockOut *pstReg2BlockOut, |
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| 75 | uint32_t *pNumRegRangesBlocked ) |
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| 76 | { |
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| 77 | uint32_t i, j; |
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| 78 | bool bGotStart = false, bGotEnd = false; |
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| 79 | bool bBlockOut = false; |
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| 80 | uint32_t ulReg2CheckStart; |
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| 81 | uint32_t ulReg2CheckEnd; |
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| 82 | BRDC_BlockOut *pstRegBlockOutList = hRdc->astBlockOut; |
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| 83 | |
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| 84 | *pNumRegRangesBlocked = 0; |
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| 85 | |
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| 86 | for (i=0; i<BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT; i++) |
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| 87 | { |
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| 88 | uint32_t ulRegBlockOutListStart, ulRegBlockOutListEnd; |
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| 89 | bGotStart = bGotEnd = false; |
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| 90 | |
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| 91 | if (pstRegBlockOutList[i].bEnable) |
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| 92 | { |
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| 93 | ulRegBlockOutListStart = pstRegBlockOutList[i].ulStartRegAddr; |
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| 94 | ulRegBlockOutListEnd = pstRegBlockOutList[i].ulStartRegAddr + |
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| 95 | ((pstRegBlockOutList[i].ulBlockSize-1) * sizeof(uint32_t)); |
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| 96 | |
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| 97 | ulReg2CheckStart = ulRegister; |
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| 98 | ulReg2CheckEnd = ulRegister + ((ulBlockSize-1) * sizeof(uint32_t)); |
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| 99 | |
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| 100 | for (j=0; j<ulBlockSize; j++) |
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| 101 | { |
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| 102 | if ((ulReg2CheckStart >= ulRegBlockOutListStart) && |
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| 103 | (ulReg2CheckStart <= ulRegBlockOutListEnd)) |
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| 104 | { |
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| 105 | if (!bGotStart) |
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| 106 | { |
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| 107 | bGotStart = true; |
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| 108 | pstReg2BlockOut[*pNumRegRangesBlocked].ulReg2BlockOutStart = |
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| 109 | (ulReg2CheckStart <= ulRegBlockOutListStart) ? ulRegBlockOutListStart : ulReg2CheckStart; |
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| 110 | } |
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| 111 | } |
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| 112 | |
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| 113 | if (!bGotEnd && bGotStart) |
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| 114 | { |
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| 115 | bGotEnd = bBlockOut = true; |
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| 116 | pstReg2BlockOut[*pNumRegRangesBlocked].ulReg2BlockOutEnd = |
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| 117 | (ulReg2CheckEnd < ulRegBlockOutListEnd) ? ulReg2CheckEnd : ulRegBlockOutListEnd; |
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| 118 | (*pNumRegRangesBlocked)++; |
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| 119 | break; |
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| 120 | } |
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| 121 | |
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| 122 | ulReg2CheckStart += sizeof(uint32_t); |
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| 123 | |
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| 124 | if (bBlockOut) |
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| 125 | { |
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| 126 | BDBG_MSG(("Register block 0x%x to 0x%x blocked", |
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| 127 | pstReg2BlockOut[*pNumRegRangesBlocked].ulReg2BlockOutStart, |
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| 128 | pstReg2BlockOut[*pNumRegRangesBlocked].ulReg2BlockOutEnd)); |
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| 129 | } |
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| 130 | } |
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| 131 | } |
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| 132 | } |
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| 133 | |
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| 134 | if (!bBlockOut) |
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| 135 | { |
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| 136 | BDBG_MSG(("Reg block 0x%x to 0x%x not blocked", ulRegister, |
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| 137 | ulRegister + (ulBlockSize - 1) * 4)); |
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| 138 | } |
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| 139 | |
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| 140 | return bBlockOut; |
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| 141 | } |
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| 142 | |
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| 143 | |
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| 144 | static bool BRDC_P_PopulateRevisedRul_isr |
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| 145 | ( BRDC_Handle hRdc, |
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| 146 | BRDC_List_Handle hList, |
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| 147 | uint32_t **pulOrigRulAddr, |
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| 148 | uint32_t **pulRevisedRulAddr, |
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| 149 | BRDC_RulEntry *pstRulEntry ) |
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| 150 | { |
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| 151 | uint32_t ulOpcode; |
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| 152 | uint32_t i; |
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| 153 | BRDC_DBG_ListEntry eEntry; |
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| 154 | uint32_t aulArgs[4]; |
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| 155 | bool bBlockOut; |
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| 156 | uint32_t ulNumRegRangesBlocked; |
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| 157 | |
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| 158 | BRDC_Reg2BlockOut astReg2BlockOut[BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT]; |
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| 159 | |
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| 160 | BKNI_Memset((void *)astReg2BlockOut, 0x0, |
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| 161 | sizeof(BRDC_Reg2BlockOut) * BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT); |
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| 162 | |
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| 163 | /* check if RUL has blocked out registers */ |
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| 164 | bBlockOut = BRDC_P_CheckAndGetBlockOutRegs(hRdc, |
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| 165 | pstRulEntry->ulDstReg, pstRulEntry->ulWriteSize, |
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| 166 | astReg2BlockOut, &ulNumRegRangesBlocked); |
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| 167 | |
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| 168 | if (bBlockOut) |
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| 169 | { |
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| 170 | uint32_t ulWriteSize = 0; |
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| 171 | uint32_t ulDstReg = pstRulEntry->ulDstReg; |
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| 172 | uint32_t ulSrcReg = pstRulEntry->ulSrcReg; |
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| 173 | uint32_t ulNumImmData; |
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| 174 | |
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| 175 | if ((pstRulEntry->ulOpcode == BRDC_OP_IMMS_TO_REGS_OPCODE) || |
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| 176 | (pstRulEntry->ulOpcode == BRDC_OP_REGS_TO_REGS_OPCODE) || |
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| 177 | (pstRulEntry->ulOpcode == BRDC_OP_REG_TO_REGS_OPCODE)) |
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| 178 | { |
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| 179 | for (i=0; i<ulNumRegRangesBlocked; i++) |
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| 180 | { |
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| 181 | /* get write size */ |
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| 182 | ulWriteSize = (astReg2BlockOut[i].ulReg2BlockOutStart - ulDstReg) / sizeof(uint32_t); |
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| 183 | |
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| 184 | /* Check if the RUL is completely inside a blocked out range. If so, exclude it. */ |
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| 185 | if (ulWriteSize > 0) |
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| 186 | { |
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| 187 | ulOpcode = pstRulEntry->ulOpcode | ((ulWriteSize & UINT32_C(0xFFF)) - 1); |
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| 188 | *(*pulRevisedRulAddr) = ulOpcode; |
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| 189 | (*pulRevisedRulAddr)++; |
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| 190 | |
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| 191 | if ((pstRulEntry->ulOpcode == BRDC_OP_REGS_TO_REGS_OPCODE) || |
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| 192 | (pstRulEntry->ulOpcode == BRDC_OP_REG_TO_REGS_OPCODE)) |
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| 193 | { |
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| 194 | *(*pulRevisedRulAddr) = BRDC_REGISTER(ulSrcReg); |
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| 195 | (*pulRevisedRulAddr)++; |
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| 196 | } |
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| 197 | |
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| 198 | *(*pulRevisedRulAddr) = BRDC_REGISTER(ulDstReg); |
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| 199 | (*pulRevisedRulAddr)++; |
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| 200 | } |
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| 201 | |
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| 202 | if (pstRulEntry->ulOpcode == BRDC_OP_IMMS_TO_REGS_OPCODE) |
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| 203 | { |
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| 204 | uint32_t j; |
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| 205 | |
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| 206 | /* The number of imm data includes the inculded and excluded data. |
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| 207 | The excluded data will be dropped. */ |
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| 208 | ulNumImmData = ulWriteSize + (((astReg2BlockOut[i].ulReg2BlockOutEnd - |
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| 209 | astReg2BlockOut[i].ulReg2BlockOutStart) / sizeof(uint32_t)) + 1); |
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| 210 | |
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| 211 | /* Get immediate data */ |
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| 212 | for (j=0; j<ulNumImmData; j++) |
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| 213 | { |
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| 214 | /* Increment original RUL list to keep in pace with the |
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| 215 | RUL entry retrieval order and amount. */ |
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| 216 | (*pulOrigRulAddr)++; |
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| 217 | |
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| 218 | if(BRDC_DBG_GetListEntry_isr(hList, &eEntry, aulArgs)) |
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| 219 | { |
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| 220 | /* error */ |
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| 221 | BDBG_ERR(("ERROR parsing list %d", __LINE__)); |
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| 222 | } |
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| 223 | else if (eEntry == BRDC_DBG_ListEntry_eEnd) |
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| 224 | { |
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| 225 | BDBG_ERR(("Incorrect number of RUL entries")); |
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| 226 | } |
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| 227 | else |
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| 228 | { |
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| 229 | /* ignore imm data after write size since the dest for these data are |
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| 230 | blocked but continue to get it to set the RUL pointer |
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| 231 | to the correct location */ |
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| 232 | if (j < ulWriteSize) |
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| 233 | { |
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| 234 | *(*pulRevisedRulAddr) = aulArgs[0]; |
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| 235 | (*pulRevisedRulAddr)++; |
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| 236 | } |
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| 237 | } |
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| 238 | } |
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| 239 | } |
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| 240 | |
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| 241 | /* get next dest reg */ |
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| 242 | ulDstReg = astReg2BlockOut[i].ulReg2BlockOutEnd + (1 * sizeof(uint32_t)); |
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| 243 | |
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| 244 | /* get next src reg */ |
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| 245 | if (pstRulEntry->ulOpcode == BRDC_OP_REGS_TO_REGS_OPCODE) |
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| 246 | { |
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| 247 | ulSrcReg += (ulWriteSize * sizeof(uint32_t)) + (astReg2BlockOut[i].ulReg2BlockOutEnd - |
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| 248 | astReg2BlockOut[i].ulReg2BlockOutStart); |
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| 249 | } |
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| 250 | } |
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| 251 | |
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| 252 | /* Check if there are some remaining writes to be made */ |
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| 253 | if (ulDstReg < (pstRulEntry->ulDstReg + (pstRulEntry->ulWriteSize * sizeof(uint32_t)))) |
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| 254 | { |
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| 255 | ulWriteSize = ((pstRulEntry->ulDstReg + (pstRulEntry->ulWriteSize * sizeof(uint32_t))) - |
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| 256 | ulDstReg) / sizeof(uint32_t); |
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| 257 | |
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| 258 | ulOpcode = pstRulEntry->ulOpcode | ((ulWriteSize & UINT32_C(0xFFF)) - 1); |
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| 259 | *(*pulRevisedRulAddr) = ulOpcode; |
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| 260 | (*pulRevisedRulAddr)++; |
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| 261 | |
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| 262 | if ((pstRulEntry->ulOpcode == BRDC_OP_REGS_TO_REGS_OPCODE) || |
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| 263 | (pstRulEntry->ulOpcode == BRDC_OP_REG_TO_REGS_OPCODE)) |
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| 264 | { |
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| 265 | *(*pulRevisedRulAddr) = BRDC_REGISTER(ulSrcReg); |
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| 266 | (*pulRevisedRulAddr)++; |
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| 267 | } |
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| 268 | |
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| 269 | *(*pulRevisedRulAddr) = BRDC_REGISTER(ulDstReg); |
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| 270 | (*pulRevisedRulAddr)++; |
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| 271 | |
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| 272 | if (pstRulEntry->ulOpcode == BRDC_OP_IMMS_TO_REGS_OPCODE) |
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| 273 | { |
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| 274 | /* Get immediate data */ |
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| 275 | for (i=0; i<ulWriteSize; i++) |
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| 276 | { |
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| 277 | /* Increment original RUL list to keep in pace with the |
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| 278 | RUL entry retrieval order and amount. */ |
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| 279 | (*pulOrigRulAddr)++; |
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| 280 | |
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| 281 | if (BRDC_DBG_GetListEntry_isr(hList, &eEntry, aulArgs)) |
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| 282 | { |
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| 283 | /* error */ |
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| 284 | BDBG_ERR(("ERROR parsing list %d", __LINE__)); |
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| 285 | } |
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| 286 | else if (eEntry == BRDC_DBG_ListEntry_eEnd) |
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| 287 | { |
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| 288 | BDBG_ERR(("Incorrect number of RUL entries")); |
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| 289 | } |
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| 290 | else |
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| 291 | { |
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| 292 | *(*pulRevisedRulAddr) = aulArgs[0]; |
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| 293 | (*pulRevisedRulAddr)++; |
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| 294 | } |
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| 295 | } |
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| 296 | } |
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| 297 | } |
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| 298 | } |
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| 299 | else |
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| 300 | { |
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| 301 | BDBG_MSG(("Register 0x%x blocked", pstRulEntry->ulDstReg)); |
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| 302 | } |
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| 303 | } |
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| 304 | |
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| 305 | return bBlockOut; |
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| 306 | } |
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| 307 | |
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| 308 | |
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| 309 | /* Searches a list and looks for the specified register blocks. If found, create a new list that |
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| 310 | excludes these registers and replace the list with the new one. */ |
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| 311 | BERR_Code BRDC_P_ParseAndReplaceRul_isr |
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| 312 | ( BRDC_List_Handle hList) |
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| 313 | { |
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| 314 | BERR_Code err = BERR_SUCCESS; |
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| 315 | BRDC_DBG_ListEntry eEntry; |
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| 316 | uint32_t aulArgs[4]; |
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| 317 | bool bRegWrite = false; |
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| 318 | bool bReg2RegWrite = false; |
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| 319 | bool bGo = false; |
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| 320 | uint32_t *pulAddress, *pulStartAddress, *pulRevisedRulStartAddr, *pulRevisedRulCurrAddr; |
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| 321 | uint32_t ulOpcode = 0, ulSrcRegAddr = 0, ulDstRegAddr = 0; |
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| 322 | uint32_t ulNumEntries; |
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| 323 | BRDC_RulEntry stRulEntry; |
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| 324 | BRDC_Handle hRdc; |
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| 325 | BRDC_List_Handle hRdcBlockOutList; |
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| 326 | |
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| 327 | BDBG_ASSERT(hList); |
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| 328 | |
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| 329 | hRdc = hList->hRdc; |
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| 330 | hRdcBlockOutList = hRdc->hRdcBlockOutList; |
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| 331 | |
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| 332 | /* get address to list */ |
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| 333 | pulStartAddress = pulAddress = BRDC_List_GetStartAddress_isr(hList); |
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| 334 | pulRevisedRulStartAddr = pulRevisedRulCurrAddr = BRDC_List_GetStartAddress_isr(hRdcBlockOutList); |
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| 335 | |
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| 336 | /* prepare to traverse this list */ |
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| 337 | err = BRDC_DBG_SetList_isr(hList); |
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| 338 | if (err != BERR_SUCCESS) |
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| 339 | { |
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| 340 | /* error */ |
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| 341 | BDBG_ERR(("ERROR parsing list %d", __LINE__)); |
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| 342 | goto done; |
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| 343 | } |
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| 344 | |
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| 345 | /* get first entry in list */ |
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| 346 | err = BRDC_DBG_GetListEntry_isr(hList, &eEntry, aulArgs); |
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| 347 | if (err != BERR_SUCCESS) |
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| 348 | { |
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| 349 | /* error */ |
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| 350 | BDBG_ERR(("ERROR parsing list %d", __LINE__)); |
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| 351 | goto done; |
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| 352 | } |
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| 353 | |
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| 354 | /* traverse until finished */ |
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| 355 | while(eEntry != BRDC_DBG_ListEntry_eEnd) |
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| 356 | { |
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| 357 | /* command entry? */ |
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| 358 | if(eEntry == BRDC_DBG_ListEntry_eCommand) |
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| 359 | { |
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| 360 | /* init */ |
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| 361 | BKNI_Memset((void *)&stRulEntry, 0x0, sizeof(BRDC_RulEntry)); |
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| 362 | stRulEntry.ulReadSize = stRulEntry.ulWriteSize = 1; |
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| 363 | ulOpcode = ulSrcRegAddr = ulDstRegAddr = 0; |
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| 364 | bRegWrite = bReg2RegWrite = false; |
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| 365 | bGo = false; |
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| 366 | |
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| 367 | /* Get the opcode and its args */ |
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| 368 | stRulEntry.ulOpcode = aulArgs[0]; |
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| 369 | |
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| 370 | /* is this a write to register command? */ |
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| 371 | switch(stRulEntry.ulOpcode) |
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| 372 | { |
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| 373 | case BRDC_OP_VAR_TO_REG_OPCODE: |
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| 374 | stRulEntry.ulArg = aulArgs[1]; |
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| 375 | bRegWrite = true; |
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| 376 | break; |
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| 377 | case BRDC_OP_IMM_TO_REG_OPCODE: |
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| 378 | stRulEntry.ulNumImmData = 1; |
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| 379 | bRegWrite = true; |
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| 380 | break; |
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| 381 | case BRDC_OP_IMMS_TO_REG_OPCODE: |
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| 382 | stRulEntry.ulNumImmData = aulArgs[1]; |
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| 383 | bRegWrite = true; |
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| 384 | break; |
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| 385 | case BRDC_OP_IMMS_TO_REGS_OPCODE: |
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| 386 | stRulEntry.ulReadSize = stRulEntry.ulWriteSize = stRulEntry.ulNumImmData = aulArgs[1]; |
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| 387 | bRegWrite = true; |
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| 388 | break; |
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| 389 | case BRDC_OP_REG_TO_REG_OPCODE: |
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| 390 | stRulEntry.ulArg = aulArgs[1]; |
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| 391 | bReg2RegWrite = true; |
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| 392 | break; |
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| 393 | case BRDC_OP_REGS_TO_REG_OPCODE: |
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| 394 | stRulEntry.ulReadSize = aulArgs[1]; |
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| 395 | bReg2RegWrite = true; |
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| 396 | break; |
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| 397 | case BRDC_OP_REGS_TO_REGS_OPCODE: |
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| 398 | stRulEntry.ulReadSize = stRulEntry.ulWriteSize = aulArgs[1]; |
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| 399 | bReg2RegWrite = true; |
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| 400 | break; |
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| 401 | case BRDC_OP_REG_TO_REGS_OPCODE: |
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| 402 | stRulEntry.ulWriteSize = aulArgs[1]; |
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| 403 | bReg2RegWrite = true; |
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| 404 | break; |
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| 405 | default: |
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| 406 | break; |
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| 407 | } |
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| 408 | |
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| 409 | /* store opcode */ |
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| 410 | ulOpcode = *pulAddress; |
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| 411 | |
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| 412 | } |
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| 413 | else if (eEntry == BRDC_DBG_ListEntry_eRegister) |
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| 414 | { |
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| 415 | if (bRegWrite) |
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| 416 | { |
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| 417 | stRulEntry.ulDstReg = aulArgs[0]; |
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| 418 | ulDstRegAddr = *pulAddress; |
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| 419 | bGo = true; |
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| 420 | } |
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| 421 | else if (bReg2RegWrite) |
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| 422 | { |
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| 423 | if (stRulEntry.ulSrcReg) |
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| 424 | { |
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| 425 | /* Got dest register block */ |
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| 426 | stRulEntry.ulDstReg = aulArgs[0]; |
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| 427 | ulDstRegAddr = *pulAddress; |
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| 428 | bGo = true; |
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| 429 | } |
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| 430 | else |
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| 431 | { |
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| 432 | /* Got src register block */ |
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| 433 | stRulEntry.ulSrcReg = aulArgs[0]; |
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| 434 | ulSrcRegAddr = *pulAddress; |
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| 435 | } |
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| 436 | } |
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| 437 | } |
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| 438 | else /* eEntry == BRDC_DBG_ListEntry_eData */ |
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| 439 | { |
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| 440 | bGo = false; |
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| 441 | } |
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| 442 | |
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| 443 | /* RUL doesn't write to any registers. |
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| 444 | Or get the rest of the immediate data if opcode |
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| 445 | involves a register write that is not blocked. |
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| 446 | */ |
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| 447 | if (!bRegWrite && !bReg2RegWrite) |
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| 448 | { |
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| 449 | /* Simply add the unrevised RUL entry */ |
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| 450 | *pulRevisedRulCurrAddr = *pulAddress; |
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| 451 | pulRevisedRulCurrAddr++; |
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| 452 | } |
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| 453 | else |
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| 454 | { |
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| 455 | if (bGo) |
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| 456 | { |
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| 457 | /* Revise the RUL entries if dest register/s is/are blocked. |
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| 458 | Any immeditate data will be grabbed inside the call.*/ |
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| 459 | if (BRDC_P_PopulateRevisedRul_isr(hRdc, hList, |
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| 460 | &pulAddress, &pulRevisedRulCurrAddr, &stRulEntry) == false) |
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| 461 | { |
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| 462 | /* Dest register/s aren't blocked so restore original RUL entries */ |
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| 463 | *pulRevisedRulCurrAddr = ulOpcode; |
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| 464 | pulRevisedRulCurrAddr++; |
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| 465 | |
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| 466 | if (ulSrcRegAddr) |
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| 467 | { |
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| 468 | *pulRevisedRulCurrAddr = ulSrcRegAddr; |
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| 469 | pulRevisedRulCurrAddr++; |
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| 470 | } |
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| 471 | |
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| 472 | *pulRevisedRulCurrAddr = ulDstRegAddr; |
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| 473 | pulRevisedRulCurrAddr++; |
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| 474 | |
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| 475 | /* this allows immediate data, if any, to get stored */ |
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| 476 | bRegWrite = bReg2RegWrite = false; |
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| 477 | } |
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| 478 | } |
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| 479 | } |
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| 480 | |
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| 481 | /* get next entry in list */ |
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| 482 | pulAddress++; |
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| 483 | |
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| 484 | if(BRDC_DBG_GetListEntry_isr(hList, &eEntry, aulArgs)) |
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| 485 | { |
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| 486 | /* error */ |
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| 487 | BDBG_ERR(("ERROR parsing list %d", __LINE__)); |
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| 488 | goto done; |
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| 489 | } |
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| 490 | } |
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| 491 | |
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| 492 | /* Recopy to current RUL */ |
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| 493 | ulNumEntries = pulRevisedRulCurrAddr - pulRevisedRulStartAddr; |
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| 494 | |
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| 495 | BDBG_MSG(("%d revised RUL entries", ulNumEntries)); |
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| 496 | BDBG_MSG(("%d orig RUL entries", (pulStartAddress - pulAddress))); |
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| 497 | |
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| 498 | BDBG_ASSERT(ulNumEntries < BRDC_P_RDC_BLOCKOUT_RUL_MAX_ENTRY); |
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| 499 | BKNI_Memcpy(pulStartAddress, pulRevisedRulStartAddr, sizeof(uint32_t) * ulNumEntries); |
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| 500 | BRDC_List_SetNumEntries_isr(hList, ulNumEntries); |
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| 501 | |
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| 502 | done: |
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| 503 | return err; |
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| 504 | } |
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| 505 | |
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| 506 | BERR_Code BRDC_P_ValidateBlockOutRegisters |
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| 507 | ( const BRDC_BlockOut *pstBlockOut, |
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| 508 | uint32_t ulRegBlock ) |
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| 509 | { |
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| 510 | BERR_Code err = BERR_SUCCESS; |
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| 511 | |
|---|
| 512 | if (ulRegBlock >= BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT) |
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| 513 | { |
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| 514 | BDBG_ERR(("Only %d register blocks are allowed", |
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| 515 | BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT)); |
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| 516 | err = BERR_INVALID_PARAMETER; |
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| 517 | return err; |
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| 518 | } |
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| 519 | else |
|---|
| 520 | { |
|---|
| 521 | uint32_t ulStartAddr; |
|---|
| 522 | uint32_t ulEndAddr; |
|---|
| 523 | |
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| 524 | ulStartAddr = pstBlockOut->ulStartRegAddr; |
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| 525 | ulEndAddr = pstBlockOut->ulStartRegAddr + (pstBlockOut->ulBlockSize * sizeof(uint32_t)); |
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| 526 | |
|---|
| 527 | #ifdef BCHP_REGISTER_END |
|---|
| 528 | if ((ulStartAddr > BCHP_REGISTER_END) || (ulEndAddr > BCHP_REGISTER_END)) |
|---|
| 529 | { |
|---|
| 530 | BDBG_ERR(("Register block 0x%x to 0x%x is out of valid register range", |
|---|
| 531 | ulStartAddr, ulEndAddr)); |
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| 532 | err = BERR_INVALID_PARAMETER; |
|---|
| 533 | return err; |
|---|
| 534 | } |
|---|
| 535 | #endif |
|---|
| 536 | } |
|---|
| 537 | return err; |
|---|
| 538 | } |
|---|
| 539 | |
|---|
| 540 | BERR_Code BRDC_P_RdcBlockOutInit |
|---|
| 541 | ( BRDC_Handle hRdc ) |
|---|
| 542 | { |
|---|
| 543 | BERR_Code err = BERR_SUCCESS; |
|---|
| 544 | |
|---|
| 545 | BKNI_Memset((void *)hRdc->astBlockOut, 0x0, sizeof(BRDC_BlockOut) * BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT); |
|---|
| 546 | |
|---|
| 547 | err = BRDC_List_Create(hRdc, BRDC_P_RDC_BLOCKOUT_RUL_MAX_ENTRY, &hRdc->hRdcBlockOutList); |
|---|
| 548 | if (err != BERR_SUCCESS) |
|---|
| 549 | { |
|---|
| 550 | BDBG_ERR(("ERROR: BRDC_List_Create")); |
|---|
| 551 | } |
|---|
| 552 | |
|---|
| 553 | hRdc->bRdcBlockOutEnabled = false; |
|---|
| 554 | return err; |
|---|
| 555 | } |
|---|
| 556 | |
|---|
| 557 | BERR_Code BRDC_P_RdcBlockOutDestroy |
|---|
| 558 | ( BRDC_Handle hRdc ) |
|---|
| 559 | { |
|---|
| 560 | BERR_Code err = BERR_SUCCESS; |
|---|
| 561 | |
|---|
| 562 | if (hRdc->hRdcBlockOutList) |
|---|
| 563 | { |
|---|
| 564 | /* deallocate RDC blockout list */ |
|---|
| 565 | err = BRDC_List_Destroy(hRdc->hRdcBlockOutList); |
|---|
| 566 | if (err != BERR_SUCCESS) |
|---|
| 567 | { |
|---|
| 568 | BDBG_ERR(("ERROR: BRDC_List_Create")); |
|---|
| 569 | return err; |
|---|
| 570 | } |
|---|
| 571 | hRdc->hRdcBlockOutList = NULL; |
|---|
| 572 | } |
|---|
| 573 | |
|---|
| 574 | hRdc->bRdcBlockOutEnabled = false; |
|---|
| 575 | |
|---|
| 576 | return err; |
|---|
| 577 | } |
|---|
| 578 | |
|---|
| 579 | bool BRDC_P_IsRdcBlockOutEnabled |
|---|
| 580 | ( BRDC_Handle hRdc ) |
|---|
| 581 | { |
|---|
| 582 | uint32_t i; |
|---|
| 583 | bool bEnabled = false; |
|---|
| 584 | |
|---|
| 585 | /* Find a register block that is enabled for block out */ |
|---|
| 586 | for(i=0; i<BRDC_MAX_RDC_BLOCKOUT_LIST_COUNT; i++) |
|---|
| 587 | { |
|---|
| 588 | if ((hRdc->astBlockOut[i].bEnable == true) && (hRdc->bRdcBlockOutEnabled)) |
|---|
| 589 | { |
|---|
| 590 | bEnabled = true; |
|---|
| 591 | break; |
|---|
| 592 | } |
|---|
| 593 | } |
|---|
| 594 | return bEnabled; |
|---|
| 595 | } |
|---|
| 596 | |
|---|
| 597 | /* End of file */ |
|---|