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bads_acquire.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* (c)2005-2012 Broadcom Corporation
3	*
4	* This program is the proprietary software of Broadcom Corporation and/or its licensors,
5	* and may only be used, duplicated, modified or distributed pursuant to the terms and
6	* conditions of a separate, written license agreement executed between you and Broadcom
7	* (an "Authorized License"). Except as set forth in an Authorized License, Broadcom grants
8	* no license (express or implied), right to use, or waiver of any kind with respect to the
9	* Software, and Broadcom expressly reserves all rights in and to the Software and all
10	* intellectual property rights therein. IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11	* HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12	* NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE.
13	*
14	* Except as expressly set forth in the Authorized License,
15	*
16	* 1. This program, including its structure, sequence and organization, constitutes the valuable trade
17	* secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof,
18	* and to use this information only in connection with your use of Broadcom integrated circuit products.
19	*
20	* 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
21	* AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR
22	* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
23	* THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES
24	* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE,
25	* LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION
26	* OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF
27	* USE OR PERFORMANCE OF THE SOFTWARE.
28	*
29	* 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS
30	* LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR
31	* EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR
32	* USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF
33	* THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT
34	* ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE
35	* LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF
36	* ANY LIMITED REMEDY.
37	*
38	* $brcm_Workfile: bads_acquire.c $
39	* $brcm_Revision: 128 $
40	* $brcm_Date: 3/23/12 3:11p $
41	*
42	* [File Description:]
43	*
44	* Revision History:
45	*
46	* $brcm_Log: /AP/ctfe/core/ads/bads_acquire.c $
47	*
48	* 128 3/23/12 3:11p farshidf
49	* SW3128-125: FW version 4.6
50	*
51	* Fw_Integration_Devel/26 3/23/12 3:09p farshidf
52	* SW3128-125: FW version 4.6
53	*
54	* Fw_Integration_Devel/AP_V4_0_ADS_DEV/2 3/19/12 6:12p cbrooks
55	* sw3128-132:Fixed Annex A symbol rate reporting
56	*
57	* Fw_Integration_Devel/AP_V4_0_ADS_DEV/1 2/28/12 12:29p cbrooks
58	* sw3128-1:fixed SlowScan mode
59	*
60	* Fw_Integration_Devel/24 2/9/12 12:14p farshidf
61	* SW3128-1: merge to integ
62	*
63	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/15 2/9/12 11:40a cbrooks
64	* sw3128-1:fixed baud loop droppouts
65	*
66	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/14 1/30/12 5:16p cbrooks
67	* sw3128-1:Fixxed FFT window, added FOI timing gain
68	*
69	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/13 1/25/12 6:02p cbrooks
70	* sw3128-1:changed timeout in FFT routine
71	*
72	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/12 12/22/11 7:51p mpovich
73	* SW3461-105: Eliminate chance of infinite loop in ADS Delay function.
74	*
75	* Fw_Integration_Devel/22 12/22/11 6:36a mpovich
76	* SW3461-105: Eliminate chance of infinite loop in ADS Delay function.
77	*
78	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/11 12/22/11 6:32a mpovich
79	* SW3461-105: Eliminate chance of infinite loop in ADS Delay function.
80	*
81	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/10 12/21/11 6:01p mpovich
82	* SW3461-105: Eliminate chance of infinite loop in ADS Delay function.
83	*
84	* Fw_Integration_Devel/21 12/15/11 12:22p farshidf
85	* SW3461-118: merge to integ
86	*
87	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/9 12/12/11 4:13p cbrooks
88	* sw3128-1:added new coeffs for FOI timing loop
89	*
90	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/8 11/21/11 6:54p mpovich
91	* SW3128-71: Support for a single, common 3128 chip family F/W binary.
92	*
93	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/SW3128-71/1 11/17/11 6:58p mpovich
94	* SW3128-71: Support for common 3128 family chip F/W.
95	*
96	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/7 10/31/11 3:51p cbrooks
97	* sw3128-1:Fixed delay in FFT
98	*
99	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/6 10/28/11 12:25p farshidf
100	* SW3461-75: fix compile error for A0 build
101	*
102	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/5 10/28/11 12:10p farshidf
103	* SW3461-75: Move to new IRQ handling
104	*
105	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/4 10/24/11 10:50a farshidf
106	* SW3128-55: new power up code
107	*
108	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/3 10/21/11 6:29p cbrooks
109	* sw3128-1:Added fix to CWC
110	*
111	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/2 10/21/11 6:16p cbrooks
112	* sw3128-1:added Taks constant spur freequency
113	*
114	* Fw_Integration_Devel/AP_V3_0_ADS_DEV/1 10/21/11 4:15p cbrooks
115	* sw3128-1:fixed symbol rate lookup for ACI rejection fine tuning
116	*
117	* Fw_Integration_Devel/17 10/18/11 6:38p farshidf
118	* SW7552-134: reset FE fifo
119	*
120	* Fw_Integration_Devel/16 10/12/11 2:30p farshidf
121	* SW3128-54: merge to integ
122	*
123	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/8 10/12/11 11:43a mpovich
124	* SW3128-38: Merge ADS Early Exit feature to devel. branch.
125	*
126	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/7 10/6/11 11:44a farshidf
127	* SW3128-1: add support for 3128 C0
128	*
129	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/SW3128-38/3 10/5/11 4:18p mpovich
130	* SW3128-38: Early exit feature - encapsulate early exit flag within
131	* bads_acquire module.
132	*
133	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/SW3128-38/2 10/4/11 3:02p mpovich
134	* SW3128-38: Early exit feature for downstream acquire.
135	*
136	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/SW3128-38/1 10/4/11 12:53a mpovich
137	* SW3128-38: Early exit feature for downstream acquire.
138	*
139	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/4 9/15/11 3:14p cbrooks
140	* SW3128-1:Changed DFE_OVERLAP_LEAK to oxD
141	*
142	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/3 8/30/11 10:41p mpovich
143	* SW3128-24: Move front-end 3128/3461 core drivers to dedicated AP VOB
144	* directory. Add support for 3128 Rev. B0 chip.
145	*
146	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/SW3128-45/1 8/28/11 10:35p mpovich
147	* SW3128-45: Build Chip Revision B0.
148	*
149	* 105 8/24/11 12:22p farshidf
150	* SW3461-18: merge to main
151	*
152	* Fw_Integration_Devel/11 8/24/11 11:59a farshidf
153	* SW3461-38: merge to integ
154	*
155	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/2 8/23/11 4:48p mpovich
156	* SW3128-24: Merge latest of SW3128-24 to devel. branch.
157	*
158	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-24/3 8/23/11 4:32p mpovich
159	* SW3128-24: Rebase with 2.0 devel. branch.
160	*
161	* Fw_Integration_Devel/AP_V2_0_ADS_DEV/1 8/17/11 5:57p farshidf
162	* SW3461-1: merge the B0 changes
163	*
164	* 103 8/12/11 3:12p farshidf
165	* SW3461-1: merge to main
166	*
167	* Fw_Integration_Devel/8 8/12/11 2:10p farshidf
168	* SW3461-1: merge to integ
169	*
170	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-24/2 8/17/11 10:12a mpovich
171	* SW3128-24: Update from SW3128-32.
172	*
173	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-32/3 8/16/11 7:34p mpovich
174	* SW3128-32: Assign Scan Status params inside BADS_P_Acquire().
175	*
176	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-32/2 8/16/11 6:31p cbrooks
177	* sw3128-1:added new FFT
178	*
179	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-24/1 8/16/11 6:37p mpovich
180	* SW3128-24: Pick up SW3128-32, "Get Scan Status" HAB command
181	*
182	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-32/1 8/16/11 5:34p cbrooks
183	* sw3128-1:added scanstatus structure
184	*
185	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/21 7/29/11 11:20a cbrooks
186	* sw3128-1:update the retry
187	*
188	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/20 7/28/11 4:37p cbrooks
189	* sw3128-1:Fixed two pass fast/slow acquisition
190	*
191	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/19 7/28/11 12:55p cbrooks
192	* sw3128-1:removed test feature from acquisition test
193	*
194	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/18 7/27/11 7:58p cbrooks
195	* sw3128-1:Added Early Exit
196	*
197	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/17 7/27/11 12:35p cbrooks
198	* sw3128-1:removed debug print message
199	*
200	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/16 7/26/11 2:59p farshidf
201	* SW3128-1: merge to dev branch
202	*
203	* 101 7/26/11 2:58p farshidf
204	* SW3128-1: remove warning
205	*
206	* 100 7/25/11 2:17p farshidf
207	* SW3128-1: remove warning
208	*
209	* 99 7/25/11 10:31a farshidf
210	* SW3128-1: merge to main
211	*
212	* 102 7/27/11 4:55p farshidf
213	* SW3128-1: remove un-necessay print
214	*
215	* 101 7/26/11 2:58p farshidf
216	* SW3128-1: remove warning
217	*
218	* 100 7/25/11 2:17p farshidf
219	* SW3128-1: remove warning
220	*
221	* 99 7/25/11 10:31a farshidf
222	* SW3128-1: merge to main
223	*
224	* Fw_Integration_Devel/7 7/25/11 10:16a farshidf
225	* SW3128-1: fix Merge
226	*
227	* Fw_Integration_Devel/6 7/25/11 10:13a farshidf
228	* SW3128-1: fix merge
229	*
230	* Fw_Integration_Devel/5 7/25/11 10:10a farshidf
231	* SW3128-1: merge to integ
232	*
233	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/15 7/22/11 4:51p cbrooks
234	* sw3128-1:Added SLow Scan for RFI interference
235	*
236	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/14 7/19/11 12:59p farshidf
237	* SW3128-1: remove extra include
238	*
239	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/13 7/18/11 6:37p cbrooks
240	* sw3128-1:removed reack count from slow mode
241	*
242	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/12 7/18/11 6:09p cbrooks
243	* sw3128-1:Added Baseand timing loop phase detector
244	*
245	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/11 7/18/11 3:43p farshidf
246	* SW3128-21: update
247	*
248	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/10 7/18/11 3:38p farshidf
249	* SW3128-21: update teh FFt IRQ
250	*
251	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/9 7/18/11 1:02p cbrooks
252	* sw3128-1:fixed timing loop mistake
253	*
254	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/8 7/18/11 9:58a farshidf
255	* SW3128-28: compile fix
256	*
257	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/7 7/15/11 6:42p farshidf
258	* SWDTV-7869: fix
259	*
260	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/6 7/15/11 6:27p farshidf
261	* SWDTV-7869: fix compile error
262	*
263	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/5 7/15/11 6:17p farshidf
264	* SWDTV-7869: check-in the B0 code
265	*
266	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/4 7/15/11 5:40p cbrooks
267	* sw3128-1:added slow acquire for RFI support
268	*
269	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/3 7/14/11 7:13p cbrooks
270	* sw3128-1:added CWC for 3461
271	*
272	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/2 7/14/11 4:36p farshidf
273	* SW3128-28: fix the FFT interrupt fro back end chip
274	*
275	* Fw_Integration_Devel/AP_V0_6_ADS_DEV/1 6/30/11 6:02p cbrooks
276	* sw3128-1:added retry capablility
277	*
278	* Fw_Integration_Devel/1 6/29/11 12:37p farshidf
279	* SW3461-13: merge to integration branch
280	*
281	* Fw_Integration_Devel/Ads_Fw_Devel_Rc04/2 6/22/11 5:32p cbrooks
282	* sw3128-1:fixed FEC reset problem
283	*
284	* Fw_Integration_Devel/Ads_Fw_Devel_Rc04/1 6/21/11 5:17p cbrooks
285	* sw3128-1:Added symbol rate to callback
286	*
287	* 95 6/9/11 6:13p mpovich
288	* SW3461-1: Merge Ver 0.4 Integ. onto main branch.
289	*
290	* SW_System_4_Integ_Test/4 6/9/11 2:14p mpovich
291	* SW3461-1: Rebase with main branch.
292	*
293	* 94 6/9/11 9:57a farshidf
294	* SW3128-1: add criticalsection for magnum compatibilty
295	*
296	* 93 6/7/11 6:02p farshidf
297	* SW3128-1: add 3123 support
298	*
299	* 92 6/7/11 3:13p farshidf
300	* SW3128-1: merge to main
301	*
302	* SW_System_4_Integ_Test/3 6/7/11 1:49p farshidf
303	* SW3128-1: sync up with backend
304	*
305	* SW_System_4_Integ_Test/2 6/7/11 11:03a farshidf
306	* SW3128-1: merge to integration branch
307	*
308	* Ads_Fw_Devel_3/4 6/7/11 10:56a cbrooks
309	* sw3128-1:Added 7552 IMC
310	*
311	* Ads_Fw_Devel_3/3 6/1/11 5:55p farshidf
312	* SW3128-1: merge from main
313	*
314	* 91 6/1/11 5:51p farshidf
315	* SW3128-1: Add double wrtite
316	*
317	* 90 5/20/11 6:38a mpovich
318	* SW3461-1: rename UFE (BUFE) module to TNR (BTNR).
319	*
320	* TNR_3461_1/1 5/19/11 6:26p mpovich
321	* SW3461-1: Change BUFE module name to BTNR
322	*
323	* 89 5/18/11 3:57p farshidf
324	* SW3128-1: remove the flag fro 3128/3461
325	*
326	* 88 5/18/11 3:23p farshidf
327	* SW3128-1: add 3128 DS fix from Charlie
328	*
329	* 86 5/17/11 4:40p mpovich
330	* SW3461-1: fix 3461 cannot acquire DS problem (added debug printfs if
331	* BKNI event cannot be created).
332	*
333	* 85 5/13/11 2:10p farshidf
334	* SW3128-1: fix from charlie
335	*
336	* 84 5/11/11 4:59p farshidf
337	* SW3128-1: merge main
338	*
339	* ADS_3128_3/20 5/11/11 4:22p cbrooks
340	* sw3128-1:merging 330 changes
341	*
342	* Hydra_Software_Devel/SWDTV-7035/2 5/10/11 12:27p farshidf
343	* SWDTV-7035: update to latest
344	*
345	* ADS_3128_3/18 5/10/11 12:17p farshidf
346	* SW3128-1: update callback
347	*
348	* ADS_3128_3/17 5/10/11 11:00a cbrooks
349	* sw3128-1:Changed status
350	*
351	* ADS_3128_3/16 5/7/11 3:53p cbrooks
352	* sw3128-1:clean up
353	*
354	* ADS_3128_3/15 5/7/11 3:47p cbrooks
355	* sw3128-1:corrected freq offset
356	*
357	* ADS_3128_3/14 5/5/11 8:46p cbrooks
358	* sw3128-1:new code
359	*
360	* ADS_3128_3/13 5/5/11 8:28p cbrooks
361	* sw3128-1:Clean up
362	*
363	* ADS_3128_3/12 5/5/11 8:14p cbrooks
364	* sw3128-1:Cleanup Code
365	*
366	* ADS_3128_3/11 5/3/11 10:29p cbrooks
367	* sw3128-1:added delat in FFT
368	*
369	* ADS_3128_3/10 5/3/11 7:42p cbrooks
370	* sw3128-1:fft changes
371	*
372	* ADS_3128_3/9 5/3/11 7:34p cbrooks
373	* sw3128-1:fixed FFT
374	*
375	* ADS_3128_3/8 5/3/11 4:30p cbrooks
376	* sw3128-1:new code for FFT timeout
377	*
378	* ADS_3128_3/7 5/1/11 3:49p cbrooks
379	* sw3128-1:new code
380	*
381	* ADS_3128_3/6 5/1/11 3:30p cbrooks
382	* sw3128-1:Cleaned up Channel Scan Code
383	*
384	* ADS_3128_3/4 4/28/11 8:07p cbrooks
385	* sw3128-1:new code for FFT
386	*
387	* ADS_3128_3/3 4/28/11 3:51p farshidf
388	* SW3128-1: merge main
389	*
390	* 81 4/28/11 8:50p farshidf
391	* SW3128-1: remove IRQ
392	*
393	* 79 4/28/11 4:36p farshidf
394	* SW3128-1: sync up with 35530
395	*
396	* 78 4/28/11 3:50p farshidf
397	* SW3128-1: merge main
398	*
399	* ADS_3128_3/2 4/28/11 2:34p cbrooks
400	* sw3128-1:fixed carrier range
401	*
402	* ADS_3128_3/1 4/28/11 1:08p cbrooks
403	* sw3128-1:New Code for scan
404	*
405	* 74 4/26/11 7:32p farshidf
406	* SW3128-1: compile fix for 3461
407	*
408	* 73 4/26/11 6:57p farshidf
409	* SW3128-1: make it host compatible
410	*
411	* 72 4/26/11 6:48p farshidf
412	* SW3128-1: error fixed
413	*
414	* 71 4/26/11 6:47p farshidf
415	* SW3128-1: merge main
416	*
417	* ADS_3128_2/7 4/26/11 5:50p farshidf
418	* SW3128: compile fix
419	*
420	* ADS_3128_2/6 4/26/11 4:59p farshidf
421	* SW3128-1: update
422	*
423	* ADS_3128_2/5 4/26/11 4:52p farshidf
424	* SW3128-1: merge main
425	*
426	* ADS_3128_2/4 4/26/11 4:25p cbrooks
427	* sw3128-1:New code for 330
428	*
429	* ADS_3128_2/3 4/13/11 5:04p cbrooks
430	* sw3128-1:new cwc code
431	*
432	* ADS_3128_2/2 4/11/11 8:31p cbrooks
433	* SW3128-1:Added CWC code
434	*
435	* ADS_3128_2/1 4/11/11 12:46p cbrooks
436	* sw3128-1:New CWC code
437	*
438	* 56 3/24/11 4:15p farshidf
439	* SW3128-1: add support for 3124
440	*
441	* 55 3/18/11 4:29p farshidf
442	* SW3461-1: merge main
443	*
444	* ADS_3128_1/2 3/17/11 12:29p cbrooks
445	* sw3128-1:Added BERT resync warning
446	*
447	* ADS_3128_1/1 3/16/11 5:21p cbrooks
448	* sw3128-1:new bert
449	*
450	* 54 3/7/11 11:19p farshidf
451	* SW3128-1: remove the OOb power control
452	*
453	* 53 3/4/11 12:34p farshidf
454	* SW3128-1: add the power seq for DS
455	*
456	* 52 3/4/11 12:16p farshidf
457	* SW3128-1: add the power seq for DS
458	*
459	* 51 3/4/11 12:00p farshidf
460	* SW3128-1: fix the last channel issue
461	*
462	* 50 3/4/11 11:55a farshidf
463	* SW3128-1: fxi compile issue
464	*
465	* 49 3/4/11 11:53a farshidf
466	* SW3128-1: add the power seq for DS cores
467	*
468	* 48 3/3/11 5:38p farshidf
469	* SW3128-1: comment the power down code
470	*
471	* 44 2/28/11 5:57p cbrooks
472	* sw3128-1:Changed acqwords to internal_params
473	*
474	* 43 2/23/11 7:39p cbrooks
475	* sw3128-1:new code
476	*
477	* 42 2/23/11 6:56p cbrooks
478	* sw3128-1:new code
479	*
480	* 41 2/15/11 7:20p cbrooks
481	* SW3128-1:New Code
482	*
483	* 40 2/9/11 10:50a cbrooks
484	* SW3128-1:LIC EST CODE
485	*
486	* 39 2/8/11 11:55a farshidf
487	* SW3128-1: reduce the number of event per channel
488	*
489	* 38 2/7/11 5:41p farshidf
490	* SW3128-1: adapt to new rdb
491	*
492	* 37 2/7/11 3:38p farshidf
493	* SW3128-1: remove printf
494	*
495	* 36 2/7/11 2:26p cbrooks
496	* sw3128-1:new code
497	*
498	* 35 2/4/11 4:26p farshidf
499	* SW3128-1: remove the timer 7 set
500	*
501	* 34 2/4/11 10:36a farshidf
502	* SW3128-1: add printf
503	*
504	* 33 2/3/11 8:02p mpovich
505	* SW3128-1: Fix precedence in conditional expression to remove compiler
506	* warning.
507	*
508	* Rom_Devel_3128/1 2/3/11 8:01p mpovich
509	* SW3128-1: Fix precedence in conditional expression to remove compiler
510	* warning.
511	*
512	* 32 2/3/11 6:51p farshidf
513	* SW3128-1: update
514	*
515	* 31 2/3/11 6:46p cbrooks
516	* sw3128-1:new code
517	*
518	* 30 1/31/11 9:11p cbrooks
519	* sw3128-1:new test code
520	*
521	* 29 1/31/11 7:51p cbrooks
522	* sw3128-1:new code
523	*
524	* 27 1/30/11 6:40p cbrooks
525	* sw3128-1:new code
526	*
527	* 26 1/30/11 6:39p cbrooks
528	* sw3128-1:new code
529	*
530	* 25 1/30/11 6:35p cbrooks
531	* sw3128-1:FFT Code
532	*
533	* 24 1/28/11 3:42p farshidf
534	* SW3128-1: adapt the files to 3461
535	*
536	* 23 1/26/11 4:12p farshidf
537	* SW3128-1: clean up
538	*
539	* 22 1/26/11 3:28p cbrooks
540	* sw3128-1:Cleanup Code
541	*
542	* 21 1/25/11 9:29p cbrooks
543	* sw3128-1: Cleanup Code
544	*
545	* 20 1/21/11 6:12p farshidf
546	* SW3461-1: update names
547	*
548	* 19 1/17/11 1:24p cbrooks
549	* sw3128-1:New Code
550	*
551	* 18 12/22/10 2:21p farshidf
552	* SW3128-1: update
553	*
554	* 17 12/18/10 10:40a farshidf
555	* SW3128-1: update
556	*
557	* 16 12/17/10 4:16p farshidf
558	* SW3128-1: update
559	*
560	* 15 12/16/10 6:16p farshidf
561	* SW3128-1: clean up
562	*
563	* 14 12/15/10 5:42p cbrooks
564	* SW3128-1:New COde
565	*
566	* 13 12/15/10 4:32p cbrooks
567	* SW3128-1:new code
568	*
569	* 12 12/14/10 4:22p cbrooks
570	* SW3128-1: update
571	*
572	* 11 12/14/10 3:18p cbrooks
573	* SW3128-1:new code
574	*
575	* 10 12/14/10 2:34p farshidf
576	* SW3128-1: update
577	*
578	* 9 12/14/10 2:11p cbrooks
579	* SW3128-1:New Code
580	*
581	* 8 12/7/10 4:15p cbrooks
582	* SW3128-1:New Code
583	*
584	* 7 12/3/10 7:12p farshidf
585	* SW3128-1: update files
586	*
587	* 6 12/3/10 3:52p farshidf
588	* SW3128-1: clean up
589	*
590	* 5 12/1/10 3:21p cbrooks
591	* SW3128-1: ADS update
592	*
593	* 4 11/30/10 11:19a farshidf
594	* SW3461-1: add BMTH_2560log10 to math lib
595	*
596	* 3 11/24/10 9:36p cbrooks
597	* SW3128-1: Third Try
598	*
599	* 2 11/22/10 6:08p farshidf
600	* SW3128-1: remove old code
601	*
602	* 1 11/12/10 5:45p farshidf
603	* SW3128-1: add ADS code
604	*
605	***************************************************************************/
606	#include "bstd.h"
607	#include "bmth.h"
608	#include "bkni.h"
609	#ifdef LEAP_BASED_CODE
610	#include "btmr.h"
611	#include "bads_def.h"
612	#include "bads_irq.h"
613	#include "bchp_leap_ctrl.h"
614	#include "bchp_tm.h"
615	#if (BCHP_FAMILY==3128)
616	#include "bwfe_global_clk.h"
617	#include "bchp_ds_b_topm.h"
618	#include "bchp_ds_b_tops.h"
619	#include "bchp_ds_wfe_cz_0.h"
620	#define WFE 1
621	#define IMC 0
622	#define HRC 0
623	#endif
624	#if (BCHP_FAMILY==3461)
625	#include "btnr_global_clk.h"
626	#define WFE 0
627	#define IMC 1
628	#define HRC 0 /disabled and not used/
629	#endif
630	#else /* host chip based code */
631	#if (BCHP_CHIP==35233)
632	#include "bads_global_clk.h"
633	#define WFE 0
634	#define IMC 0
635	#define HRC 0
636	#endif
637	#if (BCHP_CHIP==7552)
638	#include "bads_global_clk.h"
639	#define WFE 0
640	#define IMC 0
641	#define HRC 0
642	#endif
643	#include "bads.h"
644	#include "bads_mth.h"
645	#endif /* host chip based code */
646
647	#include "bads_api.h"
648	#include "bads_acquire.h"
649	#include "bads_utils.h"
650	#include "bads_priv.h"
651	#include "bads_coef.h"
652	#include "bmth.h"
653	#include "bchp_ds_topm.h"
654
655
656
657	#if (BCHP_CHIP==35233)
658	#include "bads_global_clk.h"
659	#define WFE 0
660	#define IMC 0
661	#define HRC 0
662	#endif
663
664	/****************************************trick to get emulation to run/
665	#include "bchp_ds_tops.h"
666
667	/registers needed for the functions in this file/
668	#include "bchp_ds.h"
669
670	#ifndef LEAP_BASED_CODE
671	BDBG_MODULE(bads_acquire);
672	#endif
673
674
675	/*******************************************************************************************
676	*BADS_P_Initialize() This routine initializes the ADS and is only run once
677	*******************************************************************************************/
678	BERR_Code BADS_P_Initialize(BADS_3x7x_ChannelHandle hChn)
679	{
680	BERR_Code retCode = BERR_SUCCESS;
681
682	BDBG_MSG(("BADS_P_Initialize "));
683
684	/The BADS_Acquire_Params_t, BADS_AnnexA_Sym_Rate_t and BADS_Scan_Params_t structures are set by the PI/
685	/*Initialize the BADS_Internal_Params_t Structure
686	these parameters are used locally by BBS to sent parameters into the ADS functions/
687	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Rerun_Init = INIT_BBS_RERUN_INIT;
688	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AnnexA_Burst_Mode = INIT_BBS_ANNEXA_BURST_MODE;
689	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWCe = INIT_BBS_CWC;
690	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CFLe = INIT_BBS_CFL;
691	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CIP_CO_JamLoad = INIT_BBS_CIP_CO_JAMLOAD;
692	hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe = INIT_BBS_DDAGC;
693	hChn->pChnAcqParam->BADS_Internal_Params.BBS_IMCe = INIT_BBS_IMC;
694	hChn->pChnAcqParam->BADS_Internal_Params.BBS_IQPHSe = INIT_BBS_IQPHS;
695	hChn->pChnAcqParam->BADS_Internal_Params.BBS_IQIMBe = INIT_BBS_IQIMB;
696	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Sweep_Switch = INIT_BBS_SWEEP_SWITCH;
697	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Sweep_Neg2Pos_Invert = INIT_BBS_SWEEP_NEG2POS_INVERT;
698	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Acquisition_Test = INIT_BBS_ACQUISITION_TEST;
699	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag0 = INIT_BBS_UNUSED_FLAG0;
700	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag1 = INIT_BBS_UNUSED_FLAG1;
701	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag2 = INIT_BBS_UNUSED_FLAG2;
702	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag3 = INIT_BBS_UNUSED_FLAG3;
703	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag4 = INIT_BBS_UNUSED_FLAG4;
704	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag5 = INIT_BBS_UNUSED_FLAG5;
705	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag6 = INIT_BBS_UNUSED_FLAG6;
706	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag7 = INIT_BBS_UNUSED_FLAG7;
707	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan = INIT_BBS_TIMING_SCAN;
708	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Load = INIT_BBS_TIMING_SCAN_LOAD;
709	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan = INIT_BBS_CARRIER_SCAN;
710	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Load = INIT_BBS_CARRIER_SCAN_LOAD;
711	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Acquisition_Number = INIT_BBS_ACQUISITION_NUMBER;
712	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins = INIT_BBS_TIMING_SCAN_EXTRA_BINS;
713	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Extra_Bins = INIT_BBS_CARRIER_SCAN_EXTRA_BINS;
714	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent = INIT_BBS_TIMING_SCAN_PERCENT;
715	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Percent = INIT_BBS_CARRIER_SCAN_PERCENT;
716	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Threshold = INIT_BBS_TIMING_SCAN_THRESHOLD;
717	hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Threshold = INIT_BBS_CARRIER_SCAN_THRESHOLD;
718	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC1_Fin1 = INIT_BBS_CWC1_FIN1;
719	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC2_Fin2 = INIT_BBS_CWC2_FIN2;
720	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC3_Fin3 = INIT_BBS_CWC3_FIN3;
721	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC4_Fin4 = INIT_BBS_CWC4_FIN4;
722	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC1_Foffset1 = INIT_BBS_CWC1_FOFFSET1;
723	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC2_Foffset2 = INIT_BBS_CWC2_FOFFSET2;
724	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC3_Foffset3 = INIT_BBS_CWC3_FOFFSET3;
725	hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC4_Foffset4 = INIT_BBS_CWC4_FOFFSET4;
726	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord0 = INIT_BBS_ACQWORD0;
727	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord1 = INIT_BBS_ACQWORD1;
728	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord2 = INIT_BBS_ACQWORD2;
729	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord3 = INIT_BBS_ACQWORD3;
730	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord4 = INIT_BBS_ACQWORD4;
731	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord5 = INIT_BBS_ACQWORD5;
732	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord6 = INIT_BBS_ACQWORD6;
733	hChn->pChnAcqParam->BADS_Internal_Params.BBS_AcqWord7 = INIT_BBS_ACQWORD7;
734
735	/Initialize the BADS_Local_Params_t structure/
736
737	hChn->pChnAcqParam->BADS_Local_Params.AcqType = BADS_Local_Params_AcqType_eFastAcquire;
738	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eNoPower;
739	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search = 150000;
740	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = Q256_Q1024_ANNEXB_SYMBOL_RATE;
741	hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search = Q256_Q1024_ANNEXB_SYMBOL_RATE;
742	hChn->pChnAcqParam->BADS_Local_Params.Q1024A = false;
743	hChn->pChnAcqParam->BADS_Local_Params.Q512A = false;
744	hChn->pChnAcqParam->BADS_Local_Params.Q256A = false;
745	hChn->pChnAcqParam->BADS_Local_Params.Q256B = true;
746	hChn->pChnAcqParam->BADS_Local_Params.Q64A = false;
747	hChn->pChnAcqParam->BADS_Local_Params.Q64B = false;
748	hChn->pChnAcqParam->BADS_Local_Params.Q16A = false;
749	hChn->pChnAcqParam->BADS_Local_Params.Q128A = false;
750	hChn->pChnAcqParam->BADS_Local_Params.Q32A = false;
751	hChn->pChnAcqParam->BADS_Local_Params.Q1024B = false;
752	hChn->pChnAcqParam->BADS_Local_Params.Invert_Spectrum = false;
753	hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum = false;
754	hChn->pChnAcqParam->BADS_Local_Params.ChannelPower_x256 = 0;
755
756	hChn->pChnAcqParam->BADS_Local_Params.DoneFirstTimeFlag = BADS_Local_Params_eEnable;
757	hChn->pChnAcqParam->BADS_Local_Params.Annex = BADS_Local_Params_Annex_eAnnexB;
758	hChn->pChnAcqParam->BADS_Local_Params.QAM = BADS_Local_Params_QAM_eQam64;
759	hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 = 0;
760	hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 = 0;
761	hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 = 0;
762	hChn->pChnAcqParam->BADS_Local_Params.BadBlockCount = 0;
763	hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount = 0;
764	hChn->pChnAcqParam->BADS_Local_Params.TestLockFlag = BADS_Local_Params_eDisable;
765	hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum = BADS_Local_Params_FECSpectrum_eNotInverted;
766	hChn->pChnAcqParam->BADS_Local_Params.IfFrequency = IF_FREQUENCY;
767	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Offset = 0;
768	hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime = 0;
769	hChn->pChnAcqParam->BADS_Local_Params.TotalTime = 0;
770
771	/*The following were added for the api.c and will be initialized by the PI
772	hChn->pChnAcqParam->BADS_Local_Params.lock_status
773	hChn->pChnAcqParam->BADS_Local_Params.Acquire_done
774	hChn->pChnAcqParam->BADS_Local_Params.EarlyExit */
775
776	#if 0
777	hChn->pChnAcqParam->BADS_Scan_Params.AI = BADS_Scan_Params_eEnable;
778	hChn->pChnAcqParam->BADS_Scan_Params.QM = BADS_Scan_Params_eEnable;
779	hChn->pChnAcqParam->BADS_Scan_Params.CO = BADS_Scan_Params_eEnable;
780	hChn->pChnAcqParam->BADS_Scan_Params.TO = BADS_Scan_Params_eEnable;
781	hChn->pChnAcqParam->BADS_Scan_Params.B1024 = BADS_Scan_Params_eDisable;
782	hChn->pChnAcqParam->BADS_Scan_Params.B256 = BADS_Scan_Params_eEnable;
783	hChn->pChnAcqParam->BADS_Scan_Params.B64 = BADS_Scan_Params_eEnable;
784	hChn->pChnAcqParam->BADS_Scan_Params.A1024 = BADS_Scan_Params_eDisable;
785	hChn->pChnAcqParam->BADS_Scan_Params.A512 = BADS_Scan_Params_eDisable;
786	hChn->pChnAcqParam->BADS_Scan_Params.A256 = BADS_Scan_Params_eEnable;
787	hChn->pChnAcqParam->BADS_Scan_Params.A128 = BADS_Scan_Params_eEnable;
788	hChn->pChnAcqParam->BADS_Scan_Params.A64 = BADS_Scan_Params_eEnable;
789	hChn->pChnAcqParam->BADS_Scan_Params.A32 = BADS_Scan_Params_eEnable;
790	hChn->pChnAcqParam->BADS_Scan_Params.A16 = BADS_Scan_Params_eEnable;
791	hChn->pChnAcqParam->BADS_Scan_Params.Carrier_Search = 500000/256;
792	hChn->pChnAcqParam->BADS_Scan_Params.Upper_Baud_Search = 7300000;
793	hChn->pChnAcqParam->BADS_Scan_Params.Lower_Baud_Search = 4000000;
794
795	/*volatile BADS_AcquireStartMode_t AcquireStartMode;
796	uint32_t NexusStatusMode;*/
797	hChn->pChnAcqParam->BADS_Acquire_Params.AcqType = BADS_Acquire_Params_AcqType_eScan;
798	hChn->pChnAcqParam->BADS_Acquire_Params.Auto = BADS_Acquire_Params_eEnable;
799	hChn->pChnAcqParam->BADS_Acquire_Params.IS = BADS_Acquire_Params_eDisable;
800	hChn->pChnAcqParam->BADS_Acquire_Params.Annex = BADS_Acquire_Params_Annex_eAnnexB;
801	hChn->pChnAcqParam->BADS_Acquire_Params.Qam_Mode = BADS_Acquire_Params_BPS_eQam256;
802	hChn->pChnAcqParam->BADS_Acquire_Params.Carrier_Range = 150000/256;
803	hChn->pChnAcqParam->BADS_Acquire_Params.AnnexA_Sym_Rate = 5000000;
804	#endif
805
806	return retCode;
807	}
808
809	/*******************************************************************************************
810	* BADS_P_ChnLockStatus() This routine gets the lock status of the ADS
811	*******************************************************************************************/
812	BERR_Code BADS_P_ChnLockStatus(BADS_3x7x_ChannelHandle hChn)
813	{
814	BERR_Code retCode = BERR_SUCCESS;
815
816	/local variables/
817	BADS_3x7x_ChnLockStatus_UnlockLock_t QamStatus;
818	BADS_3x7x_ChnLockStatus_UnlockLock_t FECStatus;
819	BADS_3x7x_ChnLockStatus_UnlockLock_t CurrentFECStatus;
820
821	uint8_t ReSyncFlag;
822	uint32_t HighThresh, LowThresh, SNR;
823	uint32_t BMPG1, CBERC1, UERC1, NBERC1;
824
825	uint32_t ReadReg;
826
827	/BDBG_MSG(("BADS_P_ChnLockStatus "));/
828
829	/***************************/
830	/Determine QAM Lock Status/
831	/***************************/
832	HighThresh = BREG_ReadField(hChn->hRegister, DS_EQ_SNRHT, SNRHTHRESH);
833	LowThresh = BREG_ReadField(hChn->hRegister, DS_EQ_SNRLT, SNRLTHRESH);
834	SNR = BREG_ReadField(hChn->hRegister, DS_EQ_SNR, ERRVAL);
835
836	if ((SNR < HighThresh) && (SNR > LowThresh))
837	{
838	QamStatus = BADS_3x7x_ChnLockStatus_eLock;
839	}
840	else
841	{
842	QamStatus = BADS_3x7x_ChnLockStatus_eUnlock;
843	}
844
845	/assign values to the status structure to be read by BBS/
846	hChn->pChnLockStatus->QLK = QamStatus;
847
848
849	/***************************************/
850	/Determine SNR /
851	/BBS will divide by 256 to get dB /
852	/***************************************/
853	/SNR in dB is different for each QAM Mode/
854	/16 QAM 125.4405 dB - 20log(ERRVAL) or if scaled by 256: 32113-5120log(ERRVAL)/
855	/32 QAM 122.4302 dB - 20log(ERRVAL) or if scaled by 256: 31342-5120log(ERRVAL)/
856	/64 QAM 125.6524 dB - 20log(ERRVAL) or if scaled by 256: 32167-5120log(ERRVAL)/
857	/128 QAM 122.5374 dB - 20log(ERRVAL) or if scaled by 256: 31370-5120log(ERRVAL)/
858	/256 QAM 125.7038 dB - 20log(ERRVAL) or if scaled by 256: 32180-5120log(ERRVAL)/
859	/512 QAM 122.5638 dB - 20log(ERRVAL) or if scaled by 256: 31376-5120log(ERRVAL)/
860	/1024 QAM 125.7138 dB - 20log(ERRVAL) or if scaled by 256: 32183-5120log(ERRVAL)/
861
862	/SNR/
863	ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_FECL);
864	ReadReg = (ReadReg & 0x000000F0)>>4;
865
866	switch (ReadReg)
867	{
868	case 3: hChn->pChnLockStatus->SNR = 32113 - (BMTH_2560log10(SNR)<<1); break; /16 QAM Mode/
869	case 4: hChn->pChnLockStatus->SNR = 31342 - (BMTH_2560log10(SNR)<<1); break; /32 QAM Mode/
870	case 5: hChn->pChnLockStatus->SNR = 32167 - (BMTH_2560log10(SNR)<<1); break; /64 QAM Mode/
871	case 6: hChn->pChnLockStatus->SNR = 31370 - (BMTH_2560log10(SNR)<<1); break; /128 QAM Mode/
872	case 7: hChn->pChnLockStatus->SNR = 32180 - (BMTH_2560log10(SNR)<<1); break; /256 QAM Mode/
873	case 8: hChn->pChnLockStatus->SNR = 31376 - (BMTH_2560log10(SNR)<<1); break; /512 QAM Mode/
874	case 9: hChn->pChnLockStatus->SNR = 32183 - (BMTH_2560log10(SNR)<<1); break; /1024 QAM Mode/
875	default: BDBG_MSG(("WARNING!!! UNSUPPORTED OR UNDEFINED QAM_MODE")); break;
876	}
877
878	/SNR AVERAGE/
879	/BBS will divide by 256 to get dB/
880	if (hChn->pChnLockStatus->SNRAVG == 0) /reset check/
881	{
882	hChn->pChnLockStatus->SNRAVG = hChn->pChnLockStatus->SNR;
883	}
884	else
885	{
886	hChn->pChnLockStatus->SNRAVG = ((hChn->pChnLockStatus->SNR(SNR_LEAKY_AVG)) + (16384-(SNR_LEAKY_AVG))hChn->pChnLockStatus->SNRAVG)/16384;
887	}
888
889
890	/***************************/
891	/Determine FEC Lock Status/
892	/***************************/
893
894	/clear the MPEG bad block resync flag /
895	ReSyncFlag = 0;
896
897	/Get the currect lock condition/
898	CurrentFECStatus = hChn->pChnLockStatus->FLK;
899
900	/Get the latest block error counter values/
901	BMPG1 = BREG_ReadField(hChn->hRegister, DS_BMPG1, BMPGCNTVAL);
902	CBERC1 = BREG_ReadField(hChn->hRegister, DS_CBERC1, CBERCCNTVAL);
903	UERC1 = BREG_ReadField(hChn->hRegister, DS_UERC1, UERCCNTVAL);
904	NBERC1 = BREG_ReadField(hChn->hRegister, DS_NBERC1, NBERCCNTVAL);
905
906
907	/Check for at least one good block since the last call which is 25 mS/
908	if ((NBERC1 - hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1) >= NUM_CLEAN_BLOCKS_TO_LOCK)
909	{
910	/If Annex B then check for MPEG Checksum False Sync/
911	/This is and implementation from Jorge's BCM3250/7015/7100 App note/
912	/Document 3250/7015/7100-An01-R/
913	if ((BMPG1 > 10) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexB))
914	{
915	if ((10UERC1 < 4BMPG1) \|\| (3UERC1 > 5BMPG1))
916	{
917	/resync FEC, false MPEG Lock detected/
918	/BDBG_MSG(("QAM AnnexB FEC detected an MPEG Checksum False Sync, staying locked but Resyncing FEC"));/
919	ReSyncFlag = 1;
920	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 1);
921	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 0);
922	hChn->pChnLockStatus->ReSync_Count++;
923	}
924	}
925	/Reset Bad Block Counter/
926	hChn->pChnAcqParam->BADS_Local_Params.BadBlockCount = 0;
927
928	/Declare Lock/
929	FECStatus = BADS_3x7x_ChnLockStatus_eLock;
930
931	/BDBG_MSG(("LOCK1"));/
932	}
933	else
934	{
935	/Wait for NUM_BAD_BLOCK_TO_UNLOCK bad blocks without a good one to declare unlock/
936	if((UERC1 - hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 + hChn->pChnAcqParam->BADS_Local_Params.BadBlockCount) > NUM_BAD_BLOCK_TO_UNLOCK)
937	{
938
939	/Reset Bad Block Counter/
940	hChn->pChnAcqParam->BADS_Local_Params.BadBlockCount = 0;
941
942	/Declare UnLock/
943	FECStatus = BADS_3x7x_ChnLockStatus_eUnlock;
944
945	/BDBG_MSG((" UNLOCK1"));/
946	}
947	else
948	{
949	if (CurrentFECStatus == BADS_3x7x_ChnLockStatus_eUnlock)
950	{
951	/Declare UnLock/
952	FECStatus = BADS_3x7x_ChnLockStatus_eUnlock;
953	}
954	else
955	{
956	/BDBG_MSG((" UNLOCK2"));/
957	/NUM_BAD_BLOCK_TO_UNLOCK bad blocks did not come along without a good one so wait until next call/
958	/increment bad block counter/
959	hChn->pChnAcqParam->BADS_Local_Params.BadBlockCount += (UERC1 - hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1);
960
961	/Declare Lock/
962	FECStatus = BADS_3x7x_ChnLockStatus_eLock;
963	/BDBG_MSG((" Keep LOCK2"));/
964	}
965	}
966	}
967
968	/Check for stuck FEC condition, all counters did not move since the last call to BADS_75xx_P_Get_LockStatus()/
969	if ((CBERC1 - hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 == 0) && (UERC1 - hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 == 0) &&
970	(NBERC1 - hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 == 0))
971	{
972	if ((hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount >= STUCK_FEC_RESET_COUNT) \|\| (CurrentFECStatus == BADS_3x7x_ChnLockStatus_eUnlock))
973	{
974	/Reset Counters/
975	hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount = 0;
976	hChn->pChnAcqParam->BADS_Local_Params.BadBlockCount = 0;
977
978	/Declare UnLock/
979	FECStatus = BADS_3x7x_ChnLockStatus_eUnlock;
980	/BDBG_MSG(("QAM FEC is stuck, declare an unlock condition"));/
981	}
982	else
983	{
984	hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount++;
985	/BDBG_MSG(("QAM FEC is stuck, Count = %d",h->pAcquireParam->StuckFECCount));/
986	}
987	}
988
989
990	/store counter values for the next call/
991	hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 = CBERC1;
992	hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 = UERC1;
993	hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 = NBERC1;
994
995	/clear FEC counters to prevent overflow/
996	/Resync The FEC for bad MPEG packet count/
997	/Reset FEC Counters/
998	if ((BMPG1 > POWER2_31) \|\| (CBERC1 > POWER2_31) \|\| (UERC1 > POWER2_31) \|\| (NBERC1 > POWER2_31) \|\| (ReSyncFlag == 1))
999	{
1000	BDBG_MSG((" RESYNCING"));
1001	ReSyncFlag = 0;
1002	BREG_Write32(hChn->hRegister, BCHP_DS_TPFEC, 0x000F8000);
1003	hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 = 0;
1004	hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 = 0;
1005	hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 = 0;
1006	}
1007
1008
1009	if (hChn->pChnAcqParam->BADS_Local_Params.TestLockFlag == BADS_Local_Params_eEnable)
1010	{
1011	FECStatus = BADS_3x7x_ChnLockStatus_eUnlock;
1012	}
1013
1014	/assign values to the status structure to be read by BBS AND used by the PI/
1015	hChn->pChnLockStatus->FLK = FECStatus;
1016
1017	/Hack for counter/
1018	if (hChn->pChnLockStatus->ReAck_Count == 0)
1019	{
1020	hChn->pChnLockStatus->ReAcquire_Count = 0;
1021	}
1022
1023	/LockStatus Complete/
1024	return retCode;
1025	}
1026
1027	/***************************************************************************
1028	* BADS_P_Acquire()
1029	***************************************************************************/
1030	BERR_Code BADS_P_Acquire(BADS_3x7x_ChannelHandle hChn)
1031	{
1032	BERR_Code retCode = BERR_SUCCESS;
1033	bool EarlyExit;
1034	uint8_t index,RetryIndex,RetryIndexEnd;
1035	uint8_t BaudIndex, BaudIndexStart=0, BaudIndexEnd=0, CarrierIndex, CarrierIndexEnd, EQIndex, EQIndexEnd=0;
1036	int32_t IF_Freq;
1037	uint32_t CarrierStepSize;
1038	int32_t CarrierOffset=0;
1039	int16_t Power_Check;
1040	uint32_t ReadReg;
1041	uint32_t FFT_TimingFreq=0,FFT_TimingBin=0;
1042	int32_t Carrier_Error=0, Symbol_Rate=0, Phase_Error1, Phase_Error2;
1043	uint32_t EQ[144];
1044	uint8_t QamIndex=0;
1045	bool QamTry;
1046	uint32_t FFE_Scale;
1047	int32_t FFE_I=0;
1048	int32_t FFE_Q=0;
1049	uint32_t FFE_Scaled_Value;
1050	uint8_t FECIndex=0, FECIndexEnd=0;
1051	bool FECTry;
1052	uint8_t FEC_TimeOut;
1053	uint8_t CWC_Length;
1054	uint32_t StartTime, EndTime, ElapsedTime;
1055
1056	/********************************/
1057
1058	BADS_P_AdsCallbackData_t CallbackFrontend;
1059	/********************************/
1060
1061	BDBG_MSG(("BADS_P_Acquire "));
1062	BTMR_ReadTimer(hChn->hAds->hStatusTimer, &StartTime);
1063
1064	/* Reset the Early Exit flag when acquire is just starting */
1065	hChn->pChnAcqParam->BADS_Local_Params.EarlyExit = false;
1066
1067	/Check for number of retries when Auto Acquire is on/
1068	RetryIndexEnd = 0;
1069	if (hChn->pChnAcqParam->BADS_Acquire_Params.Auto == BADS_Acquire_Params_eEnable)
1070	{
1071	switch (hChn->pChnAcqParam->BADS_Acquire_Params.AcqType)
1072	{
1073	case BADS_Acquire_Params_AcqType_eAuto : RetryIndexEnd = NUM_RETRIES_IF_AUTOACQUIRE_AND_AUTOSELECT; break;
1074	case BADS_Acquire_Params_AcqType_eFast : RetryIndexEnd = NUM_RETRIES_IF_AUTOACQUIRE_AND_FAST; break;
1075	case BADS_Acquire_Params_AcqType_eSlow : RetryIndexEnd = NUM_RETRIES_IF_AUTOACQUIRE_AND_SLOW; break;
1076	case BADS_Acquire_Params_AcqType_eScan : RetryIndexEnd = NUM_RETRIES_IF_AUTOACQUIRE_AND_SCAN; break;
1077	default: BDBG_ERR(("ERROR!!! Undefined AcqType in BADS_P_Acquire() %d",hChn->pChnAcqParam->BADS_Acquire_Params.AcqType)); break;
1078	}
1079	}
1080
1081	for (RetryIndex=0;RetryIndex<=RetryIndexEnd;RetryIndex++)
1082	{
1083	if (PRINT_DEBUG==1) BDBG_ERR(("RetryIndex = %d RetryIndexEnd = %d",RetryIndex, RetryIndexEnd));
1084
1085	/Loop each unlock retry attempt/
1086	if (hChn->pChnLockStatus->ReAck_Count == 0)
1087	{
1088	hChn->pChnAcqParam->BADS_Local_Params.TotalTime = 0;
1089	}
1090
1091	/Begin by being unlocked, increment ReAck counter, clear test lock flag used by BADS_P_AcquisitionPercentageTest()/
1092	hChn->pChnLockStatus->FLK = BADS_3x7x_ChnLockStatus_eUnlock;
1093	hChn->pChnLockStatus->QLK = BADS_3x7x_ChnLockStatus_eUnlock;
1094	hChn->pChnLockStatus->ReAck_Count++;
1095	hChn->pChnLockStatus->ReAcquire_Count++;
1096	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eNoPower;
1097	hChn->pChnAcqParam->BADS_Local_Params.TestLockFlag = BADS_Local_Params_eDisable;
1098
1099	/Reset FEC Counters and hold FEC in reset/
1100	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 1);
1101	BREG_Write32(hChn->hRegister, BCHP_DS_TPFEC, 0x000F9F00);
1102	hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 = 0;
1103	hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 = 0;
1104	hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 = 0;
1105	hChn->pChnLockStatus->ReSync_Count = 0;
1106	hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount = STUCK_FEC_RESET_COUNT;
1107
1108	/*Check if this is the first time to call acquire
1109	*The BADS_P_Initialize() will set the DoneFirstTimeFlag to BADS_Local_Params_eEnable
1110	The BADS_P_Initialize() will set the BBS_Rerun_Init to INIT_BBS_RERUN_INIT/
1111	if ((hChn->pChnAcqParam->BADS_Local_Params.DoneFirstTimeFlag == BADS_Local_Params_eDisable) \|\|
1112	(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Rerun_Init == BADS_Internal_Params_eEnable))
1113	{
1114	BADS_P_Initialize(hChn);
1115
1116	/This is for the acquisition test/
1117	BREG_Write32(hChn->hRegister, BCHP_DS_SPARE, 0);
1118	}
1119
1120	/*Range Check the Inputs
1121	*Map hChn->pChnAcqParam->BADS_Acquire_Params.Qam_Mode to hChn->pChnAcqParam->BADS_Local_Params.QAM
1122	*Map hChn->pChnAcqParam->BADS_Acquire_Params.Annex to hChn->pChnAcqParam->BADS_Local_Params.Annex
1123	This is done because the scan may change the Qam mode and Annex while searching/
1124	retCode = BADS_P_Range_Check(hChn);
1125	if (retCode != BERR_SUCCESS) goto something_bad_happened; /goto bottom of function to return error code/
1126
1127
1128
1129	/*************************************************************************************************************
1130	*BEGIN INITIALIZATION
1131	*************************************************************************************************************/
1132
1133
1134
1135
1136
1137
1138	/reset ADS core/
1139	/start with loops frozen/
1140	#if WFE
1141	BREG_Write32(hChn->hRegister, BCHP_DS_RST, 0x8006B679);
1142	BREG_Write32(hChn->hRegister, BCHP_DS_FRZ, 0x027FE78A);
1143	#else
1144	#if IMC
1145	BREG_Write32(hChn->hRegister, BCHP_DS_RST, 0x8017B679);
1146	BREG_Write32(hChn->hRegister, BCHP_DS_FRZ, 0x0B7FE78A);
1147	/Initailize and reset IMC: frozen by DS_FRZ/
1148	BREG_WriteField(hChn->hRegister, DS_EQ_CTL, IMC_EN, 0);
1149	BREG_WriteField(hChn->hRegister, DS_EQ_IMC, RESET, 1);
1150	/IF IF_FREQUENCY >= 1 MHz assume external tuner, automatically disable IMC and IQ_IMB/
1151	if ((hChn->pChnAcqParam->BADS_Local_Params.IfFrequency < 1000000) && (hChn->pChnAcqParam->BADS_Local_Params.IfFrequency > -1000000))
1152	{
1153	hChn->pChnAcqParam->BADS_Internal_Params.BBS_IMCe = BADS_Internal_Params_eEnable;
1154	}
1155	else
1156	{
1157	hChn->pChnAcqParam->BADS_Internal_Params.BBS_IMCe = BADS_Internal_Params_eDisable;
1158	}
1159	#else
1160	BREG_Write32(hChn->hRegister, BCHP_DS_RST, 0x8006B679);
1161	BREG_Write32(hChn->hRegister, BCHP_DS_FRZ, 0x027FE78A);
1162	#endif
1163	#endif
1164
1165	BREG_Write32(hChn->hRegister, BCHP_DS_CLK, 0x00000400); /Enable dedicated parallel/serial output clock/
1166	BREG_WriteField(hChn->hRegister, DS_ICB_CTL, BUS_ERR_EN, 0); /Internal Configuration Bus Control and Status and Stops bus errors/
1167
1168
1169	/Setup AGCB and AGCB_IR: frozen by DS_FRZ/
1170	BREG_Write32(hChn->hRegister, BCHP_DS_AGCB, 0x0a001201); /BW=2^-13, TH=1.0, Reset AGCB/
1171	BREG_Write32(hChn->hRegister, BCHP_DS_AGCBI, 0x03F00000);
1172	#if IMC
1173	BREG_Write32(hChn->hRegister, BCHP_DS_AGCB_IR, 0x0a001201);
1174	BREG_Write32(hChn->hRegister, BCHP_DS_AGCBI_IR , 0x03F00000);
1175	#endif
1176
1177
1178	/*************************************************************************************************************/
1179	/INITIALIZATION FINISHED: BEGIN ACQUISITION/
1180	/*************************************************************************************************************/
1181
1182
1183	/Release DPM_DC_Second_Order/AGF/AGCB/AGCB_IR loops/
1184	BREG_WriteField(hChn->hRegister, DS_FRZ, AGCBFRZ, 0); /Release AGCB/
1185	#if IMC
1186	BREG_WriteField(hChn->hRegister, DS_FRZ, AGCBFRZ_IR, 0); /Release AGCB Freeze for IMC path/
1187	#endif
1188
1189	/wait for AGCB/AGCB_IR to settle/
1190	EarlyExit = BADS_P_ADS_SLEEP(hChn, AGC_TIME_SAMPLES*1000/F_HS + 1);
1191	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1192
1193	/Reduce AGF/AGCB/AGCB_IR bandwidth to tracking values/
1194	BREG_WriteField(hChn->hRegister, DS_AGCB, AGCBBW, 0xf); /Reduce AGCB BW 2^-16/
1195	#if IMC
1196	#if BCHP_DS_CORE_V_9_1
1197	BREG_WriteField(hChn->hRegister, DS_AGCB_IR, AGCBBW_IR, 0xf); /Reduce AGCB_IR BW 2^-16/
1198	#elif (BCHP_DS_CORE_V_9_2)
1199	BREG_WriteField(hChn->hRegister, DS_AGCB_IR, AGCBBW, 0xf); /Reduce AGCB_IR BW 2^-16/
1200	#endif
1201	#endif
1202
1203	/Determine Acquisition Type and Parameters/
1204	BADS_P_Get_AcquisitionScan_Settings(hChn);
1205
1206	/Setup the Baud Steps Start and End index/
1207	index = 0;
1208	BaudIndexStart = 0;
1209	BaudIndexEnd = 0;
1210	while (index < NUM_BAUD_RATES)
1211	{
1212	if (hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search <= BaudRates_TBL[index])
1213	{
1214	BaudIndexStart = index;
1215	}
1216	if (hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search <= BaudRates_TBL[index])
1217	{
1218	BaudIndexEnd = index;
1219	}
1220	index++;
1221	}
1222
1223	/Check to see if we should leave the acquisition early due to low channel power/
1224	/This is using the lowest power QAM mode for the highest baud rate/
1225	Power_Check = ((int16_t)ChannelNoisePower_TBL[BaudIndexEnd] + SYSTEM_NF + REQUIRED_SNR16Q);
1226	Power_Check = BADS_P_Scale_Power_Check(hChn, Power_Check);
1227	BADS_P_Get_ChannelPower(hChn);
1228	ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_AGCBI);
1229	/*
1230	if ((hChn->pChnAcqParam->BADS_Local_Params.ChannelPower_x256 < 256*Power_Check) \|\| (ReadReg > AGCBI_MAX_VALUE))
1231	{
1232	//leave function if locked, this is not an Early Exit but a normal exit
1233	EarlyExit = false;
1234	goto please_leave_early; //goto bottom of function to leave early
1235	}
1236	*/
1237
1238	/Loop each Baud Rate/
1239	for (BaudIndex=BaudIndexStart;BaudIndex<=BaudIndexEnd;BaudIndex++)
1240	{
1241	if (PRINT_DEBUG==1) BDBG_ERR(("BaudIndex = %d BaudIndexStart = %d BaudIndexEnd = %d",BaudIndex,BaudIndexStart, BaudIndexEnd));
1242
1243	/Setup the Carrier Steps to find the Baud Rate, Pre-Filter/Nyquist filter BW limits the baud loop detection range/
1244	/Number of steps will always be odd with first step centered at 0 carrier offset/
1245	CarrierIndexEnd = 2hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search1000/(PRE_NYQUIST_FILTER_BW_1MHZ*BaudRates_TBL[BaudIndex]);
1246	CarrierIndexEnd = (CarrierIndexEnd%2) ? CarrierIndexEnd + 1 : CarrierIndexEnd;
1247	CarrierStepSize = (CarrierIndexEnd == 0) ? 0 : (hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search - (PRE_NYQUIST_FILTER_BW_1MHZ*BaudRates_TBL[BaudIndex]/2000))/(CarrierIndexEnd/2);
1248
1249	/Loop each CarrierOffset/
1250	for (CarrierIndex=0;CarrierIndex<=CarrierIndexEnd;CarrierIndex++)
1251	{
1252	CarrierOffset = (CarrierIndex%2 == 0) ? CarrierIndex/2 : (-1-CarrierIndex)/2;
1253	CarrierOffset = CarrierOffset*(int32_t)CarrierStepSize;
1254	if (PRINT_DEBUG==1) BDBG_ERR(("CarrierIndex = %d CarrierOffset = %d CarrierIndexEnd = %d",CarrierIndex, CarrierIndexEnd,CarrierOffset));
1255
1256	/Check to see if we should leave this BaudRate/CarrierOffset early due to low channel power/
1257	/This is using the lowest QAM constellation selected for each baud rate/
1258	Power_Check = ((int16_t)ChannelNoisePower_TBL[BaudIndex] + SYSTEM_NF + REQUIRED_SNR16Q);
1259	Power_Check = BADS_P_Scale_Power_Check(hChn, Power_Check);
1260	BADS_P_Get_ChannelPower(hChn);
1261	ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_AGCBI);
1262	/*
1263	if ((hChn->pChnAcqParam->BADS_Local_Params.ChannelPower_x256 < 256*Power_Check) \|\| (ReadReg > AGCBI_MAX_VALUE))
1264	{
1265	CarrierIndex=CarrierIndexEnd+1;
1266	BDBG_ERR(("hChn->pChnAcqParam->BADS_Local_Params.ChannelPower_x256= %d BCHP_DS_AGCBI= %#8x",hChn->pChnAcqParam->BADS_Local_Params.ChannelPower_x256,ReadReg));
1267	}
1268	*/
1269
1270	/Bypass rest of check if CarrierIndex=CarrierIndexEnd+1/
1271	if (CarrierIndex<=CarrierIndexEnd)
1272	{
1273
1274	/Reset CFL:/
1275	IF_Freq = -1*hChn->pChnAcqParam->BADS_Local_Params.IfFrequency;
1276	BREG_WriteField(hChn->hRegister, DS_FRZ, CFLFRZ, 1);
1277	BREG_Write32(hChn->hRegister, BCHP_DS_CFLI, 0);
1278	BREG_WriteField(hChn->hRegister, DS_CFL, CFLRST, 0x00000001);
1279	BADS_P_Set_CFL_Frequency(hChn, IF_Freq);
1280
1281	/Reset TL:/
1282	BREG_WriteField(hChn->hRegister, DS_FRZ, TLFRZ, 1);
1283	BREG_WriteField(hChn->hRegister, DS_TLI, TLVAL, 0);
1284	/FOI Timing Loop Setup or Transition Tracker Setup/
1285	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag5 == BADS_Internal_Params_eEnable)
1286	{
1287	BREG_Write32(hChn->hRegister, BCHP_DS_TL , 0x00000609); /Full precision PD, Enable BaseBand, reset TL/
1288	BREG_Write32(hChn->hRegister, BCHP_DS_TLC , 0x00440000);
1289	BREG_Write32(hChn->hRegister, BCHP_DS_TLAGCI , 0x06000000); /Set Timing Loop AGC to Gain 768x/
1290	}
1291	else
1292	{
1293	BREG_Write32(hChn->hRegister, BCHP_DS_TLAGCI , 0x00100000); /Set Timing Loop AGC to Gain 8x/
1294	BREG_Write32(hChn->hRegister, BCHP_DS_TL , 0x00000089); /Full precision PD, Enable Transition Tracker, reset TL/
1295	}
1296
1297	BADS_P_Set_TL_Frequency(hChn, BaudRates_TBL[BaudIndex]);
1298
1299	/Setup Frontmost Mixer Loop/
1300	/This callback function sets the frequency offset in the CIP/
1301
1302	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag6 == BADS_Internal_Params_eEnable)
1303	{
1304	CallbackFrontend.hTunerChn = (hChn->pCallbackParam[BADS_Callback_eTuner]);
1305	CallbackFrontend.Freq_Offset = CarrierOffset;
1306	CallbackFrontend.Symbol_Rate = BaudRates_TBL[BaudIndex];
1307	CallbackFrontend.Mode = BADS_CallbackMode_eSetMode;
1308	BKNI_EnterCriticalSection();
1309	(hChn->pCallback[BADS_Callback_eTuner])(&CallbackFrontend);
1310	BKNI_LeaveCriticalSection();
1311	}
1312	else
1313	{
1314	BADS_P_Set_CFL_Frequency(hChn, IF_Freq-CarrierOffset);
1315	}
1316
1317
1318	/Attempt to get Timing Lock for this BaudRates_TBL[BaudIndex] and CarrierOffset/
1319	#if BCHP_DS_CORE_V_9_1
1320	FFT_TimingFreq = BADS_P_Get_TimingScan_FFT(hChn, BaudRates_TBL[BaudIndex], false);
1321	#elif ((BCHP_DS_CORE_V_9_2) \|\| (BCHP_DS_CORE_V_9_3))
1322	FFT_TimingFreq = BADS_P_Get_TimingScan_Advanced_FFT(hChn, BaudRates_TBL[BaudIndex], false);
1323	#endif
1324	if (PRINT_DEBUG==1) BDBG_ERR(("IF_Freq = %d CarrierOffset = %d FFT_TimingFreq = %d",IF_Freq, CarrierIndexEnd,FFT_TimingFreq));
1325
1326	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eNoTiming;
1327	if (FFT_TimingFreq !=0)
1328	{
1329
1330	/Start timing loop with Trk1 coefficients/
1331	BREG_WriteField(hChn->hRegister, DS_TLC, COMBO_COEFFS, TimingLoopTrk1Coeffs_TBL[BaudIndex]);
1332	BADS_P_Set_TL_Frequency(hChn, FFT_TimingFreq);
1333	BREG_WriteField(hChn->hRegister, DS_TLI, TLVAL, 0);
1334	BREG_WriteField(hChn->hRegister, DS_FRZ, TLFRZ, 0);
1335	EarlyExit = BADS_P_ADS_SLEEP(hChn, TL_TIME_MED_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1336	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1337
1338	/Reduce timing loop coefficients to tracking bandwidths and wait/
1339	BREG_WriteField(hChn->hRegister, DS_TLC, COMBO_COEFFS, TimingLoopTrk2Coeffs_TBL[BaudIndex]);
1340	EarlyExit = BADS_P_ADS_SLEEP(hChn, TL_TIME_LOW_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1341	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1342
1343	/Check if timing is locked/
1344	#if BCHP_DS_CORE_V_9_1
1345	FFT_TimingBin = BADS_P_Get_TimingScan_FFT(hChn, BaudRates_TBL[BaudIndex], true);
1346	#elif ((BCHP_DS_CORE_V_9_2) \|\| (BCHP_DS_CORE_V_9_3))
1347	FFT_TimingBin = BADS_P_Get_TimingScan_Advanced_FFT(hChn, BaudRates_TBL[BaudIndex], true);
1348	#endif
1349
1350
1351	/Debug print/
1352	if (PRINT_DEBUG==1) BDBG_ERR(("FFT_TimingFreq = %d FFT_TimingBin = %d",FFT_TimingFreq, FFT_TimingBin));
1353
1354	/If timing is locked try to get carrier/
1355	if (FFT_TimingBin == 2048)
1356	{
1357
1358	/Reset Equalizer/
1359	/The Equalizer Initial Settings are in a Lookup Table in acquire.h/
1360	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CTL, DS_EQ_CTL_TBL[BADS_Local_Params_QAM_eQam256]);
1361
1362	/Reset FFE:/
1363	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FFE, 0x11101119); /Main tap at tap 17, length = 36 taps, main mu = 2^-6, other mu = 2^-8, update at symbol rate/
1364	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FFEU17, 0x30000000); /Initialize Main Tap 18/
1365	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_LEAK, 0x00000000); /no leakage/
1366	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FMTHR, 0x00000020); /set main tap threshhold to gen IRQ/
1367
1368	/Reset DFE:/
1369	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_DFE, 0x00001829); /DFE length = 36 taps, mu = 2^-8, reset taps/
1370
1371	/Reset CWC:/
1372	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC, 0xFF0000F0);
1373
1374	/Release Equalizer FFE, FFE Main Tap Real and ONLY THE NON_OVERLAP DFE taps/
1375	BREG_WriteField(hChn->hRegister, DS_FRZ, FFEFRZ, 0);
1376	BREG_WriteField(hChn->hRegister, DS_FRZ, FFRZMR, 0);
1377	BREG_WriteField(hChn->hRegister, DS_FRZ, DFEFRZ19_24, 0);
1378	BREG_WriteField(hChn->hRegister, DS_FRZ, DFEFRZ25_30, 0);
1379	BREG_WriteField(hChn->hRegister, DS_FRZ, DFEFRZ31_36, 0);
1380
1381	/Wait for FFE/DFE to open eye/
1382	/This is the first pass of the EQ in CMA mode without HUM-AGC/
1383	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_BLIND1_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1384	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1385
1386	/Reduce FFE Mu's /
1387	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, MAINSTEP, 0x2); /main mu = 2^-8/
1388	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, STEP, 0x3); /other mu = 2^-10/
1389
1390	/Wait for FFE/DFE to open eye some more/
1391	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_BLIND2_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1392	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1393
1394	/Freeze Equalizer to read coeffs/
1395	BREG_WriteField(hChn->hRegister, DS_FRZ, FFEFRZ, 1);
1396	BREG_WriteField(hChn->hRegister, DS_FRZ, FFRZMR, 1);
1397	BREG_WriteField(hChn->hRegister, DS_FRZ, COMBO_DFEFRZ, 0x3F);
1398
1399	/*******************************************************************/
1400	/Hack1 alert for non-square constellations carrier FFT is clipping/
1401	/*******************************************************************/
1402	/Replace this with calculation/
1403	if ((hChn->pChnAcqParam->BADS_Local_Params.Q128A == true) \|\| (hChn->pChnAcqParam->BADS_Local_Params.Q32A == true))
1404	{
1405	BREG_Write32(hChn->hRegister, BCHP_DS_AGCB, 0x00401201); /BW=2^-13, TH=1.0, Reset AGCB/
1406	EarlyExit = BADS_P_ADS_SLEEP(hChn, 10);
1407	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1408	}
1409
1410	Symbol_Rate = FFT_TimingFreq + BADS_P_Get_VID_Error(hChn);
1411	#if BCHP_DS_CORE_V_9_1
1412	Carrier_Error = BADS_P_Get_CarrierScan_FFT(hChn, Symbol_Rate, 1);
1413	#elif ((BCHP_DS_CORE_V_9_2) \|\| (BCHP_DS_CORE_V_9_3))
1414	Carrier_Error = BADS_P_Get_CarrierScan_Advanced_FFT(hChn, Symbol_Rate, 1);
1415	#endif
1416	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Offset = IF_Freq-CarrierOffset-Carrier_Error;
1417
1418	/Debug print/
1419	if (PRINT_DEBUG==1) BDBG_ERR(("Symbol_Rate = %d CarrierOffset = %d Carrier_Error = %d",Symbol_Rate,CarrierOffset,Carrier_Error));
1420
1421	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag6 == BADS_Internal_Params_eEnable)
1422	{
1423	CallbackFrontend.hTunerChn = (hChn->pCallbackParam[BADS_Callback_eTuner]);
1424	CallbackFrontend.Freq_Offset = (CarrierOffset+Carrier_Error);
1425	CallbackFrontend.Symbol_Rate = 1; /This used to be Symbol_Rate but that caused dropouts in 3461/
1426	CallbackFrontend.Mode = BADS_CallbackMode_eSetMode;
1427	BKNI_EnterCriticalSection();
1428	(hChn->pCallback[BADS_Callback_eTuner])(&CallbackFrontend);
1429	BKNI_LeaveCriticalSection();
1430	}
1431	else
1432	{
1433	BADS_P_Set_CFL_Frequency(hChn, (IF_Freq-CarrierOffset-Carrier_Error));
1434	}
1435
1436
1437
1438	/*******************************************************************/
1439	/Hack1 alert for non-square constellations carrier FFT is clipping/
1440	/*******************************************************************/
1441	/Replace this with calculation/
1442	if ((hChn->pChnAcqParam->BADS_Local_Params.Q128A == true) \|\| (hChn->pChnAcqParam->BADS_Local_Params.Q32A == true))
1443	{
1444	BREG_Write32(hChn->hRegister, BCHP_DS_AGCB, 0x0A001201);
1445	EarlyExit = BADS_P_ADS_SLEEP(hChn, 10);
1446	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1447	}
1448
1449	/**********************************************************************/
1450	/At this point the FFT has found the Timing Offset and Carrier Offset/
1451	/**********************************************************************/
1452
1453	/Allow for fast/slow scan/
1454	if ((hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag4 == BADS_Internal_Params_eEnable) &&
1455	((hChn->pChnAcqParam->BADS_Local_Params.AcqType == BADS_Local_Params_AcqType_eScan) \|\|
1456	(hChn->pChnAcqParam->BADS_Local_Params.AcqType == BADS_Local_Params_AcqType_eSlowAcquireScan)))
1457	{
1458	EQIndexEnd =1; /Two passes: Fast EQ Convergence followed by Slow EQ Convergence during non-directed acquisitions/
1459	}
1460	else
1461	{
1462	EQIndexEnd =0; /One pass:Fast or slow during directed acquisitions/
1463	}
1464
1465	for (EQIndex=0;EQIndex<=EQIndexEnd;EQIndex++)
1466	{
1467
1468	/Debug print/
1469	if (PRINT_DEBUG==1) BDBG_ERR(("EQIndex = %d EQIndex = %d",EQIndex,EQIndex));
1470
1471	/Reset Equalizer here since the EQ solution with carrier offset may not be right/
1472	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FFE, 0x11101119); /Main tap at tap 17, length = 36 taps, main mu = 2^-6, other mu = 2^-8, update at symbol rate/
1473	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FFEU17, 0x30000000); /Initialize Main Tap 20/
1474	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_LEAK, 0x00000000); /no leakage/
1475	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_DFE, 0x00001829); /DFE length = 36 taps, mu = 2^-8, reset taps/
1476
1477	/Release Equalizer FFE, FFE Main Tap Real and ONLY THE NON_OVERLAP DFE taps/
1478	BREG_WriteField(hChn->hRegister, DS_FRZ, FFEFRZ, 0);
1479	BREG_WriteField(hChn->hRegister, DS_FRZ, FFRZMR, 0);
1480	BREG_WriteField(hChn->hRegister, DS_FRZ, DFEFRZ19_24, 0);
1481	BREG_WriteField(hChn->hRegister, DS_FRZ, DFEFRZ25_30, 0);
1482	BREG_WriteField(hChn->hRegister, DS_FRZ, DFEFRZ31_36, 0);
1483
1484	/Wait for FFE/DFE to open eye/
1485	/This is the second pass of the EQ in CMA mode without HUM-AGC/
1486	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_LOCKED1_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1487	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1488
1489	/Reduce FFE Mu's /
1490	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, MAINSTEP, 0x2); /main mu = 2^-8/
1491	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, STEP, 0x3); /other mu = 2^-10/
1492
1493	/Wait for FFE/DFE to open eye some more/
1494	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_LOCKED2_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1495	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1496
1497	/Freeze Equalizer to read coeffs/
1498	BREG_WriteField(hChn->hRegister, DS_FRZ, FFEFRZ, 1);
1499	BREG_WriteField(hChn->hRegister, DS_FRZ, FFRZMR, 1);
1500	BREG_WriteField(hChn->hRegister, DS_FRZ, COMBO_DFEFRZ, 0x3F);
1501
1502	/Read Equalizer Here/
1503	for (index=0;index<144;index++)
1504	{
1505	EQ[index] = BREG_Read32(hChn->hRegister, BCHP_DS_EQ_FFEU0 + 4*index);
1506	}
1507
1508	/Setup CWC/
1509	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWCe == BADS_Internal_Params_eEnable)
1510	{
1511	/Reset/Freeze ALL CWC integrators, Freeze ALL CWC Taps/
1512	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, LF_RESET, 0xF);
1513	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, LF_FRZ, 0xF);
1514	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, FREEZE, 0xF);
1515	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, PLL_MODE, CWC_PLL);
1516	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, STEPSIZE1, CWC_MU1);
1517	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, STEPSIZE2, CWC_MU2);
1518	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, STEPSIZE3, CWC_MU3);
1519	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, STEPSIZE4, CWC_MU4);
1520	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FSBAUD, FCW_BAUD_SEL, 1);
1521	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FSBAUD, FSBAUD_Hz, F_HS/2);
1522	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FSCARR, FCW_CARR_SEL, 1);
1523	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FSCARR, FSCARR_Hz, F_1S);
1524
1525	/Auto Mode needs CWC Auto Enabled and callback enabled/
1526	if ((hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag7 == BADS_Internal_Params_eEnable) &&
1527	(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag6 == BADS_Internal_Params_eEnable))
1528	{
1529	/Get the RF Frequency using the callback function/
1530	CallbackFrontend.hTunerChn = (hChn->pCallbackParam[BADS_Callback_eTuner]);
1531	CallbackFrontend.Mode = BADS_CallbackMode_eRequestMode;
1532	BKNI_EnterCriticalSection();
1533	(hChn->pCallback[BADS_Callback_eTuner])(&CallbackFrontend);
1534	BKNI_LeaveCriticalSection();
1535	/Set_BADS_P_Set_CWC_Auto() sets CWC Length, CWC FIN1-4 and Foffset1-4/
1536	#if WFE
1537	CWC_Length = Set_BADS_P_Set_CWC_Auto(hChn, Symbol_Rate, CallbackFrontend.Total_Mix_After_ADC);
1538	#else
1539	CWC_Length = Set_BADS_P_Set_CWC_Auto(hChn, Symbol_Rate, (int32_t)CallbackFrontend.RF_Freq + CallbackFrontend.Total_Mix_After_ADC);
1540	#endif
1541	}
1542	/Manual Mode/
1543	else
1544	{
1545
1546	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN1, FIN1_HZ, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC1_Fin1);
1547	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN2, FIN2_HZ, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC2_Fin2);
1548	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN3, FIN3_HZ, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC3_Fin3);
1549	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN4, FIN4_HZ, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC4_Fin4);
1550	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS1, FOFFSET1, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC1_Foffset1);
1551	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS2, FOFFSET2, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC2_Foffset2);
1552	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS3, FOFFSET3, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC3_Foffset3);
1553	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS4, FOFFSET4, hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWC4_Foffset4);
1554	CWC_Length = MANUAL_CWC_NUM;
1555	}
1556
1557
1558	/Shift the main tap location to the left by the CWC Length/
1559	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, MAIN, (BREG_ReadField(hChn->hRegister, DS_EQ_FFE, MAIN) - CWC_Length));
1560
1561	/Shift FFE Taps to make up for the CWC and preserve the correct number of post FFE taps/
1562	for (index=0;index<72;index++)
1563	{
1564	EQ[index] = EQ[index+2*CWC_Length];
1565	}
1566
1567	/Reset the stolen FFE taps to 0/
1568	for (index=0;index<2*CWC_Length;index++)
1569	{
1570	EQ[71-index] = 0;
1571	}
1572
1573	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, LENGTH, CWC_Length);
1574
1575	/If Length is 0 write F, 1 write E, 2 write C, 3 write 8, 4 write 0/
1576	/Because of crazy CWC programming use (15 - power 2^length - 1)/
1577	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, LF_FRZ, (15 - ((1<<CWC_Length) - 1))); /Unfreeze integrator/
1578	BREG_WriteField(hChn->hRegister, DS_EQ_CWC, FREEZE, (15 - ((1<<CWC_Length) - 1))); /Unfreeze Tap Freeze/
1579
1580	}
1581
1582	for (QamIndex=0;QamIndex<6;QamIndex++)
1583	{
1584	switch (QamIndex)
1585	{
1586	case 0: QamTry = ((hChn->pChnAcqParam->BADS_Local_Params.Q256A == true) \|\| (hChn->pChnAcqParam->BADS_Local_Params.Q256B == true)) ? true : false;
1587	hChn->pChnAcqParam->BADS_Local_Params.QAM = BADS_Local_Params_QAM_eQam256;
1588	FFE_Scale = (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable) ? 256 : 256;
1589	break;
1590	case 1: QamTry = ((hChn->pChnAcqParam->BADS_Local_Params.Q64A == true) \|\| (hChn->pChnAcqParam->BADS_Local_Params.Q64B == true)) ? true : false;
1591	hChn->pChnAcqParam->BADS_Local_Params.QAM = BADS_Local_Params_QAM_eQam64;
1592	FFE_Scale = (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable) ? 254 : 253;
1593	break;
1594	case 2: QamTry = (hChn->pChnAcqParam->BADS_Local_Params.Q128A == true) ? true : false;
1595	hChn->pChnAcqParam->BADS_Local_Params.QAM= BADS_Local_Params_QAM_eQam128;
1596	FFE_Scale = (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable) ? 178 : 174;
1597	break;
1598	case 3: QamTry = (hChn->pChnAcqParam->BADS_Local_Params.Q32A == true) ? true : false;
1599	hChn->pChnAcqParam->BADS_Local_Params.QAM = BADS_Local_Params_QAM_eQam32;
1600	FFE_Scale = (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable) ? 176 : 170;
1601	break;
1602	case 4: QamTry = (hChn->pChnAcqParam->BADS_Local_Params.Q16A == true) ? true : false;
1603	hChn->pChnAcqParam->BADS_Local_Params.QAM = BADS_Local_Params_QAM_eQam16;
1604	FFE_Scale = (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable) ? 248 : 242;
1605	break;
1606	case 5: QamTry = (hChn->pChnAcqParam->BADS_Local_Params.Q1024B == true) ? true : false;
1607	hChn->pChnAcqParam->BADS_Local_Params.QAM = BADS_Local_Params_QAM_eQam1024;
1608	FFE_Scale = (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable) ? 248 : 257;
1609	break;
1610	default : BDBG_ERR(("INVALID QamTry Value"));
1611	break;
1612	}
1613
1614	if (QamTry == true)
1615	{
1616	/Freeze Equalizer to write scaled coeffs/
1617	BREG_WriteField(hChn->hRegister, DS_FRZ, FFEFRZ, 1);
1618	BREG_WriteField(hChn->hRegister, DS_FRZ, FFRZMR, 1);
1619	BREG_WriteField(hChn->hRegister, DS_FRZ, COMBO_DFEFRZ, 0x3F);
1620
1621	/Scale the EQ coeffs differently for each QAM Mode/
1622	for (index=0;index<144;index++)
1623	{
1624	/FFE Coeffs/
1625	if (index < 72)
1626	{
1627	if (index%2==0)
1628	{
1629	FFE_Scaled_Value = (((EQ[index]>>8) & 0x00FFFF00) \| ((EQ[index+1]>>24) & 0x000000FF));
1630	if ((FFE_Scaled_Value & 0x00800000) !=0)
1631	{
1632	FFE_I = -1*(POWER2_24-(int32_t)FFE_Scaled_Value);
1633	}
1634	else
1635	{
1636	FFE_I = (int32_t)FFE_Scaled_Value;
1637	}
1638	FFE_I = (FFE_Scale*FFE_I)/POWER2_8;
1639	if (FFE_I > POWER2_24_M1)
1640	{
1641	FFE_I = POWER2_24_M1;
1642	}
1643	if (FFE_I < -POWER2_24)
1644	{
1645	FFE_I = -POWER2_24;
1646	}
1647
1648	FFE_Scaled_Value = (((EQ[index]<<8) & 0x00FFFF00) \| ((EQ[index+1]>>16) & 0x000000FF));
1649	if ((FFE_Scaled_Value & 0x00800000) !=0)
1650	{
1651	FFE_Q = -1*(POWER2_24-(int32_t)FFE_Scaled_Value);
1652	}
1653	else
1654	{
1655	FFE_Q = (int32_t)FFE_Scaled_Value;
1656	}
1657	FFE_Q = (FFE_Scale*FFE_Q)/POWER2_8;
1658	if (FFE_Q > POWER2_24_M1)
1659	{
1660	FFE_Q = POWER2_24_M1;
1661	}
1662	if (FFE_Q < -POWER2_24)
1663	{
1664	FFE_Q = -POWER2_24;
1665	}
1666	/Write upper part of FFE coeffs/
1667	FFE_Scaled_Value = (uint32_t)(((FFE_I<<8) & 0xFFFF0000) \| ((FFE_Q>>8) & 0x0000FFFF));
1668	}
1669	/Write lower part of FFE coeffs: FFE_Scaled_Value has been calculated above/
1670	else
1671	{
1672	FFE_Scaled_Value = (uint32_t)(((FFE_I<<24) & 0xFF000000) \| ((FFE_Q<<16) & 0x00FF0000));
1673	}
1674	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FFEU0 + 4*index, FFE_Scaled_Value);
1675	}
1676	/Do not scale DFE/
1677	/DFE Coeffs/
1678	else
1679	{
1680	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_FFEU0 + 4*index, EQ[index]);
1681	}
1682	}
1683
1684	/**************************************************************************************************************/
1685	/Now that the EQ has been scaled to the right constellation, start EQ with HUM-AGC/IMC/CWC if they are enabled/
1686	/**************************************************************************************************************/
1687
1688	/Setup CFL:/
1689	BREG_WriteField(hChn->hRegister, DS_FRZ, CFLFRZ, 1);
1690	BREG_Write32(hChn->hRegister, BCHP_DS_CFLI, 0);
1691	BREG_WriteField(hChn->hRegister, DS_CFLC, COMBO_COEFFS, FrequencyLoopCoeffs_TBL[BaudIndex]);
1692
1693	/Setup EQ:/
1694	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CTL, DS_EQ_CTL_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM]);
1695	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_LEAK, 0x00000000);
1696
1697	/Reset hum-AGC Gain offset, leakage, reset loop integrator/
1698	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_AGC, 0x00400001);
1699	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_AGCI, 0);
1700	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_AGCC, 0x00a00050); /AGCLCOEFF = 1602^-15, AGCICOEFF = 802^-22/
1701	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_AGCPA, 0x00000000);
1702
1703	/Setup CPL:/
1704	BREG_WriteField(hChn->hRegister, DS_FRZ, CPLFRZ, 1);
1705	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CPLI, 0);
1706	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CPL, DS_EQ_CPL_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM]);
1707	BREG_WriteField(hChn->hRegister, DS_EQ_CPLC, COMBO_COEFFS, PhaseLoopAcqCoeffs_TBL[BaudIndex]);
1708
1709	/Configure SNR performance Monitoring/
1710	BREG_WriteField(hChn->hRegister, DS_EQ_SNRLT, SNRLTHRESH, SNRLTHRESH_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM]);
1711	BREG_WriteField(hChn->hRegister, DS_EQ_SNRHT, SNRHTHRESH, SNRHTHRESH_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM]);
1712
1713	/Set BWs to acquisition BWs and reset integrators and turn off leakage/
1714	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC1, CWC_ACQ_LFC1);
1715	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC2, CWC_ACQ_LFC2);
1716	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC3, CWC_ACQ_LFC3);
1717	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC4, CWC_ACQ_LFC4);
1718	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_INT1, 0);
1719	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_INT2, 0);
1720	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_INT3, 0);
1721	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_INT4, 0);
1722	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK1, 0);
1723	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK2, 0);
1724	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK3, 0);
1725	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK4, 0);
1726
1727	/Release EQ and DD-AGC/FFE (not main Tap)/
1728	BREG_WriteField(hChn->hRegister, DS_FRZ, FFEFRZ, 0); /Release FFE/
1729	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable)
1730	{
1731	BREG_WriteField(hChn->hRegister, DS_EQ_CTL, HUM_EN, 1);
1732	BREG_WriteField(hChn->hRegister, DS_FRZ, HUMAGCFRZ, 0); /Release HUM-AGC Loop/
1733	}
1734	else
1735	{
1736	BREG_WriteField(hChn->hRegister, DS_FRZ, FFRZMR, 0); /Release FFE Main Tap Real/
1737	}
1738	BREG_WriteField(hChn->hRegister, DS_FRZ, COMBO_DFEFRZ, 0); /Release DFE/
1739
1740	/use reduced FFE Mus/
1741	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, MAINSTEP, 0x2); /main mu = 2^-8/
1742	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, STEP, 0x3); /other mu = 2^-10/
1743
1744	#if IMC
1745	/Start IMC/
1746	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_IMCe == BADS_Internal_Params_eEnable)
1747	{
1748	BREG_WriteField(hChn->hRegister, DS_EQ_CTL, IMC_EN, 1);
1749	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_IMC, 0x0c001119); /36 IMC taps, main tap is 0 left of FFE main, mu = 2^-6, full LMS, update sym, leak off, coarse mode off/
1750	BREG_WriteField(hChn->hRegister, DS_FRZ, IMCFRZ, 0); /Release Image Canceller/
1751	}
1752	#endif
1753	/RFI support/
1754	/if (hChn->pChnAcqParam->BADS_Local_Params.AcqType != BADS_Local_Params_AcqType_eFastAcquire)/
1755	if((EQIndex != 0) \|\| (hChn->pChnAcqParam->BADS_Local_Params.AcqType == BADS_Local_Params_AcqType_eSlowAcquire))
1756	{
1757	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, STEP, 0x2); /other mu = 2^-8/
1758	if ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam1024) \|\|
1759	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam512) \|\|
1760	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam256) \|\|
1761	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam128) \|\|
1762	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam32))
1763	{
1764	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_SLOW_TRIM1_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1765	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1766	}
1767	else
1768	{
1769	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_SLOW_TRIM2_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1770	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1771	}
1772	BREG_WriteField(hChn->hRegister, DS_EQ_FFE, STEP, 0x3); /other mu = 2^-10/
1773	}
1774	else
1775	{
1776	EarlyExit = BADS_P_ADS_SLEEP(hChn, CMA_TIME_FAST_TRIM_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1777	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1778	}
1779
1780	/Start Carrier Phase Loop, this is a very small sweep of a KHz for FFT mode/
1781	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CPLI, (uint32_t)PhaseLoopSweepAnnexA_FFT_TBL[BaudIndex].PosSweepStart);
1782	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CPLSWP, (uint32_t)PhaseLoopSweepAnnexA_FFT_TBL[BaudIndex].PosSweepRate);
1783	BREG_WriteField(hChn->hRegister, DS_FRZ, CPLFRZ, 0); /Release Carrier Phase Loop Freeze/
1784
1785	EarlyExit = BADS_P_ADS_SLEEP(hChn, (unsigned int)PhaseLoopSweepAnnexA_FFT_TBL[BaudIndex].SweepTime);
1786	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1787
1788	BREG_WriteField(hChn->hRegister, DS_EQ_CPLSWP, SWEEP, 0); /Stop Sweeping/
1789
1790
1791	/Reduce Carrier Phase Loop coefficient to Tracking Bandwidth/
1792	/The Carrier Phase Loop coefficient are in a Lookup Table in acquire.h/
1793	BREG_WriteField(hChn->hRegister, DS_EQ_CPLC, COMBO_COEFFS, PhaseLoopTrkCoeffs_TBL[BaudIndex]);
1794
1795	/Jam the phase loop offset into the frequency loop/
1796	/This phase error will also be needed for Hack3 /
1797	Phase_Error1 = BADS_P_Get_CPL_Error(hChn, Symbol_Rate);
1798	if ((hChn->pChnAcqParam->BADS_Internal_Params.BBS_CIP_CO_JamLoad == BADS_Internal_Params_eEnable) &&
1799	(hChn->pChnAcqParam->BADS_Internal_Params.BBS_CFLe == BADS_Internal_Params_eEnable))
1800	{
1801	BADS_P_Set_CFL_Integrator(hChn, Phase_Error1);
1802	BREG_WriteField(hChn->hRegister, DS_FRZ, CFLFRZ, 0); /Release Carrier Frequency Loop Freeze/
1803	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CPLI, 0); /Clear Phase Integrator/
1804	}
1805
1806	/Set DDAGC BW for Tracking Mode/
1807	/This register makes more sense to treat as a 32 bit write/
1808	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable)
1809	{
1810	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_AGCC, 0x00400008); /AGCLCOEFF = 642^-15, AGCICOEFF = 82^-22/
1811	}
1812
1813	/Switch EQ to LMS mode/
1814	BREG_WriteField(hChn->hRegister, DS_EQ_CTL, CMAEN, 0);
1815
1816	/RFI support/
1817	/if (hChn->pChnAcqParam->BADS_Local_Params.AcqType != BADS_Local_Params_AcqType_eFastAcquire)/
1818	if((EQIndex != 0) \|\| (hChn->pChnAcqParam->BADS_Local_Params.AcqType == BADS_Local_Params_AcqType_eSlowAcquire))
1819	{
1820	if ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam1024) \|\|
1821	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam512) \|\|
1822	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam256) \|\|
1823	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam128) \|\|
1824	(hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam32))
1825	{
1826	EarlyExit = BADS_P_ADS_SLEEP(hChn, LMS_TIME_SLOW_TRIM1_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1827	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1828	}
1829	else
1830	{
1831	EarlyExit = BADS_P_ADS_SLEEP(hChn, LMS_TIME_SLOW_TRIM2_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1832	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1833	}
1834	}
1835	else
1836	{
1837	EarlyExit = BADS_P_ADS_SLEEP(hChn, LMS_TIME_FAST_TRIM_BAUD_SAMPLES*1000/FFT_TimingFreq + 1);
1838	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1839	}
1840
1841	#if IMC
1842	/Reduce IMC Bandwidth/
1843	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_IMCe == BADS_Internal_Params_eEnable)
1844	{
1845	BREG_WriteField(hChn->hRegister, DS_EQ_IMC, STEP, 2); /Set IMC Step Size = 2^-8/
1846	}
1847	#endif
1848
1849	/************************************/
1850	/Hack2 alert for 512/1024 QAM /
1851	/************************************/
1852	/extra time seems to be needed before switching the DD-AGC in 512/1024 QAM/
1853	if ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam512) \|\| (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam1024))
1854	{
1855	EarlyExit = BADS_P_ADS_SLEEP(hChn, 15);
1856	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
1857	}
1858
1859	/Switch DDAGC to DD mode/
1860	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_DDAGCe == BADS_Internal_Params_eEnable)
1861	{
1862	BREG_WriteField(hChn->hRegister, DS_EQ_CTL, FNEN, 0);
1863	}
1864
1865	/Start DFE Overlap Leak/
1866	BREG_WriteField(hChn->hRegister, DS_EQ_LEAK, DFE_LEAK_OVERLAP, 0xD);
1867
1868	/Set the final Phase Loop parameters/
1869	/Don't leak the CPL when not using the CFL, use all points/
1870	BREG_WriteField(hChn->hRegister, DS_EQ_CPL, CPLFREQEN, 0);
1871	BREG_WriteField(hChn->hRegister, DS_EQ_CPL, CPLFTYPE, 0);
1872	BREG_WriteField(hChn->hRegister, DS_EQ_CPL, CPLLK, 0);
1873
1874	/Unfreeze Front loop and start leak in carrier phase loop/
1875	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_CFLe == BADS_Internal_Params_eEnable)
1876	{
1877	BREG_WriteField(hChn->hRegister, DS_FRZ, CFLFRZ, 0);
1878	BREG_WriteField(hChn->hRegister, DS_EQ_CPL, CPLLK, 0x9); /leak at 2^-18/
1879	}
1880
1881	/Set the final CWC Loop parameters/
1882	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_CWCe == BADS_Internal_Params_eEnable)
1883	{
1884	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC1, CWC_TRK_LFC1);
1885	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC2, CWC_TRK_LFC2);
1886	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC3, CWC_TRK_LFC3);
1887	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_CWC_LFC4, CWC_TRK_LFC4);
1888	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK1, CWC_LK1);
1889	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK2, CWC_LK2);
1890	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK3, CWC_LK3);
1891	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_LEAK, CWC_LEAK4, CWC_LK4);
1892	}
1893
1894	/*******************************************************************************************/
1895	/ACQUISITION FINISHED: BEGIN LOCK CHECKING/SPECTRAL INVERSION/AUTOINVERSION/
1896	/*******************************************************************************************/
1897
1898	/************************************/
1899	/Hack3 alert for non square /
1900	/************************************/
1901
1902	/The original phase error was calculated above/
1903	Phase_Error1 = (Phase_Error1 < 0) ? -1*Phase_Error1 : Phase_Error1;
1904	Phase_Error2 = BADS_P_Get_CPL_Error(hChn, Symbol_Rate);
1905	Phase_Error2 = (Phase_Error2 < 0) ? -1*Phase_Error2 : Phase_Error2;
1906	FECIndexEnd = ((Phase_Error1+Phase_Error2) > MAX_PHASE_ERROR) ? 0 : 2;
1907	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eNoCarrier;
1908
1909	/Debug print/
1910	if (PRINT_DEBUG==1) BDBG_ERR(("Phase_Error1 = %d Phase_Error2 = %d",Phase_Error1,Phase_Error2));
1911
1912	/256 and 64QAM AnnexA or B/
1913	/FEC Index 0 is AnnexA, FEC Index 1 is AnnexA/
1914	for (FECIndex=0;FECIndex<FECIndexEnd;FECIndex++)
1915	{
1916	switch (FECIndex)
1917	{
1918	/Try if QamIndex is 0 and Q256A, 1 and Q64A, 2, 3, 4/
1919	case 0:
1920	if (((QamIndex == 0) && (hChn->pChnAcqParam->BADS_Local_Params.Q256A == true)) \|\|
1921	((QamIndex == 1) && (hChn->pChnAcqParam->BADS_Local_Params.Q64A == true)) \|\|
1922	((QamIndex >= 2) && (QamIndex <= 4)))
1923	{
1924	FECTry = true;
1925	}
1926	else
1927	{
1928	FECTry = false;
1929	}
1930	hChn->pChnAcqParam->BADS_Local_Params.Annex = BADS_Local_Params_Annex_eAnnexA;
1931	FEC_TimeOut = ANNEXA_FEC_LOCK_TIMEOUT;
1932	break;
1933	/Try if QamIndex is 0 and Q256B, 1 and Q64B, 5/
1934	case 1:
1935	if (((QamIndex == 0) && (hChn->pChnAcqParam->BADS_Local_Params.Q256B == true)) \|\|
1936	((QamIndex == 1) && (hChn->pChnAcqParam->BADS_Local_Params.Q64B == true)) \|\|
1937	(QamIndex == 5))
1938	{
1939	/Only try if the symbol rate is within the Annex B bounds/
1940	if ((((QamIndex == 0) \|\| (QamIndex == 5)) && (Symbol_Rate >= MIN_Q256_Q1024_ANNEXB_SYMBOL_RATE) && (Symbol_Rate <= MAX_Q256_Q1024_ANNEXB_SYMBOL_RATE)) \|\|
1941	(((QamIndex == 1) && (Symbol_Rate >= MIN_Q64_ANNEXB_SYMBOL_RATE) && (Symbol_Rate <= MAX_Q64_ANNEXB_SYMBOL_RATE))))
1942	{
1943	FECTry = true;
1944	}
1945	else
1946	{
1947	FECTry = false;
1948	}
1949	}
1950	else
1951	{
1952	FECTry = false;
1953	}
1954	hChn->pChnAcqParam->BADS_Local_Params.Annex = BADS_Local_Params_Annex_eAnnexB;
1955	FEC_TimeOut = ANNEXB_FEC_LOCK_TIMEOUT;
1956	break;
1957	}
1958
1959	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eNoFECLock;
1960	if (FECTry == true)
1961	{
1962	/Program the FEC/
1963	BADS_P_ProgramFEC(hChn);
1964
1965	/Set the Burst Mode parameters for Annex A/
1966	/These are values that overwrite the standard acquisition values and are only valid at high baud rates/
1967	if ((hChn->pChnAcqParam->BADS_Internal_Params.BBS_AnnexA_Burst_Mode == BADS_Internal_Params_eEnable) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA))
1968	{
1969	/Increase leakage/
1970	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_CFLe == BADS_Internal_Params_eEnable)
1971	{
1972	BREG_WriteField(hChn->hRegister, DS_EQ_CPL, CPLLK, 0xB); /leak at 2^-16/
1973	}
1974
1975	/Reduce Carrier Phase Loop coefficient to Tracking Bandwidth/
1976	/The Carrier Phase Loop coefficient are in a Lookup Table in acquire.h/
1977	/Fn=30k, Damp=0.44 for 6.9Mbaud/
1978	BREG_WriteField(hChn->hRegister, DS_EQ_CPLC, COMBO_COEFFS, PhaseLoopTrkBurstModeCoeffs_TBL[BaudIndex]);
1979
1980	/Fn=1k, Damp=0.70 for 6.9Mbaud @ Fs=54.0M/
1981	BREG_WriteField(hChn->hRegister, DS_CFLC, COMBO_COEFFS, FrequencyLoopBurstModeCoeffs_TBL[BaudIndex]);
1982
1983	/program burst registers/
1984	BREG_Write32(hChn->hRegister, BCHP_DS_BND, 0x08000000);
1985	BREG_Write32(hChn->hRegister, BCHP_DS_BND_THR, 0x00072B02);
1986
1987	/turn on erasures in FEC/
1988	BREG_Write32(hChn->hRegister, BCHP_DS_FECU, (AnnexA_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECU \| 0x0000000C));
1989	}
1990	else
1991	{
1992	/program burst registers used in the Annex A burst detection/
1993	BREG_Write32(hChn->hRegister, BCHP_DS_BND, 0x04000000);
1994	BREG_Write32(hChn->hRegister, BCHP_DS_BND_THR, 0x00000000);
1995	}
1996
1997	/Set the FEC spectrum status Flag/
1998	hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum = BADS_Local_Params_FECSpectrum_eNotInverted;
1999
2000	/Check if the spectrum is to be inverted from the default setting/
2001	if (hChn->pChnAcqParam->BADS_Acquire_Params.IS == BADS_Acquire_Params_eEnable)
2002	{
2003	ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_FECL);
2004	ReadReg = ReadReg ^ 0x00000008;
2005	BREG_Write32(hChn->hRegister, BCHP_DS_FECL, ReadReg);
2006	hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum = BADS_Local_Params_FECSpectrum_eInverted;
2007	}
2008
2009	/Reset FEC Counters/
2010	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 1);
2011	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 0);
2012	BREG_Write32(hChn->hRegister, BCHP_DS_TPFEC, 0x000F9F00);
2013	hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 = 0;
2014	hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 = 0;
2015	hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 = 0;
2016	hChn->pChnLockStatus->ReSync_Count = 0;
2017	hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount = STUCK_FEC_RESET_COUNT;
2018
2019	/Wait for FEC to sync and output data/
2020	index=0;
2021	while ((index<FEC_TimeOut) && (BREG_ReadField(hChn->hRegister, DS_NBERC1, NBERCCNTVAL) == 0))
2022	{
2023	EarlyExit = BADS_P_ADS_SLEEP(hChn, 1);
2024	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
2025	index++;
2026	}
2027	BADS_P_ChnLockStatus(hChn);
2028
2029	/Check to see if spectrum AutoInversion is activated/
2030	if (hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum == true)
2031	{
2032	/If FEC is not locked try inverting the spectrum/
2033	if (hChn->pChnLockStatus->FLK == BADS_3x7x_ChnLockStatus_eUnlock)
2034	{
2035	/Invert Spectrum if FEC is not locked/
2036	ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_FECL);
2037	ReadReg = ReadReg ^ 0x00000008; /Perform Spectral Inversion in the FEC/
2038	BREG_Write32(hChn->hRegister, BCHP_DS_FECL, ReadReg);
2039	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 1); /Reset FEC/
2040	BREG_WriteField(hChn->hRegister, DS_RST, FECRST, 0);
2041	BREG_Write32(hChn->hRegister, BCHP_DS_TPFEC, 0x000F9F00);
2042	hChn->pChnAcqParam->BADS_Local_Params.Old_CBERC1 = 0;
2043	hChn->pChnAcqParam->BADS_Local_Params.Old_UERC1 = 0;
2044	hChn->pChnAcqParam->BADS_Local_Params.Old_NBERC1 = 0;
2045	hChn->pChnLockStatus->ReSync_Count = 0;
2046	hChn->pChnAcqParam->BADS_Local_Params.StuckFECCount = STUCK_FEC_RESET_COUNT;
2047	if (hChn->pChnAcqParam->BADS_Acquire_Params.IS == BADS_Acquire_Params_eEnable)
2048	{
2049	hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum = BADS_Local_Params_FECSpectrum_eInvertedAutoInvert;
2050	}
2051	else
2052	{
2053	hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum = BADS_Local_Params_FECSpectrum_eNotInvertedAutoInvert;
2054	}
2055
2056	/Wait for FEC to sync and output data UP TO 25 ms/
2057	/This used to be 15 but it was not long enough for low SNR conditions/
2058	index=0;
2059	while ((index<FEC_TimeOut) && (BREG_ReadField(hChn->hRegister, DS_NBERC1, NBERCCNTVAL) == 0))
2060	{
2061	EarlyExit = BADS_P_ADS_SLEEP(hChn, 1);
2062	if (EarlyExit == true) goto please_leave_early; /goto bottom of function to leave early/
2063	index++;
2064	}
2065	BADS_P_ChnLockStatus(hChn);
2066	}
2067	}
2068
2069	/Removed after checkingwith Farshid and Ray W/
2070	/Clear FEC lost lock interrupt/
2071	/BREG_WriteField(hChn->hRegister, DS_IRQCLR1, FEC_LOCK_DET_ICLR , 1);/
2072
2073	/Reset SNR and Output Interface/
2074	BREG_Write32(hChn->hRegister, BCHP_DS_EQ_SNR , 0x0000000F); /Reset ERRVAL, Force update, long averaging/
2075	BREG_Write32(hChn->hRegister, BCHP_DS_OI_VCO , 0x00000004); /Reset OI control and data paths/
2076	BREG_Write32(hChn->hRegister, BCHP_DS_OI_CTL , 0x00020011);
2077	BREG_Write32(hChn->hRegister, BCHP_DS_OI_CTL , 0x00020011);
2078	/use byte clock, serial output mode, invert clock/
2079	BREG_Write32(hChn->hRegister, BCHP_DS_OI_OUT, 0); /in B0 this register muxes the transport data /
2080
2081	/Reset/Resync BER registers in chip/
2082	BREG_Write32(hChn->hRegister, BCHP_DS_BER, 0x00000004);
2083	BREG_Write32(hChn->hRegister, BCHP_DS_BERI, 0xFFFFFFFF);
2084	BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER_CTL, 0x00000004);
2085	BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER, 0xFFFFFFFF);
2086
2087	if (hChn->pChnLockStatus->FLK == BADS_3x7x_ChnLockStatus_eLock)
2088	{
2089	/RFI support/
2090	if((EQIndex != 0) \|\| (hChn->pChnAcqParam->BADS_Local_Params.AcqType == BADS_Local_Params_AcqType_eSlowAcquire))
2091	{
2092	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eLockedSlow;
2093	}
2094	else
2095	{
2096	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eLockedFast;
2097	}
2098
2099	/leave function if locked, this is not an Early Exit but a normal exit/
2100	EarlyExit = false;
2101	goto please_leave_early; /goto bottom of function to leave early/
2102	}
2103
2104	} /FECTry/
2105	} /FECIndex/
2106	} /QamTry/
2107	} /QamIndex/
2108	} /EQIndex/
2109	} /FFT_TimingBin ==2048/
2110	} /FFT_TimingFreq !=0/
2111	} /CarrierIndex<=CarrierIndexEnd/
2112	} /CarrierIndex/
2113	} /BaudIndex/
2114	}/Retry Index/
2115
2116	/goto label to return error code if something bad happened above/
2117	something_bad_happened:
2118	/goto label to exit early/
2119	please_leave_early:
2120
2121	/Check if we are performing an early exit from function/
2122	if (EarlyExit == true)
2123	{
2124	hChn->pChnAcqParam->BADS_Local_Params.AcqStatus = BADS_Local_Params_AcqStatus_eEarlyExit;
2125	BDBG_MSG(("ADS Acq. Early Exit."));
2126	}
2127
2128	/Assign the scan status parameters if locked, pass 0's if unlocked/
2129	if (hChn->pChnLockStatus->FLK != BADS_3x7x_ChnLockStatus_eLock)
2130	{
2131	hChn->pChnScanStatus->FLK = 0;
2132	hChn->pChnScanStatus->QLK = 0;
2133	hChn->pChnScanStatus->Auto = 0;
2134	hChn->pChnScanStatus->AcqType = 0;
2135	hChn->pChnScanStatus->AcqStatus = 0;
2136	hChn->pChnScanStatus->Spectrum = 0;
2137	hChn->pChnScanStatus->BPS = 0;
2138	hChn->pChnScanStatus->AB = 0;
2139	hChn->pChnScanStatus->Interleaver = 0;
2140	hChn->pChnScanStatus->RF_Offset = 0;
2141	hChn->pChnScanStatus->Symbol_Rate = 0;
2142	}
2143	else
2144	{
2145	/* FEC and QAM Lock */
2146	hChn->pChnScanStatus->FLK = (hChn->pChnLockStatus->FLK == BADS_3x7x_ChnLockStatus_eLock) ? BADS_3x7x_ChnScanStatus_eLock : BADS_3x7x_ChnScanStatus_eUnlock;
2147	hChn->pChnScanStatus->QLK = (hChn->pChnLockStatus->QLK == BADS_3x7x_ChnLockStatus_eLock) ? BADS_3x7x_ChnScanStatus_eLock : BADS_3x7x_ChnScanStatus_eUnlock;
2148
2149	/* Feedback of Acquire Parameters (Auto) */
2150	hChn->pChnScanStatus->Auto = (hChn->pChnAcqParam->BADS_Acquire_Params.Auto == BADS_Acquire_Params_eEnable) ? BADS_3x7x_ChnScanStatus_eEnable : BADS_3x7x_ChnScanStatus_eDisable;
2151
2152	/* Feedback of Acquire Parameters (AcqType) */
2153	switch ( hChn->pChnAcqParam->BADS_Acquire_Params.AcqType )
2154	{
2155	case BADS_Acquire_Params_AcqType_eAuto : hChn->pChnScanStatus->AcqType = BADS_3x7x_ChnScanStatus_AcqType_eAuto; break;
2156	case BADS_Acquire_Params_AcqType_eFast : hChn->pChnScanStatus->AcqType = BADS_3x7x_ChnScanStatus_AcqType_eFast; break;
2157	case BADS_Acquire_Params_AcqType_eSlow : hChn->pChnScanStatus->AcqType = BADS_3x7x_ChnScanStatus_AcqType_eSlow; break;
2158	case BADS_Acquire_Params_AcqType_eScan : hChn->pChnScanStatus->AcqType = BADS_3x7x_ChnScanStatus_AcqType_eScan; break;
2159	default : BDBG_ERR(("ERROR!!! UNSUPPORTED OR UNDEFINED AcqType")); break;
2160	}
2161
2162	switch (hChn->pChnAcqParam->BADS_Local_Params.AcqStatus)
2163	{
2164	case BADS_Local_Params_AcqStatus_eNoPower: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eNoPower; break;
2165	case BADS_Local_Params_AcqStatus_eNoTiming: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eNoTiming; break;
2166	case BADS_Local_Params_AcqStatus_eNoCarrier: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eNoCarrier; break;
2167	case BADS_Local_Params_AcqStatus_eNoFECLock: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eNoFECLock; break;
2168	case BADS_Local_Params_AcqStatus_eLockedFast: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eLockedFast; break;
2169	case BADS_Local_Params_AcqStatus_eLockedSlow: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eLockedSlow; break;
2170	case BADS_Local_Params_AcqStatus_eEarlyExit: hChn->pChnScanStatus->AcqStatus = BADS_3x7x_ChnScanStatus_AcqStatus_eEarlyExit; break;
2171	default : BDBG_ERR(("ERROR!!! UNSUPPORTED OR UNDEFINED AcqStatus")); break;
2172	}
2173
2174	switch (hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum)
2175	{
2176	case BADS_Local_Params_FECSpectrum_eNotInverted: hChn->pChnScanStatus->Spectrum = BADS_3x7x_ChnScanStatus_Spectrum_eNormal; break;
2177	case BADS_Local_Params_FECSpectrum_eInverted: hChn->pChnScanStatus->Spectrum = BADS_3x7x_ChnScanStatus_Spectrum_eNormal; break;
2178	case BADS_Local_Params_FECSpectrum_eNotInvertedAutoInvert: hChn->pChnScanStatus->Spectrum = BADS_3x7x_ChnScanStatus_Spectrum_eFlipped; break;
2179	case BADS_Local_Params_FECSpectrum_eInvertedAutoInvert: hChn->pChnScanStatus->Spectrum = BADS_3x7x_ChnScanStatus_Spectrum_eFlipped; break;
2180	default : BDBG_ERR(("ERROR!!! UNSUPPORTED OR UNDEFINED FECSpectrum")); break;
2181	}
2182
2183	switch (QamIndex)
2184	{
2185	case 0: hChn->pChnScanStatus->BPS = BADS_3x7x_ChnScanStatus_BPS_eQam256; break;
2186	case 1: hChn->pChnScanStatus->BPS = BADS_3x7x_ChnScanStatus_BPS_eQam64; break;
2187	case 2: hChn->pChnScanStatus->BPS = BADS_3x7x_ChnScanStatus_BPS_eQam128; break;
2188	case 3: hChn->pChnScanStatus->BPS = BADS_3x7x_ChnScanStatus_BPS_eQam32; break;
2189	case 4: hChn->pChnScanStatus->BPS = BADS_3x7x_ChnScanStatus_BPS_eQam16; break;
2190	case 5: hChn->pChnScanStatus->BPS = BADS_3x7x_ChnScanStatus_BPS_eQam1024; break;
2191	default : BDBG_ERR(("INVALID QamTry Value")); break;
2192	}
2193
2194	hChn->pChnScanStatus->AB = (FECIndex == 0) ? BADS_3x7x_ChnScanStatus_Annex_eAnnexA : BADS_3x7x_ChnScanStatus_Annex_eAnnexB;
2195
2196
2197	if (FECIndex == 0)
2198	{
2199	hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI12_J17;
2200	}
2201	else
2202	{
2203	switch (BREG_ReadField(hChn->hRegister, DS_FEC, IDS))
2204	{
2205	case 0: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI128_J1; break;
2206	case 1: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI128_J1; break;
2207	case 2: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI128_J2; break;
2208	case 3: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI64_J2; break;
2209	case 4: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI128_J3; break;
2210	case 5: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI32_J4; break;
2211	case 6: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI128_J4; break;
2212	case 7: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI16_J8; break;
2213	case 9: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI8_J16; break;
2214	case 11: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI4_J32; break;
2215	case 13: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI2_J64; break;
2216	case 15: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eI1_J128; break;
2217	default: hChn->pChnScanStatus->Interleaver = BADS_3x7x_ChnScanStatus_Interleaver_eUnsupported; break;
2218	}
2219	}
2220
2221	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag6 == BADS_Internal_Params_eEnable)
2222	{
2223	hChn->pChnScanStatus->RF_Offset = CarrierOffset+Carrier_Error;
2224	}
2225	else
2226	{
2227	hChn->pChnScanStatus->RF_Offset = 0;
2228	}
2229
2230	hChn->pChnScanStatus->Symbol_Rate = Symbol_Rate;
2231	}
2232
2233	/Get elapsed time/
2234	BTMR_ReadTimer(hChn->hAds->hStatusTimer, &EndTime);
2235	ElapsedTime = (EndTime >= StartTime) ? (EndTime - StartTime) : ((POWER2_30 - StartTime) + EndTime);
2236	hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime = (uint16_t)(ElapsedTime/(MIPS_TIMER/1000));
2237	hChn->pChnAcqParam->BADS_Local_Params.TotalTime += hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime;
2238
2239	/print acquisition results and elapsed time/
2240	if(hChn->pChnAcqParam->BADS_Local_Params.AcqStatus == BADS_Local_Params_AcqStatus_eLockedSlow)
2241	{
2242	BDBG_MSG(("Locked Slow: ElapsedTime= %d ms TotalTime= %d ms",hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime,hChn->pChnAcqParam->BADS_Local_Params.TotalTime));
2243	}
2244	else if (hChn->pChnAcqParam->BADS_Local_Params.AcqStatus == BADS_Local_Params_AcqStatus_eLockedFast)
2245	{
2246	BDBG_MSG(("Locked Fast: ElapsedTime= %d ms TotalTime= %d ms",hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime,hChn->pChnAcqParam->BADS_Local_Params.TotalTime));
2247	}
2248	else
2249	{
2250	BDBG_MSG(("Unlocked: ElapsedTime= %d ms TotalTime= %d ms",hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime,hChn->pChnAcqParam->BADS_Local_Params.TotalTime));
2251	}
2252
2253	/Test for acquisition probability using the spare register/
2254	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Acquisition_Test == BADS_Internal_Params_eEnable)
2255	{
2256	BADS_P_AcquisitionPercentageTest(hChn);
2257	}
2258	return retCode;
2259	}
2260
2261	/***************************************************************************
2262	* BADS_P_AbortAcquire()
2263	***************************************************************************/
2264	BERR_Code BADS_P_AbortAcquire(BADS_3x7x_ChannelHandle hChn)
2265	{
2266	BERR_Code retCode = BERR_INVALID_PARAMETER;
2267	if ( NULL != hChn && DEV_MAGIC_ID == hChn->magicId )
2268	{
2269	BDBG_MSG(("BADS_P_AbortAcquire"));
2270	/* Request Early Exit */
2271	hChn->pChnAcqParam->BADS_Local_Params.EarlyExit = true;
2272	retCode = BERR_SUCCESS;
2273	}
2274	return ( retCode );
2275	}
2276
2277	/********************************************************************************************
2278	*Function to program the FEC
2279	********************************************************************************************/
2280	void BADS_P_ProgramFEC(BADS_3x7x_ChannelHandle hChn)
2281	{
2282	if (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)
2283	{
2284	BREG_Write32(hChn->hRegister, BCHP_DS_FECU, AnnexA_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECU);
2285	BREG_Write32(hChn->hRegister, BCHP_DS_FECM, AnnexA_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECM);
2286	BREG_Write32(hChn->hRegister, BCHP_DS_FECL, AnnexA_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECL);
2287	BREG_Write32(hChn->hRegister, BCHP_DS_FECOUT_NCON, AnnexA_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECOUT_NCON);
2288	BREG_Write32(hChn->hRegister, BCHP_DS_FECOUT_NCODL, AnnexA_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECOUT_NCODL);
2289	}
2290	else
2291	{
2292	BREG_Write32(hChn->hRegister, BCHP_DS_FECU, AnnexB_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECU);
2293	BREG_Write32(hChn->hRegister, BCHP_DS_FECM, AnnexB_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECM);
2294	BREG_Write32(hChn->hRegister, BCHP_DS_FECL, AnnexB_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECL);
2295	BREG_Write32(hChn->hRegister, BCHP_DS_FECOUT_NCON, AnnexB_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECOUT_NCON);
2296	BREG_Write32(hChn->hRegister, BCHP_DS_FECOUT_NCODL, AnnexB_FEC_TBL[hChn->pChnAcqParam->BADS_Local_Params.QAM].DS_FECOUT_NCODL);
2297	}
2298	}
2299
2300	uint8_t Set_BADS_P_Set_CWC_Auto(BADS_3x7x_ChannelHandle hChn, uint32_t Symbol_Rate, int32_t CWC_Offset_Freq)
2301	{
2302	uint8_t spur_cnt, CWC_Length;
2303	int32_t Fin_Hz[4];
2304	int32_t upper_spur, lower_spur;
2305
2306	upper_spur = (CWC_Offset_Freq + (int32_t)Symbol_Rate/2);
2307	lower_spur = (CWC_Offset_Freq - (int32_t)Symbol_Rate/2);
2308	CWC_Length = 0;
2309	Fin_Hz[0] = 0;
2310	Fin_Hz[1] = 0;
2311	Fin_Hz[2] = 0;
2312	Fin_Hz[3] = 0;
2313
2314	/Check for special case of spurs at -1.75 MHz for AnnexB, this is the Tak special/
2315	if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag3 == BADS_Internal_Params_eEnable)
2316	{
2317	if (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexB)
2318	{
2319	Fin_Hz[CWC_Length] = -1750000;
2320	CWC_Length++;
2321	}
2322	}
2323
2324	/Search for the CWC locations using the spur table in bwfe_global_clk.h or btnr_global_clk.h/
2325	for (spur_cnt=0;spur_cnt<SPUR_TBL_SIZE;spur_cnt++)
2326	{
2327	if (CWC_Length > 4)
2328	{
2329	BDBG_ERR(("ERROR: CWC SPUR COUNT OUT OF RANGE IN Set_BADS_P_Set_CWC_Auto()\n"));
2330	}
2331	else
2332	{
2333	/Check if DC spur is enabled in the table: spur frequency = 0/
2334	if (SPUR_TBL[spur_cnt] == 0)
2335	{
2336	Fin_Hz[CWC_Length] = 0;
2337	CWC_Length++;
2338	}
2339	else
2340	{
2341	/Check the table for spur frequencies within +- buadrate/2/
2342	if (((int32_t)SPUR_TBL[spur_cnt] <= upper_spur) && ((int32_t)SPUR_TBL[spur_cnt] >= lower_spur) && (CWC_Length < 4))
2343	{
2344	Fin_Hz[CWC_Length] = (int32_t)SPUR_TBL[spur_cnt] - CWC_Offset_Freq;
2345	CWC_Length++;
2346	}
2347	}
2348
2349	if ((Fin_Hz[CWC_Length] >= POWER2_23) \|\| (Fin_Hz[CWC_Length] < -POWER2_23))
2350	{
2351	BDBG_ERR(("ERROR: CWC OUT OF RANGE IN Set_BADS_P_Set_CWC_Auto()\n"));
2352	}
2353	}
2354	}
2355
2356
2357
2358	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN1, FIN1_HZ, Fin_Hz[0]);
2359	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN2, FIN2_HZ, Fin_Hz[1]);
2360	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN3, FIN3_HZ, Fin_Hz[2]);
2361	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FIN4, FIN4_HZ, Fin_Hz[3]);
2362	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS1, FOFFSET1, 0);
2363	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS2, FOFFSET2, 0);
2364	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS3, FOFFSET3, 0);
2365	BREG_WriteField(hChn->hRegister, DS_EQ_CWC_FOFS4, FOFFSET4, 0);
2366
2367	return CWC_Length;
2368	}
2369
2370	void BADS_P_Get_AcquisitionScan_Settings(BADS_3x7x_ChannelHandle hChn)
2371	{
2372	if (hChn->pChnAcqParam->BADS_Acquire_Params.AcqType == BADS_Acquire_Params_AcqType_eScan)
2373	{
2374	/Set the acquisition Type/
2375	hChn->pChnAcqParam->BADS_Local_Params.AcqType = BADS_Local_Params_AcqType_eScan;
2376
2377	/Check if the Timing Search is enabled in the Scan params/
2378	if (hChn->pChnAcqParam->BADS_Scan_Params.TO == BADS_Scan_Params_eEnable)
2379	{
2380	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = hChn->pChnAcqParam->BADS_Scan_Params.Upper_Baud_Search;
2381	hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search = hChn->pChnAcqParam->BADS_Scan_Params.Lower_Baud_Search;
2382	}
2383	else
2384	{
2385	if (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)
2386	{
2387	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = hChn->pChnAcqParam->BADS_Acquire_Params.AnnexA_Sym_Rate;
2388	}
2389	else
2390	{
2391	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam64) ? Q64_ANNEXB_SYMBOL_RATE : Q256_Q1024_ANNEXB_SYMBOL_RATE;
2392	}
2393	hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search = hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search;
2394	}
2395
2396	/Check if the Carrier Search is enabled in the Scan params/
2397	if (hChn->pChnAcqParam->BADS_Scan_Params.CO == BADS_Scan_Params_eEnable)
2398	{
2399	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search = 256*hChn->pChnAcqParam->BADS_Scan_Params.Carrier_Search;
2400	}
2401	else
2402	{
2403	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search =256*hChn->pChnAcqParam->BADS_Acquire_Params.Carrier_Range;
2404	}
2405
2406	/Check if the QAM Search is enabled in the Scan params/
2407	if (hChn->pChnAcqParam->BADS_Scan_Params.QM == BADS_Scan_Params_eEnable)
2408	{
2409	hChn->pChnAcqParam->BADS_Local_Params.Q256A = (hChn->pChnAcqParam->BADS_Scan_Params.A256 == BADS_Scan_Params_eEnable) ? true : false;
2410	hChn->pChnAcqParam->BADS_Local_Params.Q256B = (hChn->pChnAcqParam->BADS_Scan_Params.B256 == BADS_Scan_Params_eEnable) ? true : false;
2411	hChn->pChnAcqParam->BADS_Local_Params.Q64A = (hChn->pChnAcqParam->BADS_Scan_Params.A64 == BADS_Scan_Params_eEnable) ? true : false;
2412	hChn->pChnAcqParam->BADS_Local_Params.Q64B = (hChn->pChnAcqParam->BADS_Scan_Params.B64 == BADS_Scan_Params_eEnable) ? true : false;
2413	hChn->pChnAcqParam->BADS_Local_Params.Q128A = (hChn->pChnAcqParam->BADS_Scan_Params.A128 == BADS_Scan_Params_eEnable) ? true : false;
2414	hChn->pChnAcqParam->BADS_Local_Params.Q32A = (hChn->pChnAcqParam->BADS_Scan_Params.A32 == BADS_Scan_Params_eEnable) ? true : false;
2415	hChn->pChnAcqParam->BADS_Local_Params.Q16A = (hChn->pChnAcqParam->BADS_Scan_Params.A16 == BADS_Scan_Params_eEnable) ? true : false;
2416	hChn->pChnAcqParam->BADS_Local_Params.Q1024B = (hChn->pChnAcqParam->BADS_Scan_Params.B1024 == BADS_Scan_Params_eEnable) ? true : false;
2417	}
2418	else
2419	{
2420	hChn->pChnAcqParam->BADS_Local_Params.Q256A = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam256) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)) ? true : false;
2421	hChn->pChnAcqParam->BADS_Local_Params.Q256B = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam256) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexB)) ? true : false;
2422	hChn->pChnAcqParam->BADS_Local_Params.Q64A = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam64) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)) ? true : false;
2423	hChn->pChnAcqParam->BADS_Local_Params.Q64B = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam64) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexB)) ? true : false;
2424	hChn->pChnAcqParam->BADS_Local_Params.Q128A = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam128) ? true : false;
2425	hChn->pChnAcqParam->BADS_Local_Params.Q32A = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam32) ? true : false;
2426	hChn->pChnAcqParam->BADS_Local_Params.Q16A = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam16) ? true : false;
2427	hChn->pChnAcqParam->BADS_Local_Params.Q1024B = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam1024) ? true : false;
2428	}
2429
2430	/Check if the Spectrum Search is enabled in the Scan params, set initial spectrum polarity/
2431	hChn->pChnAcqParam->BADS_Local_Params.Invert_Spectrum = (hChn->pChnAcqParam->BADS_Acquire_Params.IS == BADS_Acquire_Params_eEnable) ? true : false;
2432	if (hChn->pChnAcqParam->BADS_Scan_Params.AI == BADS_Scan_Params_eEnable)
2433	{
2434	hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum = true;
2435	}
2436	else
2437	{
2438	hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum = false;
2439	}
2440	}
2441	else
2442	{
2443	/Set the acquisition Type/
2444	/set for fast acquire initially/
2445	hChn->pChnAcqParam->BADS_Local_Params.AcqType = BADS_Local_Params_AcqType_eFastAcquire;
2446
2447	/Set Timing Search, Upper_Baud_Search and Lower_Baud_Search have the same value/
2448	if (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)
2449	{
2450	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = hChn->pChnAcqParam->BADS_Acquire_Params.AnnexA_Sym_Rate;
2451	}
2452	else
2453	{
2454	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam64) ? Q64_ANNEXB_SYMBOL_RATE : Q256_Q1024_ANNEXB_SYMBOL_RATE;
2455	}
2456	hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search = hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search;
2457
2458	/Set the Carrier Search/
2459	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search = 256*hChn->pChnAcqParam->BADS_Acquire_Params.Carrier_Range;
2460
2461	/Set the QAM Mode/
2462	hChn->pChnAcqParam->BADS_Local_Params.Q256A = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam256) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)) ? true : false;
2463	hChn->pChnAcqParam->BADS_Local_Params.Q256B = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam256) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexB)) ? true : false;
2464	hChn->pChnAcqParam->BADS_Local_Params.Q64A = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam64) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexA)) ? true : false;
2465	hChn->pChnAcqParam->BADS_Local_Params.Q64B = ((hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam64) && (hChn->pChnAcqParam->BADS_Local_Params.Annex == BADS_Local_Params_Annex_eAnnexB)) ? true : false;
2466	hChn->pChnAcqParam->BADS_Local_Params.Q128A = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam128) ? true : false;
2467	hChn->pChnAcqParam->BADS_Local_Params.Q32A = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam32) ? true : false;
2468	hChn->pChnAcqParam->BADS_Local_Params.Q16A = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam16) ? true : false;
2469	hChn->pChnAcqParam->BADS_Local_Params.Q1024B = (hChn->pChnAcqParam->BADS_Local_Params.QAM == BADS_Local_Params_QAM_eQam1024) ? true : false;
2470
2471	/set the spectrum polarity/
2472	hChn->pChnAcqParam->BADS_Local_Params.Invert_Spectrum = (hChn->pChnAcqParam->BADS_Acquire_Params.IS == BADS_Acquire_Params_eEnable) ? true : false;
2473	hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum = false;
2474
2475	/check for transition to slow acquire/
2476	if (((hChn->pChnLockStatus->ReAck_Count > NUM_FAST_ACQUIRES) && (hChn->pChnAcqParam->BADS_Acquire_Params.AcqType == BADS_Acquire_Params_AcqType_eAuto)) \|\| (hChn->pChnAcqParam->BADS_Acquire_Params.AcqType == BADS_Acquire_Params_AcqType_eSlow))
2477	{
2478	/set for slow acquire/
2479	hChn->pChnAcqParam->BADS_Local_Params.AcqType = BADS_Local_Params_AcqType_eSlowAcquire;
2480	}
2481
2482	/check for transition to slow/scan acquire/
2483	if ((hChn->pChnLockStatus->ReAck_Count > (NUM_FAST_ACQUIRES + NUM_SLOW_ACQUIRES)) && (hChn->pChnAcqParam->BADS_Acquire_Params.AcqType == BADS_Acquire_Params_AcqType_eAuto))
2484	{
2485	/set for slow/scan acquire/
2486	hChn->pChnAcqParam->BADS_Local_Params.AcqType = BADS_Local_Params_AcqType_eSlowAcquireScan;
2487
2488	/Check if the Timing Search is enabled in the Scan params and if so set to the larger value of acquire Baud Rate and scan Upper_Baud_Search/
2489	if ((hChn->pChnAcqParam->BADS_Scan_Params.TO == BADS_Scan_Params_eEnable) && (hChn->pChnAcqParam->BADS_Scan_Params.Upper_Baud_Search > hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search))
2490	{
2491	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search = hChn->pChnAcqParam->BADS_Scan_Params.Upper_Baud_Search;
2492	}
2493	/Check if the Timing Search is enabled in the Scan params and if so set to the smaller value of acquire Baud Rate and scan Lower_Baud_Search/
2494	if ((hChn->pChnAcqParam->BADS_Scan_Params.TO == BADS_Scan_Params_eEnable) && (hChn->pChnAcqParam->BADS_Scan_Params.Lower_Baud_Search < hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search))
2495	{
2496	hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search = hChn->pChnAcqParam->BADS_Scan_Params.Lower_Baud_Search;
2497	}
2498	/Check if the Carrier Search is enabled in the Scan params and if so set to the larger value of acquire Carrier_Range and scan Carrier_Search/
2499	if ((hChn->pChnAcqParam->BADS_Scan_Params.CO == BADS_Scan_Params_eEnable) && (256*hChn->pChnAcqParam->BADS_Scan_Params.Carrier_Search > hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search))
2500	{
2501	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search = 256*hChn->pChnAcqParam->BADS_Scan_Params.Carrier_Search;
2502	}
2503
2504	/Check if the QAM Mode Search is enabled in the Scan params and is so set to the union of acquire and search QAM settings/
2505
2506	if (hChn->pChnAcqParam->BADS_Scan_Params.QM == BADS_Scan_Params_eEnable)
2507	{
2508	hChn->pChnAcqParam->BADS_Local_Params.Q256A = hChn->pChnAcqParam->BADS_Local_Params.Q256A \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.A256 == BADS_Scan_Params_eEnable) ? true : false);
2509	hChn->pChnAcqParam->BADS_Local_Params.Q256B = hChn->pChnAcqParam->BADS_Local_Params.Q256B \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.B256 == BADS_Scan_Params_eEnable) ? true : false);
2510	hChn->pChnAcqParam->BADS_Local_Params.Q64A = hChn->pChnAcqParam->BADS_Local_Params.Q64A \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.A64 == BADS_Scan_Params_eEnable) ? true : false);
2511	hChn->pChnAcqParam->BADS_Local_Params.Q64B = hChn->pChnAcqParam->BADS_Local_Params.Q64B \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.B64 == BADS_Scan_Params_eEnable) ? true : false);
2512	hChn->pChnAcqParam->BADS_Local_Params.Q128A = hChn->pChnAcqParam->BADS_Local_Params.Q128A \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.A128 == BADS_Scan_Params_eEnable) ? true : false);
2513	hChn->pChnAcqParam->BADS_Local_Params.Q32A = hChn->pChnAcqParam->BADS_Local_Params.Q32A \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.A32 == BADS_Scan_Params_eEnable) ? true : false);
2514	hChn->pChnAcqParam->BADS_Local_Params.Q16A = hChn->pChnAcqParam->BADS_Local_Params.Q16A \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.A16 == BADS_Scan_Params_eEnable) ? true : false);
2515	hChn->pChnAcqParam->BADS_Local_Params.Q1024B = hChn->pChnAcqParam->BADS_Local_Params.Q1024B \|\| ((hChn->pChnAcqParam->BADS_Scan_Params.B1024 == BADS_Scan_Params_eEnable) ? true : false);
2516	}
2517
2518	/Check if the Spectrum Search is enabled in the Scan params/
2519	if (hChn->pChnAcqParam->BADS_Scan_Params.AI == BADS_Scan_Params_eEnable)
2520	{
2521	hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum = true;
2522	}
2523
2524	}
2525	}
2526
2527
2528	/Debug print/
2529	if (PRINT_DEBUG==1)
2530	{
2531	if (hChn->pChnLockStatus->ReAck_Count == 1)
2532	{
2533	BDBG_ERR((" *******************************************************************************************************************************************\n"));
2534	}
2535	if (hChn->pChnLockStatus->ReAck_Count < 9)
2536	{
2537	BDBG_ERR((" ReAck= %d AcqType= %d UBS= %d LBS= %d CS= %d SI= %d AI= %d Q256A= %d Q256B= %d Q64A= %d Q64B= %d Q128A= %d Q32A= %d Q16A= %d, Q1024B= %d\n",
2538	hChn->pChnLockStatus->ReAck_Count,
2539	hChn->pChnAcqParam->BADS_Local_Params.AcqType,
2540	hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search,
2541	hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search,
2542	hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search,
2543	hChn->pChnAcqParam->BADS_Local_Params.Invert_Spectrum,
2544	hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum,
2545	hChn->pChnAcqParam->BADS_Local_Params.Q256A,
2546	hChn->pChnAcqParam->BADS_Local_Params.Q256B,
2547	hChn->pChnAcqParam->BADS_Local_Params.Q64A,
2548	hChn->pChnAcqParam->BADS_Local_Params.Q64B,
2549	hChn->pChnAcqParam->BADS_Local_Params.Q128A,
2550	hChn->pChnAcqParam->BADS_Local_Params.Q32A,
2551	hChn->pChnAcqParam->BADS_Local_Params.Q16A,
2552	hChn->pChnAcqParam->BADS_Local_Params.Q1024B
2553	));
2554	}
2555	}
2556	}
2557
2558
2559	void BADS_P_Get_ChannelPower(BADS_3x7x_ChannelHandle hChn)
2560	{
2561	hChn->pChnAcqParam->BADS_Local_Params.ChannelPower_x256 = 0;
2562	}
2563
2564	int16_t BADS_P_Scale_Power_Check(BADS_3x7x_ChannelHandle hChn, int16_t Power_Check)
2565	{
2566	if (hChn->pChnAcqParam->BADS_Local_Params.Q16A == true)
2567	{
2568	Power_Check = Power_Check;
2569	}
2570	else if (hChn->pChnAcqParam->BADS_Local_Params.Q32A == true)
2571	{
2572	Power_Check = Power_Check + 3;
2573	}
2574	else if ((hChn->pChnAcqParam->BADS_Local_Params.Q64A == true) \|\|(hChn->pChnAcqParam->BADS_Local_Params.Q64B == true))
2575	{
2576	Power_Check = Power_Check + 6;
2577	}
2578	else if (hChn->pChnAcqParam->BADS_Local_Params.Q128A == true)
2579	{
2580	Power_Check = Power_Check + 9;
2581	}
2582	else if ((hChn->pChnAcqParam->BADS_Local_Params.Q256A == true) \|\|(hChn->pChnAcqParam->BADS_Local_Params.Q256B == true))
2583	{
2584	Power_Check = Power_Check + 12;
2585	}
2586	else if (hChn->pChnAcqParam->BADS_Local_Params.Q1024B == true)
2587	{
2588	Power_Check = Power_Check + 15;
2589	}
2590	else
2591	{
2592	Power_Check = Power_Check;
2593	}
2594	return Power_Check;
2595	}
2596
2597	/********************************************************************************************
2598	*BADS_P_AcquisitionPercentageTest
2599	********************************************************************************************/
2600	void BADS_P_AcquisitionPercentageTest(BADS_3x7x_ChannelHandle hChn)
2601	{
2602	uint32_t ReadReg;
2603	uint16_t UpperSpare, LowerSpare;
2604
2605	/Use upper 2 bytes for how many acquisitions to run, lower 2 bytes for number of sucesses/
2606	ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_SPARE);
2607	UpperSpare = (ReadReg>>16) & 0x0000FFFF;
2608	LowerSpare = ReadReg & 0x0000FFFF;
2609
2610	BDBG_MSG(("BADS_P_AcquisitionPercentageTest"));
2611	if (UpperSpare != 0)
2612	{
2613	hChn->pChnAcqParam->BADS_Local_Params.TestLockFlag = BADS_Local_Params_eEnable;
2614	if (hChn->pChnLockStatus->FLK == BADS_3x7x_ChnLockStatus_eLock)
2615	{
2616	LowerSpare++;
2617	}
2618	UpperSpare--;
2619	}
2620	else
2621	{
2622	hChn->pChnAcqParam->BADS_Local_Params.TestLockFlag = BADS_Local_Params_eDisable;
2623	}
2624
2625	/Write back to chip/
2626	ReadReg = ((UpperSpare<<16) & 0xFFFF0000) \| (LowerSpare & 0x0000FFFF);
2627	BREG_Write32(hChn->hRegister, BCHP_DS_SPARE, ReadReg);
2628
2629	}
2630
2631	/********************************************************************************************
2632	*BADS_P_ADS_SLEEP() This is used to allow early exit from acquisition by checking before each delay
2633	********************************************************************************************/
2634	bool BADS_P_ADS_SLEEP(BADS_3x7x_ChannelHandle hChn, unsigned int Delay)
2635	{
2636	static const uint8_t uShift = 5; /* 32 msec increments */
2637	volatile uint32_t uRemainderDelay = 0;
2638	volatile uint32_t uIncrementalDelay;
2639
2640	/* In rev B0 chip there will be more avail BKNI_Events to use. For now, use loop-sleep delay method */
2641	/* Divide delay by 32 msec */
2642	uIncrementalDelay = (Delay >> uShift);
2643	uRemainderDelay = Delay - (uIncrementalDelay<<uShift);
2644	if ( uRemainderDelay > Delay )
2645	{
2646	uRemainderDelay = 0;
2647	}
2648
2649	/* BDBG_MSG(("BADS_P_ADS_SLEEP: D: 0x%06X, I: 0x%06X, R: 0x%06X", Delay, uIncrementalDelay , uRemainderDelay)); */
2650
2651	/* Delay loop */
2652	while ( (0 != uIncrementalDelay) \|\| (0 != uRemainderDelay) )
2653	{
2654	/* Terminate on early exit */
2655	if ( hChn->pChnAcqParam->BADS_Local_Params.EarlyExit )
2656	{
2657	#if FALSE /* Debug only */
2658	BDBG_MSG(("** EARLY EXIT Ads Chn %d **", hChn->chnNo));
2659	BDBG_MSG(("** EARLY EXIT Ads Chn %d **", hChn->chnNo));
2660	BDBG_MSG(("** EARLY EXIT Ads Chn %d **", hChn->chnNo));
2661	#endif /* FALSE - Debug only */
2662	/* Stop while-loop*/
2663	break;
2664	}
2665	/* Delay using incremental delay count (Delay/32) */
2666	if ( uIncrementalDelay )
2667	{
2668	BKNI_Sleep((1<<uShift));
2669	--uIncrementalDelay;
2670	/* Continue while-loop*/
2671	continue;
2672	}
2673	/* Final/last Delay (Delay MOD uIncrementalDelay) */
2674	if ( 0 != uRemainderDelay )
2675	{
2676	BKNI_Sleep(uRemainderDelay);
2677	/* Stop while-loop*/
2678	break;
2679	}
2680	}
2681
2682	return ( hChn->pChnAcqParam->BADS_Local_Params.EarlyExit );
2683	}
2684
2685
2686	/THE FFT FUNCTION IS DIFFERENT BETWEEN CORES/
2687	#if BCHP_DS_CORE_V_9_1
2688	/****************************************************************************************
2689	*BADS_P_Get_TimingScan_FFT() Perform the FFT timing scan search returning the baud rate
2690	*The function will return a 0 if the peak is too small or outside of a window defined by
2691	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Threshold and
2692	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent +
2693	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins
2694	****************************************************************************************/
2695	uint32_t BADS_P_Get_TimingScan_FFT(BADS_3x7x_ChannelHandle hChn, uint32_t Upper_Baud_Search, bool ReturnBin)
2696	{
2697	/Local Variables/
2698	uint8_t NumFFTs;
2699	uint16_t FFT_Bin;
2700	int16_t FFT_Bin_Check1, FFT_Bin_Check2, FFT_Bin_Check3, FFT_DiffA, FFT_DiffB, FFT_DiffC;
2701	uint32_t FFT_Peak;
2702	uint32_t GuardBins;
2703	uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
2704
2705	#if FFT_INTERRUPT
2706	uint32_t err;
2707	#endif
2708	/* BDBG_MSG(("BADS_P_Get_TimingScan_FFT "));*/
2709	/Check to make sure symbol rate is in range, this is based only on the timing FCW/
2710	if ((Upper_Baud_Search < 500000) \|\| (Upper_Baud_Search >= F_1S/4))
2711	{
2712	BDBG_ERR(("Upper_Search_Rate out of range in BADS_P_Set_TL_Frequency()"));
2713	}
2714
2715	/these initial values prevent the comparison from being true at the beginning/
2716	FFT_Bin_Check1 = -9999;
2717	FFT_Bin_Check2 = 999;
2718	FFT_Bin_Check3 = -999;
2719	for (NumFFTs=0;NumFFTs<NUM_TIMING_FFTS;NumFFTs++)
2720	{
2721	#if FFT_INTERRUPT
2722	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_CHSCN_IMCLR_MASK);
2723	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_CHSCN_IMCLR_MASK);
2724	#endif
2725	/Registers for Fast Timing Mode/
2726	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, PKDET_DELAY, 1); /PKDET_DELAY, start window for peak return from FFT, 0 is DC, min=0 max=2047/
2727	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 0); /edge triggered start, 1: CHSCN start, 0: CHSCN stop /
2728	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_MODE, 1); /Fast Timing Acquisition, 1: CHSCN MODE ON, 0: CHSCN MODE OFF/
2729
2730	#if FFT_INTERRUPT
2731	#if (BCHP_FAMILY==3461)
2732	/* Create timing scan IRQ event */
2733	if( (err = BKNI_CreateEvent(&(hChn->hChscnEvent))) != BERR_SUCCESS)
2734	{
2735	BDBG_WRN(("OS ERROR creating event for Timing Scan interrupt!!!!! 0x%08X\n", err));
2736	}
2737	#endif
2738	BKNI_ResetEvent(hChn->hChscnEvent);
2739	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 1);
2740	if( (err = BKNI_WaitForEvent(hChn->hChscnEvent,200001000/Upper_Baud_Search)) != BERR_SUCCESS) /set interrupt timeout to 20000 symbols*/
2741	{
2742	BDBG_WRN((" CHSCN TIMEOUT EVENT or OS ERR waiting for Timing Scan interrupt!!!!! 0x%08X\n", err));
2743	}
2744	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMSET2, BCHP_DS_IRQMCLR2_CHSCN_IMCLR_MASK);
2745	#if (BCHP_FAMILY==3461)
2746	BKNI_DestroyEvent(hChn->hChscnEvent);
2747	#endif
2748	#else
2749	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 1);
2750	/BKNI_Sleep(200001000/Upper_Baud_Search);/ /This hack is to make the timeout > 5500 baud clocks and always be at least 1*/
2751	BADS_P_ADS_SLEEP(hChn, 20000*1000/Upper_Baud_Search);
2752	#endif
2753	/Get the FFT results/
2754	FFT_Peak = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_PK_VALUE);
2755	FFT_Bin = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_INDEX);
2756
2757
2758	FFT_Bin_Check3 = FFT_Bin_Check2;
2759	FFT_Bin_Check2 = FFT_Bin_Check1;
2760	FFT_Bin_Check1 = (int16_t)((FFT_Bin > 2048) ? (4096-FFT_Bin) : FFT_Bin);
2761
2762	FFT_DiffA = FFT_Bin_Check1-FFT_Bin_Check2;
2763	FFT_DiffB = FFT_Bin_Check1-FFT_Bin_Check3;
2764	FFT_DiffC = FFT_Bin_Check2-FFT_Bin_Check3;
2765
2766	/Check if they are within 1 or if the NUM_TIMING_FFTS = 1/
2767	if ((((FFT_DiffA) >= -1) && ((FFT_DiffA) <=1)) \|\|
2768	(((FFT_DiffB) >= -1) && ((FFT_DiffB) <=1)) \|\|
2769	(((FFT_DiffC) >= -1) && ((FFT_DiffC) <=1)) \|\|
2770	(NUM_TIMING_FFTS == 1))
2771
2772	{
2773	NumFFTs = NUM_TIMING_FFTS;
2774	}
2775	/BDBG_WRN(("FFT_Peak = %d FFT_Bin = %d FFT_Bin_Check1 = %d FFT_Bin_Check2 = %d FFT_Bin_Check3 = %d NumFFTs = %d",FFT_Peak,FFT_Bin,FFT_Bin_Check1,FFT_Bin_Check2,FFT_Bin_Check3,NumFFTs));/
2776
2777	}
2778
2779	/Caculater the baud rate found/
2780	ulMultA = Upper_Baud_Search;
2781	ulMultB = (FFT_Bin > 2048) ? (4096-FFT_Bin)2 : FFT_Bin2;
2782	ulDivisor = POWER2_12;
2783	BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
2784	BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
2785
2786	/disable fast timing/
2787	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 0);
2788	BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_MODE, 0);
2789
2790	/*Guard Bin Calculation
2791	*For Baud Rate the bins are symetric, a 2048 means baud rate is the one programmed
2792	2047 to 0 is symetric with 2049 to 4095 and are lower baud rates/
2793	GuardBins = 2048*(25600-(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent + hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins));
2794	GuardBins = GuardBins/(25600+(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent + hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins));
2795
2796	/BDBG_WRN(("NumFFTs = %d",NumFFTs));/
2797
2798	/Disqualify bin if threshold not met or if it is not within the window set by GuardBins/
2799	if ((FFT_Peak < hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Threshold) \|\|
2800	(FFT_Bin < GuardBins) \|\|
2801	(FFT_Bin > (4096 - GuardBins)) \|\|
2802	(NumFFTs != (NUM_TIMING_FFTS+1)))
2803	{
2804	ulNrmLo = 0;
2805
2806	}
2807
2808	/return selected value/
2809	ulNrmLo = (ReturnBin == true) ? FFT_Bin : ulNrmLo;
2810	return ulNrmLo;
2811	}
2812
2813
2814	/****************************************************************************************
2815	*BADS_P_Get_CarrierScan_FFT() Perform the FFT carrier scan search returning the carrier offset
2816	*The function will return a 0 if the peak is too small or outside of a window defined by
2817	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Threshold and
2818	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Percent +
2819	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Extra_Bins
2820	*If CMA == true the FFT will use post EQ data, if false the FFT will use pre EQ data
2821	*The timing loop must be locked for this function to return good results
2822	****************************************************************************************/
2823	int32_t BADS_P_Get_CarrierScan_FFT(BADS_3x7x_ChannelHandle hChn, uint32_t Symbol_Rate, bool CMA)
2824	{
2825	/Local Variables/
2826	uint8_t NumFFTs;
2827	uint16_t FFT_Bin;
2828	uint32_t FFT_Peak;
2829	int16_t FFT_Bin_Check1, FFT_Bin_Check2, FFT_Bin_Check3, FFT_DiffA, FFT_DiffB, FFT_DiffC;
2830	int32_t Carrier_Offset;
2831	uint32_t GuardBins;
2832	uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
2833	#if FFT_INTERRUPT
2834	uint32_t err;
2835	#endif
2836	/* BDBG_MSG(("BADS_P_Get_CarrierScan_FFT "));*/
2837	/Clamp the timing loop since it may be unlocked/
2838	if (Symbol_Rate < 500000)
2839	{
2840	Symbol_Rate = 500000;
2841	}
2842	if (Symbol_Rate >= F_1S/4)
2843	{
2844	Symbol_Rate = F_1S/4;
2845	}
2846
2847	/these initial values prevent the comparison from being true at the beginning/
2848	FFT_Bin_Check1 = -9999;
2849	FFT_Bin_Check2 = 999;
2850	FFT_Bin_Check3 = -999;
2851	for (NumFFTs=0;NumFFTs<NUM_CARRIER_FFTS;NumFFTs++)
2852	{
2853	#if FFT_INTERRUPT
2854	#ifndef LEAP_BASED_CODE
2855	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_FCA_IMCLR_MASK);
2856	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_FCA_IMCLR_MASK);
2857	#endif
2858	#endif
2859	/Registers for Fast Carrier Mode (timing must be locked for this to work)/
2860	/Carrier offset found is (FFT_INDEXBaudRate)/16384 */
2861	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, DEROT_FCW_INV, 1); /* Derotator FCW Invert, 0: normal, 1: Invert*/
2862	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, DEROT_FCW_DIS, 1); /Derotator FCW update disable, 0: Enable FCW, 1: Disable FCW/
2863	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, POST_EQ_DATA_SEL, CMA); /* FFT PRE/POSTEQ, 0: select Pre, 1: select Post*/
2864	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_START, 0); /edge triggered start, 1: FCA start, 0: FCA stop /
2865	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_MODE, 1); /Fast Carrier Acquisition, 1: FCA MODE ON, 0: FCA MODE OFF/
2866
2867
2868	#if FFT_INTERRUPT
2869	#if (BCHP_FAMILY==3461)
2870	if ( (err = BKNI_CreateEvent(&(hChn->hFcaEvent))) != BERR_SUCCESS )
2871	{
2872	BDBG_WRN(("OS ERROR creating event for Carrier Scan interrupt!!!!! 0x%08X\n", err));
2873	}
2874	#endif
2875	BKNI_ResetEvent(hChn->hFcaEvent);
2876	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_START, 1); /edge triggered start, 1: FCA start, 0: FCA stop /
2877	if( (err = BKNI_WaitForEvent(hChn->hFcaEvent,200001000/Symbol_Rate)) != BERR_SUCCESS) /set interrupt timeout to 20000 symbols*/
2878	{
2879	BDBG_WRN(("FCA TIMEOUT EVENT or OS ERR waiting for Carrier Scan interrupt!!!!! 0x%08X\n", err));
2880	}
2881	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMSET2, BCHP_DS_IRQMCLR2_FCA_IMCLR_MASK);
2882	#if (BCHP_FAMILY==3461)
2883	BKNI_DestroyEvent(hChn->hFcaEvent);
2884	#endif
2885
2886	#else
2887	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_START, 1); /edge triggered start, 1: FCA start, 0: FCA stop /
2888	/BKNI_Sleep(200001000/Symbol_Rate);/ /This hack is to make the timeout > 5500 baud clocks and always be at least 1*/
2889	BADS_P_ADS_SLEEP(hChn, 20000*1000/Symbol_Rate);
2890	#endif
2891	/Get the FFT results/
2892	FFT_Peak = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_PK_VALUE);
2893	FFT_Bin = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_INDEX);
2894
2895	FFT_Bin_Check3 = FFT_Bin_Check2;
2896	FFT_Bin_Check2 = FFT_Bin_Check1;
2897	FFT_Bin_Check1 = (int16_t)((FFT_Bin > 2048) ? (4096-FFT_Bin) : FFT_Bin);
2898
2899	FFT_DiffA = FFT_Bin_Check1-FFT_Bin_Check2;
2900	FFT_DiffB = FFT_Bin_Check1-FFT_Bin_Check3;
2901	FFT_DiffC = FFT_Bin_Check2-FFT_Bin_Check3;
2902
2903	/Check if they are within 1 or if the NUM_TIMING_FFTS = 1/
2904	if ((((FFT_DiffA) >= -1) && ((FFT_DiffA) <=1)) \|\|
2905	(((FFT_DiffB) >= -1) && ((FFT_DiffB) <=1)) \|\|
2906	(((FFT_DiffC) >= -1) && ((FFT_DiffC) <=1)) \|\|
2907	(NUM_TIMING_FFTS == 1))
2908
2909	{
2910	NumFFTs = NUM_CARRIER_FFTS;
2911	}
2912	}
2913	/Calculate the carrier offset/
2914	ulMultA = (FFT_Bin > 2047) ? (4096-FFT_Bin) : FFT_Bin;
2915	ulMultB = Symbol_Rate;
2916	ulDivisor = POWER2_14;
2917	BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
2918	BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
2919
2920	Carrier_Offset = (int32_t)ulNrmLo;
2921	Carrier_Offset = (FFT_Bin > 2047) ? -1*Carrier_Offset : Carrier_Offset;
2922
2923
2924	/disable fast carrier/
2925	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_START, 0);
2926	BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_MODE, 0);
2927
2928	/Extra Guard Bin Calculation/
2929	GuardBins = POWER2_14*(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Percent + hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Extra_Bins);
2930	GuardBins = GuardBins/25600;
2931
2932	/*Disqualify bin if threshold not met or if it is not within the window set by GuardBins
2933	*For Carrier Offset the Bin is 2's complement so + carrier offsets go from 0-2048
2934	negative offsets go from 4095 to 2048/
2935	if ( (FFT_Peak < hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Threshold) \|\|
2936	((FFT_Bin > (GuardBins-1)) && (FFT_Bin < (4096 - GuardBins))) )
2937	{
2938	/* Carrier_Offset = 0;*/
2939	}
2940	/BDBG_WRN(("Carrier FFT_Peak = %d FFT_Bin = %d FFT_Bin_Check1 = %d FFT_Bin_Check2 = %d FFT_Bin_Check3 = %d NumFFTs = %d Carrier_Offset = %d",FFT_Peak,FFT_Bin,FFT_Bin_Check1,FFT_Bin_Check2,FFT_Bin_Check3,NumFFTs, Carrier_Offset));/
2941
2942
2943	return Carrier_Offset;
2944	}
2945
2946
2947	#elif ((BCHP_DS_CORE_V_9_2) \|\| (BCHP_DS_CORE_V_9_3))
2948	/****************************************************************************************
2949	*BADS_P_Get_TimingScan_Advanced_FFT() Perform the FFT timing scan search returning the baud rate
2950	*The function will return a 0 if the peak is too small or outside of a window defined by
2951	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Threshold and
2952	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent +
2953	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins
2954	****************************************************************************************/
2955	uint32_t BADS_P_Get_TimingScan_Advanced_FFT(BADS_3x7x_ChannelHandle hChn, uint32_t Upper_Baud_Search, bool ReturnBin)
2956	{
2957
2958	/Local Variables/
2959	uint8_t NumFFTs;
2960	uint16_t FFT_Bin;
2961	int16_t FFT_Bin_Check1, FFT_Bin_Check2, FFT_Bin_Check3, FFT_DiffA, FFT_DiffB, FFT_DiffC;
2962	uint32_t FFT_Peak;
2963	uint32_t GuardBins;
2964	uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
2965
2966	#if FFT_INTERRUPT
2967	uint32_t err;
2968	#endif
2969	/* BDBG_MSG(("BADS_P_Get_TimingScan_FFT "));*/
2970	/Check to make sure symbol rate is in range, this is based only on the timing FCW/
2971	if ((Upper_Baud_Search < 500000) \|\| (Upper_Baud_Search >= F_1S/4))
2972	{
2973	BDBG_ERR(("Upper_Search_Rate out of range in BADS_P_Set_TL_Frequency()"));
2974	}
2975
2976	/these initial values prevent the comparison from being true at the beginning/
2977	FFT_Bin_Check1 = -9999;
2978	FFT_Bin_Check2 = 999;
2979	FFT_Bin_Check3 = -999;
2980	for (NumFFTs=0;NumFFTs<NUM_TIMING_FFTS;NumFFTs++)
2981	{
2982	#if FFT_INTERRUPT
2983	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_FFT_IMCLR_MASK);
2984	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_FFT_IMCLR_MASK);
2985	#endif
2986	/Registers for Fast Timing Mode/
2987	/From old FFT function/
2988	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, PKDET_DELAY, 1);/ /PKDET_DELAY, start window for peak return from FFT, 0 is DC, min=0 max=2047/
2989	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 0);/ /edge triggered start, 1: CHSCN start, 0: CHSCN stop /
2990	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_MODE, 1); / /Fast Timing Acquisition, 1: CHSCN MODE ON, 0: CHSCN MODE OFF/
2991	BREG_WriteField(hChn->hRegister, DS_FFT_PDETW, WIN_UP, 0xC00); /Upper windor bound at 3072/
2992	BREG_WriteField(hChn->hRegister, DS_FFT_PDETW, WIN_LO, 0x400); /Upper windor bound at 1024/
2993	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, DATA_SEL, 0x4); /select Nyquist Prefilter Data/
2994	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 0); /stop/
2995	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, MODE, 0x2); /Channel Scan (CHSCN) Mode /
2996
2997	#if FFT_INTERRUPT
2998	BKNI_ResetEvent(hChn->hFftEvent);
2999	/From old FFT function/
3000	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 1);/
3001	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 1); /start/
3002	if( (err = BKNI_WaitForEvent(hChn->hFftEvent, 7)) != BERR_SUCCESS) /set interrupt timeout to 7 ms which is 2x more than worst case/
3003	{
3004	BDBG_WRN((" CHSCN TIMEOUT EVENT or OS ERR waiting for Timing Scan interrupt!!!!! 0x%08X\n", err));
3005	}
3006	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMSET2, BCHP_DS_IRQMCLR2_FFT_IMCLR_MASK);
3007	#else
3008	/From old FFT function/
3009	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 1);/
3010	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 0); /start/
3011	/BKNI_Sleep(200001000/Upper_Baud_Search);/ /This hack is to make the timeout > 5500 baud clocks and always be at least 1*/
3012	BADS_P_ADS_SLEEP(hChn, 7); /set interrupt timeout to 7 ms which is 2x more than worst case/
3013	#endif
3014	/Get the FFT results/
3015	/From old FFT function/
3016	/FFT_Peak = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_PK_VALUE); /
3017	/FFT_Bin = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_INDEX);/
3018	FFT_Peak = BREG_ReadField(hChn->hRegister, DS_FFT_VAL, PEAK);
3019	FFT_Bin = BREG_ReadField(hChn->hRegister, DS_FFT_BIN, INDEX);
3020
3021	FFT_Bin_Check3 = FFT_Bin_Check2;
3022	FFT_Bin_Check2 = FFT_Bin_Check1;
3023	FFT_Bin_Check1 = (int16_t)((FFT_Bin > 2048) ? (4096-FFT_Bin) : FFT_Bin);
3024
3025	FFT_DiffA = FFT_Bin_Check1-FFT_Bin_Check2;
3026	FFT_DiffB = FFT_Bin_Check1-FFT_Bin_Check3;
3027	FFT_DiffC = FFT_Bin_Check2-FFT_Bin_Check3;
3028
3029	/Check if they are within 1 or if the NUM_TIMING_FFTS = 1/
3030	if ((((FFT_DiffA) >= -1) && ((FFT_DiffA) <=1)) \|\|
3031	(((FFT_DiffB) >= -1) && ((FFT_DiffB) <=1)) \|\|
3032	(((FFT_DiffC) >= -1) && ((FFT_DiffC) <=1)) \|\|
3033	(NUM_TIMING_FFTS == 1))
3034
3035	{
3036	NumFFTs = NUM_TIMING_FFTS;
3037	}
3038	/BDBG_WRN(("FFT_Peak = %d FFT_Bin = %d FFT_Bin_Check1 = %d FFT_Bin_Check2 = %d FFT_Bin_Check3 = %d NumFFTs = %d",FFT_Peak,FFT_Bin,FFT_Bin_Check1,FFT_Bin_Check2,FFT_Bin_Check3,NumFFTs));/
3039
3040	}
3041
3042	/Caculater the baud rate found/
3043	ulMultA = Upper_Baud_Search;
3044	ulMultB = (FFT_Bin > 2048) ? (4096-FFT_Bin)2 : FFT_Bin2;
3045	ulDivisor = POWER2_12;
3046	BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
3047	BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
3048
3049	/disable fast timing/
3050	/From old FFT function/
3051	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 0);/
3052	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_MODE, 0);/
3053	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 0); /stop/
3054	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, MODE, 0); /FFT function is off/
3055
3056	/*Guard Bin Calculation
3057	*For Baud Rate the bins are symetric, a 2048 means baud rate is the one programmed
3058	2047 to 0 is symetric with 2049 to 4095 and are lower baud rates/
3059	GuardBins = 2048*(25600-(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent + hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins));
3060	GuardBins = GuardBins/(25600+(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Percent + hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Extra_Bins));
3061
3062	/BDBG_WRN(("NumFFTs = %d",NumFFTs));/
3063
3064	/Disqualify bin if threshold not met or if it is not within the window set by GuardBins/
3065	if ((FFT_Peak < hChn->pChnAcqParam->BADS_Internal_Params.BBS_Timing_Scan_Threshold) \|\|
3066	(FFT_Bin < GuardBins) \|\|
3067	(FFT_Bin > (4096 - GuardBins)) \|\|
3068	(NumFFTs != (NUM_TIMING_FFTS+1)))
3069	{
3070	ulNrmLo = 0;
3071
3072	}
3073
3074	/return selected value/
3075	ulNrmLo = (ReturnBin == true) ? FFT_Bin : ulNrmLo;
3076	return ulNrmLo;
3077
3078	}
3079
3080
3081	/****************************************************************************************
3082	*BADS_P_Get_CarrierScan_Advanced_FFT() Perform the FFT carrier scan search returning the carrier offset
3083	*The function will return a 0 if the peak is too small or outside of a window defined by
3084	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Threshold and
3085	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Percent +
3086	*hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Extra_Bins
3087	*If CMA == true the FFT will use post EQ data, if false the FFT will use pre EQ data
3088	*The timing loop must be locked for this function to return good results
3089	****************************************************************************************/
3090	int32_t BADS_P_Get_CarrierScan_Advanced_FFT(BADS_3x7x_ChannelHandle hChn, uint32_t Symbol_Rate, bool CMA)
3091	{
3092
3093	/Local Variables/
3094	uint8_t NumFFTs;
3095	uint16_t FFT_Bin;
3096	uint32_t FFT_Peak;
3097	int16_t FFT_Bin_Check1, FFT_Bin_Check2, FFT_Bin_Check3, FFT_DiffA, FFT_DiffB, FFT_DiffC;
3098	int32_t Carrier_Offset;
3099	uint32_t GuardBins;
3100	uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
3101	#if FFT_INTERRUPT
3102	uint32_t err;
3103	#endif
3104
3105	BSTD_UNUSED(CMA);
3106	/* BDBG_MSG(("BADS_P_Get_CarrierScan_FFT "));*/
3107	/Clamp the timing loop since it may be unlocked/
3108	if (Symbol_Rate < 500000)
3109	{
3110	Symbol_Rate = 500000;
3111	}
3112	if (Symbol_Rate >= F_1S/4)
3113	{
3114	Symbol_Rate = F_1S/4;
3115	}
3116
3117	/these initial values prevent the comparison from being true at the beginning/
3118	FFT_Bin_Check1 = -9999;
3119	FFT_Bin_Check2 = 999;
3120	FFT_Bin_Check3 = -999;
3121	for (NumFFTs=0;NumFFTs<NUM_CARRIER_FFTS;NumFFTs++)
3122	{
3123	#if FFT_INTERRUPT
3124	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_FFT_IMCLR_MASK);
3125	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMCLR2, BCHP_DS_IRQMCLR2_FFT_IMCLR_MASK);
3126	#endif
3127	/Registers for Fast Carrier Mode (timing must be locked for this to work)/
3128	/Carrier offset found is (FFT_INDEXBaudRate)/16384 */
3129	/From old FFT function/
3130	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, DEROT_FCW_INV, 1);/ /* Derotator FCW Invert, 0: normal, 1: Invert*/
3131	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, DEROT_FCW_DIS, 1);/ /Derotator FCW update disable, 0: Enable FCW, 1: Disable FCW/
3132	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, POST_EQ_DATA_SEL, CMA);/ /* FFT PRE/POSTEQ, 0: select Pre, 1: select Post*/
3133	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_START, 0);/ /edge triggered start, 1: FCA start, 0: FCA stop /
3134	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_MODE, 1);/ /Fast Carrier Acquisition, 1: FCA MODE ON, 0: FCA MODE OFF/
3135	BREG_WriteField(hChn->hRegister, DS_FFT_PDETW, WIN_UP, 0xFFF); /Upper windor bound at 4095/
3136	BREG_WriteField(hChn->hRegister, DS_FFT_PDETW, WIN_LO, 0x1); /Upper windor bound at 1/
3137	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, DATA_SEL, 0x1); /select Post Equalizer data/
3138	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 0); /stop/
3139	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, MODE, 0x1); /Fast Carrier Acquisition (FCA) Mode /
3140
3141	#if FFT_INTERRUPT
3142	BKNI_ResetEvent(hChn->hFftEvent);
3143	/From old FFT function/
3144	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 1);/
3145	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 1); /start/
3146	if( (err = BKNI_WaitForEvent(hChn->hFftEvent, 11)) != BERR_SUCCESS) /set interrupt timeout to 11 ms which is 2x more than worst case/
3147	{
3148	BDBG_WRN(("FCA TIMEOUT EVENT or OS ERR waiting for Carrier Scan interrupt!!!!! 0x%08X\n", err));
3149	}
3150	BREG_Write32(hChn->hRegister, BCHP_DS_IRQMSET2, BCHP_DS_IRQMCLR2_FFT_IMCLR_MASK);
3151	#else
3152	/From old FFT function/
3153	/BREG_WriteField(hChn->hRegister, DS_EQ_CHSCN_CTL, CHSCN_START, 1);/
3154	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 1); /start/
3155	/BKNI_Sleep(200001000/Symbol_Rate);/ /This hack is to make the timeout > 5500 baud clocks and always be at least 1*/
3156	BADS_P_ADS_SLEEP(hChn, 11); /set interrupt timeout to 11 ms which is 2x more than worst case/
3157	#endif
3158	/Get the FFT results/
3159	/From old FFT function/
3160	/FFT_Peak = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_PK_VALUE); /
3161	/FFT_Bin = BREG_ReadField(hChn->hRegister, DS_EQ_FFT_VAL, FFT_INDEX);/
3162	FFT_Peak = BREG_ReadField(hChn->hRegister, DS_FFT_VAL, PEAK);
3163	FFT_Bin = BREG_ReadField(hChn->hRegister, DS_FFT_BIN, INDEX);
3164
3165	FFT_Bin_Check3 = FFT_Bin_Check2;
3166	FFT_Bin_Check2 = FFT_Bin_Check1;
3167	FFT_Bin_Check1 = (int16_t)((FFT_Bin > 2048) ? (4096-FFT_Bin) : FFT_Bin);
3168
3169	FFT_DiffA = FFT_Bin_Check1-FFT_Bin_Check2;
3170	FFT_DiffB = FFT_Bin_Check1-FFT_Bin_Check3;
3171	FFT_DiffC = FFT_Bin_Check2-FFT_Bin_Check3;
3172
3173	/Check if they are within 1 or if the NUM_TIMING_FFTS = 1/
3174	if ((((FFT_DiffA) >= -1) && ((FFT_DiffA) <=1)) \|\|
3175	(((FFT_DiffB) >= -1) && ((FFT_DiffB) <=1)) \|\|
3176	(((FFT_DiffC) >= -1) && ((FFT_DiffC) <=1)) \|\|
3177	(NUM_TIMING_FFTS == 1))
3178
3179	{
3180	NumFFTs = NUM_CARRIER_FFTS;
3181	}
3182	}
3183	/Calculate the carrier offset/
3184	ulMultA = (FFT_Bin > 2047) ? (4096-FFT_Bin) : FFT_Bin;
3185	ulMultB = Symbol_Rate;
3186	ulDivisor = POWER2_14;
3187	BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
3188	BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
3189
3190	Carrier_Offset = (int32_t)ulNrmLo;
3191	Carrier_Offset = (FFT_Bin > 2047) ? -1*Carrier_Offset : Carrier_Offset;
3192
3193	/disable fast timing/
3194	/From old FFT function/
3195	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_START, 0);/
3196	/BREG_WriteField(hChn->hRegister, DS_EQ_FCA_CTL, FCA_MODE, 0);/
3197	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, START, 0); /stop/
3198	BREG_WriteField(hChn->hRegister, DS_FFT_CTL, MODE, 0); /FFT function is off/
3199
3200
3201	/Extra Guard Bin Calculation/
3202	GuardBins = POWER2_14*(hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Percent + hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Extra_Bins);
3203	GuardBins = GuardBins/25600;
3204
3205	/*Disqualify bin if threshold not met or if it is not within the window set by GuardBins
3206	*For Carrier Offset the Bin is 2's complement so + carrier offsets go from 0-2048
3207	negative offsets go from 4095 to 2048/
3208	if ( (FFT_Peak < hChn->pChnAcqParam->BADS_Internal_Params.BBS_Carrier_Scan_Threshold) \|\|
3209	((FFT_Bin > (GuardBins-1)) && (FFT_Bin < (4096 - GuardBins))) )
3210	{
3211	/* Carrier_Offset = 0;*/
3212	}
3213	/BDBG_WRN(("Carrier FFT_Peak = %d FFT_Bin = %d FFT_Bin_Check1 = %d FFT_Bin_Check2 = %d FFT_Bin_Check3 = %d NumFFTs = %d Carrier_Offset = %d",FFT_Peak,FFT_Bin,FFT_Bin_Check1,FFT_Bin_Check2,FFT_Bin_Check3,NumFFTs, Carrier_Offset));/
3214
3215
3216	return Carrier_Offset;
3217
3218	}
3219
3220	#endif
3221
3222

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/ads/7552/bads_acquire.c

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