source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/ads/7552/bads_status.c

Last change on this file was 2, checked in by jglee, 11 years ago

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1/***************************************************************************
2 *     (c)2003-2012 Broadcom Corporation
3 * 
4 *  This program is the proprietary software of Broadcom Corporation and/or its licensors,
5 *  and may only be used, duplicated, modified or distributed pursuant to the terms and
6 *  conditions of a separate, written license agreement executed between you and Broadcom
7 *  (an "Authorized License").  Except as set forth in an Authorized License, Broadcom grants
8 *  no license (express or implied), right to use, or waiver of any kind with respect to the
9 *  Software, and Broadcom expressly reserves all rights in and to the Software and all
10 *  intellectual property rights therein.  IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11 *  HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12 *  NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE. 
13 *   
14 *  Except as expressly set forth in the Authorized License,
15 *   
16 *  1.     This program, including its structure, sequence and organization, constitutes the valuable trade
17 *  secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof,
18 *  and to use this information only in connection with your use of Broadcom integrated circuit products.
19 *   
20 *  2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
21 *  AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR
22 *  WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
23 *  THE SOFTWARE.  BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES
24 *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE,
25 *  LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION
26 *  OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF
27 *  USE OR PERFORMANCE OF THE SOFTWARE.
28 * 
29 *  3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS
30 *  LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR
31 *  EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR
32 *  USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF
33 *  THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT
34 *  ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE
35 *  LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF
36 *  ANY LIMITED REMEDY.
37 *
38 * $brcm_Workfile: bads_status.c $
39 * $brcm_Revision: 42 $
40 * $brcm_Date: 2/9/12 12:44p $
41 *
42 * Module Description:
43 *
44 * Revision History:  $
45 *
46 * $brcm_Log: /AP/ctfe/core/ads/bads_status.c $
47 *
48 * 42   2/9/12 12:44p farshidf
49 * SW3128-1: merge to main
50 *
51 * Fw_Integration_Devel/10   2/9/12 12:14p farshidf
52 * SW3128-1: merge to integ
53 *
54 * Fw_Integration_Devel/AP_V3_0_ADS_DEV/5   1/26/12 4:09p cbrooks
55 * sw3128-1:fixed a problem in HUM AGC gain
56 *
57 * Fw_Integration_Devel/AP_V3_0_ADS_DEV/4   1/26/12 3:18p cbrooks
58 * sw3128-1:added saturation to hum AGC calculation
59 *
60 * Fw_Integration_Devel/AP_V3_0_ADS_DEV/3   1/26/12 12:37p cbrooks
61 * sw3128-1:added hum AGC status
62 *
63 * Fw_Integration_Devel/AP_V3_0_ADS_DEV/2   11/21/11 6:55p mpovich
64 * SW3128-71: Support for a single, common 3128 chip family F/W binary.
65 *
66 * Fw_Integration_Devel/AP_V3_0_ADS_DEV/SW3128-71/1   11/17/11 6:57p mpovich
67 * SW3128-71: Support for common 3128 family chip F/W.
68 *
69 * Fw_Integration_Devel/AP_V3_0_ADS_DEV/1   11/10/11 11:03a dorothyl
70 * SW3128-1: move error counter reset after bert sync
71 *
72 * 37   8/24/11 12:22p farshidf
73 * SW3461-18: merge to main
74 *
75 * Fw_Integration_Devel/7   8/24/11 11:59a farshidf
76 * SW3461-38: merge to integ
77 *
78 * Fw_Integration_Devel/AP_V2_0_ADS_DEV/2   8/23/11 4:49p mpovich
79 * SW3128-24: Merge latest of SW3128-24 to devel. branch.
80 *
81 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-24/2   8/23/11 4:29p mpovich
82 * SW3128-24: Rebase with 2.0 devel. branch.
83 *
84 * Fw_Integration_Devel/AP_V2_0_ADS_DEV/1   8/18/11 1:34p mpovich
85 * SW3128-24: Merge Scan feature support into the devel. branch.
86 *
87 * 36   8/12/11 3:13p farshidf
88 * SW3461-1: merge to main
89 *
90 * Fw_Integration_Devel/5   8/12/11 2:11p farshidf
91 * SW3461-1: merge to integ
92 *
93 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-24/1   8/16/11 6:37p mpovich
94 * SW3128-24: Pick up SW3128-32, "Get Scan Status" HAB command
95 *
96 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-32/1   8/16/11 5:35p cbrooks
97 * sw3128-1:simplified ifthen for scanstatus
98 *
99 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/9   8/11/11 10:20a mpovich
100 * SW3128-31: Ensure ADS channel status may be obtained concurrently.
101 *
102 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/SW3128-31/1   8/11/11 10:09a mpovich
103 * SW3128-31: Ensure channel status may be obtained concurrently.
104 *
105 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/8   7/28/11 12:55p cbrooks
106 * sw3128-1:added EarlyExit to AcquireAtatus
107 *
108 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/7   7/27/11 7:58p cbrooks
109 * sw3128-1:added early exit
110 *
111 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/6   7/22/11 4:52p cbrooks
112 * sw3128-1:Added SLow Scan for RFI interference
113 *
114 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/4   7/8/11 4:52p cbrooks
115 * sw3128-1:fixed casting in status
116 *
117 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/3   7/8/11 10:59a cbrooks
118 * sw3128-1:LNA gain added
119 *
120 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/2   7/8/11 10:15a cbrooks
121 * sw3128-1:added callback support
122 *
123 * Fw_Integration_Devel/AP_V0_6_ADS_DEV/1   6/30/11 6:01p cbrooks
124 * SW3128-1:ADDED FREQUENCY DEPENDENT GAIN OFFSET FOR CHANNEL POWER
125 *  ESTIMATE
126 *
127 * Fw_Integration_Devel/1   6/29/11 12:38p farshidf
128 * SW3461-13: merge to integration branch
129 *
130 * Fw_Integration_Devel/Ads_Fw_Devel_Rc04/3   6/28/11 6:49p cbrooks
131 * sw3128-1:added main tap
132 *
133 * Fw_Integration_Devel/Ads_Fw_Devel_Rc04/2   6/21/11 5:17p cbrooks
134 * sw3128-1:Added racquire count
135 *
136 * Fw_Integration_Devel/Ads_Fw_Devel_Rc04/1   6/20/11 3:08p cbrooks
137 * sw3128-1:added channel power status
138 *
139 * 33   6/9/11 6:15p mpovich
140 * SW3461-1: Merge Ver 0.4 Integ. onto main branch.
141 *
142 * SW_System_4_Integ_Test/3   6/9/11 2:17p mpovich
143 * SW3461-1: Rebase with main branch.
144 *
145 * 32   6/7/11 6:03p farshidf
146 * SW3128-1: add 3123 support
147 *
148 * 31   6/7/11 3:16p farshidf
149 * SW3128-1: merge to main
150 *
151 * SW_System_4_Integ_Test/2   6/7/11 1:50p farshidf
152 * SW3128-1: sync up with backend
153 *
154 * SW_System_4_Integ_Test/1   6/6/11 1:57p mpovich
155 * SW3461-1: Integ. test all development branches together.
156 *
157 * Ads_Fw_Devel_3/2   5/27/11 3:27p cbrooks
158 * sw3128-1:Added second timer for Mark
159 *
160 * Ads_Fw_Devel_3/1   5/25/11 12:26p cbrooks
161 * sw3128-1:added gain updates
162 *
163 * 30   5/20/11 6:38a mpovich
164 * SW3461-1: rename UFE (BUFE) module to TNR (BTNR).
165 *
166 * TNR_3461_1/1   5/19/11 6:27p mpovich
167 * SW3461-1: Change BUFE module name to BTNR
168 *
169 * 29   5/18/11 3:58p farshidf
170 * SW3128-1: remove the flag fro 3128/3461
171 *
172 * 28   5/18/11 3:23p farshidf
173 * SW3128-1: add 3128 DS fix from Charlie
174 *
175 * 27   5/11/11 5:00p farshidf
176 * SW3128-1: merge main
177 *
178 * ADS_3128_3/4   5/11/11 4:22p cbrooks
179 * sw3128-1:merging 330 changes
180 *
181 * ADS_3128_3/3   5/10/11 11:00a cbrooks
182 * sw3128-1:Changed status
183 *
184 * ADS_3128_3/2   5/5/11 8:14p cbrooks
185 * sw3128-1:Cleanup Code
186 *
187 * ADS_3128_3/1   5/1/11 3:30p cbrooks
188 * sw3128-1:Cleaned up Channel Scan Code
189 *
190 * 25   4/26/11 5:51p farshidf
191 * SW3128-1: compile fix
192 *
193 * 24   4/25/11 10:23a farshidf
194 * SW3461-1: sync up with 35330
195 *
196 * 23   4/21/11 6:00p farshidf
197 * SW3461-1: make the files host compatible
198 *
199 * 22   4/19/11 11:59a farshidf
200 * SW3128-1: make host compatible
201 *
202 * 20   3/18/11 4:30p farshidf
203 * SW3461-1: merge  main
204 *
205 * ADS_3128_1/3   3/17/11 12:29p cbrooks
206 * sw3128-1:Added BERT resync warning
207 *
208 * ADS_3128_1/2   3/16/11 5:21p cbrooks
209 * sw3128-1:new bert
210 *
211 * ADS_3128_1/1   3/16/11 2:34p cbrooks
212 * sw3128-1:BERT CODE
213 *
214 * 19   3/3/11 10:58a farshidf
215 * SW3128-1: clean up
216 *
217 * 18   1/28/11 3:54p farshidf
218 * SW3128-1: update
219 *
220 * 17   1/28/11 3:47p farshidf
221 * SW3128-1: adapt the files to 3461
222 *
223 * 16   1/26/11 4:12p farshidf
224 * SW3128-1: clean up
225 *
226 * 15   1/26/11 3:27p cbrooks
227 * sw3128-1:Cleanup Code
228 *
229 * 14   1/25/11 9:29p cbrooks
230 * sw3128-1: Cleanup Code
231 *
232 * 13   1/21/11 5:19p farshidf
233 * SW3128-1: update the names
234 *
235 * 12   12/22/10 2:21p farshidf
236 * SW3128-1: update
237 *
238 * 11   12/18/10 10:40a farshidf
239 * SW3128-1: update
240 *
241 * 10   12/17/10 5:06p farshidf
242 * SW3128-1: clean up
243 *
244 *
245 ***************************************************************************/
246#include "bstd.h"
247#include "bmth.h"
248#include "bkni.h"
249#ifndef LEAP_BASED_CODE
250#include "bads.h"
251#include "bads_priv.h"
252#include "bads_global_clk.h"
253#include "bads_mth.h"
254#endif
255#include "btmr.h"
256#include "bads_api.h"
257#include "bads_acquire.h"
258#include "bads_utils.h"
259#include "bads_priv.h"
260#include "bads_def.h"
261#if (BCHP_FAMILY==3128)
262#include "bwfe_global_clk.h"
263#endif
264#if (BCHP_FAMILY==3461)
265#include "btnr_global_clk.h"
266#endif
267/*registers needed for the functions in this file*/
268#include "bchp_ds.h"
269
270#ifndef LEAP_BASED_CODE
271BDBG_MODULE(bads_status);
272#endif
273/************************************************************************************************
274 * BADS_P_ChnStatusReset()       This routine resets the status parameters
275 ************************************************************************************************/
276BERR_Code BADS_P_ChnStatusReset(BADS_3x7x_ChannelHandle hChn)
277{
278        BERR_Code retCode;
279
280        BADS_3x7x_ChannelHandle h;
281        h = hChn;
282
283        /*Reset Status1 structure*/     
284        /*hChn->pChnLockStatus->QLK;            DO NOT RESET THIS VALUE*/
285        /*hChn->pChnLockStatus->FLK;            DO NOT RESET THIS VALUE*/
286        hChn->pChnLockStatus->SNR = 0;
287        hChn->pChnLockStatus->SNRAVG = 0;
288        hChn->pChnLockStatus->ReAck_Count = 0;
289        hChn->pChnLockStatus->ReSync_Count = 0;
290        /*hChn->pChnLockStatus->ReAcquire_Count = 0;            DO NOT RESET THIS VALUE*/
291
292        /*Reset Status2 structure*/
293        h->pChnStatus->Auto = BADS_3x7x_ChnStatus_eDisable;     
294        h->pChnStatus->FLK = BADS_3x7x_ChnStatus_eUnlock; 
295        h->pChnStatus->QLK = BADS_3x7x_ChnStatus_eUnlock; 
296        h->pChnStatus->AcqType = BADS_3x7x_ChnStatus_AcqType_eFastAcquire; 
297        h->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eNoPower;
298        h->pChnStatus->AI = BADS_3x7x_ChnStatus_eDisable;
299        h->pChnStatus->AB = BADS_3x7x_ChnStatus_Annex_eAnnexA;
300        h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam16;
301        h->pChnStatus->B64 = BADS_3x7x_ChnStatus_eDisable;
302        h->pChnStatus->B256 = BADS_3x7x_ChnStatus_eDisable;
303        h->pChnStatus->B1024 = BADS_3x7x_ChnStatus_eDisable;
304        h->pChnStatus->A16 = BADS_3x7x_ChnStatus_eDisable;
305        h->pChnStatus->A32 = BADS_3x7x_ChnStatus_eDisable;
306        h->pChnStatus->A64 = BADS_3x7x_ChnStatus_eDisable;
307        h->pChnStatus->A128 = BADS_3x7x_ChnStatus_eDisable;
308        h->pChnStatus->A256 = BADS_3x7x_ChnStatus_eDisable;
309        h->pChnStatus->A512 = BADS_3x7x_ChnStatus_eDisable;
310        h->pChnStatus->A1024 = BADS_3x7x_ChnStatus_eDisable;
311        h->pChnStatus->SI = BADS_3x7x_ChnStatus_eDisable; 
312        h->pChnStatus->Interleaver = 0;
313        h->pChnStatus->ReAck_Count = 0;
314        h->pChnStatus->ReSync_Count = 0;
315        h->pChnStatus->AcquisitionTime1 = 0;
316        h->pChnStatus->AcquisitionTime2 = 0;
317        h->pChnStatus->SNR_db = 0;
318        h->pChnStatus->SNRAVG_db = 0;
319        h->pChnStatus->EstChannelPower_dbm = 0;                                 
320        h->pChnStatus->FrontEndGain_db = 0;
321        h->pChnStatus->AGCB_Gain_db = 0;
322        h->pChnStatus->EQ_Gain_db = 0;
323        h->pChnStatus->Carrier_Scan = 0;
324        h->pChnStatus->Carrier_Error = 0;
325        h->pChnStatus->Symbol_Error = 0;
326        h->pChnStatus->Phase_Error = 0;
327        h->pChnStatus->FEC_Corr_RS_Bits = 0;
328        h->pChnStatus->FEC_Corr_RS_Blocks = 0;
329        h->pChnStatus->FEC_UCorr_RS_Blocks = 0;
330        h->pChnStatus->FEC_Clean_RS_Blocks = 0;
331        h->pChnStatus->PRE_FEC_BERT = 0;
332        h->pChnStatus->BERT = 0;
333        h->pChnStatus->RF_Frequency = 0;
334        h->pChnStatus->RF_Offset = 0;
335        h->pChnStatus->Upper_Symbol_Scan = 0;
336        h->pChnStatus->Lower_Symbol_Scan = 0;
337        h->pChnStatus->Symbol_Rate = 0;
338
339       
340        /*Reset/Resync BER registers in chip*/
341        BREG_Write32(hChn->hRegister, BCHP_DS_BER, 0x00000402);
342        BREG_Write32(hChn->hRegister, BCHP_DS_BER, 0x0000004A);
343        BREG_Write32(hChn->hRegister, BCHP_DS_BER, 0x0000000A);
344        BREG_Write32(hChn->hRegister, BCHP_DS_BER, 0x0000020A);
345        BREG_Write32(hChn->hRegister, BCHP_DS_BERI, 0);
346
347        BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER_CTL, 0x00000402);
348        BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER_CTL, 0x0000004A);
349        BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER_CTL, 0x0000000A);
350        BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER_CTL, 0x0000020A);
351        BREG_Write32(hChn->hRegister, BCHP_DS_OI_BER, 0);
352
353        /*Reset Error Counters in chip ONLY for the second set, the first set is reset by the BADS_75xx_P_Get_LockStatus_ADS_Core0()*/
354        BREG_Write32(hChn->hRegister, BCHP_DS_TPFEC, 0x00001F00);
355
356        /*ADS Status Reset Complete*/
357        retCode = BERR_SUCCESS;
358        return retCode;
359}
360
361/************************************************************************************************
362 * BADS_P_Get_ChnStatus()        This routine gets the status parameters
363 ************************************************************************************************/
364BERR_Code BADS_P_ChnStatus(BADS_3x7x_ChannelHandle hChn)
365{
366        BERR_Code retCode;
367        BADS_3x7x_ChannelHandle h;
368        /*Local Variables*/
369        uint32_t ReadReg;
370        int32_t  ReadRegI;
371               
372        /********************************/
373       
374                BADS_P_AdsCallbackData_t CallbackFrontend;
375
376        /********************************/
377
378        h  = hChn;
379       
380
381        /*All of the status 2 is calculated here*/
382        /*Status 1 is calculated in BADS_P_Acquire and BADS_P_Get_LockStatus*/
383        /*values in status2 that are duplicate in status1 are read from status1*/
384        /*any status that can be calculated by reading back from the core is done that way*/
385
386        /*Get the following from AcqParam->BADS_Acquire_Params structure*/
387        h->pChnStatus->Auto = (hChn->pChnAcqParam->BADS_Acquire_Params.Auto == BADS_Acquire_Params_eEnable) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
388
389        /*Get FLK and QLK from Status->BADS_3x7x_ChnLockStatus structure*/
390        h->pChnStatus->FLK = hChn->pChnLockStatus->FLK; 
391        h->pChnStatus->QLK = hChn->pChnLockStatus->QLK; 
392
393        /*Get ReSync_Count and ReAck_Count from Status->BADS_3x7x_ChnLockStatus structure*/
394        /*Changed for Marc*/
395        /*h->pChnStatus->ReSync_Count = hChn->pChnLockStatus->ReSync_Count;*/
396        h->pChnStatus->ReAck_Count  = hChn->pChnLockStatus->ReAck_Count;
397  h->pChnStatus->ReSync_Count = hChn->pChnLockStatus->ReAcquire_Count;
398
399
400        /*Get AcquisitionTime1 and AcquisitionTime2 hChn->pChnAcqParam->BADS_Local_Params structure*/
401        h->pChnStatus->AcquisitionTime1 = hChn->pChnAcqParam->BADS_Local_Params.ElapsedTime;
402        h->pChnStatus->AcquisitionTime2 = hChn->pChnAcqParam->BADS_Local_Params.TotalTime;
403
404        /*Get the AcqType from the hChn->pChnAcqParam->BADS_Local_Params.AcqType*/
405        switch (hChn->pChnAcqParam->BADS_Local_Params.AcqType)
406        {                                                                             
407                case BADS_Local_Params_AcqType_eFastAcquire:     h->pChnStatus->AcqType = BADS_3x7x_ChnStatus_AcqType_eFastAcquire;     break;
408                case BADS_Local_Params_AcqType_eSlowAcquire:     h->pChnStatus->AcqType = BADS_3x7x_ChnStatus_AcqType_eSlowAcquire;     break;
409                case BADS_Local_Params_AcqType_eScan:            h->pChnStatus->AcqType = BADS_3x7x_ChnStatus_AcqType_eScan;            break;
410                case BADS_Local_Params_AcqType_eSlowAcquireScan: h->pChnStatus->AcqType = BADS_3x7x_ChnStatus_AcqType_eSlowAcquireScan; break;
411                default : BDBG_ERR(("ERROR!!! UNSUPPORTED OR UNDEFINED AcqType")); break;
412        }
413
414        /*Get the AcqStatus from the hChn->pChnAcqParam->BADS_Local_Params.AcqStatus*/
415        switch (hChn->pChnAcqParam->BADS_Local_Params.AcqStatus)
416        {                                                                             
417                case BADS_Local_Params_AcqStatus_eNoPower:    hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eNoPower;    break;
418                case BADS_Local_Params_AcqStatus_eNoTiming:   hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eNoTiming;   break;
419                case BADS_Local_Params_AcqStatus_eNoCarrier:  hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eNoCarrier;  break;
420                case BADS_Local_Params_AcqStatus_eNoFECLock:  hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eNoFECLock;  break;
421                case BADS_Local_Params_AcqStatus_eLockedFast: hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eLockedFast; break;
422                case BADS_Local_Params_AcqStatus_eLockedSlow: hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eLockedSlow; break;
423                case BADS_Local_Params_AcqStatus_eEarlyExit:  hChn->pChnStatus->AcqStatus = BADS_3x7x_ChnStatus_AcqStatus_eEarlyExit;  break;
424                default : BDBG_ERR(("ERROR!!! UNSUPPORTED OR UNDEFINED AcqStatus")); break;
425        }
426
427
428        /*Get the Spectrum State from the hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum*/
429        switch (hChn->pChnAcqParam->BADS_Local_Params.FECSpectrum)
430        {                                                                             
431                case BADS_Local_Params_FECSpectrum_eNotInverted:           h->pChnStatus->SI = BADS_3x7x_ChnStatus_eDisable; break;
432                case BADS_Local_Params_FECSpectrum_eInverted:              h->pChnStatus->SI = BADS_3x7x_ChnStatus_eDisable; break;
433                case BADS_Local_Params_FECSpectrum_eNotInvertedAutoInvert: h->pChnStatus->SI = BADS_3x7x_ChnStatus_eEnable;  break;
434                case BADS_Local_Params_FECSpectrum_eInvertedAutoInvert:    h->pChnStatus->SI = BADS_3x7x_ChnStatus_eEnable;  break;
435                default : BDBG_ERR(("ERROR!!! UNSUPPORTED OR UNDEFINED FECSpectrum")); break;
436        }       
437
438        /*Get the Spectrum State from the hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum*/
439        h->pChnStatus->AI = (hChn->pChnAcqParam->BADS_Local_Params.Flip_Spectrum ==     true) ? BADS_3x7x_ChnScanStatus_Spectrum_eFlipped : BADS_3x7x_ChnScanStatus_Spectrum_eNormal;
440
441        /* This is how the receiver is set*/
442        /*Get the FEC type, Interleaver Dept, Spectral Inversion State*/
443        ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_FECU);
444        if ((ReadReg & 0x00A00000) == 0x00000000)
445        {
446                h->pChnStatus->AB = BADS_3x7x_ChnStatus_Annex_eAnnexA;
447                h->pChnStatus->Interleaver = 0;
448        }
449        else if ((ReadReg & 0x00800000) == 0x00800000) 
450        {
451                h->pChnStatus->AB = BADS_3x7x_ChnStatus_Annex_eAnnexB;  /*Annex B Mode*/
452                h->pChnStatus->Interleaver = BREG_ReadField(hChn->hRegister, DS_FEC, IDS);
453        }
454        else
455        {
456                BDBG_WRN(("ERROR!!! UNSUPPORTED OR UNDEFINED FEC_MODE"));
457        }
458       
459        /*Get the QAM Mode from the bits/symbol from the FEC*/
460        ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_FECL);
461        ReadReg = (ReadReg & 0x000000F0)>>4;
462        switch (ReadReg)
463        {
464                case 3: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam16; break;                     /*16 QAM Mode*/
465                case 4: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam32; break;                     /*32 QAM Mode*/
466                case 5: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam64; break;                     /*64 QAM Mode*/
467                case 6: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam128; break;            /*128 QAM Mode*/
468                case 7: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam256; break;            /*256 QAM Mode*/
469                case 8: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam512; break;            /*512 QAM Mode*/
470                case 9: h->pChnStatus->BPS = BADS_3x7x_ChnStatus_BPS_eQam1024; break;           /*1024 QAM Mode*/
471                default: BDBG_MSG(("WARNING!!! UNSUPPORTED OR UNDEFINED QAM_MODE")); break;
472        }
473
474        /*Get the following from AcqParam->BADS_Local_Params structure*/
475        h->pChnStatus->B64   = (hChn->pChnAcqParam->BADS_Local_Params.Q64B   == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
476        h->pChnStatus->B256  = (hChn->pChnAcqParam->BADS_Local_Params.Q256B  == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
477        h->pChnStatus->B1024 = (hChn->pChnAcqParam->BADS_Local_Params.Q1024B == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
478        h->pChnStatus->A16   = (hChn->pChnAcqParam->BADS_Local_Params.Q16A   == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
479        h->pChnStatus->A32   = (hChn->pChnAcqParam->BADS_Local_Params.Q32A   == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
480        h->pChnStatus->A64   = (hChn->pChnAcqParam->BADS_Local_Params.Q64A   == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
481        h->pChnStatus->A128  = (hChn->pChnAcqParam->BADS_Local_Params.Q128A  == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
482        h->pChnStatus->A256  = (hChn->pChnAcqParam->BADS_Local_Params.Q256A  == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
483        h->pChnStatus->A512  = (hChn->pChnAcqParam->BADS_Local_Params.Q512A  == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
484        h->pChnStatus->A1024 = (hChn->pChnAcqParam->BADS_Local_Params.Q1024A == true) ? BADS_3x7x_ChnStatus_eEnable : BADS_3x7x_ChnStatus_eDisable;
485
486        h->pChnStatus->Upper_Symbol_Scan = hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search;
487        h->pChnStatus->Lower_Symbol_Scan = hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search;
488
489       
490        /*Get SNR and SNRAVG from Status->BADS_3x7x_Status1 structure*/
491        h->pChnStatus->SNR_db = hChn->pChnLockStatus->SNR;
492        h->pChnStatus->SNRAVG_db = hChn->pChnLockStatus->SNRAVG;
493       
494       
495
496        /*Get the Carrier_Scan from hChn->pChnAcqParam->BADS_Local_Params and divide by 256*/
497        h->pChnStatus->Carrier_Scan = hChn->pChnAcqParam->BADS_Local_Params.Carrier_Search/256;
498
499        /*******************************************/
500        /*Determine the VID_Sample and Symbol Rates*/
501        /*******************************************/
502
503        /*Get the Symbol Rate*/
504        h->pChnStatus->Symbol_Rate = BADS_P_Get_TL_Frequency(hChn);
505
506        /***************************************/
507        /*Determine The Carrier Frequency Error*/
508        /***************************************/
509        h->pChnStatus->Carrier_Error = -(BADS_P_Get_CFL_Frequency(hChn) + BADS_P_Get_CFL_Error(hChn) + hChn->pChnAcqParam->BADS_Local_Params.IfFrequency);
510
511        /***************************************/
512        /*Determine The Timing Frequency Error*/
513        /***************************************/
514        h->pChnStatus->Symbol_Error = BADS_P_Get_VID_Error(hChn);
515
516        /***********************************/
517        /*Determine The Carrier Phase Error*/
518        /***********************************/
519       
520        h->pChnStatus->Phase_Error = -BADS_P_Get_CPL_Error(hChn, h->pChnStatus->Symbol_Rate);
521       
522        /***********************************/
523        /*Read Error Counters***************/
524        /***********************************/
525        h->pChnStatus->FEC_Corr_RS_Bits = BREG_Read32(hChn->hRegister, BCHP_DS_CERC2);
526        h->pChnStatus->FEC_Clean_RS_Blocks = BREG_Read32(hChn->hRegister, BCHP_DS_NBERC2);
527        h->pChnStatus->FEC_UCorr_RS_Blocks = BREG_Read32(hChn->hRegister, BCHP_DS_UERC2);
528        h->pChnStatus->FEC_Corr_RS_Blocks = BREG_Read32(hChn->hRegister, BCHP_DS_CBERC2);
529
530        /***********************************/
531        /*Read BERT Counters***************/
532        /***********************************/
533        h->pChnStatus->PRE_FEC_BERT = BREG_Read32(hChn->hRegister, BCHP_DS_BERI);
534  h->pChnStatus->BERT = BREG_Read32(hChn->hRegister, BCHP_DS_OI_BER);
535
536
537        /*Get the Upper_Symbol_Scan and Lower_Symbol_Scan from hChn->pChnAcqParam->BADS_Local_Params*/
538        h->pChnStatus->Upper_Symbol_Scan = hChn->pChnAcqParam->BADS_Local_Params.Upper_Baud_Search;
539        h->pChnStatus->Lower_Symbol_Scan = hChn->pChnAcqParam->BADS_Local_Params.Lower_Baud_Search;
540
541        /*Get front end status*/
542        if (hChn->pChnAcqParam->BADS_Internal_Params.BBS_Unused_Flag6 == BADS_Internal_Params_eEnable)
543        {
544                CallbackFrontend.hTunerChn = (hChn->pCallbackParam[BADS_Callback_eTuner]);
545                CallbackFrontend.Mode = BADS_CallbackMode_eRequestMode;
546                (hChn->pCallback[BADS_Callback_eTuner])(&CallbackFrontend);     
547                               
548                h->pChnStatus->RF_Frequency = CallbackFrontend.RF_Freq;
549                h->pChnStatus->RF_Offset = CallbackFrontend.Freq_Offset;
550                               
551                /*check for unknown power levels sent from front end, -32768*/
552                if ((CallbackFrontend.PreADC_Gain_x256db == -32768) || (CallbackFrontend.PostADC_Gain_x256db == -32768))   
553                {
554                        h->pChnStatus->FrontEndGain_db = -32768;
555                }
556                else
557                {
558                        h->pChnStatus->FrontEndGain_db = (int32_t)(CallbackFrontend.PreADC_Gain_x256db + CallbackFrontend.PostADC_Gain_x256db);
559                } 
560        }
561        else
562        {
563                h->pChnStatus->RF_Frequency = 0;
564                h->pChnStatus->RF_Offset = 0;
565                h->pChnStatus->EstChannelPower_dbm = -32768;
566                h->pChnStatus->FrontEndGain_db = -32768;
567        }
568
569        /*AGCB Gain and Level Calculation*/
570        /*AGCBVAL is 32-bit 7.25 unsigned number*/
571        /*Reset value is 0x04000000 which is a gain of 2*/
572        /*  db = 20*log10(AGCBVAL/2^25)*/
573        /*  256*db = 5120*log10(AGCBVAL/2^16)-5120*log10(2^9)*/ 
574        ReadReg = BREG_ReadField(hChn->hRegister, DS_AGCBI, AGCBVAL);
575        ReadReg = 2*BMTH_2560log10(ReadReg/POWER2_16) - LOG10_POWER2_9_X5120;
576        h->pChnStatus->AGCB_Gain_db = (int32_t)ReadReg;  /*BBS will divide by 256 to get dB*/
577
578        /*Get Hum AGC Gain and EQ Gain*/
579        /*DS_EQ_AGCPA is a 26 bit signed number*/
580        /*DS_EQ_AGCPA.AGCOFFSET is a 8 bit unsigned number*/
581        /*Hum_Agc_Gain db = 20*log10(2*(AGCOFFSET*2^18+AGCPA)/2^25)*/
582  /*Hum_Agc_Gain 256*db = 5120*log10(2*(AGCOFFSET*2^18+AGCPA)/2^25)*/
583        /*Hum_Agc_Gain 256*db = 2*BMTH_2560log10(2*(AGCOFFSET*2^18+AGCPA)) - LOG10_POWER2_25_X5120*/
584        ReadRegI = 0;
585        ReadReg = BREG_ReadField(hChn->hRegister, DS_EQ_CTL, HUM_EN);
586        if (ReadReg == 1)
587        {
588                ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_EQ_AGCPA);
589                if ((ReadReg & 0x02000000) == 0) /*check sign*/
590                {
591                        ReadRegI = (int32_t)ReadReg;
592                }
593                else
594                {
595                        ReadRegI = (int32_t)(ReadReg | 0xFC000000); /*sign extend*/
596                }
597
598                ReadReg = BREG_ReadField(hChn->hRegister, DS_EQ_AGC, AGCOFFSET);
599                ReadRegI = ReadRegI + (int32_t)(ReadReg<<18);
600                ReadRegI = 2*ReadRegI;
601
602                /*saturate from 0 to 2^25-1*/
603                ReadRegI = (ReadRegI < 0) ? 0 : ((ReadRegI > POWER2_25_M1) ? POWER2_25_M1 : ReadRegI); 
604
605                ReadReg = (uint32_t)ReadRegI;
606                ReadReg = 2*BMTH_2560log10(ReadReg) - LOG10_POWER2_25_X5120;
607                ReadRegI = (int32_t)ReadReg;
608        }
609
610        /*EQ Gain is taken by looking at the main tap real value, the imaginary tap is always frozen at 0*/
611        /*Reset value of main Tap I is 0x2000 which is a gain of 2*/
612        /*  db = 20*log10(MAIN/2^12)*/
613        /*  256*db = 5120*log10(MAIN)-5120*log10(2^12)*/ 
614        ReadReg = BREG_ReadField(hChn->hRegister, DS_EQ_FFE, MAIN);
615        ReadReg = BREG_Read32(hChn->hRegister, BCHP_DS_EQ_FFEU0+(ReadReg*8));
616        ReadReg = (ReadReg & 0xffff0000)/POWER2_16;
617        h->pChnStatus->EQ_Main_Tap = ((ReadReg & 0x00008000) == 0) ? (int32_t)ReadReg : (int32_t)(ReadReg | 0xFFFF0000);
618        ReadReg = 2*BMTH_2560log10(ReadReg) - LOG10_POWER2_12_X5120;   
619        h->pChnStatus->EQ_Gain_db = ReadRegI + (int32_t)ReadReg;  /*BBS will divide by 256 to get dB*/
620
621        /*check for unknown power level sent from front end, -32768*/
622        if (CallbackFrontend.External_Gain_x256db == -32768)
623        {
624                h->pChnStatus->EstChannelPower_dbm = -32768;
625        }
626        else
627        {
628                h->pChnStatus->EstChannelPower_dbm = GAIN_OFFSET - h->pChnStatus->EQ_Gain_db - h->pChnStatus->FrontEndGain_db - h->pChnStatus->AGCB_Gain_db - (int32_t)CallbackFrontend.External_Gain_x256db;
629        }
630
631        /*ADS Status Complete*/
632        retCode = BERR_SUCCESS;
633        return retCode;
634}
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