| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2003-2011, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: bdma_queue.h $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/4 $ |
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| 12 | * $brcm_Date: 3/21/11 6:39p $ |
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| 13 | * |
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| 14 | * Module Description: |
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| 15 | * |
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| 16 | * |
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| 17 | * Revision History: |
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| 18 | * $brcm_Log: /magnum/portinginterface/dma/7400/bdma_queue.h $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/4 3/21/11 6:39p vanessah |
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| 21 | * SW7420-1431: support oflarge DMA descriptor list subset |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/3 8/17/10 12:18p vanessah |
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| 24 | * SW7335-791: After customer verification, merged into main |
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| 25 | * |
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| 26 | * Hydra_Software_Devel/SW7335-791/1 8/4/10 10:20p vanessah |
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| 27 | * SW7335-791: DMA engine hangs when continuous descriptors using |
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| 28 | * different scram modes |
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| 29 | * |
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| 30 | * Hydra_Software_Devel/2 7/11/08 3:47p syang |
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| 31 | * PR 43729: rm code for old crypto hw arch |
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| 32 | * |
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| 33 | * Hydra_Software_Devel/20 5/28/08 12:34p syang |
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| 34 | * PR 34606: clean LAST bit during dyn link even if AUTO_PEND supported; |
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| 35 | * clean up |
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| 36 | * |
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| 37 | * Hydra_Software_Devel/19 5/19/08 1:58p syang |
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| 38 | * PR 34606: clean up |
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| 39 | * |
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| 40 | * Hydra_Software_Devel/18 5/19/08 11:48a syang |
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| 41 | * PR 34606: add validation for HW reg reading |
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| 42 | * |
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| 43 | * Hydra_Software_Devel/17 1/10/08 11:10a syang |
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| 44 | * PR 31923: fix release build error |
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| 45 | * |
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| 46 | * Hydra_Software_Devel/16 12/12/07 3:40p syang |
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| 47 | * PR 31923: added auto-append support to PI |
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| 48 | * |
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| 49 | * Hydra_Software_Devel/15 12/7/07 6:38p syang |
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| 50 | * PR 34606: move SetCrypto to Tran level from Engine level for better |
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| 51 | * sharing by threads of the same progress |
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| 52 | * |
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| 53 | * Hydra_Software_Devel/14 12/7/07 4:09p syang |
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| 54 | * PR 34606: rewrite more than half of code to support hw sharing for |
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| 55 | * kernel and user-mode sides |
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| 56 | * |
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| 57 | * Hydra_Software_Devel/13 10/15/07 3:39p syang |
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| 58 | * PR 35947: add "_isr" to call back func name |
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| 59 | * |
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| 60 | * Hydra_Software_Devel/12 3/16/07 12:51p syang |
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| 61 | * PR 28173: add dynamic link support (not turn on yet) |
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| 62 | * |
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| 63 | * Hydra_Software_Devel/10 10/3/06 4:02p syang |
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| 64 | * PR 24634: replace critical section with private mutex for |
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| 65 | * mem/pci_dma_handle create/destroy. |
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| 66 | * |
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| 67 | * Hydra_Software_Devel/9 2/4/04 6:37p syang |
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| 68 | * PR 9608: change to not destroy dma desc buf for debug info |
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| 69 | * |
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| 70 | * Hydra_Software_Devel/8 2/4/04 3:02p syang |
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| 71 | * PR 9608: 1). added init for hMemDma / hPciDma of Channel, hDma of |
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| 72 | * MemDma / PciDma and hChannel of Queue; 2). split CallBackFunc type def |
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| 73 | * to mem and pci versions; 3). fixed typo in TranHandle def; 4).leave |
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| 74 | * critical section before calling BINT func; 5). fixed a bug with |
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| 75 | * nextDesc in Desc info setting; 6). use wake to start dma as in sleep |
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| 76 | * mode; 7). corrected typo in the asserts of Queue_CreateTran. |
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| 77 | * |
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| 78 | * Hydra_Software_Devel/7 11/19/03 6:53p syang |
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| 79 | * seperate Tran get_context from generic |
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| 80 | * |
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| 81 | * Hydra_Software_Devel/6 10/23/03 6:18p syang |
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| 82 | * to make linux comipler silent |
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| 83 | * |
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| 84 | * Hydra_Software_Devel/5 10/23/03 11:07a syang |
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| 85 | * first time checking after resolving comipling errors |
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| 86 | * |
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| 87 | * Hydra_Software_Devel/4 10/17/03 5:37p syang |
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| 88 | * update to use TranHandle (rather than TranId). |
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| 89 | * |
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| 90 | * Hydra_Software_Devel/3 10/10/03 3:59p syang |
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| 91 | * added more detail to queue module overview, and added ProcCancelCall |
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| 92 | * |
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| 93 | * Hydra_Software_Devel/2 9/30/03 2:43p syang |
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| 94 | * added assert, changed to use queue handle, added |
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| 95 | * BDMA_P_Queue_ProcStartCall |
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| 96 | * |
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| 97 | * Hydra_Software_Devel/1 9/25/03 6:32p syang |
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| 98 | * init version, from scratch |
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| 99 | * |
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| 100 | ***************************************************************************/ |
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| 101 | |
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| 102 | #ifndef BDMA_QUEUE_H__ |
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| 103 | #define BDMA_QUEUE_H__ |
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| 104 | |
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| 105 | #include "bdma_priv.h" /* for enum def and utility MACRO only */ |
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| 106 | |
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| 107 | #ifdef __cplusplus |
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| 108 | extern "C" { |
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| 109 | #endif |
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| 110 | |
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| 111 | /*************************************************************************** |
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| 112 | * {private} |
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| 113 | * |
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| 114 | * queue (private) module overview: |
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| 115 | * |
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| 116 | * This file implements the queue sub-module. It is used by both memory dma, |
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| 117 | * pci dma, and io dma sub-module. Queue sub-module is not a sub-module in |
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| 118 | * the sense of Magnum architecture. It is only a module in the sense of |
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| 119 | * generic programming. |
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| 120 | * |
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| 121 | * It is intended to be used privately, to run fast, and therefore it does |
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| 122 | * not perform parameter validation |
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| 123 | * |
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| 124 | * Refer to BDMA_P_Queue_Create, the queue manages a queue-entry array and |
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| 125 | * a decriptor array. Each queue-entry points to the descriptor of the same |
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| 126 | * index. The descriptor buffer is allocated from BMEM and is contiguous. |
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| 127 | * |
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| 128 | * When a new transfer is required, BDMA_P_Queue_CreateTran is called |
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| 129 | * to allocate the next un-used contiguous chunck of queue-entries / |
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| 130 | * descriptors and initialize the first entry of the chunck, that stores |
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| 131 | * the state (such as Tran status, NumBlocks of the transfer). The queue is |
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| 132 | * used in a round-robin and wrap-around manner. |
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| 133 | * |
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| 134 | * BDMA_P_Queue_StartTran is called when "start" or "start and call back" is |
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| 135 | * called by high level software. It decides whether the user ordered Tran |
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| 136 | * should be sent to HW at the moment, put as queued, or return error of |
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| 137 | * "engine busy". |
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| 138 | * |
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| 139 | * BDMA_P_Queue_DestroyTran is called when "destroy" is called by high level |
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| 140 | * software. It free the Tran's entries for future Tran creating request. |
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| 141 | * |
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| 142 | * BDMA_P_Queue_ProcEngineIdle is called to process the engine idle info. |
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| 143 | * It is ideally for DMA engine/channel's "done" interrupt handler. |
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| 144 | * It ensures HW just finished a transfer and decides which one is just |
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| 145 | * finished. It also schedules a new (async) transfer to be sent to HW if |
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| 146 | * there exists one. |
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| 147 | * |
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| 148 | * Implementaion notes: |
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| 149 | * 1. A Tran occupies a contiguous chunk of entries. Each entry represents |
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| 150 | * a transfer block. The first entry represent the Tran and stores the Tran's |
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| 151 | * status, number of blocks, user call back func, user call back para, ..., |
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| 152 | * and only fields bBlockInfoSet and pulDesc in the following entries has |
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| 153 | * siginificace (the otherfiels are set fot assersion only). |
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| 154 | * 2. Whether a Tran is active or not, is indicated by whether its status |
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| 155 | * is unknown. The entries of a non-active Tran are free for new Tran |
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| 156 | * creating. |
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| 157 | * 3. The queue module mantains two index: ulIndx_LastEntryIssued, and |
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| 158 | * ulIndx_LastEntryAssigned. If ulIndx_LastEntryIssued is in InProgress state, |
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| 159 | * the HW is busy, otherwise HW is idle. When a "done" interrupt happens, the |
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| 160 | * module tries to find the next async Tran after (wrap-aroundly) the just |
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| 161 | * finished one, to send to HW. And new Tran creating tries to use the next |
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| 162 | * free contiguoys chunk of entries after ulIndx_LastEntryAssigned (wrap- |
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| 163 | * aroundly also). By this way we try to maintan a fairness to all transfer |
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| 164 | * requests. |
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| 165 | * 4. It is assumed that all Tran causes a interrupt, in order to mantain |
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| 166 | * the channel /queue state. |
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| 167 | * 5. Queue module manages the state of the queue, the user of queue module |
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| 168 | * may only know the struct of BDMA_P_QueueEntry. |
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| 169 | */ |
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| 170 | |
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| 171 | #define BDMA_P_NUM_QUEUE_ENTRIES (2<<8) |
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| 172 | #define BDMA_P_MAX_NUM_BLOCKS (BDMA_P_NUM_QUEUE_ENTRIES >> 1) |
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| 173 | |
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| 174 | #define BDMA_P_QUEUE_GET_CONTEXT(handle, context) \ |
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| 175 | BDMA_P_GENERIC_GET_CONTEXT(handle, context, BDMA_P_QueueContext) |
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| 176 | |
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| 177 | #define BDMA_P_QUEUE_SET_BLACK_MAGIC(handle) \ |
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| 178 | BDMA_P_GENERIC_SET_BLACK_MAGIC(handle, BDMA_P_QueueContext) |
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| 179 | |
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| 180 | #define BDMA_P_QUEUE_DESTROY_CONTEXT(struct_ptr) \ |
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| 181 | BDMA_P_GENERIC_DESTROY_CONTEXT(struct_ptr, BDMA_P_QueueContext) |
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| 182 | |
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| 183 | #if BDBG_DEBUG_BUILD |
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| 184 | #define BDMA_P_QUEUE_DESTROY_ENTRY(entry_head, num_entry) \ |
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| 185 | { \ |
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| 186 | BKNI_Memset((void*)entry_head, 0xA3, num_entry * sizeof(BDMA_P_QueueEntry)); \ |
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| 187 | BKNI_Free((void*)entry_head); \ |
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| 188 | entry_head = NULL; \ |
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| 189 | } |
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| 190 | #else |
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| 191 | #define BDMA_P_QUEUE_DESTROY_ENTRY(entry_head, num_entry) \ |
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| 192 | { \ |
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| 193 | BKNI_Free((void*)entry_head); \ |
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| 194 | } |
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| 195 | #endif |
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| 196 | |
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| 197 | #if BDBG_DEBUG_BUILD |
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| 198 | #define BDMA_P_QUEUE_DESTROY_DESC(h_mem, desc_ptr, size) \ |
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| 199 | { \ |
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| 200 | BKNI_Memset((void*)desc_ptr, 0xA3, size); \ |
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| 201 | BMEM_Free(h_mem, desc_ptr); \ |
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| 202 | } |
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| 203 | #else |
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| 204 | #define BDMA_P_QUEUE_DESTROY_DESC(h_mem, desc_ptr, size) \ |
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| 205 | { \ |
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| 206 | BMEM_Free(h_mem, desc_ptr); \ |
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| 207 | } |
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| 208 | #endif |
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| 209 | |
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| 210 | #define BDMA_P_TRAN_GET_CONTEXT(handle, context) \ |
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| 211 | { \ |
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| 212 | if(!(handle) || \ |
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| 213 | (((BDMA_P_QueueEntry*)(handle))->ulBlackMagic != \ |
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| 214 | (sizeof(BDMA_P_QueueEntry) | 0xbac98700))) \ |
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| 215 | { \ |
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| 216 | BDBG_ERR(("NULL context handle\n")); \ |
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| 217 | (context) = NULL; \ |
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| 218 | } \ |
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| 219 | else \ |
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| 220 | { \ |
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| 221 | (context) = (BDMA_P_QueueEntry *)(handle); \ |
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| 222 | } \ |
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| 223 | } |
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| 224 | |
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| 225 | #define BDMA_P_TRAN_SET_BLACK_MAGIC(handle) \ |
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| 226 | { \ |
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| 227 | ((BDMA_P_QueueEntry*)(handle))->ulBlackMagic = sizeof(BDMA_P_QueueEntry) | 0xbac98700; \ |
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| 228 | } |
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| 229 | |
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| 230 | /*************************************************************************** |
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| 231 | * {private} |
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| 232 | * Dma queue handle |
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| 233 | */ |
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| 234 | typedef struct BDMA_P_QueueContext *BDMA_P_QueueHandle; |
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| 235 | |
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| 236 | /*************************************************************************** |
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| 237 | * {private} |
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| 238 | * dma queue entry info |
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| 239 | * Each queue entry corresponds to a dma descriptor, and therefore a tran |
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| 240 | * block. A transfer's state is stored in the queue entry of its first block |
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| 241 | */ |
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| 242 | typedef struct BDMA_P_QueueEntry BDMA_P_Tran; |
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| 243 | typedef void (* BDMA_P_CallbackFunc)( \ |
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| 244 | void * pUserCallBackParam,\ |
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| 245 | BDMA_P_Tran * hTran, \ |
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| 246 | BDMA_TranStatus eStatus ); |
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| 247 | |
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| 248 | typedef struct BDMA_P_QueueEntry |
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| 249 | { |
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| 250 | uint32_t ulBlackMagic; /* Black magic for handle validation */ |
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| 251 | |
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| 252 | /* created from this handle */ |
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| 253 | BDMA_P_QueueHandle hQueue; |
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| 254 | |
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| 255 | /* -------------------------------------------------- |
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| 256 | * |
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| 257 | * context for Tran only |
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| 258 | */ |
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| 259 | struct BDMA_P_QueueEntry *pNextTran; /* for dynamical link to next Tran */ |
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| 260 | |
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| 261 | uint32_t ulNumTranBlocks; /* Max number of blocks in this Tran */ |
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| 262 | uint32_t ulNumActBlocks; /* Number of blocks currently active */ |
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| 263 | BDMA_P_CallbackFunc pCallBackFunc_isr; /* call back function ptr */ |
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| 264 | void * pUserCallBackParam;/* user's info to call back func */ |
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| 265 | BDMA_TranStatus eStatus; /* status of the transfer */ |
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| 266 | |
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| 267 | /* current state of the Tran: applied to future setDmaBlockInfo */ |
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| 268 | BDMA_CryptMode eCryptMode; |
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| 269 | uint32_t ulKeySlot; |
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| 270 | bool bSgEnable; |
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| 271 | |
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| 272 | bool bSgStartStopSet; /* ever set in any block of this Tran */ |
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| 273 | |
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| 274 | bool bCachedDscrp; /* whether use cached addr to write descrp */ |
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| 275 | |
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| 276 | /* -------------------------------------------------- |
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| 277 | * |
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| 278 | * context for each block |
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| 279 | */ |
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| 280 | bool bBlockInfoSet; /* whether this block's info is set */ |
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| 281 | uint32_t ulSgStartStop; |
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| 282 | uint32_t * pulDescAddr; /* descriptor buffer - non-cached addr */ |
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| 283 | uint32_t * pulCachedDescAddr; /* descriptor buffer - cached addr */ |
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| 284 | uint32_t ulDescPhysAddr; /* descriptor buffer - phys addr */ |
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| 285 | |
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| 286 | uint32_t ulFirstBlock; /* offset into contiguous descriptor list */ |
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| 287 | } BDMA_P_QueueEntry; |
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| 288 | |
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| 289 | /*************************************************************************** |
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| 290 | * {private} |
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| 291 | * HW status enum |
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| 292 | */ |
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| 293 | typedef enum |
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| 294 | { |
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| 295 | BDMA_P_HwStatus_eIdle, |
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| 296 | BDMA_P_HwStatus_eBusy, |
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| 297 | BDMA_P_HwStatus_eSleep, |
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| 298 | BDMA_P_HwStatus_eUnknown |
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| 299 | } |
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| 300 | BDMA_P_HwStatus; |
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| 301 | |
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| 302 | /*************************************************************************** |
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| 303 | * {private} |
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| 304 | * Common dma engine settings |
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| 305 | */ |
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| 306 | typedef struct BDMA_P_CmnSettings |
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| 307 | { |
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| 308 | uint32_t ulTotalNumBlocks; |
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| 309 | uint32_t ulMaxNumBlocksPerTran; |
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| 310 | |
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| 311 | /* settings for the case of multiple BDMA instances */ |
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| 312 | BDMA_LockCallbackFunc pTryLock_isr; |
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| 313 | BDMA_LockCallbackFunc pReleaseLock_isr; |
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| 314 | void * pvParm1; |
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| 315 | int iParm2; |
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| 316 | bool bSupportCallBack; |
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| 317 | } |
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| 318 | BDMA_P_CmnSettings; |
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| 319 | |
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| 320 | /*************************************************************************** |
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| 321 | * {private} |
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| 322 | * Call back functions to deal with specific HW engine and descriptor formats |
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| 323 | */ |
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| 324 | typedef void (* BDMA_P_ReadHwRegsFunc) ( \ |
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| 325 | void * pvEngine, \ |
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| 326 | BDMA_P_HwStatus * peHwStatus, \ |
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| 327 | uint32_t * pulCurrDesc, \ |
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| 328 | uint32_t * pulScratchReg ); |
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| 329 | |
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| 330 | typedef void (* BDMA_P_AppendTranDescFunc)( \ |
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| 331 | BDMA_P_QueueEntry * pCurrTran, \ |
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| 332 | BDMA_P_QueueEntry * pNextTran ); |
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| 333 | |
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| 334 | typedef void (* BDMA_P_SendToHwFunc)( \ |
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| 335 | BDMA_P_QueueHandle hQueue, \ |
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| 336 | BDMA_P_HwStatus eHwStatus, \ |
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| 337 | bool bAppendInHw ); |
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| 338 | |
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| 339 | typedef void (* BDMA_P_CheckNextDescFunc)( \ |
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| 340 | BDMA_P_QueueEntry * pCurrTran, \ |
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| 341 | BDMA_P_QueueEntry * pNextTran ); |
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| 342 | |
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| 343 | typedef void (* BDMA_P_SafeToSendHwFunc)( \ |
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| 344 | BDMA_P_QueueHandle hQueue, \ |
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| 345 | BDMA_P_HwStatus* peHwStatus); |
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| 346 | /*************************************************************************** |
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| 347 | * {private} |
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| 348 | * Dma queue Context |
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| 349 | */ |
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| 350 | typedef struct BDMA_P_QueueContext |
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| 351 | { |
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| 352 | uint32_t ulBlackMagic; /* Black magic for handle validation */ |
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| 353 | |
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| 354 | /* created from this dma engine */ |
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| 355 | void * hEngine; |
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| 356 | |
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| 357 | uint32_t ulIndx_LastEntryAssigned; |
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| 358 | |
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| 359 | bool bDmaHwShared; |
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| 360 | bool bHwStarted; |
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| 361 | bool bSgOpenInHw; /* SgOpen: scatter-gather started, not stopped */ |
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| 362 | bool bPreLinkSgOpenInHw; /* in case dyn link fails */ |
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| 363 | bool bSgOpenInQ; |
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| 364 | BDMA_P_QueueEntry * pHeadTranInHw; |
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| 365 | BDMA_P_QueueEntry * pTailTranInHw; |
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| 366 | BDMA_P_QueueEntry * pHeadTranInQ; |
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| 367 | BDMA_P_QueueEntry * pTailTranInQ; |
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| 368 | BDMA_P_QueueEntry * pPreLinkTailTranInHw; /* in case dyn link fails */ |
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| 369 | |
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| 370 | uint32_t ulNumWordsPerDesc; |
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| 371 | BDMA_P_CmnSettings CmnSettings; |
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| 372 | |
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| 373 | uint32_t ulLockMark; |
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| 374 | uint32_t ul1stDescPhysAddr; |
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| 375 | uint32_t ulLastDescPhysAddr; |
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| 376 | BDMA_P_QueueEntry * pHeadEntry; /* pointer to the entry array */ |
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| 377 | |
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| 378 | /* call back funcs from engine to deal with specific HW */ |
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| 379 | BDMA_P_ReadHwRegsFunc pReadHwRegs_isr; |
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| 380 | BDMA_P_AppendTranDescFunc pAppendTranDesc_isr; |
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| 381 | BDMA_P_SendToHwFunc pSendToHw_isr; |
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| 382 | BDMA_P_CheckNextDescFunc pCheckNextDesc_isr; /* for err msg only */ |
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| 383 | BDMA_P_SafeToSendHwFunc pSafeToSendHw_isr; |
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| 384 | |
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| 385 | } BDMA_P_QueueContext; |
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| 386 | |
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| 387 | |
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| 388 | /*************************************************************************** |
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| 389 | * {private} |
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| 390 | * BDMA_P_Queue_Create |
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| 391 | * |
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| 392 | * To be called to create queue for a dma channel. It allocates a queue entry |
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| 393 | * array from system memory, and contiguous descriptor array from BMEM. |
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| 394 | * It then initiate the allocated queue array, including setting each |
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| 395 | * queue-entry to point to the descriptor of the same index. |
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| 396 | * |
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| 397 | * Note: assume parameters are valid |
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| 398 | */ |
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| 399 | BERR_Code BDMA_P_Queue_Create |
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| 400 | ( BDMA_P_QueueHandle * phQueue, |
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| 401 | void * hEngine, |
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| 402 | BMEM_Handle hMemory, |
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| 403 | uint32_t ulNumWordsPerDesc, |
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| 404 | const BDMA_P_CmnSettings *pCmnSettings, |
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| 405 | BDMA_P_ReadHwRegsFunc pReadHwRegs_isr, |
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| 406 | BDMA_P_AppendTranDescFunc pAppendTranDesc_isr, |
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| 407 | BDMA_P_SendToHwFunc pSendToHw_isr, |
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| 408 | BDMA_P_CheckNextDescFunc pCheckNextDesc_isr, |
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| 409 | BDMA_P_SafeToSendHwFunc pSafeToSendHw_isr); |
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| 410 | |
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| 411 | /*************************************************************************** |
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| 412 | * {private} |
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| 413 | * BDMA_P_Queue_Destroy |
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| 414 | * |
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| 415 | * To be called to destroy the queue. |
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| 416 | * |
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| 417 | * Note: assume parameters are valid |
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| 418 | */ |
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| 419 | BERR_Code BDMA_P_Queue_Destroy |
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| 420 | ( BDMA_P_QueueHandle hQueue, |
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| 421 | BMEM_Handle hMemory ); |
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| 422 | |
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| 423 | /*************************************************************************** |
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| 424 | * {private} |
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| 425 | * BDMA_P_Queue_GetEngine_isr |
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| 426 | * |
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| 427 | * To be called to get the dma engine |
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| 428 | * |
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| 429 | * Note: assume parameters are valid |
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| 430 | */ |
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| 431 | void * BDMA_P_Queue_GetEngine_isr |
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| 432 | ( BDMA_P_QueueHandle hQueue ); |
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| 433 | |
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| 434 | /*-------------------------------------------------------------------------- |
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| 435 | * {private} |
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| 436 | * BDMA_P_Queue_CheckHwAndSendNewReq_isr |
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| 437 | * |
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| 438 | * Called to check HW status, process it, and try to send the Trans queued |
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| 439 | * in SW into HW |
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| 440 | */ |
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| 441 | void BDMA_P_Queue_CheckHwAndSendNewReq_isr |
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| 442 | ( BDMA_P_QueueHandle hQueue ); |
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| 443 | |
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| 444 | /*************************************************************************** |
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| 445 | * {private} |
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| 446 | * BDMA_P_Queue_CreateTran |
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| 447 | * |
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| 448 | * To be called when a new transfer is created. It finds a free chunck of |
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| 449 | * contiguous queue entries (that corresponds to a set of contiguous |
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| 450 | * descriptors too) in the dma channel queue, and outputs the first entry |
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| 451 | * of the chunck. |
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| 452 | * |
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| 453 | * Note: assume parameters are valid, |
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| 454 | * ulNumBlocks can not be 0 |
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| 455 | */ |
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| 456 | BERR_Code BDMA_P_Queue_CreateTran_isr |
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| 457 | ( BDMA_P_QueueHandle hQueue, |
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| 458 | uint32_t ulNumBlocks, |
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| 459 | bool bCachedDesc, |
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| 460 | BDMA_P_QueueEntry ** ppNewTran ); |
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| 461 | |
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| 462 | /*************************************************************************** |
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| 463 | * {private} |
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| 464 | * BDMA_P_Queue_StartTran_isr |
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| 465 | * |
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| 466 | * To be called to process the user calling of Start or StartAndCallBack. |
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| 467 | * |
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| 468 | * pCallBackFunc_isr is assumed to indicate whether the Tran is sync or async. |
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| 469 | * |
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| 470 | * Note: assume parameters are valid |
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| 471 | */ |
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| 472 | BERR_Code BDMA_P_Queue_StartTran_isr |
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| 473 | ( BDMA_P_QueueHandle hQueue, |
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| 474 | BDMA_P_QueueEntry * pTran, |
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| 475 | uint32_t ulNumActBlocks, |
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| 476 | bool bSgOpen, |
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| 477 | BDMA_P_CallbackFunc pCallBackFunc_isr, |
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| 478 | void * pUserCallBackParam ); |
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| 479 | |
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| 480 | /*************************************************************************** |
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| 481 | * {private} |
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| 482 | * BDMA_P_Queue_DestroyTran |
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| 483 | * |
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| 484 | * To be called to destroy a Tran. It reset the Tran's entries to make the |
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| 485 | * chunk of blocks as a destroyed Tran |
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| 486 | * |
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| 487 | * Note: assume parameters are valid |
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| 488 | */ |
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| 489 | BERR_Code BDMA_P_Queue_DestroyTran_isr |
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| 490 | ( BDMA_P_QueueHandle hQueue, |
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| 491 | BDMA_P_QueueEntry * pTran ); |
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| 492 | |
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| 493 | /*************************************************************************** |
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| 494 | * {private} |
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| 495 | * BDMA_P_Queue_ResetTran |
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| 496 | * |
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| 497 | * To be called to reset a active Tran into intial eCreated state. Without |
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| 498 | * resetting, the Tran could also be used to SetBlockInfo and Start again, |
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| 499 | * but the module will not be able to check whether each block info is set. |
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| 500 | * |
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| 501 | * Note: assume parameters are valid, |
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| 502 | */ |
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| 503 | BERR_Code BDMA_P_Queue_ResetTran_isr |
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| 504 | ( BDMA_P_QueueHandle hQueue, |
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| 505 | BDMA_P_QueueEntry * pTran ); |
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| 506 | |
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| 507 | #ifdef __cplusplus |
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| 508 | } |
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| 509 | #endif |
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| 510 | |
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| 511 | #endif /* #ifndef BDMA_QUEUE_H__ */ |
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| 512 | |
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| 513 | /* End of File */ |
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