source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/dma/7552/bdma_queue.h

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1/***************************************************************************
2 *     Copyright (c) 2003-2011, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bdma_queue.h $
11 * $brcm_Revision: Hydra_Software_Devel/4 $
12 * $brcm_Date: 3/21/11 6:39p $
13 *
14 * Module Description:
15 *
16 *
17 * Revision History:
18 * $brcm_Log: /magnum/portinginterface/dma/7400/bdma_queue.h $
19 *
20 * Hydra_Software_Devel/4   3/21/11 6:39p vanessah
21 * SW7420-1431: support oflarge DMA descriptor list subset
22 *
23 * Hydra_Software_Devel/3   8/17/10 12:18p vanessah
24 * SW7335-791:  After customer verification, merged into main
25 *
26 * Hydra_Software_Devel/SW7335-791/1   8/4/10 10:20p vanessah
27 * SW7335-791:  DMA engine hangs when continuous descriptors using
28 * different scram modes
29 *
30 * Hydra_Software_Devel/2   7/11/08 3:47p syang
31 * PR 43729:  rm code for old crypto hw arch
32 *
33 * Hydra_Software_Devel/20   5/28/08 12:34p syang
34 * PR 34606: clean LAST bit during dyn link even if AUTO_PEND supported;
35 * clean up
36 *
37 * Hydra_Software_Devel/19   5/19/08 1:58p syang
38 * PR 34606:  clean up
39 *
40 * Hydra_Software_Devel/18   5/19/08 11:48a syang
41 * PR 34606:  add validation for HW reg reading
42 *
43 * Hydra_Software_Devel/17   1/10/08 11:10a syang
44 * PR 31923: fix release build error
45 *
46 * Hydra_Software_Devel/16   12/12/07 3:40p syang
47 * PR 31923: added auto-append support to PI
48 *
49 * Hydra_Software_Devel/15   12/7/07 6:38p syang
50 * PR 34606: move SetCrypto to Tran level from Engine level for better
51 * sharing by threads of the same progress
52 *
53 * Hydra_Software_Devel/14   12/7/07 4:09p syang
54 * PR 34606: rewrite more than half of code to support hw sharing for
55 * kernel and user-mode sides
56 *
57 * Hydra_Software_Devel/13   10/15/07 3:39p syang
58 * PR 35947: add "_isr" to call back func name
59 *
60 * Hydra_Software_Devel/12   3/16/07 12:51p syang
61 * PR 28173: add dynamic link support (not turn on yet)
62 *
63 * Hydra_Software_Devel/10   10/3/06 4:02p syang
64 * PR 24634: replace critical section with private mutex for
65 * mem/pci_dma_handle create/destroy.
66 *
67 * Hydra_Software_Devel/9   2/4/04 6:37p syang
68 * PR 9608: change to not destroy dma desc buf for debug info
69 *
70 * Hydra_Software_Devel/8   2/4/04 3:02p syang
71 * PR 9608: 1). added init for hMemDma / hPciDma of Channel, hDma of
72 * MemDma / PciDma and hChannel of Queue; 2). split CallBackFunc type def
73 * to mem and pci versions; 3). fixed typo in TranHandle def; 4).leave
74 * critical section before calling BINT func; 5). fixed a bug with
75 * nextDesc in Desc info setting; 6). use wake to start dma as in sleep
76 * mode; 7). corrected typo in the asserts of Queue_CreateTran.
77 *
78 * Hydra_Software_Devel/7   11/19/03 6:53p syang
79 * seperate Tran get_context from generic
80 *
81 * Hydra_Software_Devel/6   10/23/03 6:18p syang
82 * to make linux comipler silent
83 *
84 * Hydra_Software_Devel/5   10/23/03 11:07a syang
85 * first time checking after resolving comipling errors
86 *
87 * Hydra_Software_Devel/4   10/17/03 5:37p syang
88 * update to use TranHandle (rather than TranId).
89 *
90 * Hydra_Software_Devel/3   10/10/03 3:59p syang
91 * added more detail to queue module overview, and added ProcCancelCall
92 *
93 * Hydra_Software_Devel/2   9/30/03 2:43p syang
94 * added assert, changed to use queue handle, added
95 * BDMA_P_Queue_ProcStartCall
96 *
97 * Hydra_Software_Devel/1   9/25/03 6:32p syang
98 * init version, from scratch
99 *
100 ***************************************************************************/
101
102#ifndef BDMA_QUEUE_H__
103#define BDMA_QUEUE_H__
104
105#include "bdma_priv.h"        /* for enum def and utility MACRO only */
106
107#ifdef __cplusplus
108extern "C" {
109#endif
110
111/***************************************************************************
112 * {private}
113 *
114 * queue (private) module overview:
115 *
116 * This file implements the queue sub-module. It is used by both memory dma,
117 * pci dma, and io dma sub-module. Queue sub-module is not a sub-module in
118 * the sense of Magnum architecture. It is only a module in the sense of
119 * generic programming.
120 *
121 * It is intended to be used privately, to run fast, and therefore it does
122 * not perform parameter validation
123 *
124 * Refer to BDMA_P_Queue_Create, the queue manages a queue-entry array and
125 * a decriptor array. Each queue-entry points to the descriptor of the same
126 * index. The descriptor buffer is allocated from BMEM and is contiguous.
127 *
128 * When a new transfer is required, BDMA_P_Queue_CreateTran is called
129 * to allocate the next un-used contiguous chunck of queue-entries /
130 * descriptors and initialize the first entry of the chunck, that stores
131 * the state (such as Tran status, NumBlocks of the transfer). The queue is
132 * used in a round-robin and wrap-around manner.
133 *
134 * BDMA_P_Queue_StartTran is called when "start" or "start and call back" is
135 * called by high level software. It decides whether the user ordered Tran
136 * should be sent to HW at the moment, put as queued, or return error of
137 * "engine busy".
138 *
139 * BDMA_P_Queue_DestroyTran is called when "destroy" is called by high level
140 * software. It free the Tran's entries for future Tran creating request.
141 *
142 * BDMA_P_Queue_ProcEngineIdle is called to process the engine idle info.
143 * It is ideally for DMA engine/channel's "done" interrupt handler.
144 * It ensures HW just finished a transfer and decides which one is just
145 * finished. It also schedules a new (async) transfer to be sent to HW if
146 * there exists one.
147 *
148 * Implementaion notes:
149 *   1. A Tran occupies a contiguous chunk of entries. Each entry represents
150 * a transfer block. The first entry represent the Tran and stores the Tran's
151 * status, number of blocks, user call back func, user call back para, ...,
152 * and only fields bBlockInfoSet and pulDesc in the following entries has
153 * siginificace (the otherfiels are set fot assersion only).
154 *   2. Whether a Tran is active or not, is indicated by whether its status
155 * is unknown. The entries of a non-active Tran are free for new Tran
156 * creating.
157 *   3. The queue module mantains two index: ulIndx_LastEntryIssued, and
158 * ulIndx_LastEntryAssigned. If ulIndx_LastEntryIssued is in InProgress state,
159 * the HW is busy, otherwise HW is idle. When a "done" interrupt happens, the
160 * module tries to find the next async Tran after (wrap-aroundly) the just
161 * finished one, to send to HW. And new Tran creating tries to use the next
162 * free contiguoys chunk of entries after ulIndx_LastEntryAssigned (wrap-
163 * aroundly also). By this way we try to maintan a fairness to all transfer
164 * requests.
165 *   4. It is assumed that all Tran causes a interrupt, in order to mantain
166 * the channel /queue state.
167 *   5. Queue module manages the state of the queue, the user of queue module
168 * may only know the struct of BDMA_P_QueueEntry.
169 */
170
171#define BDMA_P_NUM_QUEUE_ENTRIES      (2<<8)
172#define BDMA_P_MAX_NUM_BLOCKS         (BDMA_P_NUM_QUEUE_ENTRIES >> 1)
173
174#define BDMA_P_QUEUE_GET_CONTEXT(handle, context) \
175        BDMA_P_GENERIC_GET_CONTEXT(handle, context, BDMA_P_QueueContext)
176
177#define BDMA_P_QUEUE_SET_BLACK_MAGIC(handle) \
178        BDMA_P_GENERIC_SET_BLACK_MAGIC(handle, BDMA_P_QueueContext)
179       
180#define BDMA_P_QUEUE_DESTROY_CONTEXT(struct_ptr) \
181        BDMA_P_GENERIC_DESTROY_CONTEXT(struct_ptr, BDMA_P_QueueContext)
182
183#if BDBG_DEBUG_BUILD
184#define BDMA_P_QUEUE_DESTROY_ENTRY(entry_head, num_entry) \
185{ \
186        BKNI_Memset((void*)entry_head, 0xA3, num_entry * sizeof(BDMA_P_QueueEntry)); \
187        BKNI_Free((void*)entry_head); \
188        entry_head = NULL; \
189}
190#else
191#define BDMA_P_QUEUE_DESTROY_ENTRY(entry_head, num_entry) \
192{ \
193        BKNI_Free((void*)entry_head); \
194}
195#endif 
196
197#if BDBG_DEBUG_BUILD
198#define BDMA_P_QUEUE_DESTROY_DESC(h_mem, desc_ptr, size) \
199{ \
200        BKNI_Memset((void*)desc_ptr, 0xA3, size); \
201        BMEM_Free(h_mem, desc_ptr); \
202}
203#else
204#define BDMA_P_QUEUE_DESTROY_DESC(h_mem, desc_ptr, size) \
205{ \
206        BMEM_Free(h_mem, desc_ptr); \
207}
208#endif 
209
210#define BDMA_P_TRAN_GET_CONTEXT(handle, context) \
211{ \
212        if(!(handle) || \
213           (((BDMA_P_QueueEntry*)(handle))->ulBlackMagic != \
214            (sizeof(BDMA_P_QueueEntry) | 0xbac98700))) \
215        { \
216                BDBG_ERR(("NULL context handle\n")); \
217                (context) = NULL; \
218        } \
219        else \
220        { \
221                (context) = (BDMA_P_QueueEntry *)(handle); \
222        } \
223}
224
225#define BDMA_P_TRAN_SET_BLACK_MAGIC(handle) \
226{ \
227        ((BDMA_P_QueueEntry*)(handle))->ulBlackMagic = sizeof(BDMA_P_QueueEntry) | 0xbac98700; \
228}
229
230/***************************************************************************
231 * {private}
232 * Dma queue handle
233 */
234typedef struct BDMA_P_QueueContext    *BDMA_P_QueueHandle;
235       
236/***************************************************************************   
237 * {private}
238 * dma queue entry info
239 * Each queue entry corresponds to a dma descriptor, and therefore a tran
240 * block. A transfer's state is stored in the queue entry of its first block
241 */
242typedef struct BDMA_P_QueueEntry  BDMA_P_Tran;
243typedef void (* BDMA_P_CallbackFunc)( \
244        void *  pUserCallBackParam,\
245        BDMA_P_Tran * hTran, \
246        BDMA_TranStatus  eStatus );
247
248typedef struct BDMA_P_QueueEntry
249{
250        uint32_t   ulBlackMagic;   /* Black magic for handle validation */
251
252        /* created from this handle */
253        BDMA_P_QueueHandle   hQueue;
254
255        /* --------------------------------------------------
256         *
257         * context for Tran only
258         */
259        struct BDMA_P_QueueEntry *pNextTran;   /* for dynamical link to next Tran */
260       
261        uint32_t             ulNumTranBlocks;   /* Max number of blocks in this Tran */
262        uint32_t             ulNumActBlocks;    /* Number of blocks currently active */
263        BDMA_P_CallbackFunc  pCallBackFunc_isr; /* call back function ptr */
264        void *               pUserCallBackParam;/* user's info to call back func */
265        BDMA_TranStatus      eStatus;           /* status of the transfer */
266       
267        /* current state of the Tran: applied to future setDmaBlockInfo */
268        BDMA_CryptMode       eCryptMode;
269        uint32_t             ulKeySlot;
270        bool                 bSgEnable;
271
272        bool                 bSgStartStopSet;   /* ever set in any block of this Tran */
273
274        bool                 bCachedDscrp;      /* whether use cached addr to write descrp */
275
276        /* --------------------------------------------------
277         *
278         * context for each block
279         */
280        bool                 bBlockInfoSet;     /* whether this block's info is set */
281        uint32_t             ulSgStartStop;
282        uint32_t *           pulDescAddr;       /* descriptor buffer - non-cached addr */
283        uint32_t *           pulCachedDescAddr; /* descriptor buffer - cached addr */
284        uint32_t             ulDescPhysAddr;    /* descriptor buffer - phys addr */
285       
286        uint32_t             ulFirstBlock;      /* offset into contiguous descriptor list */
287} BDMA_P_QueueEntry;
288
289/***************************************************************************
290 * {private}
291 * HW status enum
292 */
293typedef enum
294{
295        BDMA_P_HwStatus_eIdle, 
296        BDMA_P_HwStatus_eBusy,
297        BDMA_P_HwStatus_eSleep,
298        BDMA_P_HwStatus_eUnknown
299}
300BDMA_P_HwStatus;
301
302/***************************************************************************
303 * {private}
304 * Common dma engine settings
305 */
306typedef struct BDMA_P_CmnSettings
307{
308        uint32_t                           ulTotalNumBlocks;
309        uint32_t                           ulMaxNumBlocksPerTran;
310
311        /* settings for the case of multiple BDMA instances */
312        BDMA_LockCallbackFunc              pTryLock_isr;
313        BDMA_LockCallbackFunc              pReleaseLock_isr;
314        void                             * pvParm1;
315        int                                iParm2;
316        bool                               bSupportCallBack;
317}
318BDMA_P_CmnSettings;
319
320/***************************************************************************
321 * {private}
322 * Call back functions to deal with specific HW engine and descriptor formats
323 */
324typedef void (* BDMA_P_ReadHwRegsFunc) ( \
325        void *                   pvEngine, \
326        BDMA_P_HwStatus  *       peHwStatus, \
327        uint32_t  *              pulCurrDesc, \
328        uint32_t  *              pulScratchReg );
329
330typedef void (* BDMA_P_AppendTranDescFunc)(     \
331        BDMA_P_QueueEntry *      pCurrTran,  \
332        BDMA_P_QueueEntry *      pNextTran );
333
334typedef void (* BDMA_P_SendToHwFunc)( \
335        BDMA_P_QueueHandle       hQueue, \
336        BDMA_P_HwStatus          eHwStatus, \
337        bool                     bAppendInHw );
338
339typedef void (* BDMA_P_CheckNextDescFunc)( \
340        BDMA_P_QueueEntry *      pCurrTran,  \
341        BDMA_P_QueueEntry *      pNextTran );
342
343typedef void (* BDMA_P_SafeToSendHwFunc)( \
344        BDMA_P_QueueHandle       hQueue,      \
345        BDMA_P_HwStatus*         peHwStatus);
346/***************************************************************************
347 * {private}
348 * Dma queue Context
349 */
350typedef struct BDMA_P_QueueContext
351{
352        uint32_t   ulBlackMagic;   /* Black magic for handle validation */
353
354        /* created from this dma engine */
355        void *              hEngine;
356       
357        uint32_t            ulIndx_LastEntryAssigned;
358
359        bool                bDmaHwShared;
360        bool                bHwStarted;
361        bool                bSgOpenInHw; /* SgOpen: scatter-gather started, not stopped */
362        bool                bPreLinkSgOpenInHw; /* in case dyn link fails */
363        bool                bSgOpenInQ;
364        BDMA_P_QueueEntry * pHeadTranInHw;
365        BDMA_P_QueueEntry * pTailTranInHw;
366        BDMA_P_QueueEntry * pHeadTranInQ;
367        BDMA_P_QueueEntry * pTailTranInQ;
368        BDMA_P_QueueEntry * pPreLinkTailTranInHw; /* in case dyn link fails */
369       
370        uint32_t            ulNumWordsPerDesc;
371        BDMA_P_CmnSettings  CmnSettings;
372       
373        uint32_t            ulLockMark;
374        uint32_t            ul1stDescPhysAddr;
375        uint32_t                    ulLastDescPhysAddr;
376        BDMA_P_QueueEntry * pHeadEntry;         /* pointer to the entry array */
377       
378        /* call back funcs from engine to deal with specific HW */
379        BDMA_P_ReadHwRegsFunc           pReadHwRegs_isr;
380        BDMA_P_AppendTranDescFunc       pAppendTranDesc_isr;
381        BDMA_P_SendToHwFunc         pSendToHw_isr;
382        BDMA_P_CheckNextDescFunc    pCheckNextDesc_isr;  /* for err msg only */
383        BDMA_P_SafeToSendHwFunc     pSafeToSendHw_isr;
384       
385} BDMA_P_QueueContext;
386
387
388/***************************************************************************
389 * {private}
390 * BDMA_P_Queue_Create
391 *
392 * To be called to create queue for a dma channel. It allocates a queue entry
393 * array from system memory, and contiguous descriptor array from BMEM.
394 * It then initiate the allocated queue array, including setting each
395 * queue-entry to point to the descriptor of the same index.
396 *
397 * Note: assume parameters are valid
398 */
399BERR_Code BDMA_P_Queue_Create
400        ( BDMA_P_QueueHandle *      phQueue,
401          void *                    hEngine,
402          BMEM_Handle               hMemory,
403          uint32_t                  ulNumWordsPerDesc,
404          const BDMA_P_CmnSettings *pCmnSettings,
405          BDMA_P_ReadHwRegsFunc         pReadHwRegs_isr,
406          BDMA_P_AppendTranDescFunc     pAppendTranDesc_isr,
407          BDMA_P_SendToHwFunc       pSendToHw_isr,
408          BDMA_P_CheckNextDescFunc  pCheckNextDesc_isr,
409          BDMA_P_SafeToSendHwFunc   pSafeToSendHw_isr);
410
411/***************************************************************************
412 * {private}
413 * BDMA_P_Queue_Destroy
414 *
415 * To be called to destroy the queue.
416 *
417 * Note: assume parameters are valid
418 */
419BERR_Code BDMA_P_Queue_Destroy
420        ( BDMA_P_QueueHandle        hQueue,
421          BMEM_Handle               hMemory );
422
423/***************************************************************************
424 * {private}
425 * BDMA_P_Queue_GetEngine_isr
426 *
427 * To be called to get the dma engine
428 *
429 * Note: assume parameters are valid
430 */
431void * BDMA_P_Queue_GetEngine_isr
432        ( BDMA_P_QueueHandle        hQueue );
433
434/*--------------------------------------------------------------------------
435 * {private}
436 * BDMA_P_Queue_CheckHwAndSendNewReq_isr
437 *
438 * Called to check HW status, process it, and try to send the Trans queued
439 * in SW into HW
440 */
441void BDMA_P_Queue_CheckHwAndSendNewReq_isr
442        ( BDMA_P_QueueHandle       hQueue );
443
444/***************************************************************************
445 * {private}
446 * BDMA_P_Queue_CreateTran
447 *
448 * To be called when a new transfer is created. It finds a free chunck of
449 * contiguous queue entries (that corresponds to a set of contiguous
450 * descriptors too) in the dma channel queue, and outputs the first entry
451 * of the chunck.
452 *
453 * Note: assume parameters are valid,
454 *       ulNumBlocks can not be 0
455 */
456BERR_Code BDMA_P_Queue_CreateTran_isr
457        ( BDMA_P_QueueHandle       hQueue,
458          uint32_t                 ulNumBlocks,
459          bool                     bCachedDesc,
460          BDMA_P_QueueEntry **     ppNewTran );
461
462/***************************************************************************
463 * {private}
464 * BDMA_P_Queue_StartTran_isr
465 *
466 * To be called to process the user calling of Start or StartAndCallBack.
467 *
468 * pCallBackFunc_isr is assumed to indicate whether the Tran is sync or async.
469 *
470 * Note: assume parameters are valid
471 */
472BERR_Code BDMA_P_Queue_StartTran_isr
473        ( BDMA_P_QueueHandle       hQueue,
474          BDMA_P_QueueEntry *      pTran,
475          uint32_t                 ulNumActBlocks,
476          bool                     bSgOpen,
477          BDMA_P_CallbackFunc      pCallBackFunc_isr,
478          void *                   pUserCallBackParam );
479
480/***************************************************************************
481 * {private}
482 * BDMA_P_Queue_DestroyTran
483 *
484 * To be called to destroy a Tran. It reset the Tran's entries to make the
485 * chunk of blocks as a destroyed Tran
486 *
487 * Note: assume parameters are valid
488 */
489BERR_Code BDMA_P_Queue_DestroyTran_isr
490        ( BDMA_P_QueueHandle       hQueue,
491          BDMA_P_QueueEntry *      pTran );
492
493/***************************************************************************
494 * {private}
495 * BDMA_P_Queue_ResetTran
496 *
497 * To be called to reset a active Tran into intial eCreated state. Without
498 * resetting, the Tran could also be used to SetBlockInfo and Start again,
499 * but the module will not be able to check whether each block info is set.
500 *
501 * Note: assume parameters are valid,
502 */
503BERR_Code BDMA_P_Queue_ResetTran_isr
504        ( BDMA_P_QueueHandle       hQueue,
505          BDMA_P_QueueEntry *      pTran );
506
507#ifdef __cplusplus
508}
509#endif
510
511#endif /* #ifndef BDMA_QUEUE_H__ */
512
513/* End of File */
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