Context Navigation

bgrc_private.h

Last change on this file was 2, checked in by jglee, 11 years ago
first commit
Property svn:executable set to ``*
File size: 66.1 KB

Line
1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bgrc_private.h $
11	* $brcm_Revision: Hydra_Software_Devel/147 $
12	* $brcm_Date: 2/16/12 3:25p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/grc/7405/bgrc_private.h $
19	*
20	* Hydra_Software_Devel/147 2/16/12 3:25p nissen
21	* SW7405-5427: Adding flags for output mirroring when blitting
22	*
23	* Hydra_Software_Devel/146 2/8/12 11:25a nissen
24	* SW7405-3671: Added hang field to GRC structure.
25	*
26	* Hydra_Software_Devel/145 1/6/12 1:19p nissen
27	* SW7435-13 : Fixed support for 7435 A0.
28	*
29	* Hydra_Software_Devel/144 12/15/11 6:29p nissen
30	* SW7435-13 : Added support for 7435 A0.
31	*
32	* Hydra_Software_Devel/143 12/14/11 5:01p nissen
33	* SW7435-13 : Added support for 7435 A0.
34	*
35	* Hydra_Software_Devel/142 10/5/11 5:45p nissen
36	* SW7425-248: Updated use of BDBG_OBJECTs.
37	*
38	* Hydra_Software_Devel/141 10/5/11 1:04p nissen
39	* SW7425-248: Removed BDBG_OBJECT support for the 7038.
40	*
41	* Hydra_Software_Devel/140 9/17/11 7:11p nissen
42	* SW7425-248: Added BDBG_OBJECT_ID_DECLARE.
43	*
44	* Hydra_Software_Devel/139 9/17/11 6:38p nissen
45	* SW7425-248: Added BDBG_OBJECT_ASSERT.
46	*
47	* Hydra_Software_Devel/138 7/14/11 10:16a pntruong
48	* SWDTV-7838: Fixed build errors. Gotta have both mask/shift.
49	*
50	* Hydra_Software_Devel/137 4/20/11 1:20p nissen
51	* SW7630-104: Added support for A8_Y8 format and big endian 420
52	* conversion.
53	*
54	* Hydra_Software_Devel/136 9/17/10 5:58p nissen
55	* SWBLURAY-21937: Reducing M2MC stripe size during scale blits on 7630
56	* due to hang.
57	*
58	* Hydra_Software_Devel/135 7/15/10 9:18p nissen
59	* SW7405-3671: Added more interrupt support.
60	*
61	* Hydra_Software_Devel/134 7/12/10 2:34p nissen
62	* SW7405-3671: Changed packet fields in grc handle.
63	*
64	* Hydra_Software_Devel/133 6/21/10 2:16p nissen
65	* SW7405-3671: Fixed non-packet build.
66	*
67	* Hydra_Software_Devel/132 6/21/10 12:31p nissen
68	* SW7405-3671: Added support for packet context and settings.
69	*
70	* Hydra_Software_Devel/131 2/11/10 5:24p nissen
71	* SW7405-3671: Added support for cached packet memory.
72	*
73	* Hydra_Software_Devel/130 2/3/10 2:05p nissen
74	* SW7405-3671: Added batch packets.
75	*
76	* Hydra_Software_Devel/129 1/29/10 7:25p nissen
77	* SW7405-3671: Added support for using packets in any order.
78	*
79	* Hydra_Software_Devel/128 1/19/10 12:49p nissen
80	* SW7405-3671: Added packet sync offset field to GRC handle structure.
81	*
82	* Hydra_Software_Devel/127 1/9/10 10:58a nissen
83	* SW7405-3671: Added support for packet blits.
84	*
85	* Hydra_Software_Devel/126 8/20/09 12:42p nissen
86	* PR 52470: Changed some variables and functions to const and/or static.
87	*
88	* Hydra_Software_Devel/125 8/18/09 5:33p nissen
89	* PR 52470: Optimized setting registers.
90	*
91	* Hydra_Software_Devel/124 8/13/09 6:26p nissen
92	* PR 57469: Increased operation min.
93	*
94	* Hydra_Software_Devel/123 8/12/09 1:13p nissen
95	* PR 57469: Set min packet and operation sizes when opening.
96	*
97	* Hydra_Software_Devel/122 8/10/09 6:09p nissen
98	* PR 57469: Fixed problem with WaitForOperationReady function.
99	*
100	* Hydra_Software_Devel/121 7/7/09 5:47p nissen
101	* PR 56610: Moved local declaration to GRC handle structure.
102	*
103	* Hydra_Software_Devel/120 6/22/09 5:13p nissen
104	* PR 56219: Added new macro for setting register field data.
105	*
106	* Hydra_Software_Devel/119 6/7/09 5:15p nissen
107	* PR 51077: Removed ulOperationsSinceInterrupt field from BGRC_P_Handle
108	* structure.
109	*
110	* Hydra_Software_Devel/118 5/13/09 10:46a nissen
111	* PR 54982: Added code to make sure that surface rectangle positions are
112	* not negative.
113	*
114	* Hydra_Software_Devel/117 4/17/09 4:30p nissen
115	* PR 51077: Added callbacks to wait functions.
116	*
117	* Hydra_Software_Devel/116 4/7/09 2:31p nissen
118	* PR 52976: Added support for 7635/7630 and future chips using RDB
119	* defines.
120	*
121	* Hydra_Software_Devel/115 3/20/09 4:20p nissen
122	* PR 51077: Added functions to wait on operations, and better handling
123	* for running out of memory.
124	*
125	* Hydra_Software_Devel/114 1/31/09 1:15a jrubio
126	* PR51629: add 7336 support
127	*
128	* Hydra_Software_Devel/113 12/3/08 6:53p nissen
129	* PR 47763: Added support for 7420.
130	*
131	* Hydra_Software_Devel/112 7/30/08 8:16p nissen
132	* PR 33687: Added support for the 7601.
133	*
134	* Hydra_Software_Devel/111 6/23/08 12:54p nissen
135	* PR 43693: Removed scaler coefficient register overwrite fix for 3548
136	* and 3556.
137	*
138	* Hydra_Software_Devel/110 6/4/08 8:02p nissen
139	* PR 43321: Updated for 3548 and 3556.
140	*
141	* Hydra_Software_Devel/109 6/4/08 7:51p nissen
142	* PR 42985: Changed scaler coefficient define from 16 to 64 for 3563 Cx
143	* and greater.
144	*
145	* Hydra_Software_Devel/108 4/4/08 11:54a nissen
146	* PR 39460: Added support for the 3556.
147	*
148	* Hydra_Software_Devel/107 2/8/08 2:21p nissen
149	* PR 38945: Added support for the 3548.
150	*
151	* Hydra_Software_Devel/106 2/8/08 10:50a nissen
152	* PR 39221: Added pulldown register overwrite fix for 3563 C0.
153	*
154	* Hydra_Software_Devel/105 2/7/08 12:46p nissen
155	* PR 24618: Added sharper anti-flutter filter coefficient table.
156	*
157	* Hydra_Software_Devel/104 12/17/07 9:51a nissen
158	* PR 38269: Added support for inverting sources during a blit.
159	*
160	* Hydra_Software_Devel/103 12/10/07 3:03p nissen
161	* PR 29724: Fixed problem with reseting macroblock state.
162	*
163	* Hydra_Software_Devel/102 12/4/07 5:42p nissen
164	* PR 28248: Removed register overwrite fix for 3563 C0 and above.
165	*
166	* Hydra_Software_Devel/101 12/4/07 5:17p nissen
167	* PR 36878: Added support for the 7335.
168	*
169	* Hydra_Software_Devel/100 11/16/07 3:03p nissen
170	* PR 36759: Added support for setting the scale factor independently of
171	* the provided rectangle sizes.
172	*
173	* Hydra_Software_Devel/99 10/12/07 7:42a nissen
174	* PR 35920: Added support for preallocating system memory for operation
175	* structures when opening module.
176	*
177	* Hydra_Software_Devel/98 10/11/07 6:05p nissen
178	* PR 33390: Increased scale down max, and added define vertical scale
179	* down max.
180	*
181	* Hydra_Software_Devel/97 9/19/07 11:19a nissen
182	* PR 34538: Added support for building for the 7325.
183	*
184	* Hydra_Software_Devel/96 9/18/07 1:27p nissen
185	* PR 34852: Added support for building for the 3573.
186	*
187	* Hydra_Software_Devel/95 8/20/07 2:06p nissen
188	* PR 34132: Added support for setting a linear 420 source.
189	*
190	* Hydra_Software_Devel/94 8/20/07 12:46p nissen
191	* PR 33390: Reduce scale down max define from 15 to 7 for new chips, due
192	* to hang when scaling down past 7 times.
193	*
194	* Hydra_Software_Devel/93 5/2/07 11:59a nissen
195	* PR 29724: Fixed support for MacroBlock strip width.
196	*
197	* Hydra_Software_Devel/92 5/2/07 11:34a nissen
198	* PR 29724: Added support for 7405 A0 including new MacroBlock strip
199	* width setting.
200	*
201	* Hydra_Software_Devel/91 3/29/07 11:28a nissen
202	* PR 28248: Fixed problem with 3563 M2MC overwritting source color matrix
203	* and pulldown registers when writing scaler coefficent registers.
204	*
205	* Hydra_Software_Devel/90 3/28/07 9:49p nissen
206	* PR 29156: Fixed bug with palette surface identification.
207	*
208	* Hydra_Software_Devel/89 3/28/07 5:21p nissen
209	* PR 29156: Fixed bug with palette surface identification.
210	*
211	* Hydra_Software_Devel/88 3/28/07 2:26p nissen
212	* PR 25683: Fixed problem with identifying a surface when changing its
213	* palette.
214	*
215	* Hydra_Software_Devel/87 3/2/07 11:36a nissen
216	* PR 28010: Added Macroblock feature support for 7440 B0.
217	*
218	* Hydra_Software_Devel/86 3/1/07 12:33p nissen
219	* PR 25991: Fixed MacroBlock feature for 7400 B0.
220	*
221	* Hydra_Software_Devel/85 1/29/07 10:44a nissen
222	* PR 19665: Fixed problem with hardware striping while scaling.
223	*
224	* Hydra_Software_Devel/84 1/22/07 1:43p nissen
225	* PR 20763: Fixed support for 10-bit YCbCr 444 format on 3563.
226	*
227	* Hydra_Software_Devel/83 12/1/06 10:53a nissen
228	* PR 25991: Added support for 7400 B0.
229	*
230	* Hydra_Software_Devel/82 11/15/06 2:33p nissen
231	* PR 25683: Fixed problem with using new surface id.
232	*
233	* Hydra_Software_Devel/81 11/15/06 11:39a nissen
234	* PR 25668: Added support for 7403.
235	*
236	* Hydra_Software_Devel/80 11/15/06 11:00a nissen
237	* PR 25683: Added code to use new surface id.
238	*
239	* Hydra_Software_Devel/79 11/8/06 11:11a nissen
240	* PR 25683: Added support for using a surface ID to identify new
241	* surfaces.
242	*
243	* Hydra_Software_Devel/78 10/24/06 7:32p nissen
244	* PR 24648: Fixed problem with VC-1 macroblock
245	*
246	* Hydra_Software_Devel/77 10/19/06 11:02a nissen
247	* PR 24647: Added support for preallocting all device memory when module
248	* is opened.
249	*
250	* Hydra_Software_Devel/76 10/6/06 10:56a nissen
251	* PR 24719: Fixed macro used to calculate input stripe width on 7118.
252	*
253	* Hydra_Software_Devel/75 10/5/06 1:55p nissen
254	* PR 24648: Added support for VC-1 macro block range remapping and
255	* expansion for 7401 C0 and 7118.
256	*
257	* Hydra_Software_Devel/74 9/29/06 10:03a nissen
258	* PR 24618: Added support for second blurryer anti-flutter filter
259	* coefficient table.
260	*
261	* Hydra_Software_Devel/73 9/8/06 3:51p nissen
262	* PR 23517: Added support for 7440.
263	*
264	* Hydra_Software_Devel/72 8/25/06 11:22a nissen
265	* PR 20763: Added support for 10-bit YCbCr 444 and 422 formats.
266	*
267	* Hydra_Software_Devel/71 8/17/06 11:45a nissen
268	* PR 21940: Fixed filter table support for 7118.
269	*
270	* Hydra_Software_Devel/70 8/17/06 11:23a nissen
271	* PR 23179: Added support for building and running on the 3563.
272	*
273	* Hydra_Software_Devel/69 6/22/06 10:38a nissen
274	* PR 21940: Added support for 7118.
275	*
276	* Hydra_Software_Devel/68 6/15/06 9:36a nissen
277	* PR 21171: Adjusted register group counts for 7401 B0.
278	*
279	* Hydra_Software_Devel/67 5/30/06 10:45a nissen
280	* PR 21878: Added support for setting the operation time out interval
281	* with settings structure when opening module.
282	*
283	* Hydra_Software_Devel/66 5/3/06 12:38p nissen
284	* PR 21171: Added support for building and running 7401 B0.
285	*
286	* Hydra_Software_Devel/65 4/18/06 1:20p nissen
287	* PR 18369: Added support for hardware striping when scaling on the 7400
288	* and 7401.
289	*
290	* Hydra_Software_Devel/64 3/22/06 1:05p nissen
291	* PR 19551: Added register value compare macro.
292	*
293	* Hydra_Software_Devel/63 3/22/06 12:02p nissen
294	* PR 19551: Eliminted color and format BCHP_M2MC_ defines.
295	*
296	* Hydra_Software_Devel/62 3/21/06 12:58p nissen
297	* PR 20331: Calling new function to get surface and palette offsets.
298	*
299	* Hydra_Software_Devel/61 3/17/06 10:39a nissen
300	* PR 19084: Added brackets to parameter for macros that reads and writes
301	* registers
302	*
303	* Hydra_Software_Devel/60 3/15/06 1:20p nissen
304	* PR 15840: Fixed problem with YCbCr420 format without filtering enabled.
305	*
306	* Hydra_Software_Devel/59 3/15/06 12:10p nissen
307	* PR 15840: Added support for using YCbCr420 surfaces as a source.
308	*
309	* Hydra_Software_Devel/58 3/8/06 2:49p nissen
310	* PR 19575: Added support for building and running second m2mc on 7438.
311	*
312	* Hydra_Software_Devel/57 2/21/06 4:33p nissen
313	* PR 19553: Fixed problem with setting filter coefficient registers for
314	* 7400.
315	*
316	* Hydra_Software_Devel/56 2/21/06 3:27p nissen
317	* PR 19084: Fixed macros that reads and writes registers.
318	*
319	* Hydra_Software_Devel/55 2/21/06 11:58a nissen
320	* PR 19084: Added support for second m2mc device.
321	*
322	* Hydra_Software_Devel/54 2/9/06 5:27p nissen
323	* PR 19553: Adjusted register groups.
324	*
325	* Hydra_Software_Devel/53 2/1/06 5:27p nissen
326	* PR 19084: Added support for building for the 7400 A0.
327	*
328	* Hydra_Software_Devel/52 1/18/06 11:34a nissen
329	* PR 19116: Added support for inactivating operations when no interrupts
330	* are expected.
331	*
332	* Hydra_Software_Devel/51 1/12/06 5:48p nissen
333	* PR 18761: Added support for BCHP_VER macro.
334	*
335	* Hydra_Software_Devel/50 12/3/05 6:00p nissen
336	* PR 18007: Increased block size and max allocation defines.
337	*
338	* Hydra_Software_Devel/49 12/1/05 6:03p nissen
339	* PR 18007: Added code to return error when down scaling more than 15x
340	* for M2MC Cx and above.
341	*
342	* Hydra_Software_Devel/48 10/25/05 1:44p nissen
343	* PR 17518: Modified scaler and filter related defines for 7401.
344	*
345	* Hydra_Software_Devel/47 10/5/05 10:55a nissen
346	* PR 17273: Added memory cache support.
347	*
348	* Hydra_Software_Devel/46 9/13/05 4:27p nissen
349	* PR 16499: Added code to free memory past a default or specified
350	* threshold.
351	*
352	* Hydra_Software_Devel/45 8/2/05 4:12p nissen
353	* PR 16489: Fixed problem with processing interrupts for operations that
354	* have not completed.
355	*
356	* Hydra_Software_Devel/44 7/7/05 5:47p nissen
357	* PR 15108: Fixed problem with getting palette offset.
358	*
359	* Hydra_Software_Devel/43 7/5/05 5:25p nissen
360	* PR 16056: Added support for building for the 7401 A0.
361	*
362	* Hydra_Software_Devel/43 7/5/05 5:19p nissen
363	* PR 16056: Added support for building for the 7401 A0.
364	*
365	* Hydra_Software_Devel/42 5/18/05 5:31p agin
366	* PR14720: B2, C1, C2 compilation support.
367	*
368	* Hydra_Software_Devel/41 5/12/05 4:34p nissen
369	* PR 15264: Modified support for user defined phase adjustment when
370	* filtering.
371	*
372	* Hydra_Software_Devel/40 5/12/05 2:44p nissen
373	* PR 15264: Added support for user defined phase adjustment when
374	* filtering.
375	*
376	* Hydra_Software_Devel/39 5/12/05 10:25a nissen
377	* PR 15226: Modified code to store surface information when a surface is
378	* set instead of looking it up later.
379	*
380	* Hydra_Software_Devel/38 5/6/05 1:38p nissen
381	* PR 13488: Added support for M2MC C1.
382	*
383	* Hydra_Software_Devel/37 3/16/05 12:26p nissen
384	* PR 14329: Fixed setting format field for W formats.
385	*
386	* Hydra_Software_Devel/36 2/17/05 1:11p nissen
387	* PR 14086: Added support for new color matrix register precision on the
388	* 3560.
389	*
390	* Hydra_Software_Devel/35 12/17/04 1:40p nissen
391	* PR 13325: Added packet offset field to operation data structure.
392	*
393	* Hydra_Software_Devel/34 12/13/04 2:12p nissen
394	* PR 13488: Added support for M2MC C0.
395	*
396	* Hydra_Software_Devel/33 9/24/04 2:32p nissen
397	* PR 12728: Removed extra semi-colon for pedantic errors.
398	*
399	* Hydra_Software_Devel/32 9/23/04 2:07p nissen
400	* PR 12729: Added support for anti-flutter filtering.
401	*
402	* Hydra_Software_Devel/31 6/28/04 1:05p nissen
403	* PR 11700: Eliminated compiler warnings.
404	*
405	* Hydra_Software_Devel/30 6/22/04 9:10p nissen
406	* PR 11638: Added fix for expanding alpha using replication for ARGBB1555
407	* formats.
408	*
409	* Hydra_Software_Devel/29 6/11/04 10:25p nissen
410	* PR 11486: Fixed problemss with scaling.
411	*
412	* Hydra_Software_Devel/28 6/3/04 8:32p nissen
413	* PR 11349: Added functionality for tracking interrupts.
414	*
415	* Hydra_Software_Devel/27 5/24/04 5:08p jasonh
416	* PR 11189: Merge down from B0 to main-line
417	*
418	* Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/27/04 7:22p nissen
419	* PR 9635: Added support for M2MC B0.
420	*
421	* Hydra_Software_Devel/26 4/12/04 9:53a pntruong
422	* PR 10548: Changed private shift function to non-private.
423	*
424	* Hydra_Software_Devel/25 4/9/04 2:14p nissen
425	* PR 10380: Modified field setting macros to do mask and set operation
426	* for more than one field at a time.
427	*
428	* Hydra_Software_Devel/24 3/31/04 12:01p nissen
429	* PR 10165: Added macros to validate surface rectangles.
430	*
431	* Hydra_Software_Devel/23 3/12/04 2:32p nissen
432	* PR 10024: Added support for more error checking.
433	* PR 10072: Added support for no-scale filtering.
434	*
435	* Hydra_Software_Devel/22 3/5/04 2:39p nissen
436	* PR 9856: Fixed problem with rectangle width's and height's being set to
437	* zero.
438	*
439	* Hydra_Software_Devel/21 2/17/04 2:39p nissen
440	* PR 9719: Added function defintion for getting sharper filter
441	* coefficient table.
442	*
443	* Hydra_Software_Devel/20 2/10/04 11:19a nissen
444	* PR 9700: Added function definition for getting blurry filter
445	* coefficients.
446	*
447	* Hydra_Software_Devel/19 2/2/04 12:49p nissen
448	* PR 8725: Eliminated warnings from set alpha blend macro.
449	*
450	* Hydra_Software_Devel/18 1/30/04 1:49p nissen
451	* PR 9537: Fixed macro that checks if a register has changed.
452	*
453	* Hydra_Software_Devel/17 1/21/04 2:01p nissen
454	* PR 9432: Added more error checking.
455	*
456	* Hydra_Software_Devel/16 12/18/03 2:13p nissen
457	* PR 8725: Eliminated warnings.
458	*
459	* Hydra_Software_Devel/15 11/21/03 6:45p nissen
460	* Fixed problem with callback function pointer.
461	*
462	* Hydra_Software_Devel/14 11/20/03 7:01p nissen
463	* Added operation queuing mechanism and support for interrupts.
464	*
465	* Hydra_Software_Devel/13 10/20/03 1:37p nissen
466	* Removed macro.
467	*
468	* Hydra_Software_Devel/12 10/9/03 1:38p nissen
469	* Removed IKOS hacks.
470	*
471	* Hydra_Software_Devel/11 9/29/03 11:19a nissen
472	* Fixed problem with macro that sets filter coeff fields.
473	*
474	* Hydra_Software_Devel/10 9/19/03 4:00p nissen
475	* Added support for aligning ROP pattern.
476	*
477	* Hydra_Software_Devel/9 8/26/03 4:13p nissen
478	* Added macro to get surface data.
479	*
480	* Hydra_Software_Devel/8 8/21/03 1:29p nissen
481	* Fixed copy field macro.
482	*
483	* Hydra_Software_Devel/7 8/20/03 4:47p nissen
484	* Added macros to copy registers and fields. Added state structure.
485	*
486	* Hydra_Software_Devel/6 8/19/03 10:14a nissen
487	* Fixed macro that sets surface format type field. Fixed macro that reads
488	* register.
489	*
490	* Hydra_Software_Devel/5 8/12/03 11:37a nissen
491	* Changed field and register setting macros.
492	*
493	* Hydra_Software_Devel/4 8/6/03 2:36p nissen
494	* Update macros for setting registers and their fields.
495	*
496	* Hydra_Software_Devel/3 6/25/03 11:59a nissen
497	* Added macros for setting and getting register values.
498	*
499	* Hydra_Software_Devel/2 6/5/03 11:50a nissen
500	* Added macro to set surface format type field.
501	*
502	* Hydra_Software_Devel/1 5/28/03 5:33p nissen
503	* Added macros of format definition type.
504	*
505	***************************************************************************/
506
507	#ifndef BGRC_PRIVATE_H__
508	#define BGRC_PRIVATE_H__
509
510	#ifdef __cplusplus
511	extern "C" {
512	#endif
513
514	#include "bgrc_packet.h"
515	#include "bgrc_packet_priv.h"
516
517	/***************************************************************************/
518	BDBG_OBJECT_ID_DECLARE(BGRC);
519
520	/***************************************************************************/
521	#ifdef BCHP_M2MC_OUTPUT_CM_C34
522	#define BGRC_P_REG_COUNT (((BCHP_M2MC_OUTPUT_CM_C34 - BCHP_M2MC_SCRATCH_LIST) >> 2) + 1)
523	#else
524	#define BGRC_P_REG_COUNT (((BCHP_M2MC_SRC_CM_C34 - BCHP_M2MC_SCRATCH_LIST) >> 2) + 1)
525	#endif
526
527	#define BGRC_P_GROUP_COUNT 15
528	#define BGRC_P_HEADER_COUNT 2
529	#define BGRC_P_USERDATA_COUNT 3
530
531	#define BGRC_P_OPERATION_MIN 128
532	#define BGRC_P_OPERATION_MAX 256
533
534	#define BGRC_P_LIST_BLOCK_ALIGN 5
535	#define BGRC_P_LIST_BLOCK_SIZE 2048
536	#define BGRC_P_LIST_BLOCK_MIN_SIZE 16384
537
538	/***************************************************************************/
539	#if defined(BCHP_M2MC_SRC_SURFACE_1_FORMAT_DEF_1)
540	#define BGRC_P_LIST_SRC_FEEDER_GRP_CNTRL_COUNT 13
541	#define BGRC_P_LIST_BLIT_GRP_CNTRL_COUNT 17
542	#define BGRC_P_LIST_SCALE_PARAM_GRP_CNTRL_COUNT 13
543	#else
544	#define BGRC_P_LIST_SRC_FEEDER_GRP_CNTRL_COUNT 10
545	#define BGRC_P_LIST_BLIT_GRP_CNTRL_COUNT 11
546	#define BGRC_P_LIST_SCALE_PARAM_GRP_CNTRL_COUNT 9
547	#endif
548
549	#define BGRC_P_LIST_DST_FEEDER_GRP_CNTRL_COUNT 10
550	#define BGRC_P_LIST_OUTPUT_FEEDER_GRP_CNTRL_COUNT 8
551	#define BGRC_P_LIST_BLEND_PARAM_GRP_CNTRL_COUNT 4
552	#define BGRC_P_LIST_ROP_GRP_CNTRL_COUNT 5
553	#define BGRC_P_LIST_SRC_COLOR_KEY_GRP_CNTRL_COUNT 5
554	#define BGRC_P_LIST_DST_COLOR_KEY_GRP_CNTRL_COUNT 5
555
556	#if defined(BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_67)
557	#define BGRC_P_LIST_SCALE_COEF_GRP_CNTRL_COUNT 64
558	#else
559	#define BGRC_P_LIST_SCALE_COEF_GRP_CNTRL_COUNT 16
560	#endif
561
562	#define BGRC_P_LIST_SRC_COLOR_MATRIX_GRP_CNTRL_COUNT 12
563	#define BGRC_P_LIST_DST_COLOR_MATRIX_GRP_CNTRL_COUNT 12
564	#define BGRC_P_LIST_OUTPUT_COLOR_MATRIX_GRP_CNTRL_COUNT 12
565	#define BGRC_P_LIST_SRC_CLUT_GRP_CNTRL_COUNT 1
566	#define BGRC_P_LIST_DST_CLUT_GRP_CNTRL_COUNT 1
567
568	#define BGRC_P_MACROBLOCK_RANGE_NONE 8
569	#define BGRC_P_MACROBLOCK_RANGE_REMAPPING 9
570	#define BGRC_P_MACROBLOCK_RANGE_EXPANSION 16
571
572	/***************************************************************************/
573	typedef struct
574	{
575	uint32_t ulX;
576	uint32_t ulY;
577	uint32_t ulWidth;
578	uint32_t ulHeight;
579	}
580	BGRC_P_Rect;
581
582	/***************************************************************************/
583	typedef struct BGRC_P_Block BGRC_P_Block;
584	struct BGRC_P_Block
585	{
586	BGRC_P_Block pNextBlock; / pointer to next block */
587	void pvMemory; / pointer to device memory */
588	void pvCached; / pointer to cached device memory */
589	uint32_t ulOffset; /* device memory offset */
590	uint32_t ulRefCount;
591	bool bBusy; /* indicates if block is busy */
592	};
593
594	/***************************************************************************/
595	typedef struct BGRC_P_Operation BGRC_P_Operation;
596	struct BGRC_P_Operation
597	{
598	BGRC_P_Operation *pPrevOp;
599	BGRC_P_Operation *pNextOp;
600	BGRC_P_Block *pBlock;
601	BGRC_Callback pUserCallback;
602	void *pUserData;
603	uint32_t ulPacketOffset;
604	uint32_t ulPacketSize;
605	bool bSetEvent;
606	bool bSetPeriodicEvent;
607	bool bActive;
608	};
609
610	/***************************************************************************/
611	typedef struct
612	{
613	BSUR_Surface_Handle hSurface;
614	BPXL_Format eFormat;
615	void *pMemory;
616	uint32_t ulOffset;
617	uint32_t ulPitch;
618	uint32_t ulPaletteOffset;
619	uint32_t ulPaletteEntries;
620	uint32_t ulSurfaceWidth;
621	uint32_t ulSurfaceHeight;
622	uint32_t ulX;
623	uint32_t ulY;
624	uint32_t ulWidth;
625	uint32_t ulHeight;
626	uint32_t ulID;
627	}
628	BGRC_P_Surface;
629
630	/***************************************************************************/
631	typedef struct
632	{
633	BGRC_P_Surface SrcSurface; /* source surface structure */
634	BGRC_P_Surface DstSurface; /* destination surface structure */
635	BGRC_P_Surface OutSurface; /* output surface structure */
636	BGRC_P_Surface SrcAlphaSurface; /* source alpha surface structure */
637	BGRC_P_Surface DstAlphaSurface; /* destination alpha surface structure */
638	BGRC_P_Surface OutAlphaSurface; /* output alpha surface structure */
639	BGRC_P_Rect SrcRect; /* source rectangle */
640	BGRC_P_Rect DstRect; /* destination rectangle */
641	BGRC_P_Rect OutRect; /* output rectangle */
642	BGRC_FilterCoeffs eHorzCoeffs; /* horizontal scaler coefficient */
643	BGRC_FilterCoeffs eVertCoeffs; /* vertical scaler coefficient */
644	const uint32_t pulHorzFirCoeffs; / pointer to horz fir coefficients */
645	const uint32_t pulVertFirCoeffs; / pointer to vert fir coefficients */
646	uint32_t ulHorzScalerStep; /* horizontal scaler step */
647	uint32_t ulVertScalerStep; /* vertical scaler step */
648	uint32_t ulHorzInitPhase; /* horizontal initial phase */
649	uint32_t ulVertInitPhase; /* vertical initial phase */
650	uint32_t ulHorzScalerNum; /* horizontal scale factor numerator */
651	uint32_t ulHorzScalerDen; /* horizontal scale factor denominator */
652	uint32_t ulVertScalerNum; /* vertical scale factor numerator */
653	uint32_t ulVertScalerDen; /* vertical scale factor denominator */
654	uint32_t ulHorzAveragerCount; /* horizontal averager count */
655	uint32_t ulVertAveragerCount; /* vertical averager count */
656	uint32_t ulHorzAveragerCoeff; /* horizontal averager coefficient */
657	uint32_t ulVertAveragerCoeff; /* vertical averager coefficient */
658	uint32_t ulSrcStripWidth; /* src strip width for scaling*/
659	uint32_t ulOutStripWidth; /* out strip width for scaling */
660	uint32_t ulOverlapStrip; /* overlap strip for scaling */
661	uint32_t ulPhaseShift; /* Phase shift value */
662	int32_t iHorzPhaseAdj; /* horizontal initial phase ajustment */
663	int32_t iVertPhaseAdj; /* vertical initial phase ajustment */
664	uint8_t aucPattern[8]; /* 8x8 bit ROP pattern */
665	bool bHorzFilter; /* enables horizontal filter */
666	bool bVertFilter; /* enables vertical filter */
667	bool bSrcPaletteBypass; /* enables bypassing src palette */
668	bool bDstPaletteBypass; /* enables bypassing dst palette */
669	bool bSrcRightToLeft;
670	bool bSrcBottomToTop;
671	bool bDstRightToLeft;
672	bool bDstBottomToTop;
673	bool bOutRightToLeft;
674	bool bOutBottomToTop;
675	uint32_t ulMacroBlockRangeY;
676	uint32_t ulMacroBlockRangeC;
677	uint32_t ulMacroBlockStripWidth;
678	bool bMacroBlockLinear;
679	bool bMacroBlockBigEndian;
680	}
681	BGRC_P_State;
682
683	/***************************************************************************/
684	BDBG_OBJECT_ID_DECLARE(BGRC);
685	typedef struct BGRC_P_Handle
686	{
687	BDBG_OBJECT(BGRC)
688	BCHP_Handle hChip; /* handle to chip module */
689	BREG_Handle hRegister; /* handle to register module */
690	BMEM_Handle hMemory; /* handle to memory module */
691	BINT_Handle hInterrupt; /* handle to interrupt module */
692	BINT_CallbackHandle hInterruptCallback; /* handle to interrupt callback */
693	BKNI_EventHandle hInterruptEvent; /* handle to interrupt event */
694	BKNI_EventHandle hPeriodicEvent; /* handle to periodic event */
695	uint32_t aulCurrentRegs[BGRC_P_REG_COUNT]; /* array of current m2mc registers */
696	uint32_t aulDefaultRegs[BGRC_P_REG_COUNT]; /* array of default m2mc registers */
697	uint32_t aulActualRegs[BGRC_P_REG_COUNT]; /* array of actual m2mc registers */
698	uint32_t aulStoredRegs[BGRC_P_REG_COUNT]; /* array of stored m2mc registers */
699	BGRC_P_State CurrentState; /* current state information */
700	BGRC_P_State DefaultState; /* default state information */
701	BGRC_P_State StoredState; /* stored state information */
702	uint32_t ulSurfaceID; /* current surface id */
703	uint32_t ulPeriodicInterrupts; /* count of pending periodic interrupts */
704	bool bNoScaleFilter; /* indicates filtering without scaling */
705	bool bYCbCr420Source; /* source is YCbCr420 */
706	bool bUninitialized; /* indicates if module is inited */
707	bool bSetEvent; /* indicates if isr should set event */
708	bool bPeriodicInterrupt; /* indicates if interrupt should be fired */
709
710	BGRC_P_Block pCurrListBlock; / pointer to current list memory block */
711	BGRC_P_Block pPrevListBlock; / pointer to current list memory block */
712	uint32_t ulListBlockPos; /* position within current list memory block */
713	BGRC_Callback pPrevUserCallback; /* pointer to previous user interrupt callback */
714	uint32_t pulPrevPacket; / pointer to previous list packet */
715	uint32_t ulPacketMemorySize; /* amount of memory allocated for packets */
716	uint32_t ulOperationCount; /* count allocated operations */
717	uint32_t ulPacketMemoryMax; /* max packet memory */
718	uint32_t ulOperationMax; /* max operations */
719	uint32_t ulIntExpected; /* number of interrupts expected */
720	uint32_t ulIntReceived; /* number of interrupts received */
721	uint32_t ulDeviceNum; /* number of M2MC device being used */
722	uint32_t ulWaitTimeout; /* seconds to wait before assuming device is hung */
723	uint32_t ulPacketMemorySinceInterrupt; /* packet memory allocated since periodic interrupt */
724	bool bPreAllocMemory; /* allocate memory when opening module */
725
726	BGRC_P_Operation *pCurrOp;
727	BGRC_P_Operation *pLastOp;
728	BGRC_P_Operation *pFreeOp;
729
730	BSUR_Surface_Handle hWaitSurface;
731	BGRC_Callback pPeriodicCallback;
732	void *pPeriodicData;
733
734	/* packets */
735	BGRC_PacketContext_Handle hContext;
736	BINT_CallbackHandle hCallback;
737	BGRC_Callback callback_isr;
738	void *callback_data;
739
740	BLST_D_HEAD(context_list, BGRC_P_PacketContext) context_list;
741
742	uint32_t *fifo_memory_addr;
743	uint32_t *fifo_cached_addr;
744	uint32_t *fifo_base_addr;
745	uint32_t fifo_base_offset;
746	uint32_t fifo_total_size;
747
748	uint32_t *prev_fifo_addr;
749	uint32_t *curr_fifo_addr;
750	uint32_t curr_fifo_offset;
751	uint32_t *last_fifo_addr;
752	uint32_t last_fifo_offset;
753
754	uint32_t *start_flush_addr;
755	uint32_t *end_flush_addr;
756
757	bool advance_interrupt;
758	bool advance_hung;
759	bool sync_hung;
760	}
761	BGRC_P_Handle;
762
763	/***************************************************************************/
764	#define BCHP_M2MC_LIST_PACKET_HEADER_1 BCHP_M2MC_SCRATCH_LIST
765
766	/***************************************************************************/
767	#ifdef BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1
768	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1 BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1
769	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_FORMAT_TYPE_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_FORMAT_TYPE_MASK
770	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_FORMAT_TYPE_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_FORMAT_TYPE_SHIFT
771	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH0_NUM_BITS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH0_NUM_BITS_MASK
772	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH1_NUM_BITS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH1_NUM_BITS_MASK
773	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH2_NUM_BITS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH2_NUM_BITS_MASK
774	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH3_NUM_BITS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH3_NUM_BITS_MASK
775	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH0_NUM_BITS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH0_NUM_BITS_SHIFT
776	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH1_NUM_BITS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH1_NUM_BITS_SHIFT
777	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH2_NUM_BITS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH2_NUM_BITS_SHIFT
778	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_1_CH3_NUM_BITS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_1_CH3_NUM_BITS_SHIFT
779	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2 BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2
780	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH0_LSB_POS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH0_LSB_POS_MASK
781	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH1_LSB_POS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH1_LSB_POS_MASK
782	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH2_LSB_POS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH2_LSB_POS_MASK
783	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH3_LSB_POS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH3_LSB_POS_MASK
784	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH0_LSB_POS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH0_LSB_POS_SHIFT
785	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH1_LSB_POS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH1_LSB_POS_SHIFT
786	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH2_LSB_POS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH2_LSB_POS_SHIFT
787	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_2_CH3_LSB_POS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_2_CH3_LSB_POS_SHIFT
788	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3 BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3
789	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH0_DISABLE_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH0_DISABLE_MASK
790	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH1_DISABLE_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH1_DISABLE_MASK
791	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH2_DISABLE_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH2_DISABLE_MASK
792	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH3_DISABLE_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH3_DISABLE_MASK
793	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH0_DISABLE_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH0_DISABLE_SHIFT
794	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH1_DISABLE_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH1_DISABLE_SHIFT
795	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH2_DISABLE_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH2_DISABLE_SHIFT
796	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CH3_DISABLE_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CH3_DISABLE_SHIFT
797	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_PALETTE_BYPASS_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_PALETTE_BYPASS_MASK
798	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_PALETTE_BYPASS_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_PALETTE_BYPASS_SHIFT
799	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_PALETTE_BYPASS_DONT_LOOKUP BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_PALETTE_BYPASS_DONT_LOOKUP
800	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_PALETTE_BYPASS_LOOKUP BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_PALETTE_BYPASS_LOOKUP
801	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CHROMA_FILTER_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CHROMA_FILTER_MASK
802	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CHROMA_FILTER_REPLICATE BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CHROMA_FILTER_REPLICATE
803	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CHROMA_FILTER_FILTER BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CHROMA_FILTER_FILTER
804	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_CHROMA_FILTER_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_CHROMA_FILTER_SHIFT
805	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_ZERO_PAD_MASK BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_ZERO_PAD_MASK
806	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_ZERO_PAD_ZERO_PAD BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_ZERO_PAD_ZERO_PAD
807	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_ZERO_PAD_REPLICATE BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_ZERO_PAD_REPLICATE
808	#define BCHP_M2MC_SRC_SURFACE_FORMAT_DEF_3_ZERO_PAD_SHIFT BCHP_M2MC_SRC_SURFACE_0_FORMAT_DEF_3_ZERO_PAD_SHIFT
809	#define BCHP_M2MC_BLIT_SRC_TOP_LEFT BCHP_M2MC_BLIT_SRC_TOP_LEFT_0
810	#define BCHP_M2MC_BLIT_SRC_TOP_LEFT_LEFT_MASK BCHP_M2MC_BLIT_SRC_TOP_LEFT_0_LEFT_MASK
811	#define BCHP_M2MC_BLIT_SRC_TOP_LEFT_LEFT_SHIFT BCHP_M2MC_BLIT_SRC_TOP_LEFT_0_LEFT_SHIFT
812	#define BCHP_M2MC_BLIT_SRC_TOP_LEFT_TOP_MASK BCHP_M2MC_BLIT_SRC_TOP_LEFT_0_TOP_MASK
813	#define BCHP_M2MC_BLIT_SRC_TOP_LEFT_TOP_SHIFT BCHP_M2MC_BLIT_SRC_TOP_LEFT_0_TOP_SHIFT
814	#define BCHP_M2MC_BLIT_SRC_SIZE BCHP_M2MC_BLIT_SRC_SIZE_0
815	#define BCHP_M2MC_BLIT_SRC_SIZE_SURFACE_WIDTH_MASK BCHP_M2MC_BLIT_SRC_SIZE_0_SURFACE_WIDTH_MASK
816	#define BCHP_M2MC_BLIT_SRC_SIZE_SURFACE_WIDTH_SHIFT BCHP_M2MC_BLIT_SRC_SIZE_0_SURFACE_WIDTH_SHIFT
817	#define BCHP_M2MC_BLIT_SRC_SIZE_SURFACE_HEIGHT_MASK BCHP_M2MC_BLIT_SRC_SIZE_0_SURFACE_HEIGHT_MASK
818	#define BCHP_M2MC_BLIT_SRC_SIZE_SURFACE_HEIGHT_SHIFT BCHP_M2MC_BLIT_SRC_SIZE_0_SURFACE_HEIGHT_SHIFT
819	#define BCHP_M2MC_BLIT_INPUT_STRIPE_WIDTH BCHP_M2MC_BLIT_INPUT_STRIPE_WIDTH_0
820	#define BCHP_M2MC_BLIT_INPUT_STRIPE_WIDTH_STRIPE_WIDTH_MASK BCHP_M2MC_BLIT_INPUT_STRIPE_WIDTH_0_STRIPE_WIDTH_MASK
821	#define BCHP_M2MC_BLIT_INPUT_STRIPE_WIDTH_STRIPE_WIDTH_SHIFT BCHP_M2MC_BLIT_INPUT_STRIPE_WIDTH_0_STRIPE_WIDTH_SHIFT
822	#define BCHP_M2MC_BLIT_STRIPE_OVERLAP BCHP_M2MC_BLIT_STRIPE_OVERLAP_0
823	#define BCHP_M2MC_BLIT_STRIPE_OVERLAP_STRIPE_WIDTH_MASK BCHP_M2MC_BLIT_STRIPE_OVERLAP_0_STRIPE_WIDTH_MASK
824	#define BCHP_M2MC_BLIT_STRIPE_OVERLAP_STRIPE_WIDTH_SHIFT BCHP_M2MC_BLIT_STRIPE_OVERLAP_0_STRIPE_WIDTH_SHIFT
825	#define BCHP_M2MC_HORIZ_SCALER_INITIAL_PHASE BCHP_M2MC_HORIZ_SCALER_0_INITIAL_PHASE
826	#define BCHP_M2MC_HORIZ_SCALER_INITIAL_PHASE_PHASE_MASK BCHP_M2MC_HORIZ_SCALER_0_INITIAL_PHASE_PHASE_MASK
827	#define BCHP_M2MC_HORIZ_SCALER_INITIAL_PHASE_PHASE_SHIFT BCHP_M2MC_HORIZ_SCALER_0_INITIAL_PHASE_PHASE_SHIFT
828	#define BCHP_M2MC_HORIZ_SCALER_STEP BCHP_M2MC_HORIZ_SCALER_0_STEP
829	#define BCHP_M2MC_HORIZ_SCALER_STEP_STEP_MASK BCHP_M2MC_HORIZ_SCALER_0_STEP_STEP_MASK
830	#define BCHP_M2MC_HORIZ_SCALER_STEP_STEP_SHIFT BCHP_M2MC_HORIZ_SCALER_0_STEP_STEP_SHIFT
831	#define BCHP_M2MC_VERT_SCALER_INITIAL_PHASE BCHP_M2MC_VERT_SCALER_0_INITIAL_PHASE
832	#define BCHP_M2MC_VERT_SCALER_INITIAL_PHASE_PHASE_MASK BCHP_M2MC_VERT_SCALER_0_INITIAL_PHASE_PHASE_MASK
833	#define BCHP_M2MC_VERT_SCALER_INITIAL_PHASE_PHASE_SHIFT BCHP_M2MC_VERT_SCALER_0_INITIAL_PHASE_PHASE_SHIFT
834	#define BCHP_M2MC_VERT_SCALER_STEP BCHP_M2MC_VERT_SCALER_0_STEP
835	#define BCHP_M2MC_VERT_SCALER_STEP_STEP_MASK BCHP_M2MC_VERT_SCALER_0_STEP_STEP_MASK
836	#define BCHP_M2MC_VERT_SCALER_STEP_STEP_SHIFT BCHP_M2MC_VERT_SCALER_0_STEP_STEP_SHIFT
837	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_01_COEFF_0_MASK BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE0_01_COEFF_0_MASK
838	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_01_COEFF_1_MASK BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE0_01_COEFF_1_MASK
839	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_2_COEFF_2_MASK BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE0_2_COEFF_2_MASK
840	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE1_01_COEFF_0_MASK BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE1_01_COEFF_0_MASK
841	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE1_01_COEFF_1_MASK BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE1_01_COEFF_1_MASK
842	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE1_2_COEFF_2_MASK BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE1_2_COEFF_2_MASK
843	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_01_COEFF_0_SHIFT BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE0_01_COEFF_0_SHIFT
844	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_01_COEFF_1_SHIFT BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE0_01_COEFF_1_SHIFT
845	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_2_COEFF_2_SHIFT BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE0_2_COEFF_2_SHIFT
846	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE1_01_COEFF_0_SHIFT BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE1_01_COEFF_0_SHIFT
847	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE1_01_COEFF_1_SHIFT BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE1_01_COEFF_1_SHIFT
848	#define BCHP_M2MC_HORIZ_FIR_COEFF_PHASE1_2_COEFF_2_SHIFT BCHP_M2MC_HORIZ_FIR_0_COEFF_PHASE1_2_COEFF_2_SHIFT
849
850	#define BCHP_M2MC_1_SRC_SURFACE_FORMAT_DEF_1 BCHP_M2MC_1_SRC_SURFACE_0_FORMAT_DEF_1
851	#define BCHP_M2MC_1_SRC_SURFACE_FORMAT_DEF_2 BCHP_M2MC_1_SRC_SURFACE_0_FORMAT_DEF_2
852	#define BCHP_M2MC_1_SRC_SURFACE_FORMAT_DEF_3 BCHP_M2MC_1_SRC_SURFACE_0_FORMAT_DEF_3
853	#define BCHP_M2MC_1_BLIT_SRC_TOP_LEFT BCHP_M2MC_1_BLIT_SRC_TOP_LEFT_0
854	#define BCHP_M2MC_1_BLIT_SRC_SIZE BCHP_M2MC_1_BLIT_SRC_SIZE_0
855	#define BCHP_M2MC_1_BLIT_INPUT_STRIPE_WIDTH BCHP_M2MC_1_BLIT_INPUT_STRIPE_WIDTH_0
856	#define BCHP_M2MC_1_BLIT_STRIPE_OVERLAP BCHP_M2MC_1_BLIT_STRIPE_OVERLAP_0
857	#define BCHP_M2MC_1_HORIZ_SCALER_INITIAL_PHASE BCHP_M2MC_1_HORIZ_SCALER_0_INITIAL_PHASE
858	#define BCHP_M2MC_1_HORIZ_SCALER_STEP BCHP_M2MC_1_HORIZ_SCALER_0_STEP
859	#define BCHP_M2MC_1_VERT_SCALER_INITIAL_PHASE BCHP_M2MC_1_VERT_SCALER_0_INITIAL_PHASE
860	#define BCHP_M2MC_1_VERT_SCALER_STEP BCHP_M2MC_1_VERT_SCALER_0_STEP
861
862	#define BCHP_M2MC1_SRC_SURFACE_FORMAT_DEF_1 BCHP_M2MC1_SRC_SURFACE_0_FORMAT_DEF_2
863	#define BCHP_M2MC1_SRC_SURFACE_FORMAT_DEF_2 BCHP_M2MC1_SRC_SURFACE_0_FORMAT_DEF_1
864	#define BCHP_M2MC1_SRC_SURFACE_FORMAT_DEF_3 BCHP_M2MC1_SRC_SURFACE_0_FORMAT_DEF_3
865	#define BCHP_M2MC1_BLIT_SRC_TOP_LEFT BCHP_M2MC1_BLIT_SRC_TOP_LEFT_0
866	#define BCHP_M2MC1_BLIT_SRC_SIZE BCHP_M2MC1_BLIT_SRC_SIZE_0
867	#define BCHP_M2MC1_BLIT_INPUT_STRIPE_WIDTH BCHP_M2MC1_BLIT_INPUT_STRIPE_WIDTH_0
868	#define BCHP_M2MC1_BLIT_STRIPE_OVERLAP BCHP_M2MC1_BLIT_STRIPE_OVERLAP_0
869	#define BCHP_M2MC1_HORIZ_SCALER_INITIAL_PHASE BCHP_M2MC1_HORIZ_SCALER_0_INITIAL_PHASE
870	#define BCHP_M2MC1_HORIZ_SCALER_STEP BCHP_M2MC1_HORIZ_SCALER_0_STEP
871	#define BCHP_M2MC1_VERT_SCALER_INITIAL_PHASE BCHP_M2MC1_VERT_SCALER_0_INITIAL_PHASE
872	#define BCHP_M2MC1_VERT_SCALER_STEP BCHP_M2MC1_VERT_SCALER_0_STEP
873	#endif
874
875	/***************************************************************************/
876	#if defined(BCHP_M2MC_HORIZ_FIR_COEFF_PHASE0_67)
877	#define BGRC_P_FIR_PHASE_COUNT 8
878	#define BGRC_P_FIR_TAP_COUNT 8
879	#define BGRC_P_FIR_FRAC_BITS 10
880	#define BGRC_P_FIR_OVERLAP_MIN 4
881	#else
882	#define BGRC_P_FIR_PHASE_COUNT 2
883	#define BGRC_P_FIR_TAP_COUNT 4
884	#define BGRC_P_FIR_FRAC_BITS 8
885	#define BGRC_P_FIR_OVERLAP_MIN 3
886	#endif
887	#define BGRC_P_FIR_FRAC_SCALE (1 << BGRC_P_FIR_FRAC_BITS)
888
889	#ifdef BCHP_M2MC_HORIZ_SCALER_0_STEP_reserved0_SHIFT
890	#define BGRC_P_SCALER_STEP_FRAC_BITS (BCHP_M2MC_HORIZ_SCALER_0_STEP_reserved0_SHIFT - 4)
891	#else
892	#define BGRC_P_SCALER_STEP_FRAC_BITS (BCHP_M2MC_HORIZ_SCALER_STEP_reserved0_SHIFT - 4)
893	#endif
894
895	#define BGRC_P_SCALER_STEP_FRAC_MASK ((1 << BGRC_P_SCALER_STEP_FRAC_BITS) - 1)
896
897	#define BGRC_P_AVERAGER_COEFF_FRAC_BITS 19
898	#define BGRC_P_AVERAGER_COEFF_FRAC_MASK ((1 << BGRC_P_AVERAGER_COEFF_FRAC_BITS) - 1)
899
900	#if (BCHP_CHIP==7630)
901	#define BGRC_P_STRIP_WIDTH_MAX 120
902	#else
903	#define BGRC_P_STRIP_WIDTH_MAX 128
904	#endif
905
906	#define BGRC_P_MATRIX_FRAC_BITS 10
907
908	#define BGRC_P_SCALE_DOWN_MAX 15
909	#define BGRC_P_SCALE_DOWN_MAX_Y 7
910
911	#if (BCHP_M2MC_SRC_CM_C04_CM_C04_MASK & 0xF000)
912	#define BGRC_P_MATRIX_ADD_FRAC_BITS 4
913	#else
914	#define BGRC_P_MATRIX_ADD_FRAC_BITS 0
915	#endif
916
917	#define BGRC_P_YCbCr420_STRIP_WIDTH 64
918
919	#define BGRC_P_SCALER_STEP_TO_STRIPE_WIDTH_SHIFT (BGRC_P_SCALER_STEP_FRAC_BITS - 16)
920
921	/***************************************************************************/
922	#define BGRC_P_MIN( v0, v1 ) (((v0) < (v1)) ? (v0) : (v1))
923	#define BGRC_P_MAX( v0, v1 ) (((v0) > (v1)) ? (v0) : (v1))
924	#define BGRC_P_CLAMP( v, mn, mx ) BGRC_P_MIN(BGRC_P_MAX(v, mn), mx)
925
926	/***************************************************************************/
927	#define BGRC_P_REG_INDEX( reg ) ((BCHP_M2MC_##reg - BCHP_M2MC_SCRATCH_LIST) >> 2)
928
929	/***************************************************************************/
930	#define BGRC_P_GET_FIELD_DATA( reg, field ) \
931	((hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] & \
932	(BCHP_M2MC_##reg##_##field##_MASK)) >> \
933	(BCHP_M2MC_##reg##_##field##_SHIFT))
934
935	/***************************************************************************/
936	#define BGRC_P_COMPARE_FIELD( reg, field, flag ) \
937	(((hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] & \
938	(BCHP_M2MC_##reg##_##field##_MASK)) >> \
939	(BCHP_M2MC_##reg##_##field##_SHIFT)) == \
940	(BCHP_M2MC_##reg##_##field##_##flag))
941
942	/***************************************************************************/
943	#define BGRC_P_COMPARE_VALUE( reg, field, value ) \
944	(((hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] & \
945	(BCHP_M2MC_##reg##_##field##_MASK)) >> \
946	(BCHP_M2MC_##reg##_##field##_SHIFT)) == value)
947
948	/***************************************************************************/
949	#define BGRC_P_SET_FIELD_FULL( reg, value ) \
950	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] = ((uint32_t) (value))
951
952	/***************************************************************************/
953	#define BGRC_P_SET_FIELD_DATA( reg, field, value ) \
954	{ \
955	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] &= \
956	(~(BCHP_M2MC_##reg##_##field##_MASK)); \
957	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] \|= \
958	(((uint32_t) (value)) << \
959	(BCHP_M2MC_##reg##_##field##_SHIFT)) & \
960	(BCHP_M2MC_##reg##_##field##_MASK); \
961	}
962
963	/***************************************************************************/
964	#define BGRC_P_SET_FIELD_ENUM( reg, field, flag ) \
965	{ \
966	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] &= \
967	(~(BCHP_M2MC_##reg##_##field##_MASK)); \
968	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] \|= \
969	(BCHP_M2MC_##reg##_##field##_##flag << \
970	(BCHP_M2MC_##reg##_##field##_SHIFT)) & \
971	(BCHP_M2MC_##reg##_##field##_MASK); \
972	}
973
974	/***************************************************************************/
975	#define BGRC_P_SET_FIELD_COMP( reg, field, flag_true, flag_false, comp ) \
976	{ \
977	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] &= \
978	(~(BCHP_M2MC_##reg##_##field##_MASK)); \
979	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] \|= (((comp) ? \
980	(BCHP_M2MC_##reg##_##field##_##flag_true) : \
981	(BCHP_M2MC_##reg##_##field##_##flag_false)) << \
982	(BCHP_M2MC_##reg##_##field##_SHIFT)) & \
983	(BCHP_M2MC_##reg##_##field##_MASK); \
984	}
985
986	/***************************************************************************/
987	#define BGRC_P_SET_FIELD_COMP_DATA( reg, field, data_true, data_false, comp ) \
988	{ \
989	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] &= \
990	(~(BCHP_M2MC_##reg##_##field##_MASK)); \
991	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] \|= (((comp) ? \
992	(data_true) : (data_false)) << \
993	(BCHP_M2MC_##reg##_##field##_SHIFT)) & \
994	(BCHP_M2MC_##reg##_##field##_MASK); \
995	}
996
997	/***************************************************************************/
998	#define BGRC_P_LOAD_LIST_GRP( reg, field, flag, pState, pulRegs ) \
999	{ \
1000	if( ((pulRegs)[BGRC_P_REG_INDEX(reg)] & BCHP_M2MC_##reg##_##field##_MASK) == 0 ) \
1001	{ \
1002	(pulRegs)[BGRC_P_REG_INDEX(reg)] &= \
1003	(~(BCHP_M2MC_##reg##_##field##_MASK)); \
1004	(pulRegs)[BGRC_P_REG_INDEX(reg)] \|= \
1005	(BCHP_M2MC_##reg##_##field##_##flag << \
1006	(BCHP_M2MC_##reg##_##field##_SHIFT)) & \
1007	(BCHP_M2MC_##reg##_##field##_MASK); \
1008	} \
1009	}
1010
1011	/***************************************************************************/
1012	#define BGRC_P_SET_FIELD_FORMAT( reg, field, format, alpha, bypass ) \
1013	{ \
1014	if( BPXL_IS_YCbCr444_10BIT_FORMAT(format) ) \
1015	{ \
1016	/* YCbCr444 10-bit */ \
1017	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 8 ); \
1018	} \
1019	else if( BPXL_IS_YCbCr420_FORMAT(format) ) \
1020	{ \
1021	/* YCbCr420 */ \
1022	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, pState->bMacroBlockBigEndian ? 0 : 7 ); \
1023	} \
1024	else if( BPXL_IS_YCbCr422_10BIT_FORMAT(format) ) \
1025	{ \
1026	/* YCbCr422 10-bit */ \
1027	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 6 ); \
1028	} \
1029	else if( BPXL_IS_ALPHA_ONLY_FORMAT(format) ) \
1030	{ \
1031	/* ALPHA */ \
1032	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 5 ); \
1033	} \
1034	else if( BPXL_IS_YCbCr422_FORMAT(format) ) \
1035	{ \
1036	/* YCbCr422 */ \
1037	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 4 ); \
1038	} \
1039	else if( (!(bypass)) && BPXL_IS_PALETTE_FORMAT(format) ) \
1040	{ \
1041	/* PALETTE */ \
1042	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 3 ); \
1043	} \
1044	else if( (alpha) && \
1045	(BPXL_COMPONENT_SIZE(format, 3) == 0) && \
1046	(BPXL_COMPONENT_SIZE(format, 2) == 5) && \
1047	(BPXL_COMPONENT_SIZE(format, 1) == 6) && \
1048	(BPXL_COMPONENT_SIZE(format, 0) == 5) ) \
1049	{ \
1050	/* WRGB_1565 */ \
1051	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 2 ); \
1052	} \
1053	else if( BPXL_IS_WINDOW_FORMAT(format) \|\| ( \
1054	(BPXL_COMPONENT_SIZE(format, 3) == 1) && \
1055	(BPXL_COMPONENT_SIZE(format, 2) == 5) && \
1056	(BPXL_COMPONENT_SIZE(format, 1) == 5) && \
1057	(BPXL_COMPONENT_SIZE(format, 0) == 5)) ) \
1058	{ \
1059	/* WRGB_1555 */ \
1060	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 1 ); \
1061	} \
1062	else \
1063	{ \
1064	/* OTHER */ \
1065	BGRC_P_SET_FIELD_DATA( reg##_SURFACE_FORMAT_DEF_1, field, 0 ); \
1066	} \
1067	}
1068
1069	/***************************************************************************/
1070	#define BGRC_P_SET_FIELD_CHANNELS( reg, format, surface ) \
1071	{ \
1072	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_1)] &= ~( \
1073	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH0_NUM_BITS_MASK \| \
1074	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH1_NUM_BITS_MASK \| \
1075	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH2_NUM_BITS_MASK \| \
1076	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH3_NUM_BITS_MASK); \
1077	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_2)] &= ~( \
1078	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH0_LSB_POS_MASK \| \
1079	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH1_LSB_POS_MASK \| \
1080	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH2_LSB_POS_MASK \| \
1081	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH3_LSB_POS_MASK); \
1082	if( surface ) \
1083	{ \
1084	if( BPXL_IS_YCbCr444_10BIT_FORMAT(format) ) \
1085	{ \
1086	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_1)] \|= \
1087	(BPXL_COMPONENT_SIZE(format, 0) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH0_NUM_BITS_SHIFT) \| \
1088	(BPXL_COMPONENT_SIZE(format, 1) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH1_NUM_BITS_SHIFT) \| \
1089	(BPXL_COMPONENT_SIZE(format, 2) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH2_NUM_BITS_SHIFT); \
1090	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_2)] \|= \
1091	(BPXL_COMPONENT_POS(format, 0) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH0_LSB_POS_SHIFT) \| \
1092	(BPXL_COMPONENT_POS(format, 1) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH1_LSB_POS_SHIFT) \| \
1093	(BPXL_COMPONENT_POS(format, 2) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH2_LSB_POS_SHIFT); \
1094	} \
1095	else \
1096	{ \
1097	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_1)] \|= \
1098	(BPXL_COMPONENT_SIZE(format, 0) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH0_NUM_BITS_SHIFT) \| \
1099	(BPXL_COMPONENT_SIZE(format, 1) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH1_NUM_BITS_SHIFT) \| \
1100	(BPXL_COMPONENT_SIZE(format, 2) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH2_NUM_BITS_SHIFT) \| \
1101	(BPXL_COMPONENT_SIZE(format, 3) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_1_CH3_NUM_BITS_SHIFT); \
1102	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_2)] \|= \
1103	(BPXL_COMPONENT_POS(format, 0) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH0_LSB_POS_SHIFT) \| \
1104	(BPXL_COMPONENT_POS(format, 1) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH1_LSB_POS_SHIFT) \| \
1105	(BPXL_COMPONENT_POS(format, 2) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH2_LSB_POS_SHIFT) \| \
1106	(BPXL_COMPONENT_POS(format, 3) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_2_CH3_LSB_POS_SHIFT); \
1107	} \
1108	} \
1109	}
1110
1111	#define BGRC_P_SET_FIELD_CHANNEL_DISABLE( reg, format, surface ) \
1112	{ \
1113	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_3)] &= ~( \
1114	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH0_DISABLE_MASK \| \
1115	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH1_DISABLE_MASK \| \
1116	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH2_DISABLE_MASK \| \
1117	BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH3_DISABLE_MASK); \
1118	if( surface ) \
1119	{ \
1120	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_3)] \|= \
1121	((BPXL_HAS_MASKED_ALPHA(format) ? 1 : 0) << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH3_DISABLE_SHIFT); \
1122	} \
1123	else \
1124	{ \
1125	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_SURFACE_FORMAT_DEF_3)] \|= \
1126	(1 << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH0_DISABLE_SHIFT) \| \
1127	(1 << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH1_DISABLE_SHIFT) \| \
1128	(1 << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH2_DISABLE_SHIFT) \| \
1129	(1 << BCHP_M2MC_##reg##_SURFACE_FORMAT_DEF_3_CH3_DISABLE_SHIFT); \
1130	} \
1131	}
1132
1133	/***************************************************************************/
1134	#define BGRC_P_GET_FIELD_MATRIX_ENTRY( entry, left, right ) \
1135	(((((entry) * (((entry) < 0) ? -1 : 1)) << (left)) >> (right)) * (((entry) < 0) ? -1 : 1))
1136
1137	/***************************************************************************/
1138	#define BGRC_P_SET_FIELD_MATRIX_ROW( reg, row, matrix, index, shift ) \
1139	{ \
1140	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_CM_C##row##0_C##row##1)] = \
1141	BCHP_FIELD_DATA(M2MC_##reg##_CM_C##row##0_C##row##1, CM_C##row##0, \
1142	BGRC_P_GET_FIELD_MATRIX_ENTRY( (matrix)[(index) + 0], BGRC_P_MATRIX_FRAC_BITS, shift ) & \
1143	BCHP_MASK(M2MC_##reg##_CM_C##row##0_C##row##1, CM_C##row##1)) \| \
1144	BCHP_FIELD_DATA(M2MC_##reg##_CM_C##row##0_C##row##1, CM_C##row##1, \
1145	BGRC_P_GET_FIELD_MATRIX_ENTRY( (matrix)[(index) + 1], BGRC_P_MATRIX_FRAC_BITS, shift ) & \
1146	BCHP_MASK(M2MC_##reg##_CM_C##row##0_C##row##1, CM_C##row##1)); \
1147	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_CM_C##row##2_C##row##3)] = \
1148	BCHP_FIELD_DATA(M2MC_##reg##_CM_C##row##2_C##row##3, CM_C##row##2, \
1149	BGRC_P_GET_FIELD_MATRIX_ENTRY( (matrix)[(index) + 2], BGRC_P_MATRIX_FRAC_BITS, shift ) & \
1150	BCHP_MASK(M2MC_##reg##_CM_C##row##2_C##row##3, CM_C##row##3)) \| \
1151	BCHP_FIELD_DATA(M2MC_##reg##_CM_C##row##2_C##row##3, CM_C##row##3, \
1152	BGRC_P_GET_FIELD_MATRIX_ENTRY( (matrix)[(index) + 3], BGRC_P_MATRIX_FRAC_BITS, shift ) & \
1153	BCHP_MASK(M2MC_##reg##_CM_C##row##2_C##row##3, CM_C##row##3)); \
1154	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg##_CM_C##row##4)] = \
1155	BCHP_FIELD_DATA(M2MC_##reg##_CM_C##row##4, CM_C##row##4, \
1156	BGRC_P_GET_FIELD_MATRIX_ENTRY( (matrix)[(index) + 4], BGRC_P_MATRIX_ADD_FRAC_BITS, shift ) & \
1157	BCHP_MASK(M2MC_##reg##_CM_C##row##4, CM_C##row##4)); \
1158	}
1159
1160	/***************************************************************************/
1161	#define BGRC_P_SET_FIELD_BLEND( reg, srca, srcb, srcc, srcd, srce, subcd, sube ) \
1162	{ \
1163	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(BLEND_##reg##_OP)] = \
1164	(BGRC_P_GetBlendOp( srca ) << BCHP_M2MC_BLEND_##reg##_OP_OP_A_SHIFT) \| \
1165	(BGRC_P_GetBlendOp( srcb ) << BCHP_M2MC_BLEND_##reg##_OP_OP_B_SHIFT) \| \
1166	(BGRC_P_GetBlendOp( srcc ) << BCHP_M2MC_BLEND_##reg##_OP_OP_C_SHIFT) \| \
1167	(BGRC_P_GetBlendOp( srcd ) << BCHP_M2MC_BLEND_##reg##_OP_OP_D_SHIFT) \| \
1168	(BGRC_P_GetBlendOp( srce ) << BCHP_M2MC_BLEND_##reg##_OP_OP_E_SHIFT) \| \
1169	(BGRC_P_GetBlendOpInv( srca ) << BCHP_M2MC_BLEND_##reg##_OP_OP_A_INV_SHIFT) \| \
1170	(BGRC_P_GetBlendOpInv( srcb ) << BCHP_M2MC_BLEND_##reg##_OP_OP_B_INV_SHIFT) \| \
1171	(BGRC_P_GetBlendOpInv( srcc ) << BCHP_M2MC_BLEND_##reg##_OP_OP_C_INV_SHIFT) \| \
1172	(BGRC_P_GetBlendOpInv( srcd ) << BCHP_M2MC_BLEND_##reg##_OP_OP_D_INV_SHIFT) \| \
1173	(BGRC_P_GetBlendOpInv( srce ) << BCHP_M2MC_BLEND_##reg##_OP_OP_E_INV_SHIFT) \| \
1174	(((subcd) ? 1 : 0) << BCHP_M2MC_BLEND_##reg##_OP_SUBTRACT_CD_SHIFT) \| \
1175	(((sube) ? 1 : 0) << BCHP_M2MC_BLEND_##reg##_OP_SUBTRACT_E_SHIFT); \
1176	}
1177
1178	/***************************************************************************/
1179	#define BGRC_P_SET_FIELD_COLORKEY( nsnd, nsd, snd, sd ) \
1180	{ \
1181	hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(BLEND_COLOR_KEY_ACTION)] = \
1182	((nsnd) << BCHP_M2MC_BLEND_COLOR_KEY_ACTION_ACTION_NOT_SRC_NOT_DEST_SHIFT) \| \
1183	((nsd) << BCHP_M2MC_BLEND_COLOR_KEY_ACTION_ACTION_NOT_SRC_DEST_SHIFT) \| \
1184	((snd) << BCHP_M2MC_BLEND_COLOR_KEY_ACTION_ACTION_SRC_NOT_DEST_SHIFT) \| \
1185	((sd) << BCHP_M2MC_BLEND_COLOR_KEY_ACTION_ACTION_SRC_DEST_SHIFT); \
1186	}
1187
1188	/***************************************************************************/
1189	#define BGRC_P_SET_FIELD_DIRECTION( surf0, surf1, surf2, dir, coord, fore, back ) \
1190	{ \
1191	if( BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_TOP_LEFT, coord ) < \
1192	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_TOP_LEFT, coord ) ) \
1193	{ \
1194	BGRC_P_SET_FIELD_ENUM( BLIT_CTRL, surf0##_##dir##_DIRECTION, back ); \
1195	BGRC_P_SET_FIELD_ENUM( BLIT_CTRL, surf1##_##dir##_DIRECTION, back ); \
1196	BGRC_P_SET_FIELD_COMP( BLIT_CTRL, surf2##_##dir##_DIRECTION, back, fore, \
1197	BGRC_P_COMPARE_FIELD( surf2##_FEEDER_ENABLE, ENABLE, ENABLE ) ); \
1198	} \
1199	else \
1200	{ \
1201	BGRC_P_SET_FIELD_ENUM( BLIT_CTRL, surf0##_##dir##_DIRECTION, fore ); \
1202	BGRC_P_SET_FIELD_ENUM( BLIT_CTRL, surf1##_##dir##_DIRECTION, fore ); \
1203	BGRC_P_SET_FIELD_ENUM( BLIT_CTRL, surf2##_##dir##_DIRECTION, fore ); \
1204	} \
1205	}
1206
1207	/***************************************************************************/
1208	#define BGRC_P_SURFACE_INTERSECT( surf0, surf1 ) (( \
1209	BGRC_P_GET_FIELD_DATA( surf0##_SURFACE_ADDR_0, ADDR ) == \
1210	BGRC_P_GET_FIELD_DATA( surf1##_SURFACE_ADDR_0, ADDR )) && (!((( \
1211	BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_TOP_LEFT, LEFT ) + \
1212	BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_SIZE, SURFACE_WIDTH )) < \
1213	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_TOP_LEFT, LEFT )) \|\| ( \
1214	BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_TOP_LEFT, LEFT ) > ( \
1215	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_TOP_LEFT, LEFT ) + \
1216	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_SIZE, SURFACE_WIDTH ))) \|\| (( \
1217	BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_TOP_LEFT, TOP ) + \
1218	BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_SIZE, SURFACE_HEIGHT )) < \
1219	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_TOP_LEFT, TOP )) \|\| ( \
1220	BGRC_P_GET_FIELD_DATA( BLIT_##surf0##_TOP_LEFT, TOP ) > ( \
1221	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_TOP_LEFT, TOP ) + \
1222	BGRC_P_GET_FIELD_DATA( BLIT_##surf1##_SIZE, SURFACE_HEIGHT ))))))
1223
1224	/***************************************************************************/
1225	#define BGRC_P_COPY_FIELD( pState, dst, src, type, reg, field ) \
1226	{ \
1227	if( ((dst)[BGRC_P_REG_INDEX(reg)] & (BCHP_M2MC_##reg##_##field##_MASK)) != \
1228	((src)[BGRC_P_REG_INDEX(reg)] & (BCHP_M2MC_##reg##_##field##_MASK)) ) \
1229	{ \
1230	(dst)[BGRC_P_REG_INDEX(reg)] &= \
1231	(~(BCHP_M2MC_##reg##_##field##_MASK)); \
1232	(dst)[BGRC_P_REG_INDEX(reg)] \|= (src)[BGRC_P_REG_INDEX(reg)] & \
1233	(BCHP_M2MC_##reg##_##field##_MASK); \
1234	BGRC_P_LOAD_LIST_GRP( LIST_PACKET_HEADER_1, type, GRP_ENABLE, pState, dst ); \
1235	} \
1236	}
1237
1238	/***************************************************************************/
1239	#define BGRC_P_COPY_REGISTER( pState, dst, src, type, reg ) \
1240	{ \
1241	if( (dst)[BGRC_P_REG_INDEX(reg)] != (src)[BGRC_P_REG_INDEX(reg)]) \
1242	{ \
1243	(dst)[BGRC_P_REG_INDEX(reg)] = (src)[BGRC_P_REG_INDEX(reg)]; \
1244	BGRC_P_LOAD_LIST_GRP( LIST_PACKET_HEADER_1, type, GRP_ENABLE, pState, dst ); \
1245	} \
1246	}
1247
1248	/***************************************************************************/
1249	#define BGRC_P_REGISTER_CHANGED( reg ) \
1250	(hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)] != hGrc->aulActualRegs[BGRC_P_REG_INDEX(reg)])
1251
1252	/***************************************************************************/
1253	#if ((BCHP_CHIP==7400) && (BCHP_VER == BCHP_VER_A0)) \|\| \
1254	((BCHP_CHIP==7438) && (BCHP_VER >= BCHP_VER_A0)) \|\| \
1255	((BCHP_CHIP==7440) && (BCHP_VER >= BCHP_VER_A0))
1256	#define BGRC_P_READ_REG( reg ) \
1257	(uint32_t) BREG_Read32( hGrc->hRegister, (hGrc->ulDeviceNum ? BCHP_M2MC_1_##reg : BCHP_M2MC_##reg) )
1258	#define BGRC_P_WRITE_REG( reg, val ) \
1259	BREG_Write32( hGrc->hRegister, (hGrc->ulDeviceNum ? BCHP_M2MC_1_##reg : BCHP_M2MC_##reg), (val) )
1260	#elif (BCHP_CHIP==7435)
1261	#define BGRC_P_READ_REG( reg ) \
1262	(uint32_t) BREG_Read32( hGrc->hRegister, (hGrc->ulDeviceNum ? BCHP_M2MC1_##reg : BCHP_M2MC_##reg) )
1263	#define BGRC_P_WRITE_REG( reg, val ) \
1264	BREG_Write32( hGrc->hRegister, (hGrc->ulDeviceNum ? BCHP_M2MC1_##reg : BCHP_M2MC_##reg), (val) )
1265	#else
1266	#define BGRC_P_READ_REG( reg ) \
1267	(uint32_t) BREG_Read32( hGrc->hRegister, BCHP_M2MC_##reg )
1268	#define BGRC_P_WRITE_REG( reg, val ) \
1269	BREG_Write32( hGrc->hRegister, BCHP_M2MC_##reg, (val) )
1270	#endif
1271
1272	/***************************************************************************/
1273	#define BGRC_P_SET_REGISTER( reg ) \
1274	{ \
1275	hGrc->aulActualRegs[BGRC_P_REG_INDEX(reg)] = hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)]; \
1276	*pulPacket++ = hGrc->aulCurrentRegs[BGRC_P_REG_INDEX(reg)]; \
1277	}
1278
1279	/***************************************************************************/
1280	#define BGRC_P_SET_REGISTERS( group, reg ) \
1281	{ \
1282	uint32_t ulIndex = BGRC_P_REG_INDEX(reg); \
1283	uint32_t *pulActualRegs = &hGrc->aulActualRegs[ulIndex]; \
1284	uint32_t *pulCurrentRegs = &hGrc->aulCurrentRegs[ulIndex]; \
1285	uint32_t ii; \
1286	for( ii = 0; ii < BGRC_P_LIST_##group##_GRP_CNTRL_COUNT; ++ii ) \
1287	{ \
1288	pulActualRegs++ = pulCurrentRegs; \
1289	pulPacket++ = pulCurrentRegs++; \
1290	} \
1291	}
1292
1293	/***************************************************************************/
1294	#define BGRC_P_SET_PALETTE_ENTRY( reg, num, value ) \
1295	pOp->aulPaletteEntries[(num)] = (value)
1296
1297	/***************************************************************************/
1298	#define BGRC_P_SET_PALETTE( reg, surface, count ) \
1299	{ \
1300	BSUR_Palette_Handle hPalette; \
1301	uint32_t *pulEntries; \
1302	uint32_t ii; \
1303	\
1304	BSUR_Surface_GetPalette( (surface), &hPalette ); \
1305	if( hPalette ) \
1306	{ \
1307	BSUR_Palette_GetAddress( hPalette, (void *) (&pulEntries) ); \
1308	if( pulEntries ) \
1309	{ \
1310	for( ii = 0; ii < (count); ++ii ) \
1311	BGRC_P_SET_PALETTE_ENTRY( reg, ii, pulEntries[ii] ); \
1312	} \
1313	} \
1314	}
1315
1316	/***************************************************************************/
1317	#define BGRC_P_VALIDATE_SURFACE_DIMENSIONS( x, y, width, height ) ( \
1318	(!(((x) \|\| (y)) && (((width) == 0) \|\| ((height) == 0)))) && \
1319	(((int32_t) (x) >= 0) && ((int32_t) (y) >= 0)) )
1320
1321	/***************************************************************************/
1322	#define BGRC_P_VALIDATE_SURFACE_RECTANGLE( rect ) \
1323	BGRC_P_VALIDATE_SURFACE_DIMENSIONS( (rect)->ulX, (rect)->ulY, (rect)->ulWidth, (rect)->ulHeight )
1324
1325	/***************************************************************************/
1326	#define BGRC_P_VALIDATE_SURFACE_BOUNDS( state, sur ) \
1327	(!((state)->sur##Surface.hSurface && ( \
1328	(((state)->sur##Surface.ulX + (state)->sur##Surface.ulWidth) > (state)->sur##Surface.ulSurfaceWidth) \|\| \
1329	(((state)->sur##Surface.ulY + (state)->sur##Surface.ulHeight) > (state)->sur##Surface.ulSurfaceHeight))))
1330
1331	/***************************************************************************/
1332	#define BGRC_P_GET_SURFACE_DATA( newsurface, newdata, olddata ) \
1333	{ \
1334	BSUR_Palette_Handle hPalette = 0; \
1335	BPXL_Format eFormat = 0; \
1336	uint32_t ulPaletteOffset = 0; \
1337	uint32_t ulSurfaceID = 0; \
1338	if( (newsurface) ) \
1339	{ \
1340	if( BSUR_Surface_GetID( (newsurface), &ulSurfaceID ) != BERR_SUCCESS ) \
1341	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1342	if( ulSurfaceID == 0 ) \
1343	{ \
1344	ulSurfaceID = ++hGrc->ulSurfaceID; \
1345	if( BSUR_Surface_SetID( (newsurface), ulSurfaceID ) != BERR_SUCCESS ) \
1346	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1347	} \
1348	if( BSUR_Surface_GetFormat( (newsurface), &eFormat ) != BERR_SUCCESS ) \
1349	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1350	if( BPXL_IS_PALETTE_FORMAT( eFormat ) ) \
1351	{ \
1352	if( BSUR_Surface_GetPalette( (newsurface), &hPalette ) != BERR_SUCCESS ) \
1353	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1354	if( BSUR_Palette_GetOffset( hPalette, &ulPaletteOffset ) != BERR_SUCCESS ) \
1355	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1356	} \
1357	} \
1358	if( hGrc->bUninitialized \|\| ((newsurface) != (olddata).hSurface) \|\| \
1359	(ulSurfaceID != (olddata).ulID) \|\| (ulPaletteOffset != (olddata).ulPaletteOffset) ) \
1360	{ \
1361	bSurfaceChanged = true; \
1362	BKNI_Memset( &(newdata), 0, sizeof (BGRC_P_Surface) ); \
1363	if( (newsurface) ) \
1364	{ \
1365	(newdata).ulID = ulSurfaceID; \
1366	(newdata).hSurface = (newsurface); \
1367	(newdata).eFormat = eFormat; \
1368	if( BSUR_Surface_GetAddress( (newsurface), &((newdata).pMemory), &((newdata).ulPitch) ) != BERR_SUCCESS ) \
1369	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1370	if( BSUR_Surface_GetDimensions( (newsurface), &((newdata).ulSurfaceWidth), &((newdata).ulSurfaceHeight) ) != BERR_SUCCESS ) \
1371	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1372	if( BSUR_Surface_GetOffset( (newsurface), &((newdata).ulOffset) ) != BERR_SUCCESS ) \
1373	return BERR_TRACE(BERR_INVALID_PARAMETER); \
1374	if( BPXL_IS_PALETTE_FORMAT((newdata).eFormat) ) \
1375	{ \
1376	(newdata).ulPaletteOffset = ulPaletteOffset; \
1377	(newdata).ulPaletteEntries = (uint32_t) BPXL_NUM_PALETTE_ENTRIES((newdata).eFormat); \
1378	} \
1379	} \
1380	} \
1381	}
1382
1383	/***************************************************************************/
1384	#define BGRC_P_SET_SURFACE_DIMENSIONS( reg, surface, xx, yy, width, height ) \
1385	{ \
1386	if( (surface) ) \
1387	{ \
1388	uint32_t ulWidth = (width); \
1389	uint32_t ulHeight = (height); \
1390	uint32_t ulTemp; \
1391	if( (ulWidth == 0) \|\| (ulHeight == 0) ) \
1392	BSUR_Surface_GetDimensions( (surface), \
1393	(ulWidth == 0) ? (&ulWidth) : (&ulTemp), \
1394	(ulHeight == 0) ? (&ulHeight) : (&ulTemp) ); \
1395	BGRC_P_SET_FIELD_DATA( BLIT_##reg##_TOP_LEFT, LEFT, (xx) ); \
1396	BGRC_P_SET_FIELD_DATA( BLIT_##reg##_TOP_LEFT, TOP, (yy) ); \
1397	BGRC_P_SET_FIELD_DATA( BLIT_##reg##_SIZE, SURFACE_WIDTH, ulWidth ); \
1398	BGRC_P_SET_FIELD_DATA( BLIT_##reg##_SIZE, SURFACE_HEIGHT, ulHeight ); \
1399	if( BGRC_P_REGISTER_CHANGED( BLIT_##reg##_SIZE ) \|\| \
1400	BGRC_P_REGISTER_CHANGED( BLIT_##reg##_TOP_LEFT ) ) \
1401	BGRC_P_SET_FIELD_ENUM( LIST_PACKET_HEADER_1, BLIT_GRP_CNTRL, GRP_ENABLE ); \
1402	} \
1403	}
1404
1405	/***************************************************************************/
1406	#define BGRC_P_ALIGN_PATTERN( pout, pin, xx, yy ) \
1407	{ \
1408	uint32_t ii; \
1409	for( ii = 0; ii < 8; ++ii ) \
1410	((uint8_t ) (pout))[ii] = ((uint8_t ) (pin))[(ii + (yy)) & 7]; \
1411	for( ii = 0; ii < 8; ++ii ) \
1412	((uint8_t ) (pout))[ii] = (uint8_t) ((((uint8_t ) (pout))[ii] >> (8 - ((xx) & 7))) \| \
1413	(((uint8_t *) (pout))[ii] << ((xx) & 7))); \
1414	}
1415
1416	/***************************************************************************/
1417	#define BGRC_P_WRITE_REGISTER( reg ) \
1418	BREG_Write32( hGrc->hRegister, BCHP_M2MC_##reg, pOp->aulRegs[BGRC_P_REG_INDEX(reg)] )
1419
1420	#define BGRC_P_WRITE_REGISTER_COEFF( reg, num ) \
1421	BREG_Write32( hGrc->hRegister, BCHP_M2MC_##reg##_FIR_COEFF_PHASE0_01 + (num) * 4, \
1422	pOp->aulRegs[BGRC_P_REG_INDEX(reg##_FIR_COEFF_PHASE0_01) + (num)] );
1423
1424	#define BGRC_P_WRITE_REGISTER_ENTRY( reg, num ) \
1425	BREG_Write32( hGrc->hRegister, BCHP_M2MC_##reg##_CLUT_ENTRY_i_ARRAY_BASE + (num) * 4, \
1426	pOp->aulPaletteEntries[(num)] );
1427
1428	/****************************************************************************/
1429	uint32_t BGRC_P_GetBlendOp( BGRC_Blend_Source eSource );
1430	uint32_t BGRC_P_GetBlendOpInv( BGRC_Blend_Source eSource );
1431
1432	BERR_Code BGRC_P_Blit( BGRC_Handle hGrc, BGRC_Callback pCallback, void *pData, bool bSetEvent );
1433	BERR_Code BGRC_P_FilterBlit( BGRC_Handle hGrc, BGRC_Callback pCallback, void *pData, bool bSetEvent );
1434
1435	void BGRC_P_Source_CopyState( BGRC_P_State pDstState, BGRC_P_State pSrcState, uint32_t aulDstRegs[], uint32_t aulSrcRegs[] );
1436	void BGRC_P_Destination_CopyState( BGRC_P_State pDstState, BGRC_P_State pSrcState, uint32_t aulDstRegs[], uint32_t aulSrcRegs[] );
1437	void BGRC_P_Pattern_CopyState( BGRC_P_State pDstState, BGRC_P_State pSrcState, uint32_t aulDstRegs[], uint32_t aulSrcRegs[] );
1438	void BGRC_P_Blend_CopyState( BGRC_P_State pDstState, BGRC_P_State pSrcState, uint32_t aulDstRegs[], uint32_t aulSrcRegs[] );
1439	void BGRC_P_Output_CopyState( BGRC_P_State pDstState, BGRC_P_State pSrcState, uint32_t aulDstRegs[], uint32_t aulSrcRegs[] );
1440	void BGRC_P_PrintRegisters( BGRC_Handle hGrc );
1441
1442	bool BGRC_P_List_InitPacketMemory( BGRC_Handle hGrc, uint32_t ulMemorySize );
1443	void BGRC_P_List_FreePacketMemory( BGRC_Handle hGrc );
1444	void BGRC_P_List_CleanupPacketMemory( BGRC_Handle hGrc );
1445	void BGRC_P_List_PacketIsr( void *pvParam1, int iParam2 );
1446
1447	void BGRC_P_Operation_FreeAll( BGRC_Handle hGrc );
1448	void BGRC_P_Operation_CleanupList( BGRC_Handle hGrc );
1449	bool BGRC_P_Operation_Prealloc( BGRC_Handle hGrc, uint32_t ulCount );
1450
1451	#ifdef __cplusplus
1452	}
1453	#endif
1454
1455	#endif /* #ifndef BGRC_PRIVATE_H__ */
1456
1457	/* end of file */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/grc/7552/bgrc_private.h

Download in other formats: