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bkir.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bkir.c $
11	* $brcm_Revision: Hydra_Software_Devel/115 $
12	* $brcm_Date: 2/21/12 6:34p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/kir/7405/bkir.c $
19	*
20	* Hydra_Software_Devel/115 2/21/12 6:34p jkim
21	* SW7425-2283: Add API to enable/disable filter1
22	*
23	* Hydra_Software_Devel/114 11/21/11 6:20p mward
24	* SW7435-7: Add 7435.
25	*
26	* Hydra_Software_Devel/113 10/14/11 4:28p jkim
27	* SW7231-370: Add simultaneout spport for 32/48 bit for NEC
28	*
29	* Hydra_Software_Devel/112 9/20/11 2:11p jkim
30	* SW7429-10: Add 7429 support
31	*
32	* Hydra_Software_Devel/111 9/20/11 1:59p jkim
33	* SWBLURAY-27433: Add Toshiba IR support
34	*
35	* Hydra_Software_Devel/110 9/20/11 1:34p jkim
36	* SWBLURAY-27433: Add Toshiba IR support
37	*
38	* Hydra_Software_Devel/109 4/29/11 6:13p jkim
39	* SW7405-5300: Add variable length RCMM support. It was tested with 32bit
40	* RCMM and 24bit RCMM data.
41	*
42	* Hydra_Software_Devel/108 2/8/11 3:18p jkim
43	* SW7340-248: 1. Remove redundant code to clear interrupt status bit in
44	* BKIR_ReadIsr(). It is already cleared in BKIR_P_HandleInterrupt_Isr()
45	* . 2. Guard a call to BKIR_Read_Isr() in BKIR_Read() by calling
46	* BKNI_EnterCriticalSection().
47	*
48	* Hydra_Software_Devel/107 1/26/11 2:26p etrudeau
49	* SWBLURAY-23692: add 7640 support
50	*
51	* Hydra_Software_Devel/106 12/27/10 2:19p xhuang
52	* SW7358-29: Add 7358/7552 support
53	*
54	* Hydra_Software_Devel/105 12/7/10 6:13p jrubio
55	* SW7344-9: add 7344/7346 support
56	*
57	* Hydra_Software_Devel/104 12/2/10 10:31a katrep
58	* SW7231-4:add support for 7231
59	*
60	* Hydra_Software_Devel/103 11/2/10 5:04p hongtaoz
61	* SW7425-9: added 7425 support;
62	*
63	* Hydra_Software_Devel/102 10/13/10 2:53p jkim
64	* SW7630-98: Add support for RCA remote
65	*
66	* Hydra_Software_Devel/101 10/7/10 4:53p nickh
67	* SW7422-74: Add 7422 support
68	*
69	* Hydra_Software_Devel/100 7/23/10 10:45a jkim
70	* SW7550-471: use BKIR_HAS_DATA_FILTER instead of BCHP_CHIP
71	*
72	* Hydra_Software_Devel/99 6/25/10 11:28a jkim
73	* SW7550-471:Add support for pattern matching and 48 bit data
74	*
75	* Hydra_Software_Devel/98 3/3/10 5:39p jkim
76	* HW7420-766: modified CIR parameters to use a new variable length IR
77	* decoder from a leading edge to a leading edge.
78	*
79	* Hydra_Software_Devel/97 12/13/09 6:41p rpereira
80	* SW7550-41: Fixed compilation issues for 7550
81	*
82	* Hydra_Software_Devel/95 11/6/09 4:18p gmohile
83	* SW7408-1 : Add 7408 support
84	*
85	* Hydra_Software_Devel/94 9/15/09 10:33a rpereira
86	* SW7630-45: Adding support for 7630
87	*
88	* Hydra_Software_Devel/93 9/4/09 12:46p jkim
89	* SW7405-340: fine tune r-step parameters based on the spec.
90	*
91	* Hydra_Software_Devel/92 9/2/09 2:51p jkim
92	* SW7325-524: fixed a bug where CIR parameters were only partially
93	* written to CIR register.
94	*
95	* Hydra_Software_Devel/91 9/1/09 9:21p rpereira
96	* SW7550-30: Adding 7550 support
97	*
98	* Hydra_Software_Devel/90 8/24/09 1:49p jkim
99	* SW7405-340: Add RC6 Mode 0 support
100	*
101	* Hydra_Software_Devel/89 8/20/09 4:23p mward
102	* PR55545: Support 7125.
103	*
104	* Hydra_Software_Devel/88 8/10/09 4:41p jrubio
105	* PR55232: add 7340/7342 support
106	*
107	* Hydra_Software_Devel/87 8/3/09 6:42p jkim
108	* PR56525: check if preamble A or B is used.
109	*
110	* Hydra_Software_Devel/86 8/3/09 10:53a jkim
111	* PR56525: Fix it per Cisco's request
112	*
113	* Hydra_Software_Devel/85 7/27/09 7:06p jkim
114	* PR56525: add a function to set custom device type
115	*
116	* Hydra_Software_Devel/84 7/22/09 3:12p jkim
117	* PR37963: Add functions to check preamble status
118	*
119	* Hydra_Software_Devel/83 7/14/09 6:09p jkim
120	* PR56525: Add API to get default cir paramters so that it can be
121	* modified and copied to cutom cir
122	*
123	* Hydra_Software_Devel/82 4/17/09 11:18a agin
124	* PR54338: Moved BKIR_N_CHANNELS to bkir.h because other files need this.
125	*
126	* Hydra_Software_Devel/81 4/10/09 5:29p jkim
127	* PR37963: modify rstep parameters according to the spec
128	*
129	* Hydra_Software_Devel/80 4/9/09 5:23p rpereira
130	* PR52971: adding 7635 support
131	*
132	* Hydra_Software_Devel/79 4/9/09 4:27p jkim
133	* PR53968: use DEBUG_MSG instead of DEBUG_WRN
134	*
135	* Hydra_Software_Devel/78 4/8/09 10:01a jkim
136	* PR53968: update using the changes made by Gorden Chen, which was
137	* tested on Samsung HR24.
138	*
139	* Hydra_Software_Devel/77 4/6/09 1:59p jkim
140	* PR38349: modify RCMM parameters basedon the latest spec
141	*
142	* Hydra_Software_Devel/76 3/12/09 6:01p jkim
143	* PR37963: create a duplicate XMP-2 CIR parameters used for RCU without
144	* supporting ACK. This way is needed for better performance since we do
145	* not have to support XMP-2 data and ACK at the same time.
146	*
147	* Hydra_Software_Devel/75 3/6/09 1:09p jkim
148	* PR52510: remove a global variable
149	*
150	* Hydra_Software_Devel/74 2/17/09 8:28p jkim
151	* PR37963: modified xmp-2 parameters to support a new spec using a single
152	* cir parameters
153	*
154	* Hydra_Software_Devel/73 2/9/09 8:45p jkim
155	* PR37963: Add XIR parameter for XMP-2 ACK/NAK
156	*
157	* Hydra_Software_Devel/72 1/31/09 1:10a jrubio
158	* PR51629: add 7336 support
159	*
160	* Hydra_Software_Devel/71 12/2/08 4:44p kaushikb
161	* PR49867: Adding support for 7420
162	*
163	* Hydra_Software_Devel/71 12/2/08 4:42p kaushikb
164	* PR49867: Adding support for 7420
165	*
166	* Hydra_Software_Devel/70 9/22/08 4:16p jkim
167	* PR37963: add xmp-2 cir param
168	*
169	* Hydra_Software_Devel/69 8/21/08 9:00a fbasso
170	* PR 44541: added support for 7601.
171	*
172	* Hydra_Software_Devel/68 7/28/08 1:42p jkim
173	* PR45065: add R-step remote support
174	*
175	* Hydra_Software_Devel/67 6/27/08 1:47p brianlee
176	* PR44259: Need to program CIR registers 23, 25, 26, 27 for all remote
177	* types.
178	*
179	* Hydra_Software_Devel/66 4/4/08 2:21p farshidf
180	* PR39191: add 3548/3556 support
181	*
182	* Hydra_Software_Devel/65 4/3/08 2:11p brianlee
183	* PR23894: Initialize user callback pointer to NULL when opening and
184	* closing a channel.
185	*
186	* Hydra_Software_Devel/64 4/1/08 4:19p brianlee
187	* PR23894: Added functions to register user callback with KIR PI.
188	*
189	* Hydra_Software_Devel/63 3/27/08 1:09p jkim
190	* PR37963: Add one byte xmp-2 support
191	*
192	* Hydra_Software_Devel/62 2/21/08 4:31p brianlee
193	* PR18303: Fixed the bkir read function for 7325.
194	*
195	* Hydra_Software_Devel/61 1/4/08 12:49p erickson
196	* PR38536: check for hChnCallback before destroying it
197	*
198	* Hydra_Software_Devel/60 11/28/07 10:16a farshidf
199	* PR36888:Add 7335 support
200	*
201	* Hydra_Software_Devel/59 11/27/07 6:16p farshidf
202	* PR36888: Add support for 7335
203	*
204	* Hydra_Software_Devel/58 10/14/07 3:53p jkim
205	* PR14344: add 7325 support
206	*
207	* Hydra_Software_Devel/57 10/13/07 11:35a jkim
208	* PR14344: Add 7325 support and modify RCMM parameters
209	*
210	* Hydra_Software_Devel/56 5/21/07 4:05p jkim
211	* PR30841: Add 7405 support
212	*
213	* Hydra_Software_Devel/55 5/2/07 5:39p jkim
214	* PR30225: use preamble B as repeat flag
215	*
216	* Hydra_Software_Devel/54 4/23/07 2:48p jkim
217	* PR14344: Modify nec paramters per request by Mahesh Danke and add 7440
218	* support when needed
219	*
220	* Hydra_Software_Devel/53 4/12/07 10:33a jkim
221	* PR14344: Fix compiler warning
222	*
223	* Hydra_Software_Devel/52 4/9/07 4:51p jkim
224	* PR28061: Add RCMM support
225	*
226	* Hydra_Software_Devel/51 2/28/07 11:01a jkim
227	* PR14344: Remove unnecessary printf()
228	*
229	* Hydra_Software_Devel/50 2/16/07 11:35a jkim
230	* PR14344: Added 7440 support
231	*
232	* Hydra_Software_Devel/49 2/2/07 11:22a jkim
233	* PR27238: Modify to use the correct IRQ definition
234	*
235	* Hydra_Software_Devel/48 1/12/07 4:21p jkim
236	* PR14344: Add 3563 support
237	*
238	* Hydra_Software_Devel/47 12/1/06 4:07p jkim
239	* PR26238: Remove compiler warning
240	*
241	* Hydra_Software_Devel/46 11/28/06 11:40a jkim
242	* PR25664: Added RC6 remote support. Simultaneous support for two remote
243	* should be working but can not be tested using broadcom reference
244	* board.
245	*
246	* Hydra_Software_Devel/45 11/9/06 11:19a jkim
247	* PR14344: Added 7403 support
248	*
249	* Hydra_Software_Devel/44 9/26/06 11:12a agin
250	* PR24562: Support 4th IR receiver for 7400.
251	*
252	* Hydra_Software_Devel/43 9/19/06 5:20p agin
253	* PR24339: Resolve compiler warning for DEBUG=n builds for UPG modules.
254	*
255	* Hydra_Software_Devel/42 8/9/06 11:04a agin
256	* PR23362: Add 3563 support.
257	*
258	* Hydra_Software_Devel/41 7/18/06 2:47p jkim
259	* PR14344: fixed the problem related to legacy mode Echostar UHF where
260	* unwanted interrupt is happening.
261	*
262	* Hydra_Software_Devel/40 6/15/06 5:14p mward
263	* PR21681: Add support for 7118 chip 97118.
264	*
265	* Hydra_Software_Devel/39 3/21/06 3:04p jkim
266	* PR20326: Add support for 7438
267	*
268	* Hydra_Software_Devel/38 2/1/06 11:49a rjlewis
269	* PR19044: endian issue when storing by longs.
270	*
271	* Hydra_Software_Devel/37 1/15/06 9:13a agin
272	* PR19076: Support BCM7400.
273	*
274	* Hydra_Software_Devel/36 12/22/05 10:44a agin
275	* PR18787: Update I2C, KIR with C3 defines using new version method.
276	*
277	* Hydra_Software_Devel/35 11/14/05 1:33p jkim
278	* PR16923: change the value of "min dead time after fault" to 30 per
279	* Linda Lau's request
280	*
281	* Hydra_Software_Devel/34 10/21/05 2:09p jkim
282	* PR14344:write 0x0000007F for UHF remote
283	*
284	* Hydra_Software_Devel/33 10/11/05 2:57p jkim
285	* PR16923: Add legacy support for directtv uhf
286	*
287	* Hydra_Software_Devel/32 9/30/05 3:26p jkim
288	* PR14344: Add UHF legacy support
289	*
290	* Hydra_Software_Devel/30 8/23/05 5:27p jkim
291	* PR14344: adding 7401 support
292	*
293	* Hydra_Software_Devel/29 5/18/05 12:43a agin
294	* PR14720: B2, C1, C2 compilation support.
295	*
296	* Hydra_Software_Devel/28 5/10/05 2:59p brianlee
297	* PR15254: Fixed a warning.
298	*
299	* Hydra_Software_Devel/27 5/10/05 9:26a brianlee
300	* PR15254: Increase tolerance on data bit periods for RF UEI remote.
301	* This is needed to make LIST and down arrow keys work.
302	*
303	* Hydra_Software_Devel/26 5/6/05 3:43p brianlee
304	* PR14284: Fixed problem where RF UEI mode does not turn off other
305	* protocols correctly.
306	*
307	* Hydra_Software_Devel/24 4/7/05 10:49a agin
308	* PR14698: unused parameters.
309	*
310	* Hydra_Software_Devel/23 4/4/05 3:14p agin
311	* PR14558: Removed printf in the ISR.
312	*
313	* Hydra_Software_Devel/22 4/4/05 2:40p agin
314	* PR14558: Add pointer to array for BKIR_Read function.
315	*
316	* Hydra_Software_Devel/21 3/28/05 8:34p vinwang
317	* PR14240: Fix Ir1_in not enable because auto select does not work for
318	* 93560 board.
319	*
320	* Hydra_Software_Devel/20 3/21/05 10:28p vsilyaev
321	* PR 14413: Added BERR_TRACE's
322	*
323	* Hydra_Software_Devel/19 3/17/05 4:12p vsilyaev
324	* PR 14413: Added support for 3560.
325	*
326	* Hydra_Software_Devel/18 3/3/05 11:48a brianlee
327	* PR14284: Fixed compile error.
328	*
329	* Hydra_Software_Devel/17 3/3/05 10:54a brianlee
330	* PR14284: Disable SEJIN and TWIRP for RF UEI.
331	*
332	* Hydra_Software_Devel/16 2/28/05 2:27p brianlee
333	* PR14284: Add support for UEI RF remote.
334	*
335	* Hydra_Software_Devel/15 12/10/04 11:52a brianlee
336	* PR13515: Changed UEI remote spacing tolerance to improve response.
337	*
338	* Hydra_Software_Devel/14 6/1/04 11:13a brianlee
339	* PR11291: Added code to support KIR3.
340	*
341	* Hydra_Software_Devel/13 5/26/04 8:45a dlwin
342	* PR 11189: Merging to Main Branch
343	*
344	* Hydra_Software_Devel/Refsw_Devel_7038_B0/3 5/25/04 3:14p brianlee
345	* PR11209: Update RC5 remote to handle both field values.
346	*
347	* Hydra_Software_Devel/Refsw_Devel_7038_B0/2 5/5/04 2:11p brianlee
348	* PR10969: Make static structures constant.
349	*
350	* Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/28/04 2:33p brianlee
351	* PR10857: Version for B0.
352	*
353	* Hydra_Software_Devel/12 3/26/04 4:32p brianlee
354	* PR8971: Remove BDBG_ASSERT() for malloc failure.
355	*
356	* Hydra_Software_Devel/11 3/4/04 5:36p brianlee
357	* PR9958: Added BKIR_KirDevice_eCirCustom type and the function
358	* BKIR_SetCustomCir() to allow user to set custom KIR settings.
359	*
360	* Hydra_Software_Devel/10 12/29/03 3:59p marcusk
361	* PR9117: Updated with changes required to support interrupt ids rather
362	* than strings.
363	*
364	* Hydra_Software_Devel/9 11/4/03 6:52p brianlee
365	* Get rid of enter/leave macros.
366	*
367	* Hydra_Software_Devel/8 10/17/03 10:42a brianlee
368	* 1.) Added a function to check for repeat key.
369	* 2.) Fixed CIR write function.
370	*
371	* Hydra_Software_Devel/7 10/2/03 10:40a brianlee
372	* Fixed BKIR_Read so that it outputs interrupt device type, not IR device
373	* type.
374	*
375	* Hydra_Software_Devel/6 9/24/03 11:58a brianlee
376	* Changed the names of header files.
377	*
378	* Hydra_Software_Devel/5 9/23/03 10:37a brianlee
379	* Added support for Sony variable length packet detection.
380	*
381	* Hydra_Software_Devel/4 9/19/03 1:45p brianlee
382	* Fixed warnings from Midas build.
383	*
384	* Hydra_Software_Devel/3 9/16/03 6:31p brianlee
385	* Writing to IRQ0_IRQEN register does not require coreoffset.
386	*
387	* Hydra_Software_Devel/2 9/16/03 10:41a brianlee
388	* Fixed coreoffset calculation.
389	*
390	* Hydra_Software_Devel/1 9/15/03 10:29a brianlee
391	* Initial version.
392	*
393	***************************************************************************/
394	#include "bstd.h"
395	#include "bkir.h"
396	#include "bkir_priv.h"
397	#include "bchp_kbd1.h"
398	#if BKIR_N_CHANNELS > 1
399	#include "bchp_kbd2.h"
400	#if BKIR_N_CHANNELS > 2
401	#include "bchp_kbd3.h"
402	#if BKIR_N_CHANNELS > 3
403	#include "bchp_kbd4.h"
404	#endif
405	#endif
406	#endif
407	#include "bchp_irq0.h"
408	#include "bchp_int_id_irq0.h"
409	#if (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| BCHP_CHIP==7344 \|\| BCHP_CHIP==7346 \|\|\
410	(BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
411	#include "bchp_int_id_irq0_aon.h"
412	#include "bchp_irq0_aon.h"
413	#endif
414
415
416
417	BDBG_MODULE(bkir);
418
419	#define DEV_MAGIC_ID ((BERR_KIR_ID<<16) \| 0xFACE)
420
421	#define BKIR_CHK_RETCODE( rc, func ) \
422	do { \
423	if( (rc = BERR_TRACE(func)) != BERR_SUCCESS ) \
424	{ \
425	goto done; \
426	} \
427	} while(0)
428
429	#define MAX_KIR_CHANNELS BKIR_N_CHANNELS
430
431	#define KBD_CMD_TWIRP_ENABLE 0x01
432	#define KBD_CMD_SEJIN_ENABLE 0x02
433	#define KBD_CMD_REMOTE_A_ENABLE 0x04
434	#define KBD_CMD_REMOTE_B_ENABLE 0x08
435	#define KBD_CMD_CIR_ENABLE 0x10
436
437	#define KBD_STATUS_DEVICE_MASK 0x1c
438	#define KBD_STATUS_DEVICE_SHIFTS 2
439
440	#if (BCHP_CHIP==3563) \|\| (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556)
441	#ifndef BCHP_INT_ID_kbd1_irqen
442	#define BCHP_INT_ID_kbd1_irqen BCHP_INT_ID_kbd1
443	#endif
444	#endif
445
446	#ifndef RCMM_VARIABLE_LENGTH_SUPPORT
447	#define RCMM_VARIABLE_LENGTH_SUPPORT 0
448	#endif
449
450	/*******************************************************************************
451	*
452	* Private Data
453	*
454	*******************************************************************************/
455	static const CIR_Param giParam = {
456	270-1, /* count divisor: divide by 270 for 10us period */
457	{ {900,0}, {450,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
458	{ {900,0}, {225,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
459	2, /* number of entries in pa[] */
460	2, /* number of entries in pb[] */
461	1, /* measure preamble pulse: */
462	/* 0 => even counts specifies cycle period */
463	/* 1 => even counts specifies off pulse period */
464	1, /* if true, pb[] matches a repeat sequence */
465	50, /* pulse tolerance */
466	275, /* T0 */
467	225, /* delta T */
468	0, /* false => fix symbol pulse between edges 0 & 1 */
469	/* true => fix symbol pulse between edges 1 & 2 */
470	0, /* false => measure spacing for complete cycle */
471	/* true => measure spacing between 2 consecutive edges */
472	{50,3}, /* data symbol fix-width pulse period, */
473	/* tolerance = pulse tolerance (above) */
474	{0, 0}, /* spacing tolerance value = not applicable, */
475	/* and select code = 12.5% */
476	16-1, /* no. of symbols for sequence with preamble A */
477	0, /* no. of symbols for sequence with preamble B */
478	1-1, /* no. of data bits per symbol */
479	0, /* most/!least significant symbol received first */
480	0, /* left/!right adjust received data */
481	0, /* bi-phase/!pulse-spacing coded */
482	0, /* two symbols per cycle */
483	0, /* check stop symbol */
484	0, /* variable length data */
485	50-1, /* time-out clock divisor: divide by 50 or .5 ms */
486	200, /* frame time-out = 100 ms */
487	22, /* edge time-out = 11 ms */
488	6, /* minimum dead-time after fault = 3 ms */
489	{0, 0}, /* stop symbol pulse or cycle period */
490	0, /* data symbol timeout */
491	0,
492	0,
493	0,
494	0,
495	0,
496	0,
497	0,
498	0,
499	0,
500	0,
501	0,
502	0,
503	0,
504	0,
505	0,
506	0,
507	0
508	};
509
510
511	static const CIR_Param sa_e2050Param = {
512	100-1, /count divisor: divide by 100 for 3.70us period /
513	{ {910,0}, {890,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
514	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
515	2, /* number of entries in pa[] */
516	0, /* number of entries in pb[] */
517	1, /* measure preamble pulse: */
518	/* 0 => even counts specifies cycle period */
519	/* 1 => even counts specifies off pulse period */
520	0, /* if true, pb[] matches a repeat sequence */
521	227, /* pulse tolerance = 0.841 ms */
522	450, /* T0 = 1.667 ms */
523	450, /* delta T = 1.667 ms */
524	0, /* false => fix symbol pulse between edges 0 & 1 */
525	/* true => fix symbol pulse between edges 1 & 2 */
526	0, /* false => measure spacing for complete cycle */
527	/* true => measure spacing between 2 consecutive edges */
528	{227,3}, /* data symbol fix-width pulse period = 0.841ms, */
529	/* tolerance = pulse tolerance (above) */
530	{0, 0}, /* spacing tolerance value = not applicable, */
531	/* and select code = 12.5% */
532	22-1, /* no. of symbols for sequence with preamble A */
533	0, /* no. of symbols for sequence with preamble B */
534	1-1, /* no. of data bits per symbol */
535	0, /* most/!least significant symbol received first */
536	0, /* left/!right adjust received data */
537	0, /* bi-phase/!pulse-spacing coded */
538	0, /* two symbols per cycle */
539	0, /* check stop symbol */
540	0, /* variable length data */
541	135-1, /* time-out clock divisor: divide by 135 or .5ms */
542	140, /* frame time-out = 70 ms */
543	9, /* edge time-out = 4.5 ms */
544	9, /* minimum dead-time after fault = 4.5 ms */
545	{0, 0}, /* stop symbol pulse or cycle period */
546	0, /* data symbol timeout */
547	0,
548	0,
549	0,
550	0,
551	0,
552	0,
553	0,
554	0,
555	0,
556	0,
557	0,
558	0,
559	0,
560	0,
561	0,
562	0,
563	0
564	};
565
566
567	static const CIR_Param twirpParam = {
568	90-1, /* count divisor: divide by 90 for 3.33us period */
569	{ {84,1}, {0,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
570	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
571	1, /* number of entries in pa[] */
572	0, /* number of entries in pb[] */
573	0, /* measure preamble pulse: */
574	/* 0 => even counts specifies cycle period */
575	/* 1 => even counts specifies off pulse period */
576	0, /* if true, pb[] matches a repeat sequence */
577	84, /* pulse tolerance = 0.280 ms */
578	300, /* T0 = 1.0000 ms */
579	40+(3<<10), /* delta T = 0.1358 ms (40.75t) /
580	1, /* false => fix symbol pulse between edges 0 & 1 */
581	/* true => fix symbol pulse between edges 1 & 2 */
582	0, /* false => measure spacing for complete cycle */
583	/* true => measure spacing between 2 consecutive edges */
584	{84,1}, /* data symbol fix-width pulse period = 0.280, */
585	/* tolerance = 25% */
586	{20, 3}, /* spacing tolerance value = .5 DeltaT, */
587	/* and select code = value */
588	8-1, /* no. of symbols for sequence with preamble A */
589	0, /* no. of symbols for sequence with preamble B */
590	4-1, /* no. of data bits per symbol */
591	1, /* most/!least significant symbol received first */
592	0, /* left/!right adjust received data */
593	0, /* bi-phase/!pulse-spacing coded */
594	0, /* two symbols per cycle */
595	0, /* check stop symbol */
596	1, /* variable length data */
597	150-1, /* time-out clock divisor: divide by 150 or .5ms */
598	52, /* frame time-out = 26 ms */
599	8, /* edge time-out = 4 ms */
600	8, /* minimum dead-time after fault = 4 ms */
601	{0, 0}, /* stop symbol pulse or cycle period */
602	972, /* data symbol timeout */
603	0,
604	0,
605	0,
606	0,
607	0,
608	0,
609	0,
610	0,
611	0,
612	0,
613	0,
614	0,
615	0,
616	0,
617	0,
618	0,
619	0
620	};
621
622
623	static const CIR_Param sonyParam = {
624	72-1, /* count divisor: divide by 72 for 2.66us period */
625	{ {900,0}, {0,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
626	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
627	1, /* number of entries in pa[] */
628	0, /* number of entries in pb[] */
629	0, /* measure preamble pulse: */
630	/* 0 => even counts specifies cycle period */
631	/* 1 => even counts specifies off pulse period */
632	0, /* if true, pb[] matches a repeat sequence */
633	225, /* pulse tolerance = 0.500 ms */
634	450, /* T0 = 1.200 ms */
635	225, /* delta T = 0.600 ms */
636	0, /* false => fix symbol pulse between edges 0 & 1 */
637	/* true => fix symbol pulse between edges 1 & 2 */
638	0, /* false => measure spacing for complete cycle */
639	/* true => measure spacing between 2 consecutive edges */
640	{225,3}, /* data symbol fix-width pulse period = 0.600ms, */
641	/* tolerance = pulse tolerance (above) */
642	{0, 0}, /* spacing tolerance value = not applicable, */
643	/* and select code = 12.5% */
644	12-1, /* no. of symbols for sequence with preamble A */
645	0, /* no. of symbols for sequence with preamble B */
646	1-1, /* no. of data bits per symbol */
647	0, /* most/!least significant symbol received first */
648	0, /* left/!right adjust received data */
649	0, /* bi-phase/!pulse-spacing coded */
650	0, /* two symbols per cycle */
651	0, /* check stop symbol */
652	1, /* variable length data */
653	188-1, /* time-out clock divisor: divide by 188 or .5ms */
654	90, /* frame time-out = 45 ms */
655	7, /* edge time-out = 3.5 ms */
656	3, /* minimum dead-time after fault = 1.5 ms */
657	{0, 0}, /* stop symbol pulse or cycle period */
658	0x308, /* data symbol timeout */
659	0,
660	0,
661	0,
662	0,
663	0,
664	0,
665	0,
666	0,
667	0,
668	0,
669	0,
670	0,
671	0,
672	0,
673	0,
674	0,
675	0
676	};
677
678
679	static const CIR_Param recs80Param = {
680	226-1, /* count divisor: divide by 226 for 8.370 us period */
681	{ {17,2}, {907,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
682	{ {17,2}, {453,0}, {17,2}, {453,0} }, /* pb[], preamble B pulse sequence */
683	2, /* number of entries in pa[] */
684	4, /* number of entries in pb[] */
685	0, /* measure preamble pulse: */
686	/* 0 => even counts specifies cycle period */
687	/* 1 => even counts specifies off pulse period */
688	0, /* if true, pb[] matches a repeat sequence */
689	17, /* pulse tolerance = 0.1432 ms */
690	605, /* T0 = 5.060 ms */
691	302, /* delta T = 2.5279 ms */
692	0, /* false => fix symbol pulse between edges 0 & 1 */
693	/* true => fix symbol pulse between edges 1 & 2 */
694	0, /* false => measure spacing for complete cycle */
695	/* true => measure spacing between 2 consecutive edges */
696	{17,3}, /* data symbol fix-width pulse period = 0.142ms, */
697	/* tolerance = pulse tolerance (above) */
698	{0, 0}, /* spacing tolerance value = not applicable, */
699	/* and select code = 12.5% */
700	10-1, /* no. of symbols for sequence with preamble A */
701	11-1, /* no. of symbols for sequence with preamble B */
702	1-1, /* no. of data bits per symbol */
703	0, /* most/!least significant symbol received first */
704	0, /* left/!right adjust received data */
705	0, /* bi-phase/!pulse-spacing coded */
706	0, /* two symbols per cycle */
707	0, /* check stop symbol */
708	0, /* variable length data */
709	60-1, /* time-out clock divisor: divide by 60 or .5ms */
710	190, /* frame time-out = 95 ms */
711	17, /* edge time-out = 8.5 ms */
712	17, /* minimum dead-time after fault = 8.5 ms */
713	{0, 0}, /* stop symbol pulse or cycle period */
714	0, /* data symbol timeout */
715	0,
716	0,
717	0,
718	0,
719	0,
720	0,
721	0,
722	0,
723	0,
724	0,
725	0,
726	0,
727	0,
728	0,
729	0,
730	0,
731	0
732	};
733
734
735	static const CIR_Param rc5Param = {
736	54-1, /* count divisor: divide by 54 for 2.000 us period */
737	{ {445,1}, {889,1}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
738	{ {889,1}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
739	2, /* number of entries in pa[] */
740	1, /* number of entries in pb[] */
741	0, /* measure preamble pulse: */
742	/* 0 => even counts specifies cycle period */
743	/* 1 => even counts specifies off pulse period */
744	0, /* if true, pb[] matches a repeat sequence */
745	445, /* pulse tolerance = value not used */
746	889, /* bit Period = 1.778 ms (PS T0) */
747	0, /* not used for bi-phase (PS delta T) */
748	0, /* - " - (symbol pulse position) */
749	0, /* - " - (measure spacing for complete cycle) */
750	{0, 0}, /* - " - (data symbol fix-width pulse period) */
751	{0, 0}, /* bit period tolerance value = not applicable, */
752	/* and select code = 12.5% */
753	12-1, /* no. of symbols for sequence with preamble A */
754	12-1, /* no. of symbols for sequence with preamble B */
755	1-1, /* no. of data bits per symbol */
756	1, /* most/!least significant symbol received first */
757	0, /* left/!right adjust received data */
758	1, /* bi-phase/!pulse-spacing coded */
759	0, /* two symbols per cycle */
760	0, /* check stop symbol */
761	0, /* variable length data */
762	250-1, /* time-out clock divisor: divide by 250 or .5ms */
763	56, /* frame time-out = 28 ms */
764	5, /* edge time-out = 2.5 ms */
765	3, /* minimum dead-time after fault = 1.5 ms */
766	{0, 0}, /* stop symbol pulse or cycle period */
767	0, /* data symbol timeout */
768	0,
769	0,
770	0,
771	0,
772	0,
773	0,
774	0,
775	0,
776	0,
777	0,
778	0,
779	0,
780	0,
781	0,
782	0,
783	0,
784	0
785	};
786
787	static const CIR_Param ueiParam = {
788	270-1, /* count divisor */
789	{ {600,0}, {120,3}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
790	{ {300,0}, {120,3}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
791	2, /* number of entries in pa[] */
792	2, /* number of entries in pb[] */
793	1, /* measure preamble pulse: */
794	/* 0 => even counts specifies cycle period */
795	/* 1 => even counts specifies off pulse period */
796	0, /* if true, pb[] matches a repeat sequence */
797	26, /* pulse tolerance = value not used */
798	60, /* T0 */
799	60, /* not used for bi-phase (PS delta T) */
800	0, /* - " - (symbol pulse position) */
801	1, /* - " - (measure spacing for complete cycle) */
802	{60, 1}, /* - " - (data symbol fix-width pulse period) */
803	{12, 3}, /* bit period tolerance value = not applicable, */
804	/* and select code */
805	8-1, /* no. of symbols for sequence with preamble A */
806	8-1, /* no. of symbols for sequence with preamble B */
807	1-1, /* no. of data bits per symbol */
808	1, /* most/!least significant symbol received first */
809	0, /* left/!right adjust received data */
810	0, /* bi-phase/!pulse-spacing coded */
811	1, /* two symbols per cycle */
812	1, /* check stop symbol */
813	0, /* variable length data */
814	50-1, /* time-out clock divisor */
815	74, /* frame time-out */
816	14, /* edge time-out */
817	16, /* minimum dead-time after fault */
818	{900, 0}, /* stop symbol pulse or cycle period */
819	1100, /* data symbol timeout */
820	0,
821	0,
822	0,
823	0,
824	0,
825	0,
826	0,
827	0,
828	0,
829	0,
830	0,
831	0,
832	0,
833	0,
834	0,
835	0,
836	0
837	};
838
839	static const CIR_Param RfueiParam = {
840	270-1, /* count divisor */
841	{ {600,1}, {120,3}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
842	{ {300,1}, {120,3}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
843	2, /* number of entries in pa[] */
844	2, /* number of entries in pb[] */
845	1, /* measure preamble pulse: */
846	/* 0 => even counts specifies cycle period */
847	/* 1 => even counts specifies off pulse period */
848	0, /* if true, pb[] matches a repeat sequence */
849	26, /* pulse tolerance = value not used */
850	60, /* T0 */
851	60, /* delta T */
852	0, /* not used: symbol pulse position */
853	1, /* not used: measure spacing for complete cycle */
854	{60, 0}, /* not used: data symbol fix-width pulse period */
855	{0, 1}, /* bit period tolerance value = not applicable, */
856	/* and select code */
857	20-1, /* no. of symbols for sequence with preamble A */
858	20-1, /* no. of symbols for sequence with preamble B */
859	1-1, /* no. of data bits per symbol */
860	1, /* most/!least significant symbol received first */
861	0, /* left/!right adjust received data */
862	0, /* bi-phase/!pulse-spacing coded */
863	1, /* two symbols per cycle */
864	0, /* check stop symbol */
865	0, /* variable length data */
866	10-1, /* time-out clock divisor */
867	940, /* frame time-out */
868	70, /* edge time-out */
869	16, /* minimum dead-time after fault */
870	{60, 0}, /* stop symbol pulse or cycle period */
871	0, /* data symbol timeout */
872	0,
873	0,
874	0,
875	0,
876	0,
877	0,
878	0,
879	0,
880	0,
881	0,
882	0,
883	0,
884	0,
885	0,
886	0,
887	0,
888	0
889	};
890
891
892	static const CIR_Param echoDishRemoteParam = {
893	/* Symbol time spec. includes 400us ON pulse. */
894	270-1, /* count divisor: divide by 135 for 10us period */
895	{ {40,3}, {658,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
896	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
897	2, /* number of entries in pa[] */
898	0, /* number of entries in pb[] */
899	0, /* measure preamble pulse: */
900	/* 0 => even counts specifies cycle period */
901	/* 1 => even counts specifies off pulse period */
902	0, /* if true, pb[] matches a repeat sequence */
903	40, /* pulse tolerance = 400us */
904	325, /* T0 = 3.25ms */
905	907 \| 1<<10, /* DeltaT = -1.1675ms */
906	0, /* false => fix symbol pulse between edges 0 & 1 */
907	/* true => fix symbol pulse between edges 1 & 2 */
908	0, /* false => measure spacing for complete cycle */
909	/* true => measure spacing between 2 consecutive edges */
910	/* (for stop/IWG symbol) */
911	{40,3}, /* data/stop symbol fix-width pulse period, */
912	/* tolerance = pulse tolerace (above) */
913	{0, 0}, /* spacing tolerance value = not applicable, */
914	/* and spacing tolerance = 12.5% */
915	16-1, /* no. of symbols for sequence with preamble A */
916	0, /* no. of symbols for sequence with preamble B */
917	1-1, /* no. of data bits per symbol */
918	0, /* most/!least significant symbol received first */
919	0, /* left/!right adjust received data */
920	0, /* bi-phase/!pulse-spacing coded */
921	0, /* two sub-symbols per cycle */
922	1, /* have inter-word gap or stop symbol */
923	1, /* variable length data */
924	50-1, /* time-out clock divisor: divide by 50 or .5 ms */
925	148, /* frame time-out = 74 ms */
926	16, /* edge time-out = 8.0 ms */
927	16, /* minimum dead-time after fault = 8.0 ms */
928	{658,0}, /* stop/IWG off/cycle period = 6.5ms, 12.5% */
929	744, /* data symbol time-out */
930	0,
931	0,
932	0,
933	0,
934	0,
935	0,
936	0,
937	0,
938	0,
939	0,
940	0,
941	0,
942	0,
943	0,
944	0,
945	0,
946	0
947	};
948
949	static const CIR_Param echostarUHFParam =
950	{ /* Manchester */
951	/* Symbol time spec. includes 400us ON pulse. */
952	108-1, /* count unit @ 27MHz = 4us */
953	{ {500,0}, {250,0}, {500,0}, {250,0}}, /* pa[], preamble A pulse sequence */
954	{ {500,0}, {500,0}, {250,0}, {250,0}}, /* pb[], preamble B pulse sequence */
955	3, /* number of entries in pa[] */
956	3, /* number of entries in pb[] */
957	1, /* measure preamble pulse: */
958	/* 0 => even counts specifies cycle period */
959	/* 1 => even counts specifies off pulse period */
960	0, /* if true, pb[] matches a repeat sequence */
961	0, /* pulse tolerance = 400us */
962	250, /* T0 = 1ms */
963	0, /* DeltaT = 0ms */
964	0, /* false => fix symbol pulse between edges 0 & 1 */
965	/* true => fix symbol pulse between edges 1 & 2 */
966	0, /* false => measure spacing for complete cycle */
967	/* true => measure spacing between 2 consecutive edges */
968	/* (for stop/IWG symbol) */
969	{0,0}, /* data/stop symbol fix-width pulse period, */
970	/* tolerance = pulse tolerace (above) */
971	{0,0}, /* spacing tolerance value = not applicable, */
972	/* and spacing tolerance = 12.5% */
973	26-1, /* no. of symbols for sequence with preamble A */
974	5-1, /* no. of symbols for sequence with preamble B */
975	1-1, /* no. of data bits per symbol */
976	1, /* most/!least significant symbol received first */
977	0, /* left/!right adjust received data */
978	1, /* bi-phase/!pulse-spacing coded */
979	0, /* two sub-symbols per cycle */
980	0, /* have inter-word gap or stop symbol */
981	0, /* variable length data */
982	50-1, /* time-out unit @ 27MHz = 200us */
983	253, /* frame time-out = 50.5 ms */
984	25, /* edge time-out = 5.0 ms */
985	2, /* minimum dead-time after fault = 3.0 ms */
986	{0,0}, /* stop/IWG off/cycle period = 6.5ms, 12.5% */
987	0, /* data symbol time-out */
988	0,
989	0,
990	0,
991	0,
992	0,
993	0,
994	0,
995	0,
996	0,
997	0,
998	0,
999	0,
1000	0,
1001	0,
1002	0,
1003	0,
1004	0
1005	};
1006
1007	static const CIR_Param necParam = {
1008	270-1, /* count divisor */
1009	{ {900,0}, {450,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
1010	{ {900,0}, {225,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1011	2, /* number of entries in pa[] */
1012	2, /* number of entries in pb[] */
1013	1, /* measure preamble pulse: */
1014	/* 0 => even counts specifies cycle period */
1015	/* 1 => even counts specifies off pulse period */
1016	1, /* if true, pb[] matches a repeat sequence */
1017	50, /* pulse tolerance */
1018	113, /* bit Period = 1.778 ms (PS T0) */
1019	113, /* delta T */
1020	0, /* - " - (symbol pulse position) */
1021	0, /* - " - (measure spacing for complete cycle) */
1022	{50, 3}, /* - " - (data symbol fix-width pulse period) */
1023	{0, 0}, /* bit period tolerance value = not applicable, */
1024	/* and select code = 12.5% */
1025	48-1, /* no. of symbols for sequence with preamble A */
1026	0, /* no. of symbols for sequence with preamble B */
1027	1-1, /* no. of data bits per symbol */
1028	0, /* most/!least significant symbol received first */
1029	0, /* left/!right adjust received data */
1030	0, /* bi-phase/!pulse-spacing coded */
1031	0, /* two symbols per cycle */
1032	0, /* check stop symbol */
1033	1, /* variable length data */
1034	50-1, /* time-out clock divisor */
1035	255, /* frame time-out */
1036	22, /* edge time-out */
1037	6, /* minimum dead-time after fault = 1.5 ms */
1038	{0, 0}, /* stop symbol pulse or cycle period */
1039	256, /* data symbol timeout */
1040	280,
1041	0,
1042	0,
1043	0,
1044	0,
1045	0,
1046	0,
1047	0,
1048	0,
1049	0,
1050	0,
1051	0,
1052	0,
1053	0,
1054	0,
1055	0,
1056	0
1057	};
1058
1059	static const CIR_Param giSatParam = {
1060	270-1, /* count divisor: divide by 270 for 10us period */
1061	{ {500,0}, {200,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
1062	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1063	2, /* number of entries in pa[] */
1064	0, /* number of entries in pb[] */
1065	1, /* measure preamble pulse: */
1066	/* 0 => even counts specifies cycle period */
1067	/* 1 => even counts specifies off pulse period */
1068	0, /* if true, pb[] matches a repeat sequence */
1069	50, /* pulse tolerance */
1070	200, /* T0 */
1071	200, /* delta T */
1072	0, /* false => fix symbol pulse between edges 0 & 1 */
1073	/* true => fix symbol pulse between edges 1 & 2 */
1074	0, /* false => measure spacing for complete cycle */
1075	/* true => measure spacing between 2 consecutive edges */
1076	{100,3}, /* data symbol fix-width pulse period, */
1077	/* tolerance = pulse tolerance (above) */
1078	{0, 0}, /* spacing tolerance value = not applicable, */
1079	/* and select code = 12.5% */
1080	12-1, /* no. of symbols for sequence with preamble A */
1081	0, /* no. of symbols for sequence with preamble B */
1082	1-1, /* no. of data bits per symbol */
1083	0, /* most/!least significant symbol received first */
1084	0, /* left/!right adjust received data */
1085	0, /* bi-phase/!pulse-spacing coded */
1086	0, /* two symbols per cycle */
1087	0, /* check stop symbol */
1088	0, /* variable length data */
1089	50-1, /* time-out clock divisor: divide by 50 or .5 ms */
1090	200, /* frame time-out = 100 ms */
1091	22, /* edge time-out = 11 ms */
1092	6, /* minimum dead-time after fault = 3 ms */
1093	{0, 0}, /* stop symbol pulse or cycle period */
1094	0, /* data symbol timeout */
1095	0,
1096	0,
1097	0,
1098	0,
1099	0,
1100	0,
1101	0,
1102	0,
1103	0,
1104	0,
1105	0,
1106	0,
1107	0,
1108	0,
1109	0,
1110	0,
1111	0
1112	};
1113
1114	static const CIR_Param directvUHFParam = {
1115	270-1, /* count divisor */
1116	{ {600,0}, {120,3}, {0,0}, {0,0} }, /* pa[], preamble A pulse
1117	sequence */
1118	{ {300,0}, {120,3}, {0,0}, {0,0} }, /* pb[], preamble B pulse
1119	sequence */
1120	2, /* number of entries in pa[] */
1121	2, /* number of entries in pb[] */
1122	1, /* measure preamble pulse: */
1123	/* 0 => even counts specifies cycle period */
1124	/* 1 => even counts specifies off pulse period */
1125	0, /* if true, pb[] matches a repeat sequence */
1126	26, /* pulse tolerance = value not used */
1127	60, /* T0 */
1128	60, /* not used for bi-phase (PS delta T) */
1129	0, /* - " - (symbol pulse position) */
1130	0, /* - " - (measure spacing for complete cycle) */
1131	{0, 0}, /* - " - (data symbol fix-width pulse period) */
1132	{0, 0}, /* bit period tolerance value = not applicable, */
1133	/* and select code */
1134	20-1, /* no. of symbols for sequence with preamble A */
1135	20-1, /* no. of symbols for sequence with preamble B */
1136	1-1, /* no. of data bits per symbol */
1137	1, /* most/!least significant symbol received first */
1138	0, /* left/!right adjust received data */
1139	0, /* bi-phase/!pulse-spacing coded */
1140	1, /* two symbols per cycle */
1141	0, /* check stop symbol */
1142	0, /* variable length data */
1143	5-1, /* time-out clock divisor */
1144	1880, /* frame time-out */
1145	140, /* edge time-out */
1146	30, /* minimum dead-time after fault */
1147	{600, 0}, /* stop symbol pulse or cycle period */
1148	0, /* data symbol timeout */
1149	0,
1150	0,
1151	0,
1152	0,
1153	0,
1154	0,
1155	0,
1156	0,
1157	0,
1158	0,
1159	0,
1160	0,
1161	0,
1162	0,
1163	0,
1164	0,
1165	0
1166	};
1167
1168	static CIR_Param rC6Mode0Param = {
1169	/*
1170	* CIR configuration parameters for RC6 Mode 0
1171	*
1172	*/
1173	125-1, /* count divisor: count period = T/96 @ 27MHz, T=444.44.us */
1174	{ {576,1}, {192,1}, {96,1}, {0,0} },
1175	/* pa[], preamble A pulse sequence */
1176	{ {0,0}, {0,0}, {0,0}, {0,0} },
1177	/* pb[], preamble B pulse sequence */
1178	3, /* number of entries in pa[] */
1179	0, /* number of entries in pb[] */
1180	1, /* preamble pulse type: */
1181	/* 0 => even counts specifies cycle period */
1182	/* 1 => even counts specifies off pulse period */
1183	0, /* if true, pb[] matches a repeat sequence */
1184	0, /* not used: pulse tolerance */
1185	192, /* T0 = 888.88us (2T) */
1186	0, /* not used: DeltaT */
1187	0, /* not used */
1188	0, /* not used */
1189	{0,0}, /* not used: stop symbol */
1190	{0,1}, /* bit period tolerance = ~12.5% */
1191	0, /* not used: no. of symbols for sequence with preamble A */
1192	0, /* not used: no. of symbols for sequence with preamble B */
1193	1-1, /* no. of data bits per symbol = 1 */
1194	1, /* most/!least significant symbol received first */
1195	0, /* left/!right adjust received data */
1196	1, /* bi-phase/!pulse-spacing coded */
1197	0, /* two sub-symbols per cycle */
1198	0, /* have inter-word gap or stop symbol */
1199	1, /* variable length data */
1200	96-1, /* time-out clock divisor: divide by 96 for 0.444ms period */
1201	100, /* frame time-out = 100T */
1202	8, /* edge time-out = 8T */
1203	8, /* minimum dead-time after fault = 8T */
1204	{0,0}, /* not used: stop/IWG off/cycle period */
1205	672, /* data symbol time-out = 3.11ms = 7T */
1206	0, /* not used: repeat timer timeout */
1207	0, /* stop parameter unit selector: */
1208	/* 0: stop has count units */
1209	/* 1: stop has timout units */
1210	0, /* data symbol timer clock tick dataSymTimeout units selector: */
1211	/* 0: dataSymTimeout has count units */
1212	/* 1: dataSymTimeout has timout units */
1213	0, /* not used for biphase: ignore data symbol timer expiration */
1214	/* while waiting for Edge 1: 0:false, 1:true */
1215	0, /* enable data symbol time-out expiration flag to lflag */
1216	/* status register: 0:false, 1:true */
1217	0, /* enable havePreambleAftStop parameter for */
1218	/* non-biphase decoding: 0:false, 1:true */
1219	0, /* have preamble after stop symbol: 0:false, 1:true */
1220	1, /* restrictive decoding enabled: 0:false, 1:true */
1221	1, /* RC6 encoded: 0:false, 1:true. Requires biphaseCoded=1 */
1222	1, /* don't validate RC mode bits: 0:false, 1:true */
1223	0, /* RC6 mode bits (3 bits): 0 for Mode 0, 6 for Mode 6 */
1224	0, /* Reserved for future use */
1225	0, /* Reserved for future use */
1226	1, /* don't validate control field bits: 0:false, 1:true */
1227	0, /* RC6M0 control field (8 bits) or RC6M6A customer code bits (16 bits) */
1228	8-1, /* number of RC6M0 control field bits: 0..15 for 1..16 bits */
1229	1 /* RC6 mode bits and control field pass-through control: */
1230	/* 0: Exclude mode bits and control field from */
1231	/* received data. The nccb field determines */
1232	/* the size of the control field. */
1233	/* 1: Exclude mode bits from the received data, but, */
1234	/* include control field. */
1235	/* 2: Not allowed. */
1236	/* 3: Include both mode bits and customer code in */
1237	/* the received data. */
1238	};
1239
1240
1241	static const CIR_Param rC6Mode6AParam = {
1242	/*
1243	* CIR configuration parameters for RC6 Mode 6A
1244	*
1245	*/
1246	125-1, /* count divisor: count period = T/96 @ 27MHz, T=444.44.us */
1247	{ {576,1}, {192,1}, {96,1}, {0,0} },
1248	/* pa[], preamble A pulse sequence */
1249	{ {0,0}, {0,0}, {0,0}, {0,0} },
1250	/* pb[], preamble B pulse sequence */
1251	3, /* number of entries in pa[] */
1252	0, /* number of entries in pb[] */
1253	1, /* preamble pulse type: */
1254	/* 0 => even counts specifies cycle period */
1255	/* 1 => even counts specifies off pulse period */
1256	0, /* if true, pb[] matches a repeat sequence */
1257	0, /* not used: pulse tolerance */
1258	192, /* T0 = 888.88us (2T) */
1259	0, /* not used: DeltaT */
1260	0, /* not used */
1261	0, /* not used */
1262	{0,0}, /* not used: stop symbol */
1263	{0,1}, /* bit period tolerance = ~12.5% */
1264	0, /* not used: no. of symbols for sequence with preamble A */
1265	0, /* not used: no. of symbols for sequence with preamble B */
1266	1-1, /* no. of data bits per symbol = 1 */
1267	1, /* most/!least significant symbol received first */
1268	0, /* left/!right adjust received data */
1269	1, /* bi-phase/!pulse-spacing coded */
1270	0, /* two sub-symbols per cycle */
1271	0, /* have inter-word gap or stop symbol */
1272	1, /* variable length data */
1273	96-1, /* time-out clock divisor: divide by 96 for 0.444ms period */
1274	100, /* frame time-out = 100T */
1275	8, /* edge time-out = 8T */
1276	8, /* minimum dead-time after fault = 8T */
1277	{0,0}, /* not used: stop/IWG off/cycle period */
1278	672, /* data symbol time-out = 3.11ms = 7T */
1279	0, /* not used: repeat timer timeout */
1280	0, /* stop parameter unit selector: */
1281	/* 0: stop has count units */
1282	/* 1: stop has timout units */
1283	0, /* data symbol timer clock tick dataSymTimeout units selector: */
1284	/* 0: dataSymTimeout has count units */
1285	/* 1: dataSymTimeout has timout units */
1286	0, /* not used for biphase: ignore data symbol timer expiration */
1287	/* while waiting for Edge 1: 0:false, 1:true */
1288	0, /* enable data symbol time-out expiration flag to lflag */
1289	/* status register: 0:false, 1:true */
1290	0, /* enable havePreambleAftStop parameter for */
1291	/* non-biphase decoding: 0:false, 1:true */
1292	0, /* have preamble after stop symbol: 0:false, 1:true */
1293	1, /* restrictive decoding enabled: 0:false, 1:true */
1294	1, /* RC6 encoded: 0:false, 1:true. Requires biphaseCoded=1 */
1295	1, /* don't validate RC mode bits: 0:false, 1:true */
1296	6, /* RC6 mode bits (3 bits): 6 for Mode 6A */
1297	0, /* Reserved: don't validate RC6 trailer: 0:false, 1:true */
1298	0, /* Reserved: RC6 trailer (1 bit): 0 for Mode 6A */
1299	1, /* don't validate customer code bits: 0:false, 1:true */
1300	0, /* RC6 customer code bits (16 bits) */
1301	0, /* number of RC6 customer code bits: 0..15 for 1..16 bits */
1302	3 /* RC6 mode bits and customer code pass-through control: */
1303	/* 0: Exclude mode bits and customer code from */
1304	/* received data. The nccb field determines */
1305	/* the size of the customer code. */
1306	/* 1: Exclude mode bits from the received data, but, */
1307	/* include customer code. */
1308	/* 2: Not allowed. */
1309	/* 3: Include both mode bits and customer code in */
1310	/* the received data. */
1311	};
1312
1313	#if RCMM_VARIABLE_LENGTH_SUPPORT != 1
1314	static const CIR_Param s_RCMMParam = {
1315	/*
1316	* CIR configuration parameters for RCMM
1317	*
1318	* T0 = 444.44us
1319	* deltaT = 166.67us
1320	* Data 3 symbol OFF pulse width = 944.44us - 166.67us = 777.77us
1321	* Maximum pulse width = max(416.66, 277.77, 166.66, 777.77)
1322	* = 777.77us
1323	* Maximum frame duration = 416.66us + 277.77us + 166.66us
1324	* + 16 * 944.44us
1325	* = 15972.22us
1326	*/
1327	30-1, /* count divisor: divide by for 1.111us period */
1328	{ {411,2}, {625,3}, {0,0}, {0,0} }, /* {411,2}->457us ONTIME+/- 50%, {625,3}->695us(ON+OFF) and use pulse tolerance of 54 */
1329	/* pa[], preamble A pulse sequence */
1330	{ {0,0}, {0,0}, {0,0}, {0,0} },
1331	/* pb[], preamble B pulse sequence */
1332	2, /* number of entries in pa[] */
1333	0, /* number of entries in pb[] */
1334	0, /* measure preamble pulse: */
1335	/* 0 => even counts specifies cycle period, meaning 625 in preamble denote ON+OFF */
1336	/* 1 => even counts specifies off pulse period */
1337	0, /* if true, pb[] matches a repeat sequence */
1338	54, /* pulse tolerance = 58us */
1339	400, /* T0 = 444.44us */
1340	150, /* DeltaT = 166.67ms */
1341	0, /* false => fix symbol pulse between edges 0 & 1 */
1342	/* true => fix symbol pulse between edges 1 & 2 */
1343	0, /* false => measure spacing for complete cycle */
1344	/* true => measure spacing between 2
1345	consecutive edges */
1346	{150,2}, /* data/stop symbol fix-width pulse period = 166.6us, tolerance = 50% */
1347	{54, 3}, /* spacing tolerance value = 58us, !!! */
1348	16-1, /* no. of symbols for sequence with preamble A */
1349	0, /* no. of symbols for sequence with preamble B */
1350	2-1, /* no. of data bits per symbol */
1351	1, /* most/!least significant symbol received first */
1352	0, /* left/!right adjust received data */
1353	0, /* bi-phase/!pulse-spacing coded */
1354	0, /* two sub-symbols per cycle */
1355	0, /* have inter-word gap or stop symbol */
1356	0, /* variable length data */
1357	50-1, /* time-out clock divisor: divide by 50
1358	or 55.55us */
1359	328, /* frame time-out = 18,222us */
1360	18, /* edge time-out = 1000us */
1361	18, /* minimum dead-time after fault = 1000us */
1362	{0,0}, /* not used: stop/IWG off/cycle period */
1363	0, /* data symbol timeout */
1364	0,
1365	0,
1366	0,
1367	0,
1368	0,
1369	0,
1370	0,
1371	0,
1372	0,
1373	0,
1374	0,
1375	0,
1376	0,
1377	0,
1378	0,
1379	0,
1380	0
1381	};
1382	#else
1383	static const CIR_Param s_RCMMParam = {
1384	/*
1385	* CIR configuration parameters for RCMM
1386	*
1387	* T0 = 444.44us
1388	* deltaT = 166.67us
1389	* Data 3 symbol OFF pulse width = 944.44us - 166.67us = 777.77us
1390	* Maximum pulse width = max(416.66, 277.77, 166.66, 777.77)
1391	* = 777.77us
1392	* Maximum frame duration = 416.66us + 277.77us + 166.66us
1393	* + 16 * 944.44us
1394	* = 15972.22us
1395	*/
1396	30-1, /* count divisor: divide by for 1.111us period */
1397	{ {411,2}, {625,3}, {0,0}, {0,0} }, /* {411,2}->457us ONTIME+/- 50%, {625,3}->695us(ON+OFF) and use pulse tolerance of 54 */
1398	/* pa[], preamble A pulse sequence */
1399	{ {0,0}, {0,0}, {0,0}, {0,0} },
1400	/* pb[], preamble B pulse sequence */
1401	2, /* number of entries in pa[] */
1402	0, /* number of entries in pb[] */
1403	0, /* measure preamble pulse: */
1404	/* 0 => even counts specifies cycle period, meaning 625 in preamble denote ON+OFF */
1405	/* 1 => even counts specifies off pulse period */
1406	0, /* if true, pb[] matches a repeat sequence */
1407	54, /* pulse tolerance = 58us */
1408	400, /* T0 = 444.44us */
1409	150, /* DeltaT = 166.67ms */
1410	0, /* false => fix symbol pulse between edges 0 & 1 */
1411	/* true => fix symbol pulse between edges 1 & 2 */
1412	0, /* false => measure spacing for complete cycle */
1413	/* true => measure spacing between 2
1414	consecutive edges */
1415	{150,2}, /* data/stop symbol fix-width pulse period = 166.6us, tolerance = 50% */
1416	{54, 3}, /* spacing tolerance value = 58us, !!! */
1417	16-1, /* ot used with variable length data, no. of symbols for sequence with preamble A */
1418	0, /* no. of symbols for sequence with preamble B */
1419	2-1, /* no. of data bits per symbol */
1420	1, /* most/!least significant symbol received first */
1421	0, /* left/!right adjust received data */
1422	0, /* bi-phase/!pulse-spacing coded */
1423	0, /* two sub-symbols per cycle */
1424	0, /* have inter-word gap or stop symbol */
1425	1, /* variable length data */
1426	50-1, /* time-out clock divisor: divide by 50
1427	or 55.55us */
1428	328, /* frame time-out = 18,222us */
1429	18, /* edge time-out = 1000us */
1430	18, /* minimum dead-time after fault = 1000us */
1431	{0,0}, /* not used: stop/IWG off/cycle period */
1432	906, /* data symbol timeout: require > max Data 3 period = 850 + 54 count units (= 944.4us+60us) = 904 units */
1433	0,
1434	0,
1435	0,
1436	0,
1437	0,
1438	0,
1439	0,
1440	0,
1441	0,
1442	0,
1443	0,
1444	0,
1445	0,
1446	0,
1447	0,
1448	0,
1449	0
1450	};
1451	#endif
1452
1453	static const CIR_Param rStepParam = {
1454	54-1, /* count divisor: divide by 54 for 2.000 us period */
1455	{ {165,3}, {0,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
1456	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1457	1, /* number of entries in pa[] */
1458	0, /* number of entries in pb[] */
1459	0, /* measure preamble pulse: */
1460	/* 0 => even counts specifies cycle period */
1461	/* 1 => even counts specifies off pulse period */
1462	0, /* if true, pb[] matches a repeat sequence */
1463	67, /* pulse tolerance = 672=134us; pa ul = 330+134= 464; pall = 330-134=196 /
1464	325, /* bit Period = 3252=650 us (PS T0) /
1465	0, /* not used for bi-phase (PS delta T) */
1466	0, /* - " - (symbol pulse position) */
1467	0, /* - " - (measure spacing for complete cycle) */
1468	{0, 0}, /* - " - (data symbol fix-width pulse period) */
1469	{67, 3}, /* bit period tolerance value = 532=106us; ul = 650+134=784; ll=650-134=516/
1470	17-1, /* no. of symbols for sequence with preamble A */
1471	17-1, /* no. of symbols for sequence with preamble B */
1472	1-1, /* no. of data bits per symbol */
1473	1, /* most/!least significant symbol received first */
1474	0, /* left/!right adjust received data */
1475	1, /* bi-phase/!pulse-spacing coded */
1476	0, /* two symbols per cycle */
1477	0, /* check stop symbol */
1478	0, /* variable length data */
1479	250-1, /* time-out clock divisor: divide by 250 or .5ms */
1480	24+1, /* frame time-out = 12 ms */
1481	3+1, /* edge time-out = 1.5 ms */
1482	3, /* minimum dead-time after fault = 1.5 ms */
1483	{0, 0}, /* stop symbol pulse or cycle period */
1484	0, /* data symbol timeout */
1485	0,
1486	0,
1487	0,
1488	0,
1489	0,
1490	0,
1491	0,
1492	1, /* validate a short pulse */
1493	0,
1494	0,
1495	0,
1496	0,
1497	0,
1498	0,
1499	0,
1500	0,
1501	0
1502	};
1503
1504	#ifdef XMP2_NO_ACK
1505	static const CIR_Param xmp2Param = {
1506	90-1, /* count divisor: 90 divide by 27MHz for 3.333us period */
1507	{ {70,2}, {0,0}, {0,0}, {0,0} }, /* pa[], 673.33=223us, 1=+/125% 2= +/- 50%, 3=use purse tolerance/
1508	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1509	0, /* number of entries in pa[] */
1510	0, /* number of entries in pb[] */
1511	0, /* measure preamble pulse: */
1512	/* 0 => even counts specifies cycle period */
1513	/* 1 => even counts specifies off pulse period */
1514	0, /* if true, pb[] matches a repeat sequence */
1515	35, /* pulse tolerance = 293.33 = 166.55us. Only used if tolerance code is 3 /
1516	291, /* T0 = 970us (969.98+0136.71) /
1517	41, /* delta T = 136.71us 413.333=136.653/
1518	0, /* false => fix symbol pulse between edges 0 & 1 */
1519	/* true => fix symbol pulse between edges 1 & 2 */
1520	0, /* false => measure spacing for complete cycle */
1521	/* true => measure spacing between 2 consecutive edges */
1522	{70,2}, /* data symbol fix-width pulse period = 0.280, */
1523	/* tolerance 2 = 50% */
1524	{21, 3}, /* spacing tolerance value = .5 DeltaT, */
1525	/* and select code = value */
1526	8-1, /* no. of symbols for sequence with preamble A */
1527	0, /* no. of symbols for sequence with preamble B */
1528	4-1, /* no. of data bits per symbol */
1529	1, /* most/!least significant symbol received first */
1530	0, /* left/!right adjust received data */
1531	0, /* bi-phase/!pulse-spacing coded */
1532	0, /* two symbols per cycle */
1533	0, /* check stop symbol */
1534	0, /* variable length data */
1535	150-1, /* time-out clock divisor: 3.333us150 = .5ms /
1536	60, /* frame time-out = 60 ms */
1537	8, /* edge time-out = 4 ms */
1538	8, /* minimum dead-time after fault = 4 ms */
1539	{0, 0}, /* stop symbol pulse or cycle period */
1540	0, /* data symbol timeout used with variable length data: 9373.333us=3123us. After this time, we assume all data are captured /
1541	0,
1542	0,
1543	0,
1544	0,
1545	0,
1546	0,
1547	0,
1548	0,
1549	0,
1550	0,
1551	0,
1552	0,
1553	0,
1554	0,
1555	0,
1556	0,
1557	0
1558	};
1559	#else
1560	#ifdef XMP2_NEW_LE_TO_LE
1561	/* This is the new XMP2 decoder.
1562	* This can decode a variable length IR input from leading edge to leading edge.
1563	* When used, this should decode XMXP-2 data and ack/nak IR input more reliably
1564	* than using falling edge since there are more jitter on the falling edge of IR input
1565	*/
1566	static const CIR_Param xmp2Param = {
1567	90-1, /* count divisor: 90 divide by 27MHz for 3.333us period */
1568	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pa[], 673.33=223us, 1=+/125% 2= +/- 50%, 3=use pulse tolerance/
1569	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1570	0, /* number of entries in pa[] */
1571	0, /* number of entries in pb[] */
1572	0, /* measure preamble pulse: */
1573	/* 0 => even counts specifies cycle period */
1574	/* 1 => even counts specifies off pulse period */
1575	0, /* if true, pb[] matches a repeat sequence */
1576	74, /* pulse tolerance = 743.33 = 245us. Only used if tolerance code is 3 /
1577	291, /* one cycle of data 0: 970us/3.33=291 */
1578	41, /* delta T = 136.71us 413.333=136.653/
1579	0, /* false => fix symbol pulse between edges 0 & 1 */
1580	/* true => fix symbol pulse between edges 1 & 2 */
1581	0, /* false => measure spacing for complete cycle*/
1582	/* true => measure spacing between 2 consecutive edges */
1583	{116,3}, /* data symbol fix-width pulse period = 1163.33=385us /
1584	/* hilim = 500us+107us+23us=630us lolim = 214us-54us-20us=140 */
1585	/* midpoint = (hilim+lolim)/2=385us. 385us/3.33us=116*/
1586	/* tolerance 3 = use T0 tolerance value = (385-140)/3.33=74 */
1587	{21, 3}, /* spacing tolerance value = .5 DeltaT, */
1588	/* and select code = value */
1589	0, /* no. of symbols for sequence with preamble A */
1590	0, /* no. of symbols for sequence with preamble B */
1591	4-1, /* no. of data bits per symbol */
1592	1, /* most/!least significant symbol received first */
1593	0, /* left/!right adjust received data */
1594	0, /* bi-phase/!pulse-spacing coded */
1595	0, /* two symbols per cycle */
1596	0, /* check stop symbol */
1597	1, /* variable length data */
1598	150-1, /* time-out clock divisor: 3.333us150 = .5ms /
1599	60, /* frame time-out = 60 ms */
1600	8, /* edge time-out = 4 ms */
1601	8, /* minimum dead-time after fault = 4 ms */
1602	{0, 0}, /* stop symbol pulse or cycle period */
1603	1090, /* data symbol timeout used with variable length data: */
1604	/* 10903.333us=3629us. After this time, we assume all data are captured /
1605	0,
1606	0,
1607	0,
1608	0,
1609	0,
1610	0,
1611	0,
1612	0,
1613	0,
1614	0,
1615	0,
1616	0,
1617	0,
1618	0,
1619	0,
1620	0,
1621	0
1622	};
1623	#else
1624	static const CIR_Param xmp2Param = {
1625	90-1, /* count divisor: 90 divide by 27MHz for 3.333us period */
1626	{ {70,2}, {0,0}, {0,0}, {0,0} }, /* pa[], 673.33=223us, 1=+/125% 2= +/- 50%, 3=use pulse tolerance/
1627	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1628	1, /* number of entries in pa[] */
1629	0, /* number of entries in pb[] */
1630	0, /* measure preamble pulse: */
1631	/* 0 => even counts specifies cycle period */
1632	/* 1 => even counts specifies off pulse period */
1633	0, /* if true, pb[] matches a repeat sequence */
1634	74, /* pulse tolerance = 743.33 = 245us. Only used if tolerance code is 3 /
1635	205, /* 2053.33us=683us: T0 = 970us-214us=756us. Reduced it to make it work when on pulse is bigger and off pulse is smaller/
1636	41, /* delta T = 136.71us 413.333=136.653/
1637	1, /* false => fix symbol pulse between edges 0 & 1 */
1638	/* true => fix symbol pulse between edges 1 & 2 */
1639	1, /* false => measure spacing for complete cycle*/
1640	/* true => measure spacing between 2 consecutive edges */
1641	{116,3}, /* data symbol fix-width pulse period = 397us */
1642	/* hilim = 500us+107us+23us=630us lolim = 214us-54us-20us=140 */
1643	/* midpoint = (hilim+lolim)/2=385us. 385us/3.33us=116*/
1644	/* tolerance 2 = 50% 3 = use T0 tolerance value = 385-140/3.33=74 */
1645	{21, 3}, /* spacing tolerance value = .5 DeltaT, */
1646	/* and select code = value */
1647	8-1, /* no. of symbols for sequence with preamble A */
1648	0, /* no. of symbols for sequence with preamble B */
1649	4-1, /* no. of data bits per symbol */
1650	1, /* most/!least significant symbol received first */
1651	0, /* left/!right adjust received data */
1652	0, /* bi-phase/!pulse-spacing coded */
1653	0, /* two symbols per cycle */
1654	0, /* check stop symbol */
1655	1, /* variable length data */
1656	150-1, /* time-out clock divisor: 3.333us150 = .5ms /
1657	60, /* frame time-out = 60 ms */
1658	8, /* edge time-out = 4 ms */
1659	8, /* minimum dead-time after fault = 4 ms */
1660	{0, 0}, /* stop symbol pulse or cycle period */
1661	1090, /* data symbol timeout used with variable length data: */
1662	/* 10903.333us=3629us. After this time, we assume all data are captured /
1663	0,
1664	0,
1665	0,
1666	0,
1667	0,
1668	0,
1669	0,
1670	0,
1671	0,
1672	0,
1673	0,
1674	0,
1675	0,
1676	0,
1677	0,
1678	0,
1679	0
1680	};
1681	#endif /* #ifdef XMP2_NEW_LE_TO_LE*/
1682
1683
1684	#endif /* ifdef XMP2_NO_ACK */
1685
1686	static const CIR_Param xmp2AckParam = {
1687	90-1, /* count divisor: 90 divide by 27MHz for 3.333us period */
1688	{ {70,2}, {0,0}, {0,0}, {0,0} }, /* pa[], 673.33=223us, 1=+/125% 2= +/- 50%, 3=use purse tolerance/
1689	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1690	0, /* number of entries in pa[] */
1691	0, /* number of entries in pb[] */
1692	0, /* measure preamble pulse: */
1693	/* 0 => even counts specifies cycle period */
1694	/* 1 => even counts specifies off pulse period */
1695	0, /* if true, pb[] matches a repeat sequence */
1696	35, /* pulse tolerance = 293.33 = 166.55us. Only used if tolerance code is 3 /
1697	291, /* T0 = 970us (969.98+0136.71) /
1698	41, /* delta T = 136.71us 413.333=136.653/
1699	0, /* false => fix symbol pulse between edges 0 & 1 */
1700	/* true => fix symbol pulse between edges 1 & 2 */
1701	0, /* false => measure spacing for complete cycle */
1702	/* true => measure spacing between 2 consecutive edges */
1703	{70,2}, /* data symbol fix-width pulse period = 0.280, */
1704	/* tolerance 2 = 50% */
1705	{21, 3}, /* spacing tolerance value = .5 DeltaT, */
1706	/* and select code = value */
1707	2-1, /* no. of symbols for sequence with preamble A */
1708	0, /* no. of symbols for sequence with preamble B */
1709	4-1, /* no. of data bits per symbol */
1710	1, /* most/!least significant symbol received first */
1711	0, /* left/!right adjust received data */
1712	0, /* bi-phase/!pulse-spacing coded */
1713	0, /* two symbols per cycle */
1714	0, /* check stop symbol */
1715	0, /* variable length data */
1716	150-1, /* time-out clock divisor: 3.333us150 = .5ms /
1717	60, /* frame time-out = 60 ms */
1718	8, /* edge time-out = 4 ms */
1719	10, /* minimum dead-time after fault = 5 ms. Make sure only 1 interrupt is received when 4 byte packet is received */
1720	{0, 0}, /* stop symbol pulse or cycle period */
1721	0, /* data symbol timeout used with variable length data: 9723.333us=3239us. After this time, we assume all data are captured /
1722	0,
1723	0,
1724	0,
1725	0,
1726	0,
1727	0,
1728	0,
1729	0,
1730	0,
1731	0,
1732	0,
1733	0,
1734	0,
1735	0,
1736	0,
1737	0,
1738	0
1739	};
1740
1741	static const CIR_Param rcaParam = {
1742	270-1, /* count divisor 270/27Mhz = 10us */
1743	{ {400,0}, {400,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
1744	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1745	2, /* number of entries in pa[] */
1746	0, /* number of entries in pb[] */
1747	1, /* measure preamble pulse: */
1748	/* 0 => even counts specifies cycle period */
1749	/* 1 => even counts specifies off pulse period */
1750	0, /* if true, pb[] matches a repeat sequence */
1751	50, /* pulse tolerance */
1752	150, /* bit Period = 1.50 ms (PS T0) */
1753	100, /* delta T = 1000us */
1754	0, /* - " - (symbol pulse position) */
1755	0, /* - " - (measure spacing for complete cycle) */
1756	{50, 1}, /* - " - (data symbol fix-width pulse period) */
1757	{30, 3}, /* bit period tolerance value = not applicable, */
1758	/* and select code = 12.5% */
1759	24-1, /* no. of symbols for sequence with preamble A */
1760	0, /* no. of symbols for sequence with preamble B */
1761	1-1, /* no. of data bits per symbol */
1762	1, /* most/!least significant symbol received first */
1763	0, /* left/!right adjust received data */
1764	0, /* bi-phase/!pulse-spacing coded */
1765	0, /* two symbols per cycle */
1766	0, /* check stop symbol */
1767	0, /* variable length data */
1768	50-1, /* time-out clock divisor = 10us50 = 500us /
1769	200, /* frame time-out */
1770	21, /* edge time-out = 10ms*/
1771	13, /* minimum dead-time after fault = 6 ms */
1772	{0, 0}, /* stop symbol pulse or cycle period */
1773	0, /* data symbol timeout */
1774	0,
1775	0,
1776	0,
1777	0,
1778	0,
1779	0,
1780	0,
1781	0,
1782	0,
1783	0,
1784	0,
1785	0,
1786	0,
1787	0,
1788	0,
1789	0,
1790	0
1791	};
1792
1793	static const CIR_Param toshibaTC9012Param = {
1794	/*
1795	* Initial frame has 32 bits of data. Using variable length decoding, Repeat
1796	* code treated as frame with 1 bit of data.
1797	*/
1798	270-1, /* count divisor: divide by 270 for 10us/count */
1799	{ {450,0}, {900,0}, {0,0}, {0,0} }, /* pa[], preamble A pulse sequence */
1800	{ {0,0}, {0,0}, {0,0}, {0,0} }, /* pb[], preamble B pulse sequence */
1801	2, /* number of entries in pa[] */
1802	0, /* number of entries in pb[] */
1803	0, /* measure preamble pulse: */
1804	/* 0 => even counts specifies cycle period */
1805	/* 1 => even counts specifies off pulse period */
1806	0, /* if true, pb[] matches a repeat sequence */
1807	0, /* pulse tolerance */
1808	112, /* T0 = 1.12ms */
1809	113, /* delta = 1.13ms */
1810	0, /* false => fix symbol pulse between edges 0 & 1 */
1811	/* true => fix symbol pulse between edges 1 & 2 */
1812	0, /* false => measure spacing for complete cycle */
1813	/* true => measure spacing between 2 consecutive edges */
1814	{56, 2}, /* data symbol fix-width pulse period and tolerance:
1815	!!! TODO:adjust 50% */
1816	{0, 0}, /* spacing tolerance value = not applicable, */
1817	/* and tolerance select code = 12.5% */
1818	0, /* no. of symbols for sequence with preamble A */
1819	0, /* no. of symbols for sequence with preamble B */
1820	1-1, /* no. of data bits per symbol */
1821	0, /* most/!least significant symbol received first */
1822	0, /* left/!right adjust received data */
1823	0, /* bi-phase/!pulse-spacing coded */
1824	0, /* two symbols per cycle */
1825	0, /* check stop symbol */
1826	1, /* variable length data */
1827	50-1, /* time-out clock divisor: 500us per time-out unit */
1828	200, /* frame time-out: 100ms */
1829	16, /* edge time-out: 8ms */
1830	16, /* minimum dead-time after fault = 8 ms */
1831	{0, 0}, /* stop symbol pulse or cycle period */
1832	254, /* data symbol timeout: T1 max + 2 */
1833	0,
1834	0,
1835	0,
1836	0,
1837	0,
1838	0,
1839	0,
1840	0,
1841	0,
1842	0,
1843	0,
1844	0,
1845	0,
1846	0,
1847	0,
1848	0,
1849	0
1850	};
1851
1852	#if 0
1853	/* this is moved inside channel handle */
1854	static const CIR_Param customCirParam; /* for custom CIR parameters */
1855	#endif
1856
1857	/*******************************************************************************
1858	*
1859	* Private Module Handles
1860	*
1861	*******************************************************************************/
1862
1863	typedef struct BKIR_P_Handle
1864	{
1865	uint32_t magicId; /* Used to check if structure is corrupt */
1866	BCHP_Handle hChip;
1867	BREG_Handle hRegister;
1868	BINT_Handle hInterrupt;
1869	unsigned int maxChnNo;
1870	BKIR_ChannelHandle hKirChn[MAX_KIR_CHANNELS];
1871	} BKIR_P_Handle;
1872
1873	typedef struct BKIR_P_ChannelHandle
1874	{
1875	uint32_t magicId; /* Used to check if structure is corrupt */
1876	BKIR_Handle hKir;
1877	uint32_t chnNo;
1878	uint32_t coreOffset;
1879	BKNI_EventHandle hChnEvent;
1880	BINT_CallbackHandle hChnCallback;
1881	BKIR_KirPort irPort; /* port select setting */
1882	BKIR_KirPort irPortSelected; /* which port was selected (auto mode) */
1883	bool intMode;
1884	bool repeatFlag; /* flag indicating remote A repeat condition */
1885	bool isCirMode;
1886	BKIR_Callback kirCb; /* callback function */
1887	void cbData; / data passed to callback function */
1888	CIR_Param customCirParam;
1889	BKIR_KirDevice customDevice; /* device that this custom cir is used for */
1890	/* this flag will be used for special handling. */
1891	bool cir_pa; /* preamble A is detected. */
1892	bool cir_pb; /* preamble B is detected. */
1893	} BKIR_P_ChannelHandle;
1894
1895
1896
1897	/*******************************************************************************
1898	*
1899	* Default Module Settings
1900	*
1901	*******************************************************************************/
1902	static const BKIR_Settings defKirSettings = NULL;
1903
1904	static const BKIR_ChannelSettings defKir0ChnSettings =
1905	{
1906	BKIR_KirPortAuto,
1907	true,
1908	0
1909	};
1910
1911	static const BKIR_ChannelSettings defKir1ChnSettings =
1912	{
1913	BKIR_KirPortAuto,
1914	true,
1915	0
1916	};
1917
1918	static const BKIR_ChannelSettings defKir2ChnSettings =
1919	{
1920	BKIR_KirPortAuto,
1921	true,
1922	0
1923	};
1924
1925	#if (BCHP_CHIP==7400)
1926	static const BKIR_ChannelSettings defKir3ChnSettings =
1927	{
1928	BKIR_KirPortAuto,
1929	true,
1930	0
1931	};
1932	#endif
1933
1934	/*******************************************************************************
1935	*
1936	* Public Module Functions
1937	*
1938	*******************************************************************************/
1939	BERR_Code BKIR_Open(
1940	BKIR_Handle pKir, / [output] Returns handle */
1941	BCHP_Handle hChip, /* Chip handle */
1942	BREG_Handle hRegister, /* Register handle */
1943	BINT_Handle hInterrupt, /* Interrupt handle */
1944	const BKIR_Settings pDefSettings / Default settings */
1945	)
1946	{
1947	BERR_Code retCode = BERR_SUCCESS;
1948	BKIR_Handle hDev;
1949	unsigned int chnIdx;
1950	BSTD_UNUSED(pDefSettings);
1951
1952	/* Sanity check on the handles we've been given. */
1953	BDBG_ASSERT( hChip );
1954	BDBG_ASSERT( hRegister );
1955	BDBG_ASSERT( hInterrupt );
1956
1957	/* Alloc memory from the system heap */
1958	hDev = (BKIR_Handle) BKNI_Malloc( sizeof( BKIR_P_Handle ) );
1959	if( hDev == NULL )
1960	{
1961	*pKir = NULL;
1962	retCode = BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
1963	BDBG_ERR(("BKIR_Open: BKNI_malloc() failed\n"));
1964	goto done;
1965	}
1966
1967	hDev->magicId = DEV_MAGIC_ID;
1968	hDev->hChip = hChip;
1969	hDev->hRegister = hRegister;
1970	hDev->hInterrupt = hInterrupt;
1971	hDev->maxChnNo = MAX_KIR_CHANNELS;
1972	for( chnIdx = 0; chnIdx < hDev->maxChnNo; chnIdx++ )
1973	{
1974	hDev->hKirChn[chnIdx] = NULL;
1975	}
1976
1977	*pKir = hDev;
1978
1979	done:
1980	return( retCode );
1981	}
1982
1983	BERR_Code BKIR_Close(
1984	BKIR_Handle hDev /* Device handle */
1985	)
1986	{
1987	BERR_Code retCode = BERR_SUCCESS;
1988
1989
1990	BDBG_ASSERT( hDev );
1991	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
1992
1993	BKNI_Free( (void *) hDev );
1994
1995	return( retCode );
1996	}
1997
1998	BERR_Code BKIR_GetDefaultSettings(
1999	BKIR_Settings pDefSettings, / [output] Returns default setting */
2000	BCHP_Handle hChip /* Chip handle */
2001	)
2002	{
2003	BERR_Code retCode = BERR_SUCCESS;
2004	BSTD_UNUSED(hChip);
2005
2006	*pDefSettings = defKirSettings;
2007
2008	return( retCode );
2009	}
2010
2011	BERR_Code BKIR_GetTotalChannels(
2012	BKIR_Handle hDev, /* Device handle */
2013	unsigned int totalChannels / [output] Returns total number downstream channels supported */
2014	)
2015	{
2016	BERR_Code retCode = BERR_SUCCESS;
2017
2018
2019	BDBG_ASSERT( hDev );
2020	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
2021
2022	*totalChannels = hDev->maxChnNo;
2023
2024	return( retCode );
2025	}
2026
2027	BERR_Code BKIR_GetChannelDefaultSettings(
2028	BKIR_Handle hDev, /* Device handle */
2029	unsigned int channelNo, /* Channel number to default setting for */
2030	BKIR_ChannelSettings pChnDefSettings / [output] Returns channel default setting */
2031	)
2032	{
2033	BERR_Code retCode = BERR_SUCCESS;
2034
2035	#if !BDBG_DEBUG_BUILD
2036	BSTD_UNUSED(hDev);
2037	#endif
2038
2039	BDBG_ASSERT( hDev );
2040	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
2041
2042	switch (channelNo)
2043	{
2044	case 0:
2045	*pChnDefSettings = defKir0ChnSettings;
2046	break;
2047
2048	case 1:
2049	*pChnDefSettings = defKir1ChnSettings;
2050	break;
2051
2052	case 2:
2053	*pChnDefSettings = defKir2ChnSettings;
2054	break;
2055
2056	#if (BCHP_CHIP==7400)
2057	case 3:
2058	*pChnDefSettings = defKir3ChnSettings;
2059	break;
2060	#endif
2061
2062	default:
2063	retCode = BERR_TRACE(BERR_INVALID_PARAMETER);
2064	break;
2065
2066	}
2067
2068	return( retCode );
2069	}
2070
2071	BERR_Code BKIR_GetDefaultCirParam (
2072	BKIR_ChannelHandle hChn, /* Device channel handle */
2073	BKIR_KirDevice device, /* device type to enable */
2074	CIR_Param pCustomCirParam / [output] Returns default setting */
2075	)
2076	{
2077	BERR_Code retCode = BERR_SUCCESS;
2078	const CIR_Param *pCirParam = NULL;
2079
2080	BSTD_UNUSED(hChn);
2081	switch (device)
2082	{
2083	case BKIR_KirDevice_eCirGI:
2084	pCirParam = &giParam;
2085	break;
2086	case BKIR_KirDevice_eCirSaE2050:
2087	pCirParam = &sa_e2050Param;
2088	break;
2089	case BKIR_KirDevice_eCirTwirp:
2090	pCirParam = &twirpParam;
2091	break;
2092	case BKIR_KirDevice_eCirSony:
2093	pCirParam = &sonyParam;
2094	break;
2095	case BKIR_KirDevice_eCirRecs80:
2096	pCirParam = &recs80Param;
2097	break;
2098	case BKIR_KirDevice_eCirRc5:
2099	pCirParam = &rc5Param;
2100	break;
2101	case BKIR_KirDevice_eCirUei:
2102	pCirParam = &ueiParam;
2103	break;
2104	case BKIR_KirDevice_eCirRfUei:
2105	pCirParam = &RfueiParam;
2106	break;
2107	case BKIR_KirDevice_eCirEchoStar:
2108	pCirParam = &echoDishRemoteParam;
2109	break;
2110	case BKIR_KirDevice_eCirNec:
2111	pCirParam = &necParam;
2112	break;
2113	case BKIR_KirDevice_eCirGISat:
2114	pCirParam = &giSatParam;
2115	break;
2116	case BKIR_KirDevice_eCirCustom:
2117	pCirParam = &(hChn->customCirParam);
2118	break;
2119	case BKIR_KirDevice_eCirRC6:
2120	pCirParam = &rC6Mode6AParam;
2121	break;
2122	case BKIR_KirDevice_eCirDirectvUhfr:
2123	pCirParam = &directvUHFParam;
2124	break;
2125	case BKIR_KirDevice_eCirEchostarUhfr:
2126	pCirParam = &echostarUHFParam;
2127	break;
2128	case BKIR_KirDevice_eCirRcmmRcu:
2129	pCirParam = &s_RCMMParam;
2130	break;
2131	case BKIR_KirDevice_eCirRstep:
2132	pCirParam = &rStepParam;
2133	break;
2134	case BKIR_KirDevice_eCirXmp2:
2135	pCirParam = &xmp2Param;
2136	break;
2137	case BKIR_KirDevice_eCirXmp2Ack:
2138	pCirParam = &xmp2AckParam;
2139	break;
2140	case BKIR_KirDevice_eCirRC6Mode0:
2141	pCirParam = &rC6Mode0Param;
2142	break;
2143	case BKIR_KirDevice_eCirRca:
2144	pCirParam = &rcaParam;
2145	break;
2146	case BKIR_KirDevice_eCirToshibaTC9012:
2147	pCirParam = &toshibaTC9012Param;
2148	break;
2149	default:
2150	retCode = BERR_TRACE(BERR_INVALID_PARAMETER);
2151	break;
2152	}
2153	if (retCode == BERR_SUCCESS)
2154	{
2155	BKNI_Memcpy ((void )pCustomCirParam, (void )pCirParam, sizeof(CIR_Param));
2156	}
2157
2158	return( retCode );
2159	}
2160
2161	BERR_Code BKIR_OpenChannel(
2162	BKIR_Handle hDev, /* Device handle */
2163	BKIR_ChannelHandle phChn, / [output] Returns channel handle */
2164	unsigned int channelNo, /* Channel number to open */
2165	const BKIR_ChannelSettings pChnDefSettings / Channel default setting */
2166	)
2167	{
2168	BERR_Code retCode = BERR_SUCCESS;
2169	BKIR_ChannelHandle hChnDev;
2170	uint32_t lval;
2171
2172	BDBG_ASSERT( hDev );
2173	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
2174
2175	hChnDev = NULL;
2176
2177	if( channelNo < hDev->maxChnNo )
2178	{
2179	if( hDev->hKirChn[channelNo] == NULL )
2180	{
2181	/* Alloc memory from the system heap */
2182	hChnDev = (BKIR_ChannelHandle) BKNI_Malloc( sizeof( BKIR_P_ChannelHandle ) );
2183	if( hChnDev == NULL )
2184	{
2185	*phChn = NULL;
2186	retCode = BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
2187	BDBG_ERR(("BKIR_OpenChannel: BKNI_malloc() failed\n"));
2188	goto done;
2189	}
2190
2191	BKIR_CHK_RETCODE( retCode, BKNI_CreateEvent( &(hChnDev->hChnEvent) ) );
2192	hChnDev->magicId = DEV_MAGIC_ID;
2193	hChnDev->hKir = hDev;
2194	hChnDev->chnNo = channelNo;
2195	hChnDev->irPort = pChnDefSettings->irPort;
2196	hChnDev->isCirMode = false;
2197	hChnDev->kirCb = NULL;
2198	hChnDev->cbData = NULL;
2199	hChnDev->customDevice = pChnDefSettings->customDevice;
2200	hDev->hKirChn[channelNo] = hChnDev;
2201
2202	/*
2203	* Offsets are based off of BSCA
2204	*/
2205	if (channelNo == 0)
2206	hChnDev->coreOffset = 0;
2207	#if BKIR_N_CHANNELS > 1
2208	else if (channelNo == 1)
2209	hChnDev->coreOffset = BCHP_KBD2_STATUS - BCHP_KBD1_STATUS;
2210	#if BKIR_N_CHANNELS > 2
2211	else if (channelNo == 2)
2212	hChnDev->coreOffset = BCHP_KBD3_STATUS - BCHP_KBD1_STATUS;
2213	#if BKIR_N_CHANNELS > 3
2214	else if (channelNo == 3)
2215	hChnDev->coreOffset = BCHP_KBD4_STATUS - BCHP_KBD1_STATUS;
2216	#endif
2217	#endif
2218	#endif
2219
2220	/*
2221	* Enable interrupt for this channel
2222	*/
2223	hChnDev->intMode = pChnDefSettings->intMode;
2224	if (hChnDev->intMode == true)
2225	{
2226	static const BINT_Id IntId[BKIR_N_CHANNELS] =
2227	{
2228	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438)
2229	BCHP_INT_ID_kbd1_irqen
2230	#elif BCHP_CHIP==7400
2231	BCHP_INT_ID_kbd1_irqen
2232	#elif (BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
2233	(BCHP_CHIP==3563) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7340) \|\| (BCHP_CHIP==7342) \|\| (BCHP_CHIP==3548) \|\| \
2234	(BCHP_CHIP==3556) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| (BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| \
2235	(BCHP_CHIP==7468) \|\| (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| \
2236	(BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
2237	BCHP_INT_ID_kbd1_irqen
2238	#else /* BCHP_CHIP==3560 */
2239	BCHP_INT_ID_kbd1
2240	#endif
2241	#if BKIR_N_CHANNELS > 1
2242	,BCHP_INT_ID_kbd2_irqen
2243	#if BKIR_N_CHANNELS > 2
2244	,BCHP_INT_ID_kbd3_irqen
2245	#if BKIR_N_CHANNELS > 3
2246	,BCHP_INT_ID_kbd4_irqen
2247	#endif
2248	#endif
2249	#endif
2250	};
2251	/*
2252	* Register and enable L2 interrupt.
2253	*/
2254	BKIR_CHK_RETCODE( retCode, BINT_CreateCallback(
2255	&(hChnDev->hChnCallback), hDev->hInterrupt, IntId[channelNo],
2256	BKIR_P_HandleInterrupt_Isr, (void *) hChnDev, 0x00 ) );
2257	BKIR_CHK_RETCODE( retCode, BINT_EnableCallback( hChnDev->hChnCallback ) );
2258
2259	BKNI_EnterCriticalSection();
2260
2261	/*
2262	* Enable KIR interrupt in UPG
2263	*/
2264	lval = BREG_Read32(hDev->hRegister, BCHP_IRQ0_IRQEN);
2265	if (channelNo == 0)
2266	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438)
2267	lval \|= BCHP_IRQ0_IRQEN_kbd1_irqen_MASK;
2268	#elif BCHP_CHIP==7400
2269	lval \|= BCHP_IRQ0_IRQEN_kbd1_irqen_MASK;
2270	#elif (BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
2271	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7340) \|\| (BCHP_CHIP==7342) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2272	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468)
2273	lval \|= BCHP_IRQ0_IRQEN_kbd1_irqen_MASK;
2274	#elif (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2275	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
2276	lval \|= BCHP_IRQ0_AON_IRQEN_kbd1_irqen_MASK;
2277	#else /* BCHP_CHIP==3560 \|\| BCHP_CHIP==3563 \|\| (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) */
2278	lval \|= BCHP_IRQ0_IRQEN_kbd1_MASK;
2279	#endif
2280	#if BKIR_N_CHANNELS > 1
2281	else if (channelNo == 1)
2282	#if (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2283	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7435)
2284	lval \|= BCHP_IRQ0_AON_IRQEN_kbd2_irqen_MASK;
2285	#else
2286	lval \|= BCHP_IRQ0_IRQEN_kbd2_irqen_MASK;
2287	#endif
2288	#if BKIR_N_CHANNELS > 2
2289	else if (channelNo == 2)
2290	#if (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2291	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7435)
2292	lval \|= BCHP_IRQ0_AON_IRQEN_kbd3_irqen_MASK;
2293	#else
2294	lval \|= BCHP_IRQ0_IRQEN_kbd3_irqen_MASK;
2295	#endif
2296	#if BKIR_N_CHANNELS > 3
2297	else if (channelNo == 3)
2298	lval \|= BCHP_IRQ0_IRQEN_kbd4_irqen_MASK;
2299	#endif
2300	#endif
2301	#endif
2302	BREG_Write32( hDev->hRegister, BCHP_IRQ0_IRQEN, lval );
2303
2304	/*
2305	* Enable KIR interrupt in KIR
2306	*/
2307	BKIR_P_EnableInt (hChnDev);
2308	#if (BCHP_CHIP==3560 \|\| BCHP_CHIP==3563) \|\| (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556)
2309	/* Auto select does not work because ir2_in is low, force to use ir1_in */
2310	BREG_Write32(hDev->hRegister, hChnDev->coreOffset + BCHP_KBD1_SWITCH_CONFIG, 0x00000006L);
2311	#endif
2312	BKNI_LeaveCriticalSection();
2313	}
2314	else
2315	{
2316	hChnDev->hChnCallback = NULL;
2317
2318	BKNI_EnterCriticalSection();
2319	/*
2320	* Disable KIR interrupt in UPG
2321	*/
2322	lval = BREG_Read32(hDev->hRegister, BCHP_IRQ0_IRQEN);
2323	if (channelNo == 0)
2324	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438)
2325	lval &= ~BCHP_IRQ0_IRQEN_kbd1_irqen_MASK;
2326	#elif (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| \
2327	(BCHP_CHIP==7118) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| (BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| \
2328	(BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| (BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468)
2329	lval &= ~BCHP_IRQ0_IRQEN_kbd1_irqen_MASK;
2330	#elif (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| \
2331	(BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
2332	lval &= ~BCHP_IRQ0_AON_IRQEN_kbd1_irqen_MASK;
2333	#else /* BCHP_CHIP==3560 \|\| BCHP_CHIP==3563 \|\| (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) */
2334	lval &= ~BCHP_IRQ0_IRQEN_kbd1_MASK;
2335	#endif
2336	#if BKIR_N_CHANNELS > 1
2337	else if (channelNo == 1)
2338	#if (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| \
2339	(BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7435)
2340	lval &= ~BCHP_IRQ0_AON_IRQEN_kbd2_irqen_MASK;
2341	#else
2342	lval &= ~BCHP_IRQ0_IRQEN_kbd2_irqen_MASK;
2343	#endif
2344	#if BKIR_N_CHANNELS > 2
2345	else if (channelNo == 2)
2346	#if (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425)\|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| \
2347	(BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7435)
2348	lval &= ~BCHP_IRQ0_AON_IRQEN_kbd3_irqen_MASK;
2349	#else
2350	lval &= ~BCHP_IRQ0_IRQEN_kbd3_irqen_MASK;
2351	#endif
2352	#if BKIR_N_CHANNELS > 3
2353	else if (channelNo == 3)
2354	lval &= ~BCHP_IRQ0_IRQEN_kbd4_irqen_MASK;
2355	#endif
2356	#endif
2357	#endif
2358	BREG_Write32( hDev->hRegister, BCHP_IRQ0_IRQEN, lval );
2359
2360	/*
2361	* Disable KIR interrupt in KIR
2362	*/
2363	BKIR_P_DisableInt (hChnDev);
2364	BKNI_LeaveCriticalSection();
2365	}
2366
2367	*phChn = hChnDev;
2368	}
2369	else
2370	{
2371	retCode = BERR_TRACE(BKIR_ERR_NOTAVAIL_CHN_NO);
2372	}
2373	}
2374	else
2375	{
2376	retCode = BERR_TRACE(BERR_INVALID_PARAMETER);
2377	}
2378
2379	done:
2380	if( retCode != BERR_SUCCESS )
2381	{
2382	if( hChnDev != NULL )
2383	{
2384	BKNI_DestroyEvent( hChnDev->hChnEvent );
2385	BKNI_Free( hChnDev );
2386	hDev->hKirChn[channelNo] = NULL;
2387	*phChn = NULL;
2388	}
2389	}
2390	return( retCode );
2391	}
2392
2393	BERR_Code BKIR_CloseChannel(
2394	BKIR_ChannelHandle hChn /* Device channel handle */
2395	)
2396	{
2397	BERR_Code retCode = BERR_SUCCESS;
2398	BKIR_Handle hDev;
2399	unsigned int chnNo;
2400
2401
2402	BDBG_ASSERT( hChn );
2403	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2404
2405	hDev = hChn->hKir;
2406	/*
2407	* Disable interrupt for this channel
2408	*/
2409	BKNI_EnterCriticalSection();
2410	BKIR_P_DisableInt (hChn);
2411	BKNI_LeaveCriticalSection();
2412
2413	if (hChn->hChnCallback) {
2414	BKIR_CHK_RETCODE( retCode, BINT_DisableCallback( hChn->hChnCallback ) );
2415	BKIR_CHK_RETCODE( retCode, BINT_DestroyCallback( hChn->hChnCallback ) );
2416	}
2417	hChn->kirCb = NULL;
2418	hChn->cbData = NULL;
2419	BKNI_DestroyEvent( hChn->hChnEvent );
2420	chnNo = hChn->chnNo;
2421	BKNI_Free( hChn );
2422	hDev->hKirChn[chnNo] = NULL;
2423
2424	done:
2425	return( retCode );
2426	}
2427
2428	BERR_Code BKIR_GetDevice(
2429	BKIR_ChannelHandle hChn, /* Device channel handle */
2430	BKIR_Handle phDev / [output] Returns Device handle */
2431	)
2432	{
2433	BERR_Code retCode = BERR_SUCCESS;
2434
2435
2436	BDBG_ASSERT( hChn );
2437	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2438
2439	*phDev = hChn->hKir;
2440
2441	return( retCode );
2442	}
2443
2444
2445	BERR_Code BKIR_EnableIrDevice (
2446	BKIR_ChannelHandle hChn, /* Device channel handle */
2447	BKIR_KirDevice device /* device type to enable */
2448	)
2449	{
2450	BERR_Code retCode = BERR_SUCCESS;
2451	uint32_t lval;
2452	BKIR_Handle hDev;
2453	bool isCirDevice = false;
2454	BKIR_KirDevice tempDevice;
2455
2456	BDBG_ASSERT( hChn );
2457	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2458
2459	hDev = hChn->hKir;
2460
2461	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
2462	switch( device )
2463	{
2464	case BKIR_KirDevice_eTwirpKbd:
2465	lval = lval \| KBD_CMD_TWIRP_ENABLE;
2466	break;
2467
2468	case BKIR_KirDevice_eSejin38KhzKbd:
2469	lval = (lval \| KBD_CMD_SEJIN_ENABLE) & ~BCHP_KBD1_CMD_alt_table_MASK;
2470	break;
2471
2472	case BKIR_KirDevice_eSejin56KhzKbd:
2473	lval = lval \| KBD_CMD_SEJIN_ENABLE \| BCHP_KBD1_CMD_alt_table_MASK;
2474	break;
2475
2476	case BKIR_KirDevice_eRemoteA:
2477	lval = lval \| KBD_CMD_REMOTE_A_ENABLE;
2478	break;
2479
2480	case BKIR_KirDevice_eRemoteB:
2481	lval = lval \| KBD_CMD_REMOTE_B_ENABLE;
2482	break;
2483
2484	case BKIR_KirDevice_eCirGI:
2485	case BKIR_KirDevice_eCirSaE2050:
2486	case BKIR_KirDevice_eCirTwirp:
2487	case BKIR_KirDevice_eCirSony:
2488	case BKIR_KirDevice_eCirRecs80:
2489	case BKIR_KirDevice_eCirRc5:
2490	case BKIR_KirDevice_eCirUei:
2491	case BKIR_KirDevice_eCirRfUei:
2492	case BKIR_KirDevice_eCirEchoStar:
2493	case BKIR_KirDevice_eCirNec:
2494	case BKIR_KirDevice_eCirGISat:
2495	case BKIR_KirDevice_eCirCustom:
2496	case BKIR_KirDevice_eCirDirectvUhfr:
2497	case BKIR_KirDevice_eCirEchostarUhfr:
2498	case BKIR_KirDevice_eCirRC6:
2499	case BKIR_KirDevice_eCirRcmmRcu:
2500	case BKIR_KirDevice_eCirRstep:
2501	case BKIR_KirDevice_eCirXmp2:
2502	case BKIR_KirDevice_eCirXmp2Ack:
2503	case BKIR_KirDevice_eCirRC6Mode0:
2504	case BKIR_KirDevice_eCirRca:
2505	case BKIR_KirDevice_eCirToshibaTC9012:
2506	isCirDevice = true;
2507	if ((device == BKIR_KirDevice_eCirUei) \|\| (device == BKIR_KirDevice_eCirDirectvUhfr) \|\| (device == BKIR_KirDevice_eCirRfUei))
2508	{
2509	/* This flag is used to read repeat flag in ISR.
2510	* This flag should apply to all CIR devices.
2511	* Until, we test more CIR devices, use it for
2512	* UEI device only.
2513	*/
2514	hChn->isCirMode = true;
2515	}
2516	if (device == BKIR_KirDevice_eCirCustom)
2517	{
2518	if ((hChn->customDevice == BKIR_KirDevice_eCirUei) \|\| (hChn->customDevice == BKIR_KirDevice_eCirDirectvUhfr) \|\| (hChn->customDevice == BKIR_KirDevice_eCirRfUei))
2519	{
2520	/* This flag is used to read repeat flag in ISR.
2521	* This flag should apply to all CIR devices.
2522	* Until, we test more CIR devices, use it for
2523	* UEI device only.
2524	*/
2525	hChn->isCirMode = true;
2526	}
2527	}
2528	lval = lval \| KBD_CMD_CIR_ENABLE;
2529	if ((device == BKIR_KirDevice_eCirRfUei) \|\|
2530	(device == BKIR_KirDevice_eCirDirectvUhfr) \|\|
2531	(device == BKIR_KirDevice_eCirEchostarUhfr) \|\|
2532	(device == BKIR_KirDevice_eCirRC6))
2533	lval &= 0xf0; /* disable TWIRP, SEJIN, REMOTE A, and REMOTE B */
2534
2535	if (device == BKIR_KirDevice_eCirCustom)
2536	{
2537	if ((hChn->customDevice == BKIR_KirDevice_eCirRfUei) \|\|
2538	(hChn->customDevice == BKIR_KirDevice_eCirDirectvUhfr) \|\|
2539	(hChn->customDevice == BKIR_KirDevice_eCirEchostarUhfr) \|\|
2540	(hChn->customDevice == BKIR_KirDevice_eCirRC6))
2541	lval &= 0xf0; /* disable TWIRP, SEJIN, REMOTE A, and REMOTE B */
2542	}
2543	break;
2544
2545	default:
2546	retCode = BERR_INVALID_PARAMETER;
2547	goto done;
2548	}
2549
2550	BDBG_MSG(("%s Write32(%x, %x)", __FUNCTION__, hChn->coreOffset + BCHP_KBD1_CMD, lval));
2551	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
2552
2553	/* Set KBD3.FILTER1 to 0x0000007F for UHF */
2554	tempDevice = device; /* to do special handling */
2555	if (device == BKIR_KirDevice_eCirCustom)
2556	{
2557	/* Use custom device to set special filter */
2558	tempDevice = hChn->customDevice ;
2559	}
2560	switch ( tempDevice )
2561	{
2562	case BKIR_KirDevice_eCirDirectvUhfr:
2563	case BKIR_KirDevice_eCirEchostarUhfr:
2564	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1, 0x0000003F \| BCHP_KBD1_FILTER1_filter_en_MASK);
2565	break;
2566	case BKIR_KirDevice_eCirUei:
2567	BDBG_MSG(("%s Write32(%x, %x -> %x)", __FUNCTION__, hChn->coreOffset + BCHP_KBD1_FILTER1, BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1), 0x00000034 \| BCHP_KBD1_FILTER1_filter_en_MASK));
2568	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1, 0x00000034 \| BCHP_KBD1_FILTER1_filter_en_MASK);
2569	break;
2570	case BKIR_KirDevice_eCirXmp2:
2571	case BKIR_KirDevice_eCirXmp2Ack:
2572	BDBG_MSG(("%s Write32(%x, %x -> %x)", __FUNCTION__, hChn->coreOffset + BCHP_KBD1_FILTER1, BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1), 0x00000011 \| BCHP_KBD1_FILTER1_filter_en_MASK));
2573	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1, 0x00000011 \| BCHP_KBD1_FILTER1_filter_en_MASK);
2574	break;
2575	default:
2576	BDBG_MSG(("%s Write32(%x, %x)", __FUNCTION__, hChn->coreOffset + BCHP_KBD1_FILTER1, 0x00000000 & ~BCHP_KBD1_FILTER1_filter_en_MASK));
2577	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1, 0x00000000 & ~BCHP_KBD1_FILTER1_filter_en_MASK);
2578	break;
2579	}
2580
2581	/* Program CIR reg file for CIR devices */
2582	if (isCirDevice)
2583	{
2584	BKIR_P_ConfigCir (hChn, device);
2585	}
2586
2587	done:
2588
2589	return( retCode );
2590	}
2591
2592	BERR_Code BKIR_DisableIrDevice (
2593	BKIR_ChannelHandle hChn, /* Device channel handle */
2594	BKIR_KirDevice device /* device type to enable */
2595	)
2596	{
2597	BERR_Code retCode = BERR_SUCCESS;
2598	uint32_t lval;
2599	BKIR_Handle hDev;
2600
2601	BDBG_ASSERT( hChn );
2602	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2603
2604	hDev = hChn->hKir;
2605
2606	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
2607
2608	switch( device )
2609	{
2610	case BKIR_KirDevice_eTwirpKbd:
2611	lval = lval & ~KBD_CMD_TWIRP_ENABLE;
2612	break;
2613
2614	case BKIR_KirDevice_eSejin38KhzKbd:
2615	case BKIR_KirDevice_eSejin56KhzKbd:
2616	lval = lval & ~KBD_CMD_SEJIN_ENABLE;
2617	break;
2618
2619	case BKIR_KirDevice_eRemoteA:
2620	lval = lval & ~KBD_CMD_REMOTE_A_ENABLE;
2621	break;
2622
2623	case BKIR_KirDevice_eRemoteB:
2624	lval = lval & ~KBD_CMD_REMOTE_B_ENABLE;
2625	break;
2626
2627	case BKIR_KirDevice_eCirGI:
2628	case BKIR_KirDevice_eCirSaE2050:
2629	case BKIR_KirDevice_eCirTwirp:
2630	case BKIR_KirDevice_eCirSony:
2631	case BKIR_KirDevice_eCirRecs80:
2632	case BKIR_KirDevice_eCirRc5:
2633	case BKIR_KirDevice_eCirUei:
2634	case BKIR_KirDevice_eCirRfUei:
2635	case BKIR_KirDevice_eCirEchoStar:
2636	case BKIR_KirDevice_eCirNec:
2637	case BKIR_KirDevice_eCirGISat:
2638	case BKIR_KirDevice_eCirCustom:
2639	case BKIR_KirDevice_eCirDirectvUhfr:
2640	case BKIR_KirDevice_eCirEchostarUhfr:
2641	case BKIR_KirDevice_eCirRC6:
2642	case BKIR_KirDevice_eCirRcmmRcu:
2643	case BKIR_KirDevice_eCirRstep:
2644	case BKIR_KirDevice_eCirXmp2:
2645	case BKIR_KirDevice_eCirXmp2Ack:
2646	case BKIR_KirDevice_eCirRC6Mode0:
2647	case BKIR_KirDevice_eCirRca:
2648	case BKIR_KirDevice_eCirToshibaTC9012:
2649	lval = lval & ~KBD_CMD_CIR_ENABLE;
2650	break;
2651	default:
2652	retCode = BERR_TRACE(BERR_INVALID_PARAMETER);
2653	goto done;
2654	}
2655
2656	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
2657	done:
2658	return( retCode );
2659	}
2660
2661	#if BKIR_HAS_DATA_FILTER
2662	BERR_Code BKIR_EnableDataFilter (
2663	BKIR_ChannelHandle hChn, /* Device channel handle */
2664	unsigned int pat0, /* pattern to match(LSB) */
2665	unsigned int pat1, /* pattern to match(MSB)*/
2666	unsigned int mask0, /* don's care bits in the pattern(LSB) */
2667	unsigned int mask1 /* don's care bits in the pattern(MSB) */
2668	)
2669	{
2670	BERR_Code retCode = BERR_SUCCESS;
2671	uint32_t lval;
2672	BKIR_Handle hDev;
2673
2674	BDBG_ASSERT( hChn );
2675	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2676
2677	hDev = hChn->hKir;
2678
2679	/* write pattern to match and mask bits */
2680	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_KBD_PAT0, pat0);
2681	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_KBD_PAT1, pat1);
2682	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_KBD_MASK0, mask0);
2683	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_KBD_MASK1, mask1);
2684
2685	/* enable data filtering based on pattern */
2686	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
2687	lval = (lval \| BCHP_KBD1_CMD_data_filtering_MASK);
2688	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
2689
2690	return( retCode );
2691	}
2692
2693	BERR_Code BKIR_DisableDataFilter (
2694	BKIR_ChannelHandle hChn /* Device channel handle */
2695	)
2696	{
2697	BERR_Code retCode = BERR_SUCCESS;
2698	uint32_t lval;
2699	BKIR_Handle hDev;
2700
2701	BDBG_ASSERT( hChn );
2702	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2703
2704	hDev = hChn->hKir;
2705
2706	/* disable data filtering */
2707	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
2708	lval = (lval & ~BCHP_KBD1_CMD_data_filtering_MASK);
2709	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
2710
2711	return( retCode );
2712	}
2713	#endif
2714
2715	BERR_Code BKIR_EnableFilter1 (
2716	BKIR_ChannelHandle hChn, /* Device channel handle */
2717	unsigned int filter_width /* filter width if smaller than this to be rejected */
2718	)
2719	{
2720	BERR_Code retCode = BERR_SUCCESS;
2721	uint32_t lval;
2722	BKIR_Handle hDev;
2723
2724	BDBG_ASSERT( hChn );
2725	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2726
2727	hDev = hChn->hKir;
2728
2729	/* enable filter1 and write filter width. */
2730	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1);
2731	lval &= ~BCHP_KBD1_FILTER1_filter_en_MASK;
2732	lval &= ~BCHP_KBD1_FILTER1_filter_width_MASK;
2733	lval = (lval \| BCHP_KBD1_FILTER1_filter_en_MASK \| filter_width);
2734	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1, lval);
2735
2736	return( retCode );
2737	}
2738
2739	BERR_Code BKIR_DisableFilter1 (
2740	BKIR_ChannelHandle hChn /* Device channel handle */
2741	)
2742	{
2743	BERR_Code retCode = BERR_SUCCESS;
2744	uint32_t lval;
2745	BKIR_Handle hDev;
2746
2747	BDBG_ASSERT( hChn );
2748	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2749
2750	hDev = hChn->hKir;
2751
2752	/* disable filter1 and clear filter width. */
2753	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1);
2754	lval &= ~BCHP_KBD1_FILTER1_filter_en_MASK;
2755	lval &= ~BCHP_KBD1_FILTER1_filter_width_MASK;
2756	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_FILTER1, lval);
2757
2758	return( retCode );
2759	}
2760
2761	BERR_Code BKIR_DisableAllIrDevices (
2762	BKIR_ChannelHandle hChn /* Device channel handle */
2763	)
2764	{
2765	BERR_Code retCode = BERR_SUCCESS;
2766	uint32_t lval;
2767	BKIR_Handle hDev;
2768
2769	BDBG_ASSERT( hChn );
2770	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2771
2772	hDev = hChn->hKir;
2773
2774	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
2775
2776	lval &= ~( KBD_CMD_TWIRP_ENABLE \|
2777	KBD_CMD_SEJIN_ENABLE \|
2778	KBD_CMD_REMOTE_A_ENABLE \|
2779	KBD_CMD_REMOTE_B_ENABLE \|
2780	KBD_CMD_CIR_ENABLE);
2781
2782	BDBG_WRN(("%s Write32(%x, %x)", __FUNCTION__, hChn->coreOffset + BCHP_KBD1_CMD, lval));
2783	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
2784
2785	return( retCode );
2786	}
2787
2788	BERR_Code BKIR_GetEventHandle(
2789	BKIR_ChannelHandle hChn, /* Device channel handle */
2790	BKNI_EventHandle phEvent / [output] Returns event handle */
2791	)
2792	{
2793	BERR_Code retCode = BERR_SUCCESS;
2794
2795
2796	BDBG_ASSERT( hChn );
2797	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2798
2799	*phEvent = hChn->hChnEvent;
2800
2801	return( retCode );
2802	}
2803
2804
2805
2806	BERR_Code BKIR_IsDataReady (
2807	BKIR_ChannelHandle hChn, /* Device channel handle */
2808	bool dataReady / [output] flag to indicate if data is ready */
2809	)
2810	{
2811	BERR_Code retCode = BERR_SUCCESS;
2812	uint32_t lval;
2813	BKIR_Handle hDev;
2814
2815	BDBG_ASSERT( hChn );
2816	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2817
2818	hDev = hChn->hKir;
2819
2820	/*
2821	* This function should only be called when polling for data ready.
2822	* If interrupt is enabled, the caller should pend on interrupt event
2823	*/
2824	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS);
2825	*dataReady = (lval & BCHP_KBD1_STATUS_irq_MASK) ? true : false;
2826
2827	return( retCode );
2828	}
2829
2830
2831	BERR_Code BKIR_Read_Isr(
2832	BKIR_ChannelHandle hChn, /* Device channel handle */
2833	BKIR_KirInterruptDevice pDevice, / [output] pointer to IR device type that generated the key */
2834	unsigned char data / [output] pointer to data received */
2835	)
2836	{
2837	BERR_Code retCode = BERR_SUCCESS;
2838	uint32_t lval;
2839	BKIR_Handle hDev;
2840
2841	BDBG_ASSERT( hChn );
2842	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2843
2844	hDev = hChn->hKir;
2845
2846	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS);
2847	*pDevice = (BKIR_KirInterruptDevice)((lval & KBD_STATUS_DEVICE_MASK) >> KBD_STATUS_DEVICE_SHIFTS);
2848
2849	#if (BCHP_CHIP==3560) \|\| (BCHP_CHIP==3563) \|\| (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| \
2850	(BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| (BCHP_CHIP==7336) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
2851	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2852	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| \
2853	(BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
2854	/* 3560 and 7401 data registers consist of 32-bit wide registers, not byte-wide */
2855	{
2856	uint32_t data0 = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA0);
2857	uint32_t data1 = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA1);
2858	data[0] = data0 & 0xff;
2859	data[1] = data0 >> 8 & 0xff;
2860	data[2] = data0 >> 16 & 0xff;
2861	data[3] = data0 >> 24 & 0xff;
2862	data[4] = data1 & 0xff;
2863	#if BKIR_HAS_DATA_FILTER
2864	/* 7550 can store up to 48 bit */
2865	data[5] = data1 >> 8 & 0xff;
2866	#endif
2867	}
2868	#else
2869	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438)
2870	#if BCHP_VER >= BCHP_VER_C0
2871	data[4] = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA4);
2872	#endif
2873	data[3] = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA3);
2874	data[2] = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA2);
2875	#else
2876	data[3] = data[2] = 0;
2877	#endif
2878	data[1] = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA1);
2879	data[0] = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_DATA0);
2880	#endif
2881
2882
2883	#if 0
2884	/* Clear interrupt */
2885	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS);
2886	lval &= ~BCHP_KBD1_STATUS_irq_MASK;
2887	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS, lval);
2888	#endif
2889
2890	return( retCode );
2891	}
2892
2893
2894	BERR_Code BKIR_Read(
2895	BKIR_ChannelHandle hChn, /* Device channel handle */
2896	BKIR_KirInterruptDevice pDevice, / [output] pointer to IR device type that generated the key */
2897	unsigned char data / [output] pointer to data received */
2898	)
2899	{
2900	BERR_Code rc;
2901
2902	BKNI_EnterCriticalSection();
2903	rc = BKIR_Read_Isr (hChn, pDevice, data);
2904	BKNI_LeaveCriticalSection();
2905
2906	return rc;
2907	}
2908
2909	BERR_Code BKIR_IsRepeated(
2910	BKIR_ChannelHandle hChn, /* [in] Device channel handle */
2911	bool repeatFlag / [out] flag to remote A repeat condition */
2912	)
2913	{
2914	BERR_Code retCode = BERR_SUCCESS;
2915
2916	BDBG_ASSERT( hChn );
2917	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2918
2919	*repeatFlag = hChn->repeatFlag;
2920
2921	return( retCode );
2922	}
2923
2924	BERR_Code BKIR_IsPreambleA(
2925	BKIR_ChannelHandle hChn, /* [in] Device channel handle */
2926	bool preambleFlag / [out] flag to remote A repeat condition */
2927	)
2928	{
2929	BERR_Code retCode = BERR_SUCCESS;
2930
2931	BDBG_ASSERT( hChn );
2932	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2933
2934	*preambleFlag = hChn->cir_pa;
2935
2936	return( retCode );
2937	}
2938
2939	BERR_Code BKIR_IsPreambleB(
2940	BKIR_ChannelHandle hChn, /* [in] Device channel handle */
2941	bool preambleFlag / [out] flag to remote A repeat condition */
2942	)
2943	{
2944	BERR_Code retCode = BERR_SUCCESS;
2945
2946	BDBG_ASSERT( hChn );
2947	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2948
2949	*preambleFlag = hChn->cir_pb;
2950
2951	return( retCode );
2952	}
2953
2954	void BKIR_SetCustomDeviceType (
2955	BKIR_ChannelHandle hChn, /* Device channel handle */
2956	BKIR_KirDevice customDevice /* device that this custom cir is used for */
2957	)
2958	{
2959	hChn->customDevice = customDevice;
2960	}
2961
2962	void BKIR_SetCustomCir (
2963	BKIR_ChannelHandle hChn, /* Device channel handle */
2964	CIR_Param *pCirParam
2965	)
2966	{
2967	BSTD_UNUSED(hChn);
2968	BKNI_Memcpy ((void )&(hChn->customCirParam), (void )pCirParam, sizeof(CIR_Param));
2969	}
2970
2971	void BKIR_RegisterCallback (
2972	BKIR_ChannelHandle hChn, /* Device channel handle */
2973	BKIR_Callback callback, /* Callback function to register */
2974	void pData / Data passed to callback function */
2975	)
2976	{
2977	BDBG_ASSERT( hChn );
2978	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2979
2980	hChn->kirCb = callback;
2981	hChn->cbData = pData;
2982	}
2983
2984	void BKIR_UnregisterCallback (
2985	BKIR_ChannelHandle hChn /* Device channel handle */
2986	)
2987	{
2988	BDBG_ASSERT( hChn );
2989	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
2990
2991	hChn->kirCb = NULL;
2992	hChn->cbData = NULL;
2993	}
2994
2995	/*******************************************************************************
2996	*
2997	* Private Module Functions
2998	*
2999	*******************************************************************************/
3000	void BKIR_P_EnableInt(
3001	BKIR_ChannelHandle hChn /* Device channel handle */
3002	)
3003	{
3004	uint32_t lval;
3005	BKIR_Handle hDev;
3006
3007	hDev = hChn->hKir;
3008	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS, 0); /* clear any previous interrupt */
3009	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
3010	lval \|= BCHP_KBD1_CMD_kbd_irqen_MASK;
3011	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
3012
3013	}
3014
3015	void BKIR_P_DisableInt(
3016	BKIR_ChannelHandle hChn /* Device channel handle */
3017	)
3018	{
3019	uint32_t lval;
3020	BKIR_Handle hDev;
3021
3022	hDev = hChn->hKir;
3023
3024	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD);
3025	lval &= ~BCHP_KBD1_CMD_kbd_irqen_MASK;
3026	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CMD, lval);
3027
3028	}
3029
3030	static void BKIR_P_HandleInterrupt_Isr
3031	(
3032	void pParam1, / Device channel handle */
3033	int parm2 /* not used */
3034	)
3035	{
3036	BKIR_ChannelHandle hChn;
3037	BKIR_Handle hDev;
3038	uint32_t lval;
3039	BSTD_UNUSED(parm2);
3040
3041	hChn = (BKIR_ChannelHandle) pParam1;
3042	BDBG_ASSERT( hChn );
3043
3044	hDev = hChn->hKir;
3045	/* Clear interrupt */
3046	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS);
3047
3048	/* Check if preamble is detected */
3049	hChn->cir_pa = false;
3050	hChn->cir_pb = false;
3051
3052	/* If we're in Cir Mode then test the 'cir_pb' status for repeat keys. */
3053	if ( hChn->isCirMode )
3054	{
3055	hChn->cir_pa = (lval & BCHP_KBD1_STATUS_cir_pa_MASK) ? true : false;
3056	hChn->cir_pb = (lval & BCHP_KBD1_STATUS_cir_pb_MASK) ? true : false;
3057	hChn->repeatFlag = (lval & BCHP_KBD1_STATUS_cir_pb_MASK) ? true : false;
3058	}
3059	else
3060	{
3061	hChn->cir_pa = (lval & BCHP_KBD1_STATUS_cir_pa_MASK) ? true : false;
3062	hChn->cir_pb = (lval & BCHP_KBD1_STATUS_cir_pb_MASK) ? true : false;
3063	hChn->repeatFlag = (lval & BCHP_KBD1_STATUS_rflag_MASK) ? true : false;
3064	}
3065
3066	lval &= ~BCHP_KBD1_STATUS_irq_MASK;
3067	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_STATUS, lval);
3068
3069	/*
3070	* Call any callback function if installed
3071	*/
3072	if (hChn->kirCb)
3073	{
3074	(*hChn->kirCb)( hChn, hChn->cbData );
3075	}
3076
3077	BKNI_SetEvent( hChn->hChnEvent );
3078	return;
3079	}
3080
3081	void BKIR_P_WriteCirParam (
3082	BKIR_ChannelHandle hChn, /* Device channel handle */
3083	uint32_t addr,
3084	uint32_t data
3085	)
3086	{
3087	BKIR_Handle hDev;
3088	uint32_t lval;
3089
3090	hDev = hChn->hKir;
3091	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CIR_ADDR, addr);
3092	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438)
3093	lval = (data >> 8) & 0xFF;
3094	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CIR_DATA1, lval);
3095	lval = data& 0xFF;
3096	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CIR_DATA0, lval);
3097	#elif (BCHP_CHIP==3560) \|\| (BCHP_CHIP==3563) \|\| (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| \
3098	(BCHP_CHIP==7420) \|\| (BCHP_CHIP==7118) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7340) \|\| \
3099	(BCHP_CHIP==7342) \|\| (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| (BCHP_CHIP==7125) \|\| \
3100	(BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| \
3101	(BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
3102	lval = data& 0xFFF;
3103	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_KBD1_CIR_DATA, lval);
3104	#else
3105	#error "Not supported"
3106	#endif
3107	}
3108
3109	void BKIR_P_ConfigCir (
3110	BKIR_ChannelHandle hChn, /* Device channel handle */
3111	BKIR_KirDevice device /* device type to enable */
3112	)
3113	{
3114	uint32_t ulData;
3115	uint32_t uli, ulj;
3116	const CIR_Param *pCirParam;
3117	BKIR_Handle hDev;
3118
3119	hDev = hChn->hKir;
3120	switch (device)
3121	{
3122	case BKIR_KirDevice_eCirGI:
3123	pCirParam = &giParam;
3124	break;
3125	case BKIR_KirDevice_eCirSaE2050:
3126	pCirParam = &sa_e2050Param;
3127	break;
3128	case BKIR_KirDevice_eCirTwirp:
3129	pCirParam = &twirpParam;
3130	break;
3131	case BKIR_KirDevice_eCirSony:
3132	pCirParam = &sonyParam;
3133	break;
3134	case BKIR_KirDevice_eCirRecs80:
3135	pCirParam = &recs80Param;
3136	break;
3137	case BKIR_KirDevice_eCirRc5:
3138	pCirParam = &rc5Param;
3139	break;
3140	case BKIR_KirDevice_eCirUei:
3141	pCirParam = &ueiParam;
3142	break;
3143	case BKIR_KirDevice_eCirRfUei:
3144	pCirParam = &RfueiParam;
3145	break;
3146	case BKIR_KirDevice_eCirEchoStar:
3147	pCirParam = &echoDishRemoteParam;
3148	break;
3149	case BKIR_KirDevice_eCirNec:
3150	pCirParam = &necParam;
3151	break;
3152	case BKIR_KirDevice_eCirGISat:
3153	pCirParam = &giSatParam;
3154	break;
3155	case BKIR_KirDevice_eCirCustom:
3156	pCirParam = &(hChn->customCirParam);
3157	break;
3158	case BKIR_KirDevice_eCirRC6:
3159	pCirParam = &rC6Mode6AParam;
3160	break;
3161	case BKIR_KirDevice_eCirDirectvUhfr:
3162	pCirParam = &directvUHFParam;
3163	break;
3164	case BKIR_KirDevice_eCirEchostarUhfr:
3165	pCirParam = &echostarUHFParam;
3166	break;
3167	case BKIR_KirDevice_eCirRcmmRcu:
3168	pCirParam = &s_RCMMParam;
3169	break;
3170	case BKIR_KirDevice_eCirRstep:
3171	pCirParam = &rStepParam;
3172	break;
3173	case BKIR_KirDevice_eCirXmp2:
3174	pCirParam = &xmp2Param;
3175	break;
3176	case BKIR_KirDevice_eCirXmp2Ack:
3177	pCirParam = &xmp2AckParam;
3178	break;
3179	case BKIR_KirDevice_eCirRC6Mode0:
3180	pCirParam = &rC6Mode0Param;
3181	break;
3182	case BKIR_KirDevice_eCirRca:
3183	pCirParam = &rcaParam;
3184	break;
3185	case BKIR_KirDevice_eCirToshibaTC9012:
3186	pCirParam = &toshibaTC9012Param;
3187	break;
3188	default:
3189	return;
3190	}
3191
3192	BKIR_P_WriteCirParam (hChn, 0, pCirParam->frameTimeout);
3193
3194	ulData = (pCirParam->stop.tol << 10) \| (pCirParam->stop.val);
3195	BKIR_P_WriteCirParam (hChn, 1, ulData);
3196
3197	ulData = (pCirParam->pbCount << 3) \| pCirParam->paCount;
3198	BKIR_P_WriteCirParam (hChn, 2, ulData);
3199
3200	for (uli=0, ulj=3; uli<4; uli++) {
3201	ulData = ((pCirParam->pa)[uli].tol << 10) \| (pCirParam->pa)[uli].val;
3202	BKIR_P_WriteCirParam (hChn, ulj++, ulData);
3203	ulData = ((pCirParam->pb)[uli].tol << 10) \| (pCirParam->pb)[uli].val;
3204	BKIR_P_WriteCirParam (hChn, ulj++, ulData);
3205	}
3206
3207	/* 6th bit needed 48 bit support for symbol A is in bit 11 for backward compatibility. */
3208	ulData = (pCirParam->nSymB << 5) \| (pCirParam->nSymA & 0x1F) \| ((pCirParam->nSymA >> 5) << 11);
3209	BKIR_P_WriteCirParam (hChn, 11, ulData);
3210
3211	ulData = (pCirParam->symPulseWidth.tol << 10) \| pCirParam->symPulseWidth.val;
3212	BKIR_P_WriteCirParam (hChn, 12, ulData);
3213
3214	ulData = (pCirParam->spacingTol.tol << 10) \| pCirParam->spacingTol.val;
3215	BKIR_P_WriteCirParam (hChn, 13, ulData);
3216
3217	BKIR_P_WriteCirParam (hChn, 14, pCirParam->t0);
3218	BKIR_P_WriteCirParam (hChn, 15, pCirParam->delT);
3219	BKIR_P_WriteCirParam (hChn, 16, pCirParam->countDivisor);
3220	BKIR_P_WriteCirParam (hChn, 17, pCirParam->pulseTol);
3221
3222	ulData = (pCirParam->varLenData << 11)
3223	\| (pCirParam->chkStopSym << 10)
3224	\| (pCirParam->twoSymPerCy << 9)
3225	\| (pCirParam->biphaseCoded << 8)
3226	\| (pCirParam->mostSignifSymRecvFirst << 7)
3227	\| (pCirParam->leftAdjustRecvData << 6)
3228	\| (pCirParam->pbRepeat << 5)
3229	\| (pCirParam->measurePreamblePulse << 4)
3230	\| (pCirParam->measureSymPulse << 3)
3231	\| (pCirParam->fixSymPulseLast << 2)
3232	\| (pCirParam->bitsPerSym & 3);
3233	BKIR_P_WriteCirParam (hChn, 18, ulData);
3234
3235	BKIR_P_WriteCirParam (hChn, 19, pCirParam->timeoutDivisor);
3236	BKIR_P_WriteCirParam (hChn, 20, pCirParam->edgeTimeout);
3237	BKIR_P_WriteCirParam (hChn, 21, pCirParam->faultDeadTime);
3238	BKIR_P_WriteCirParam (hChn, 22, pCirParam->dataSymTimeout);
3239
3240	#if (BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7340) \|\| \
3241	(BCHP_CHIP==7342) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| (BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
3242	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7231) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| \
3243	(BCHP_CHIP==7640) \|\| (BCHP_CHIP==7435)
3244	BKIR_P_WriteCirParam(hChn, 23, pCirParam->repeatTimeout);
3245
3246	ulData = (pCirParam->havePreambleAftStop << 5)
3247	\| (pCirParam->enHavePreambleAftStop << 4)
3248	\| (pCirParam->dataSymTimerExpStatEn << 3)
3249	\| (pCirParam->ignoreDataSymTimerEdge1 << 2)
3250	\| (pCirParam->stopParamUnit << 1)
3251	\| (pCirParam->dataSymClkTickUnit);
3252	BKIR_P_WriteCirParam(hChn, 25, ulData);
3253
3254	ulData = (pCirParam->restrictiveDecode << 10)
3255	\| (pCirParam->passModeCustCodePass << 8)
3256	\| (pCirParam->dontValidateMode << 7)
3257	\| (pCirParam->dontValidateTrailer << 6)
3258	\| (pCirParam->dontValidateCustCode << 5)
3259	\| (pCirParam->modeBits << 2)
3260	\| (pCirParam->trailer << 1)
3261	\| (pCirParam->rc6);
3262	BKIR_P_WriteCirParam(hChn, 26, ulData);
3263
3264	ulData = (pCirParam->nCustCodeBits << 16)
3265	\| (pCirParam->custCode);
3266	BKIR_P_WriteCirParam(hChn, 27, ulData);
3267	#endif
3268	}
3269

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/kir/7552/bkir.c

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