source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/tnr/7552/btnr_init.c

Last change on this file was 2, checked in by jglee, 11 years ago

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1/*************************************************************************
2*     (c)2005-2012 Broadcom Corporation
3*
4*  This program is the proprietary software of Broadcom Corporation and/or its licensors,
5*  and may only be used, duplicated, modified or distributed pursuant to the terms and
6*  conditions of a separate, written license agreement executed between you and Broadcom
7*  (an "Authorized License").  Except as set forth in an Authorized License, Broadcom grants
8*  no license (express or implied), right to use, or waiver of any kind with respect to the
9*  Software, and Broadcom expressly reserves all rights in and to the Software and all
10*  intellectual property rights therein.  IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11*  HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12*  NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE.
13*
14* $brcm_Workfile: btnr_init.c $
15* $brcm_Revision: 32 $
16* $brcm_Date: 3/23/12 2:52p $
17*
18* [File Description:]
19*
20* Revision History:
21*
22 * $brcm_Log: /AP/ctfe/core/tnr/btnr_init.c $
23 *
24 * 32   3/23/12 2:52p farshidf
25 * SW3128-125: FW version 4.6
26 *
27 * Fw_Integration_Devel/18   3/23/12 2:51p farshidf
28 * SW3128-125: FW version 4.6
29 *
30 * Fw_Integration_Devel/AP_V4_0_TNR_DEV/4   3/12/12 6:09p farshidf
31 * SW3462-6: merge top Dev branch
32 *
33 * Fw_Integration_Devel/AP_V4_0_TNR_DEV/SW3462-6/2   2/29/12 5:27p farshidf
34 * SW3461-165 : Chip version clean up & fix tuner for 3462
35 *
36 * Fw_Integration_Devel/AP_V4_0_TNR_DEV/SW3462-6/1   2/28/12 6:04p mpovich
37 * SW3462-6: Rebase with SW3462-3 dev. branch.  Important Note:  Element 4
38 *  changes of V3_0 TNR Dev not picked up.
39 *
40 * Fw_Integration_Devel/AP_V3_0_TNR_DEV/SW3462-3/1   2/28/12 10:08a jputnam
41 * SW3462-5: Temporary change to force use of TNR_CORE_V_1_1 for 3462A0
42 *  until proper version methodology is adopted in the tuner driver
43 *
44 * Fw_Integration_Devel/AP_V3_0_TNR_DEV/4   1/23/12 5:28p cbrooks
45 * sw3461-1:added new breakpoints for the ACI filters
46 *
47 * Fw_Integration_Devel/AP_V4_0_TNR_DEV/1   2/9/12 11:48a cbrooks
48 * sw3461-1:fixed baud rate droppouts
49 *
50 * Fw_Integration_Devel/AP_V3_0_TNR_DEV/4   1/23/12 5:28p cbrooks
51 * sw3461-1:added new breakpoints for the ACI filters
52 *
53 * Fw_Integration_Devel/AP_V3_0_TNR_DEV/3   1/18/12 10:11a jputnam
54 * SW3461-88: Update UFE AGC thresholds for better compromise between LTE
55 *  and impulse noise performance
56 *
57 * Fw_Integration_Devel/AP_V3_0_TNR_DEV/2   12/26/11 8:49p shchang
58 * SW3461-120: modify AGC threshold settings for DVB-T LTE scenarios
59 *
60 * Fw_Integration_Devel/AP_V3_0_TNR_DEV/1   9/26/11 5:31p mbsingh
61 * SW3461-1: Incorporate correct register writes for B0
62 *
63 * Fw_Integration_Devel/12   9/22/11 4:44p farshidf
64 * SW3461-1: merge to integ
65 *
66 * Fw_Integration_Devel/AP_V2_0_TNR_DEV/3   9/21/11 4:14p farshidf
67 * SW3461-1: update files for B0
68 *
69 * Fw_Integration_Devel/AP_V2_0_TNR_DEV/2   9/7/11 11:31a jputnam
70 * SW3461-1: Added new UFE filter coefficients for SmartTune
71 *  FreqPlanAlternate
72 *
73 * 25   8/26/11 3:45p farshidf
74 * SW3461-1: merge to main
75 *
76 * Fw_Integration_Devel/10   8/26/11 3:38p farshidf
77 * SW3461-1: merge to integ
78 *
79 * Fw_Integration_Devel/AP_V2_0_TNR_DEV/1   8/24/11 4:51p mbsingh
80 * bcm3461-1: Removing Terrestrial Init() to save code size. This function
81 *  is not required.
82 *
83 * Fw_Integration_Devel/8   8/2/11 6:39p farshidf
84 * SW3461-1: fix compile issue
85 *
86 * Fw_Integration_Devel/7   8/2/11 6:20p farshidf
87 * SW3461-1: merge to integ
88 *
89 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/7   8/2/11 6:11p farshidf
90 * SW3461-1: update the tuner structure
91 *
92 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/6   7/29/11 1:59p jputnam
93 * SW3461-1: Added AGC control for external low-IF tuner
94 *
95 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/5   7/27/11 1:12p farshidf
96 * SW3461-1: make it maganum compatible
97 *
98 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/4   7/14/11 5:35p cbrooks
99 * sw3461-1:removed print statements
100 *
101 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/3   7/14/11 5:21p cbrooks
102 * sw3461-1:added callback support for gains
103 *
104 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/2   7/7/11 4:47p cbrooks
105 * SW3461-1:working on callbacak functions and status
106 *
107 * Fw_Integration_Devel/AP_V0_6_TNR_DEV/1   7/1/11 3:19p cbrooks
108 * sw3461-1:added ADS callback support
109 *
110 * Fw_Integration_Devel/2   7/19/11 7:43p farshidf
111 * SW3461-1: compile fix
112 *
113 * Fw_Integration_Devel/1   6/29/11 12:39p farshidf
114 * SW3461-13: merge to integration branch
115 *
116 * Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/2   6/22/11 6:52p cbrooks
117 * sw3461-1:fixed bug
118 *
119 * Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/1   6/22/11 6:47p cbrooks
120 * sw3461-1:Added Callback Support
121 *
122 * 20   6/12/11 12:41p farshidf
123 * SW3461-1: clean up
124 *
125 * 19   6/12/11 12:35p farshidf
126 * SW3461-1: code clean up
127 *
128 * 18   6/9/11 6:40p mpovich
129 * SW3461-1: Merge Ver 0.4 Integ. onto main branch.
130 *
131 * SW_System_4_Integ_Test/2   6/9/11 4:48p farshidf
132 * SW3461-1: sync up with 7552 code
133*
134* 17   5/20/11 6:43a mpovich
135* SW3461-1: rename UFE (BUFE) module to TNR (BTNR).
136*
137* TNR_3461_1/1   5/19/11 5:12p mpovich
138* SW3461-1: Change BUFE module prefix to BTNR
139*
140* 16   5/3/11 1:40p mpovich
141* SW3461-1: Merge to main of intermediate label, FW_3461_A0_05022011_1100
142*  (05/02/2011 Pace build).
143*
144* TNR_3461_1/5   5/2/11 6:13p lukose
145* SW3461-1: Added sensitivity improvements in TerrestrialInit function
146*
147* 15   4/19/11 3:50p farshidf
148* SW3461-1: merge main
149*
150* TNR_3461_1/4   4/13/11 7:41p cbrooks
151* sw3461-1:added reset to fix ds core code
152*
153* TNR_3461_1/3   3/22/11 4:02p jputnam
154* SW3461-1: Change AGC back-offs from 10dB to 15dB to slightly reduce
155*  sprinkle in high-QAM constellations
156*
157* TNR_3461_1/2   3/18/11 4:07p farshidf
158* SW3461-1: merge  main
159*
160* 13   3/18/11 4:06p farshidf
161* SW3461-1: merge to main
162*
163* TNR_3461_1/1   3/12/11 2:58p cbrooks
164* sw3461-1added hanli changes to init.c
165*
166* 9   3/9/11 7:21p cbrooks
167* sw3461-1:added tnr programming code
168*
169* 8   3/3/11 12:40p farshidf
170* SW3461-1: update the power seq
171*
172* 7   3/2/11 4:58p mpovich
173* SW3461-1: Fix TNR struct compiler bugs.  Add HAB related updates for T2
174*  and for TNR.
175*
176* Rom_Devel_3461/1   3/2/11 4:21p mpovich
177* SW3461-1: Fix TNR struct compiler bugs.  Add HAB related updates for T2
178*  and for TNR.
179*
180* 6   2/28/11 3:38p cbrooks
181* SW3461-1:new code for tuner
182*
183* 5   2/24/11 3:18p farshidf
184* SW3461-1: update the code for tuner
185*
186* 4   2/24/11 11:34a farshidf
187* SW3461-1: add the tuner code
188*
189*
190***************************************************************************/
191#include "bstd.h"
192#include "bkni.h"
193#include "bmth.h"
194#include "btmr.h"
195#ifndef LEAP_BASED_CODE
196#include "btnr.h"
197#include "bdbg.h"
198#include "btnr_priv.h"
199#include "btnr_3x7x_priv.h"
200#else
201#include "btnr_api.h"
202#endif
203
204#include "bchp_ufe.h"
205#include "bchp_ufe_misc.h"
206#include "bchp_ufe_misc2.h"
207#include "bchp_ufe_saw.h"
208#include "btnr_struct.h"
209
210#include "btnr_init.h"
211#include "btnr_tune.h"
212#include "btnr_global_clk.h"
213#include "bchp_ufe_afe.h"
214
215#ifndef LEAP_BASED_CODE
216BDBG_MODULE(btnr_init);
217#define POWER2_31 2147483648UL
218#define POWER2_16 65536
219#define LOG10_POWER2_9_X5120 13871
220#define Twos_Complement32(x) ((uint32_t)((x ^ 0xFFFFFFFF) + 1))
221#endif
222
223#define BCHP_UFE_MISC_CTRL_CLKGEN_DATA_RESET_SHIFT     BCHP_UFE_MISC_CTRL_DATA_RESET_SHIFT
224#define BCHP_UFE_MISC_CTRL_CLKGEN_DATA_RESET_MASK  (BCHP_UFE_MISC_CTRL_DATA_RESET_MASK | BCHP_UFE_MISC_CTRL_CLKGEN_RESET_MASK)
225
226#if 0
227/******************************************************************************
228*  BTNR_3x7x_P_TerrestrialInit
229******************************************************************************/
230BERR_Code BTNR_P_TerrestrialInit(BTNR_3x7x_Handle hTnr)
231{
232
233
234
235/*      BREG_Write32(hTnr->hRegister, BCHP_UFE_MISC2_CLK_RESET, 0x00000000 ); */
236
237        BREG_Write32(hTnr->hRegister, BCHP_UFE_CTRL,            0x001B000A );
238        BREG_Write32(hTnr->hRegister, BCHP_UFE_BYP,             0x00001004 );
239        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0xC0000FFF );        /* reset the clock gen after BYP/CIC programming */
240        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0x40000FFF );        /* clear clock gen reset, but hold datapath reset*/
241        BREG_Write32(hTnr->hRegister, BCHP_UFE_DCO_CTRL,        0x00000008 );
242        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1,            0x0000000D );
243        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2,            0x0000000B );
244        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3,            0x00000009 );
245        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
246        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
247        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
248        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_AMP_CTRL,  0x00000007 );
249        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_PHS_CTRL,  0x00000007 );
250        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF0,      0x00000076 );
251        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF1,      0x000000D6 );
252        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF2,      0x0007FF7B );
253        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF3,      0x0007FF2A );
254        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF4,      0x0000018A );
255        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF5,      0x0000004B );
256        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF6,      0x0007FD32 );
257        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF7,      0x000001A9 );
258        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF8,      0x0000032C );
259        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF9,      0x0007FB02 );
260        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF10,     0x0007FF06 );
261        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF11,     0x0000082C );
262        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF12,     0x0007FB27 );
263        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF13,     0x0007F7F4 );
264        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF14,     0x00000D12 );
265        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF15,     0x00000149 );
266        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF16,     0x0007ECD0 );
267        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF17,     0x00000CF2 );
268        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF18,     0x00001067 );
269        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF19,     0x0007E1B1 );
270        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF20,     0x000000F6 );
271        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF21,     0x000028A2 );
272        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF22,     0x0007DF25 );
273        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF23,     0x0007E192 );
274        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF24,     0x000045EC );
275        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF25,     0x0007F389 );
276        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF26,     0x0007A36C );
277        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF27,     0x000060BC );
278        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF28,     0x0000444C );
279        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF29,     0x000709F6 );
280        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF30,     0x000070D3 );
281        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF31,     0x0003FFFF );
282        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF32,     0x00000000 );
283        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0x40000000 );        /* clear clock gen reset, but hold datapath reset */
284        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1_LF,         0x06000000 );
285        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2_LF,         0x02000000 );
286        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3_LF,         0x02000000 );
287        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_AMP_LF,    0x00000000 );
288        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_PHS_LF,    0x00000000 );
289        BREG_Write32(hTnr->hRegister, BCHP_UFE_FRZ,             0x00000000 );
290        BREG_WriteField(hTnr->hRegister,UFE_CTRL, VID_QUANT,    0x2);                                   /* reprogram VID_QUANT*/
291        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0x00000000 );        /* clear any remaining data reset*/
292        BREG_WriteField(hTnr->hRegister,UFE_MISC_CTRL, BYP_HRC, 0x1);                           /* set hard-bypass bit*/
293        BREG_WriteField(hTnr->hRegister,UFE_MISC_CTRL, CLKGEN_DATA_RESET,       0x0);   /* clear data/clkgen reset*/
294
295        BREG_WriteField(hTnr->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_low_I_mode, 0x1);  /*0: high linearity mode , 1: low power mode,Reset value: 0x0*/
296        BREG_WriteField(hTnr->hRegister, UFE_AFE_TNR0_MXR_03, i_MIXER_bias_ctrl, 0x0);   /*mixer bias current control, Reset value: 0x6*/
297        BREG_WriteField(hTnr->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg, 0x7); /*RFVGA control for degeneration resistors on all Gm stages thus changing the Max Gain*/
298                return BERR_SUCCESS;
299
300}
301
302#endif
303/******************************************************************************
304*  BTNR_P_TnrMiniInit
305******************************************************************************/
306BERR_Code BTNR_P_TnrMiniInit(BTNR_3x7x_Handle hTnr)
307{
308        /*These are scan parameters that should be reset*/
309        hTnr->pTunerParams->BTNR_Local_Params.RF_Offset   = 0;   
310        hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate = 0;
311
312        BREG_WriteField(hTnr->hRegister, UFE_RST, DATA_RESET, 0x1 );        /* clear any remaining data reset*/
313        BREG_WriteField(hTnr->hRegister, UFE_RST, DATA_RESET, 0x0 );        /* clear any remaining data reset*/
314
315                return BERR_SUCCESS;
316}
317
318/******************************************************************************
319*  BTNR_P_TnrInit
320******************************************************************************/
321BERR_Code BTNR_P_TnrInit(BTNR_3x7x_Handle hTnr)
322{
323        /*These are scan parameters that should be reset*/
324        hTnr->pTunerParams->BTNR_Local_Params.RF_Offset   = 0;   
325        hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate = 0;
326
327#if 0
328
329        if (hTnr->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eCable)
330        {
331//#if 0
332                BTNR_P_CableInit(hTnr);
333//#endif
334        }
335        else
336        {
337                BTNR_P_TerrestrialInit(hTnr);
338        }
339#endif
340
341
342/*Try me and remove above*/
343                BTNR_P_Program_TNR(hTnr);
344
345        return BERR_SUCCESS;
346}
347
348
349
350/******************************************************************************
351*  BTNR_P_Program_TNR()
352******************************************************************************/
353void BTNR_P_Program_TNR(BTNR_3x7x_Handle hTnr)
354{
355        bool HRC_Flag;
356        bool Terr_Flag;
357        bool Real_Flag;
358        uint32_t IF_Freq;
359
360        HRC_Flag  = (hTnr->pTunerParams->BTNR_Internal_Params.HRC_Enable == BTNR_Internal_Params_eEnable) ? true : false;
361  Terr_Flag = (hTnr->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eTerrestrial) ? true : false;
362        Real_Flag = (hTnr->pTunerParams->BTNR_Internal_Params.SDADC_Input == BTNR_Internal_Params_SDADC_Input_eExtReal) ? true : false;
363        IF_Freq   = hTnr->pTunerParams->BTNR_Internal_Params.IF_Freq;
364
365        if (HRC_Flag == true)
366        {
367                BDBG_ERR(("ERROR!!!  HRC IS UNSUPPORTED in "));
368        }
369#if 0
370        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, INPUT_FMT, 0);
371        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, INPUT_EDGE, 0);
372        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, IQ_SWAP, 0);
373        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, NEGATE_I, 0);
374        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, NEGATE_Q, 0);
375        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, SPINV_FRONT, 0);
376        //BREG_WriteField(hTnr->hRegister, UFE_CTRL, SPINV_BACK, 0);
377#endif
378        /*HRC is bypassed*/
379        BREG_WriteField(hTnr->hRegister, UFE_CTRL, USE_EXT_VID_FREQ, 0);
380  BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, BYP_HRC, 0x1);
381
382        /*CIC is not bypassed*/
383        BREG_WriteField(hTnr->hRegister, UFE_BYP, CIC, 0);
384
385/*replaced for callback function
386        if (IF_Freq == 0)
387        {
388                BREG_WriteField(hTnr->hRegister, UFE_BYP, BACK_MIX, 1);
389        }
390        else
391        {
392                BREG_WriteField(hTnr->hRegister, UFE_BYP, BACK_MIX, 0);
393                BTNR_P_Program_Back_DDFS(hTnr);
394        }
395
396
397        if (Real_Flag == true)
398        {
399                BREG_WriteField(hTnr->hRegister, UFE_CTRL, ZERO_Q, 1);
400                BREG_WriteField(hTnr->hRegister, UFE_CTRL, LO_IF, 1);
401                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_PHS, 1);
402                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_AMP, 1);
403
404        }
405        else
406        {
407                BREG_WriteField(hTnr->hRegister, UFE_CTRL, ZERO_Q, 0);
408                BREG_WriteField(hTnr->hRegister, UFE_CTRL, LO_IF, 0);
409                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_PHS, 0);
410                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_AMP, 0);
411                BTNR_P_Program_Back_DDFS(hTnr);
412        }
413*/
414        if (Real_Flag == true)
415        {
416                BREG_WriteField(hTnr->hRegister, UFE_CTRL, ZERO_Q, 1);
417                BREG_WriteField(hTnr->hRegister, UFE_CTRL, LO_IF, 1);
418                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_PHS, 1);
419                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_AMP, 1);
420#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)  /* TO FIX */
421    /* Setup AGC control for DTV Module w/NuTune FK1605 */
422          BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, AAGC_DIN_SEL, 1);          /* select CIC output to AAGC */
423#else
424        /* Setup AGC control for DTV Module w/NuTune FK1605 */
425          BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL_SEL, AAGC_DIN_SEL, 1);          /* select CIC output to AAGC */       
426#endif
427          /* BREG_Write32(hTnr->hRegister, BCHP_UFE_MISC_AGC_THRES, 0x00016B54); */  /* THRES = dec2hex(floor(10^(-9/20)*2^18)), back off 9dB, 2.18 format */   
428          BREG_Write32(hTnr->hRegister, BCHP_UFE_MISC_AGC_THRES, 0x0000103a);        /* THRES = dec2hex(floor(10^(-36/20)*2^18)), back off 36dB, 2.18 format - WHY????*/ 
429          BREG_Write32(hTnr->hRegister, BCHP_UFE_MISC_AGC_CTRL, 0x00140100);         /* BW = 2^-20, inv threshold compare, unfreeze */
430          BREG_Write32(hTnr->hRegister, BCHP_UFE_MISC_AGC_INT_UT, 0x00000000);       /* Upper threshold corresponds to 0.6V */
431          BREG_Write32(hTnr->hRegister, BCHP_UFE_MISC_AGC_INT_LT, 0xb0000000);       /* Lower threshold corresponds to 1.6V */
432                BREG_WriteField(hTnr->hRegister, UFE_CTRL, SPINV_BACK, 1);           
433        }
434        else
435        {
436                BREG_WriteField(hTnr->hRegister, UFE_CTRL, ZERO_Q, 0); 
437                BREG_WriteField(hTnr->hRegister, UFE_CTRL, LO_IF, 0);
438                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_PHS, 0);
439                BREG_WriteField(hTnr->hRegister, UFE_BYP, IQ_AMP, 0);
440        }
441
442        /*always use back mixer*/
443        BREG_WriteField(hTnr->hRegister, UFE_BYP, BACK_MIX, 0);
444        BTNR_P_Program_Back_DDFS(hTnr);
445
446        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0xC0000FFF );        /* reset the clock gen after BYP/CIC programming*/
447        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0x40000FFF );        /* clear clock gen reset, but hold datapath reset*/
448        BREG_Write32(hTnr->hRegister, BCHP_UFE_DCO_CTRL,        0x00000008 );
449        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1,            0x0000000D );
450        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2,            0x0000000B );
451        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3,            0x00000009 );
452        switch (hTnr->pTunerParams->BTNR_Acquire_Params.Application)
453        {
454    case BTNR_TunerApplicationMode_eTerrestrial:
455                BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1_THRESH,     0x0000830e );        /* 18dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
456                BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2_THRESH,     0x0000830e );        /* 18dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
457                BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
458        break;
459    case BTNR_TunerApplicationMode_eCable:             
460                BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
461                BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
462                BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3_THRESH,     0x0001030e );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/     
463        break;
464        default:
465                BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",hTnr->pTunerParams->BTNR_Acquire_Params.Application));
466                /*retCode = BERR_INVALID_PARAMETER;*/
467                /*goto bottom of function to return error code*/
468                /*goto something_bad_happened;*/
469        }                       
470        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_AMP_CTRL,  0x00000007 );
471        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_PHS_CTRL,  0x00000007 );
472
473  BTNR_P_Program_VID_CIC_HB_SAW(hTnr);
474
475        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC1_LF,         0x06000000 );
476        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC2_LF,         0x02000000 );
477        /*BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3_LF,         0x02000000 );*/
478        BREG_Write32(hTnr->hRegister, BCHP_UFE_AGC3_LF,         0x20000000 );
479        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_AMP_LF,    0x00000000 );
480        BREG_Write32(hTnr->hRegister, BCHP_UFE_IQIMB_PHS_LF,    0x00000000 );
481        BREG_Write32(hTnr->hRegister, BCHP_UFE_FRZ,             0x00000000 );
482        BREG_Write32(hTnr->hRegister, BCHP_UFE_RST,             0x00000000 );        /* clear any remaining data reset*/
483        BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, CLKGEN_DATA_RESET, 0x3); /* set data/clkgen reset*/
484        BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, CLKGEN_DATA_RESET, 0x0); /* clear data/clkgen reset*/
485}
486
487/******************************************************************************
488*  BTNR_P_Program_VID_CIC_HB_SAW()
489******************************************************************************/
490void BTNR_P_Program_VID_CIC_HB_SAW(BTNR_3x7x_Handle hTnr)
491{
492        bool Terr_Flag;
493        bool QAM_Flag;
494        bool SmartTune_Flag;
495        uint8_t  Vid_Quant;
496        uint16_t Vid_Div;
497        uint8_t  CIC, HB;
498        uint8_t  CoeffSet, Index;
499
500        Terr_Flag = (hTnr->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eTerrestrial) ? true : false;
501        QAM_Flag = (hTnr->pTunerParams->BTNR_Acquire_Params.Standard == BTNR_Standard_eQAM) ? true : false;
502  SmartTune_Flag = (hTnr->pTunerParams->BTNR_Local_Params.SmartTune == BTNR_Local_Params_SmartTune_FreqPlanA) ? true : false;
503 
504        /*Program VID_QUANT and VID_DIV*/
505        /*These values need to match what is in btnr_global_clk.h*/
506        Vid_Quant  = (Terr_Flag == true) ? 0x2 : 0x4;
507        Vid_Div    = (Terr_Flag == true) ? 0xA : 0x24;
508
509        /*Tables are defined for Terrestrial 8 MHz, 7 MHz, 6 MHz, 5 MHz and 1.7 MHz*/
510        /*For Cable 8 MHz and 7 MHz use the same table, and 6 MHz, 5 MHz and 1.7 MHz use the same table*/
511        switch (hTnr->pTunerParams->BTNR_Acquire_Params.LPF_Bandwidth)
512        {
513                case BTNR_LPF_Bandwidth_e8MHz :
514                        CIC                      = (Terr_Flag == true) ? 3 : 3;
515                        HB                       = (Terr_Flag == true) ? 2 : 2;
516                        CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 0 : 0) : 0;
517                        break;
518                case BTNR_LPF_Bandwidth_e7MHz :
519                        CIC                      = (Terr_Flag == true) ? 3 : 3;
520                        HB                       = (Terr_Flag == true) ? 2 : 2;
521                        CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 1 : 1) : 2;
522                        break;
523                case BTNR_LPF_Bandwidth_e6MHz :
524                        CIC                      = (Terr_Flag == true) ? 3 : 3;
525                        HB                       = (Terr_Flag == true) ? 2 : 2;
526                        CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 2 : 2) : 3;
527                        break;
528                case BTNR_LPF_Bandwidth_e5MHz :
529                        CIC                      = (Terr_Flag == true) ? 0 : 0;
530                        HB                       = (Terr_Flag == true) ? 0 : 0;
531                        CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 3 : 3) : 4;
532                        break;
533                case BTNR_LPF_Bandwidth_e1_7MHz :
534                        CIC                      = (Terr_Flag == true) ? 3 : 3;
535                        HB                       = (Terr_Flag == true) ? 0 : 0;
536                        CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 4 : 4) : 8;
537                        break;
538                case BTNR_LPF_Bandwidth_eVariable :
539                        CIC                      = (Terr_Flag == true) ? 3 : 3;
540                        HB                       = (Terr_Flag == true) ? 2 : 2;
541                        CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 0 : 0) : 0;
542                if ((hTnr->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth > MAX_LPF_VARIABLE_BW) ||
543                          (hTnr->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth < MIN_LPF_VARIABLE_BW))
544                {
545                        BDBG_ERR(("ERROR!!!  VARIABLE LPF BANDWIDTH UNSUPPORTED SETTING TO 8 MHZ for Terrestrial and 8 MHz for Cable"));
546                        BDBG_ERR(("ERROR!!! Invalid Tuner_Variable_BW in BTNR_P_Write_SAW() , Value is %d", hTnr->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth));
547                }
548                break;
549        default :
550                CIC                      = (Terr_Flag == true) ? 3 : 3;
551                HB                       = (Terr_Flag == true) ? 2 : 2;
552                CoeffSet = (Terr_Flag == true) ? ((SmartTune_Flag == true) ? 0 : 0) : 0;
553                BDBG_ERR(("ERROR!!! Invalid Tuner_BW selected in BTNR_P_Write_SAW() , Value is %d", hTnr->pTunerParams->BTNR_Acquire_Params.LPF_Bandwidth));
554                break;
555        }
556
557        /*Override Filters if symbol rate is not 0, means function is called by scan and QAM standard*/
558        if ((hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 0) && (QAM_Flag == true))
559        {
560                if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 6058796)  /*6250000->5830000->6058796*/
561                {
562                        CIC                      = 3;
563                        HB                       = 2;
564                        CoeffSet = 0;
565                }
566                else if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 5028631)   /*5360000->5000000->5028631*/
567                {
568                        CIC                      = 3;
569                        HB                       = 2;
570                        CoeffSet = 2;           
571                }
572                else if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 4173624)   /*4460000->4170000->4173624*/
573                {
574                        CIC                      = 3;
575                        HB                       = 2;
576                        CoeffSet = 3;           
577                }
578                else if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 3463992)           /*3580000->3330000->3463992)*/
579                {
580                        CIC                      = 0;
581                        HB                       = 0;
582                        CoeffSet = 4;           
583                }
584                else if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 2539117)           /*2700000->2500000->2539117)*/
585                {
586                        CIC                      = 3;
587                        HB                       = 1;
588                        CoeffSet = 5;           
589                }
590                else if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 1749080)  /*1800000->1670000->1749080*/
591                {
592                        CIC                      = 1;
593                        HB                       = 0;
594                        CoeffSet = 6;           
595                }
596                else if (hTnr->pTunerParams->BTNR_Local_Params.Symbol_Rate > 1544728) /*1500000->1500000->1544728*/
597                {
598                        CIC                      = 2; 
599                        HB                       = 0;
600                        CoeffSet = 7;           
601                }
602                else
603                {
604                        CIC                      = 3;
605                        HB                       = 0;
606                        CoeffSet = 8;   
607                }
608        }
609
610
611        /*Write VID, CIC and HB values*/
612        BREG_WriteField(hTnr->hRegister, UFE_CTRL, VID_QUANT, Vid_Quant);
613        BREG_WriteField(hTnr->hRegister, UFE_CTRL, VID_DIV, Vid_Div);
614        BREG_WriteField(hTnr->hRegister, UFE_CTRL, CIC_DEC_RATIO, CIC);
615        BREG_WriteField(hTnr->hRegister, UFE_BYP, HB, HB);
616
617        /*Write SAW Coeffs*/
618        if (CoeffSet > (BTNR_SAW_TABLE_SIZE-1))
619        {
620                BDBG_ERR(("ERROR!!! Reading outside of table size in  BWFE_P_HAB_Read_LIC_EQ_DCO()"));
621        }
622
623        for (Index=0;Index<BTNR_SAW_COEFF_SIZE;Index++)
624        {
625          if (Terr_Flag)
626                  if (SmartTune_Flag)
627                          BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF0+(4*Index), BTNR_SAW_Table_FreqPlanAlternate[CoeffSet][Index]);       
628                  else
629                          BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF0+(4*Index), BTNR_SAW_Table_FreqPlanDefault[CoeffSet][Index]);
630                else
631                  BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_COEFF0+(4*Index), BTNR_SAW_Table[CoeffSet][Index]);                         
632        }
633
634        /*Reset clock gen*/
635        BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, CLKGEN_RESET, 1);
636        BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, CLKGEN_RESET, 0);
637}
638
639/******************************************************************************
640*  BTNR_P_Program_Back_DDFS()
641******************************************************************************/
642void BTNR_P_Program_Back_DDFS(BTNR_3x7x_Handle hTnr)
643{
644        bool     Terr_Flag;
645        bool             QAM_Flag;
646        uint8_t  CIC, HB;
647        uint32_t DDFS_Input_Freq;
648        uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
649        bool  IsNegative = false;
650        int32_t DDFS_Freq;
651
652        Terr_Flag = (hTnr->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eTerrestrial) ? true : false;
653        QAM_Flag = (hTnr->pTunerParams->BTNR_Acquire_Params.Standard == BTNR_Standard_eQAM) ? true : false;
654
655        CIC = BREG_ReadField(hTnr->hRegister, UFE_CTRL, CIC_DEC_RATIO);
656        HB  = BREG_ReadField(hTnr->hRegister, UFE_BYP, HB);
657
658        /*translate values for calculating DDFS FCW*/
659        CIC =  CIC+2;
660        HB  = (hTnr->pTunerParams->BTNR_Internal_Params.SDADC_Input == BTNR_Internal_Params_SDADC_Input_eExtReal)       ? (16>>HB) : (32>>HB);
661        if (CIC*HB == 0)
662        {
663                        BDBG_ERR(("ERROR!!!  Divide by 0 in BTNR_P_Write_Back_DDFS()"));
664        }
665
666        /*FCW = F*2^32/DDFS_Input_Freq if is positive and FCW = (DDFS_Input_Freq-F)*2^32/DDFS_Input_Freq*/
667        DDFS_Input_Freq = (Terr_Flag == true) ? (TERR_PHYPLL6_FREQ/(CIC*HB)): (CABLE_PHYPLL6_FREQ/(CIC*HB));
668       
669        /*find the desired DDFS Frequency*/
670        /*for some reason the mixer DDFS is negative*/
671        DDFS_Freq = -1*(int32_t)hTnr->pTunerParams->BTNR_Internal_Params.IF_Freq;
672        if (QAM_Flag == true)
673        {
674                DDFS_Freq = DDFS_Freq - hTnr->pTunerParams->BTNR_Local_Params.RF_Offset;
675        }
676       
677        /*Detect if DDFS_Freq is negative*/
678        if (DDFS_Freq < 0)
679        {
680                IsNegative = true;
681                DDFS_Freq = (DDFS_Freq == (int32_t)0x80000000) ? -1 * (DDFS_Freq + 1) : -1 * DDFS_Freq;
682        }
683
684        ulMultA = 2*(uint32_t)DDFS_Freq;
685        ulMultB = POWER2_31;
686        ulDivisor = DDFS_Input_Freq;
687        BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
688        BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
689        if (ulNrmHi != 0x00000000)
690        {
691     BDBG_ERR(("DDFS is outside of the 32 bit range in BTNR_P_Write_Back_DDFS()"));
692        }
693
694        /*If result should be negative, take twos complement of output*/
695        ulNrmLo = (IsNegative == true) ? Twos_Complement32(ulNrmLo) : ulNrmLo;
696
697        /*Write DDFS value*/
698        BREG_Write32(hTnr->hRegister, BCHP_UFE_BMIX_FCW, ulNrmLo);
699
700}
701
702void BTNR_P_InitStatus(BTNR_3x7x_Handle hTnr)
703{
704        bool     Terr_Flag;
705        uint8_t  CIC, HB;
706        uint32_t ReadReg;
707        uint32_t DDFS_Input_Freq;
708        int32_t  Freq;
709        bool RegIsNegative = false;
710        uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
711       
712
713        CIC = BREG_ReadField(hTnr->hRegister, UFE_CTRL, CIC_DEC_RATIO);
714        HB  = BREG_ReadField(hTnr->hRegister, UFE_BYP, HB);
715
716        /*translate values for calculating DDFS FCW*/
717        CIC =  CIC+2;
718        HB  = (hTnr->pTunerParams->BTNR_Internal_Params.SDADC_Input == BTNR_Internal_Params_SDADC_Input_eExtReal)       ? (16>>HB) : (32>>HB);
719        if (CIC*HB == 0)
720        {
721                        BDBG_ERR(("ERROR!!!  Divide by 0 in BTNR_P_Write_Back_DDFS()"));
722        }
723
724        /*F = FCW*DDFS_Input_Freq/2^32 if is positive and F = DDFS_Input_Freq - FCW*DDFS_Input_Freq/2^32 if negative*/
725        DDFS_Input_Freq = (Terr_Flag == true) ? (TERR_PHYPLL6_FREQ/(CIC*HB)): (CABLE_PHYPLL6_FREQ/(CIC*HB));
726
727        /*Read DDFS value*/
728        ReadReg = BREG_Read32(hTnr->hRegister, BCHP_UFE_BMIX_FCW);
729
730        /*Detect if DDFS_Freq is negative*/
731        if ((ReadReg & 0x80000000) != 0)
732        {
733                RegIsNegative = true;
734                ReadReg = (ReadReg == 0x80000000) ? Twos_Complement32(0x80000001) : Twos_Complement32(ReadReg);
735        }
736
737        ulMultA = ReadReg;
738        ulMultB = DDFS_Input_Freq/2;
739        ulDivisor = POWER2_31;
740        BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
741        BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
742        if (ulNrmHi != 0x00000000)
743        {
744     BDBG_ERR(("F is outside of the 32 bit range in BTNR_P_Write_Back_DDFS()"));
745        }
746
747        /*for some reason the mixer DDFS is negative*/
748        Freq = (RegIsNegative == true) ? (int32_t)ulNrmLo : -1*(int32_t)ulNrmLo;
749
750        /*Assign value*/
751        hTnr->pTunerParams->BTNR_Local_Params.Total_Mix_After_ADC = Freq;
752
753
754        /*this is the sum of the 3 AGC's in 3461 UFE*/
755        /*AGC1 AGC2 AGC3 Gain and Level Calculation*/
756        /*AGCF is 32-bit 7.25 unsigned number*/
757        /*Reset value is 0x02000000 which is a gain of 1*/
758        /*  db = 20*log10(AGC1/2^25)*/
759        /*  256*db = 5120*log10(AGC1/2^16)-5120*log10(2^9)*/ 
760        ReadReg = BREG_Read32(hTnr->hRegister, BCHP_UFE_AGC1_LF); 
761        ReadReg = 2*BMTH_2560log10(ReadReg/POWER2_16) - LOG10_POWER2_9_X5120;
762        ReadReg = ReadReg & 0x0000FFFF;
763        hTnr->pTunerParams->BTNR_Local_Params.PostADC_Gain_x256db = (int16_t)ReadReg;  /*BBS will divide by 256 to get dB*/
764
765        ReadReg = BREG_Read32(hTnr->hRegister, BCHP_UFE_AGC2_LF); 
766        ReadReg = 2*BMTH_2560log10(ReadReg/POWER2_16) - LOG10_POWER2_9_X5120;
767        ReadReg = ReadReg & 0x0000FFFF;
768        hTnr->pTunerParams->BTNR_Local_Params.PostADC_Gain_x256db += (int16_t)ReadReg;  /*BBS will divide by 256 to get dB*/
769
770        ReadReg = BREG_Read32(hTnr->hRegister, BCHP_UFE_AGC3_LF); 
771        ReadReg = 2*BMTH_2560log10(ReadReg/POWER2_16) - LOG10_POWER2_9_X5120;
772        ReadReg = ReadReg & 0x0000FFFF;
773
774        /*Assign value*/
775        hTnr->pTunerParams->BTNR_Local_Params.PostADC_Gain_x256db += (int16_t)ReadReg;  /*BBS will divide by 256 to get dB*/
776
777}
778
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