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btnr_tune.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1
2	/***************************************************************************
3	* (c)2005-2012 Broadcom Corporation
4	*
5	* This program is the proprietary software of Broadcom Corporation and/or its licensors,
6	* and may only be used, duplicated, modified or distributed pursuant to the terms and
7	* conditions of a separate, written license agreement executed between you and Broadcom
8	* (an "Authorized License"). Except as set forth in an Authorized License, Broadcom grants
9	* no license (express or implied), right to use, or waiver of any kind with respect to the
10	* Software, and Broadcom expressly reserves all rights in and to the Software and all
11	* intellectual property rights therein. IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
12	* HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
13	* NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE.
14	*
15	* Except as expressly set forth in the Authorized License,
16	*
17	* 1. This program, including its structure, sequence and organization, constitutes the valuable trade
18	* secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof,
19	* and to use this information only in connection with your use of Broadcom integrated circuit products.
20	*
21	* 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
22	* AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR
23	* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
24	* THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES
25	* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE,
26	* LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION
27	* OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF
28	* USE OR PERFORMANCE OF THE SOFTWARE.
29	*
30	* 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS
31	* LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR
32	* EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR
33	* USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF
34	* THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT
35	* ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE
36	* LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF
37	* ANY LIMITED REMEDY.
38	*
39	* $brcm_Workfile: btnr_tune.c $
40	* $brcm_Revision: 79 $
41	* $brcm_Date: 3/27/12 12:17p $
42	*
43	* [File Description:]
44	*
45	* Revision History:
46	*
47	* $brcm_Log: /AP/ctfe/core/tnr/btnr_tune.c $
48	*
49	* 79 3/27/12 12:17p farshidf
50	* SW3461-1: remove warning
51	*
52	* Fw_Integration_Devel/47 3/27/12 12:16p farshidf
53	* SW3461-1: remove warning
54	*
55	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/20 3/27/12 12:14p farshidf
56	* SW3461-1: remove warning
57	*
58	* 78 3/23/12 2:54p farshidf
59	* SW3128-125: FW version 4.6
60	*
61	* Fw_Integration_Devel/46 3/23/12 2:53p farshidf
62	* SW3128-125: FW version 4.6
63	*
64	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/19 3/23/12 11:33a farshidf
65	* SW3461-180: version 4.6 FW
66	*
67	* Fw_Integration_Devel/45 3/23/12 11:32a farshidf
68	* SW3461-180: version 4.6 FW
69	*
70	* SW3461-173/1 3/15/12 3:37p shchang
71	* SW3461-120: fix huawei Ch.538MHz sensitivity issue
72	*
73	* 76 3/12/12 3:45p farshidf
74	* SW3461-171: merge to inetg
75	*
76	* Fw_Integration_Devel/44 3/12/12 3:44p farshidf
77	* SW3461-171: merge to inetg
78	*
79	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/17 3/12/12 3:39p shchang
80	* SW3461-120: fix time varying sync
81	*
82	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/16 3/8/12 6:35p mbsingh
83	* SW3461-1: Fixed tuner frequency calculation
84	*
85	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/15 3/7/12 10:47p shchang
86	* SW3461-120: fix AGC TOP settings
87	*
88	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/14 3/7/12 5:49p shchang
89	* SW3461-125: improve ACI performance while without affecting C/N and
90	* echo tests.
91	*
92	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/13 3/2/12 10:52a mbsingh
93	* SW3461-145: Fix Signal Strength Calculations
94	*
95	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/12 2/27/12 5:51p shchang
96	* SW3461-1: fix "dead zone" issue on J83A
97	*
98	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/11 2/23/12 12:51p farshidf
99	* SW3461-120: remove warning
100	*
101	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/10 2/23/12 12:39p farshidf
102	* SW3461-120: change BTNR_J83B_SUPPORT to #ifdnef BTNR_J83A_SUPPORT
103	*
104	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/9 2/23/12 12:35p farshidf
105	* SW3461-120: rename STCE40 compile flag to BTNR_J83B_SUPPORT
106	*
107	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/8 2/22/12 5:56p mbsingh
108	* SW3461-145: Changed LNA start from mid gain to improve Signal Strength
109	* convergence on 3461
110	*
111	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/7 2/22/12 11:41a shchang
112	* SW34610120: 1. update tuner status such that dithering can be changed
113	* without retune. 2. move SCTE-40 settings to ifdef.
114	*
115	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/6 2/16/12 5:09p shchang
116	* SW3461-1: improve N+/-4
117	*
118	* Fw_Integration_Devel/35 2/16/12 9:41a farshidf
119	* SW7552-209: compile fix
120	*
121	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/5 2/16/12 9:40a farshidf
122	* SW7552-109: compile fix
123	*
124	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/4 2/15/12 2:56p farshidf
125	* SW3461-1: compile fix
126	*
127	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/3 2/15/12 9:24a farshidf
128	* SW3461-120: add the 7552 register name for 7552 A0
129	*
130	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/2 2/14/12 10:58p shchang
131	* SW3461-120: change RFVGA initial gain to maximum
132	*
133	* Fw_Integration_Devel/AP_V4_0_TNR_DEV/1 2/10/12 12:06p shchang
134	* SW3461-120: 1. add ADC6B reset 2. fix 7552 shift-gear
135	*
136	* Fw_Integration_Devel/31 2/3/12 2:15p farshidf
137	* SW3461-120: merge to main
138	*
139	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/27 1/31/12 7:22p shchang
140	* SW3461-120: fix 1. LO DDFS reset 2. tuner status 3. PHYPLL change on-
141	* the-fly
142	*
143	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/26 1/30/12 11:28a farshidf
144	* SW3461-120: put the A0 tuner code under its own flag
145	*
146	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/25 1/16/12 7:17p shchang
147	* SW3461-120: differetiate PLL not lock/not use
148	*
149	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/24 1/16/12 1:42p shchang
150	* SW3461-120: improve N+/-4 ACI performance
151	*
152	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/23 1/11/12 4:08p shchang
153	* SW3461-120: add power mode e_Lna_Daisy inside the power control
154	*
155	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/22 1/11/12 10:29a farshidf
156	* SW3461-1: fix the second 3461 tuner setting for UHF mode
157	*
158	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/21 1/5/12 6:10p shchang
159	* SW3461-120: add smart tune to relsove LO spur around 845MHz
160	*
161	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/20 1/3/12 11:41p shchang
162	* SW3461-120: B0 use PHYPLL with CMOS input; B1 use PHYPLL with CML input
163	*
164	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/19 12/26/11 8:50p shchang
165	* SW3461-120: 1. optimize tuner settings for DVB-T LTE scenarios. 2.
166	* optimize tuner settings to pass SCTE-40 spec
167	*
168	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/18 12/22/11 11:10a farshidf
169	* SW3461-120: merge to dev
170	*
171	* 59 12/22/11 11:08a farshidf
172	* SW3461-120: make A0 compatible
173	*
174	* 58 12/20/11 6:40p farshidf
175	* SW3128-1: remove warning
176	*
177	* 57 12/15/11 5:59p farshidf
178	* SW3461-118: update the tuner to work on B0 and B1
179	*
180	* 56 12/8/11 3:18p shchang
181	* SW3461-1: power down REFPLL, use PHYPLL to save power
182	*
183	* 55 11/23/11 11:12a farshidf
184	* SW3461-99: merge to integ
185	*
186	* Fw_Integration_Devel/26 11/23/11 11:12a farshidf
187	* SW3461-99: merge to integ
188	*
189	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/15 11/23/11 11:10a farshidf
190	* SW3461-99:compile fix
191	*
192	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/14 11/22/11 12:24p farshidf
193	* SW3461-99: warning fix
194	*
195	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/13 11/22/11 12:20p farshidf
196	* SW3461-99: merge Dave's Mixer PLL fix
197	*
198	* 52 11/21/11 11:26p farshidf
199	* SW7552-139: fix compile issue
200	*
201	* 51 11/16/11 6:50p shchang
202	* SW3461-1: add BTNR_P_Tuner_PowerUpPLL() to resolve MIXPLL unlock issue
203	*
204	* 50 11/4/11 4:11p farshidf
205	* SW3461-82: merge to main
206	*
207	* Fw_Integration_Devel/24 11/4/11 11:38a farshidf
208	* SW3461-82: merge to integ
209	*
210	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/12 11/1/11 12:21p shchang
211	* SW3461-1: increase LDO voltage to fix sensitivity issue
212	*
213	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/11 10/25/11 5:18p jputnam
214	* CDFEDEMOD-6: Consolidated SmartTune logic such that only PLL dividers
215	* are changed rather than calling P_TunerInit(). This seems to
216	* eliminate occassional instability associated with repeatedly tuning
217	* between FreqPlanA and FreqPlanDefault
218	*
219	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/10 10/25/11 11:17a shchang
220	* SW7552-137: fix re-scan issue below 334MHz for DVB-C
221	*
222	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/9 10/25/11 8:16a jputnam
223	* CDFEDEMOD-6: Added 756MHz to SmartTune frequency list
224	*
225	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/8 10/17/11 7:42p shchang
226	* SW3461-1: 1. add dithering off 2. modified registers in power control
227	* subroutine
228	*
229	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/7 10/16/11 9:42p farshidf
230	* SW3461-1: fix th LDO osng lock issue from Dave
231	*
232	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/6 10/14/11 12:56a farshidf
233	* SW3461-64: fix warning
234	*
235	* 48 10/14/11 12:05a farshidf
236	* SW3461-64: fix tuner compile issues
237	*
238	* 47 10/13/11 11:58p farshidf
239	* SW3461-64: merge to main
240	*
241	* Fw_Integration_Devel/22 10/13/11 7:18p farshidf
242	* SW3461-64: merge to integ
243	*
244	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/5 10/13/11 7:17p farshidf
245	* SW3461-1: fix teh a0 compile issue
246	*
247	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/4 10/11/11 2:18p shchang
248	* SW3461-1: optimize AGC for DVB-T2
249	*
250	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/3 10/5/11 1:01p shchang
251	* SW3461-1: 1. Select RFAGC clock from REFPLL 2. Set internal LNA bias
252	* current 3. Remove dithering off
253	*
254	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/2 9/27/11 11:52a mbsingh
255	* SW3461-1: Made the code compile for B0 with new register changes
256	*
257	* Fw_Integration_Devel/AP_V3_0_TNR_DEV/1 9/26/11 5:26p mbsingh
258	* SW3461-1: Incorporate correct register writes for B0
259	*
260	* Fw_Integration_Devel/21 9/22/11 4:44p farshidf
261	* SW3461-1: merge to integ
262	*
263	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/16 9/21/11 4:14p farshidf
264	* SW3461-1: update files for B0
265	*
266	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/15 9/14/11 10:53p shchang
267	* SW3461-1: fix tune-delay issue.
268	*
269	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/14 9/12/11 4:02p shchang
270	* SW3461-1: 1. change LNA AGC settings 2. improve AGC shift gear
271	*
272	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/13 9/10/11 9:20p shchang
273	* SW3461-1: 1. fix DDFS FCW resolution. 2. add AGC shift gear. 3.
274	* sensitivity fix.
275	*
276	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/12 9/7/11 11:32a jputnam
277	* SW3461-1: Added explicit assertion of PHYPLL reset for reliable
278	* SmartTune operation, rather than assuming PHYPLL reset is already
279	* asserted prior to P_TunerInit().
280	*
281	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/11 9/6/11 11:42a shchang
282	* SW3461-1: fix 143/537MHz locking issue.
283	*
284	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/10 9/6/11 11:03a jputnam
285	* SW3461-1: Restore call to P_TunerInit() when SmartTune indicates
286	* change in PLL programming required
287	*
288	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/9 9/1/11 4:50p shchang
289	* SW3461-1: optimize AGC settings for DVB-T2 ACI_CCI
290	*
291	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/8 9/1/11 9:17a jputnam
292	* SW3461-1: Added Ch K8 (198.5MHz) to SmartTune list
293	*
294	* 41 8/29/11 1:32p farshidf
295	* SW3461-1: merge to main
296	*
297	* Fw_Integration_Devel/16 8/29/11 1:31p farshidf
298	* SW3461-1: merge to integ
299	*
300	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/6 8/29/11 1:30p farshidf
301	* SW3461-1: add back the TunerInit to fix the AGC problem
302	*
303	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/5 8/26/11 4:58p farshidf
304	* SW3461-1: make SmartTuneEnabled magnum compatible
305	*
306	* 39 8/26/11 3:45p farshidf
307	* SW3461-1: merge to main
308	*
309	* Fw_Integration_Devel/14 8/26/11 3:38p farshidf
310	* SW3461-1: merge to integ
311	*
312	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/4 8/26/11 2:29p farshidf
313	* SW3461-42: remove the extra initTune and reduce the sleep for DCO
314	* stabilization from 100ms to 20ms
315	*
316	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/3 8/24/11 12:40p mbsingh
317	* sw3461-1: Fixed tune to work till 1Hz resolution
318	*
319	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/2 8/23/11 5:04p jputnam
320	* SW3461-1: Assert load_en so that PLL divider changes are effective.
321	* Enable SmartTune by default
322	*
323	* Fw_Integration_Devel/AP_V2_0_TNR_DEV/1 8/22/11 12:44p jputnam
324	* SW3461-1: Added SmartTune
325	*
326	* Fw_Integration_Devel/11 8/2/11 6:23p farshidf
327	* SW3461-1: merge to integ
328	*
329	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/15 8/2/11 6:11p farshidf
330	* SW3461-1: update the tuner structure
331	*
332	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/14 7/29/11 1:57p jputnam
333	* SW3461-1: Zero reported LNA and PreADC gains in low-IF mode
334	*
335	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/13 7/28/11 3:54p jputnam
336	* SW3461-1: Added hooks for low-IF mode
337	*
338	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/12 7/28/11 3:41p farshidf
339	* SW3461-1: fix the LNA register usage
340	*
341	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/11 7/27/11 4:36p farshidf
342	* SW3461-1: magnum fix
343	*
344	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/10 7/27/11 1:33p farshidf
345	* SW3461-1: magnum compatible
346	*
347	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/9 7/27/11 1:15p farshidf
348	* SW3461-1: make it magnum compatile
349	*
350	* Fw_Integration_Devel/AP_V0_6_TNR_DEV/8 7/21/11 5:46p farshidf
351	* SW3461-1: add DCO fix from Dave
352	*
353	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/16 7/21/11 5:42p farshidf
354	* SW3461-1: add DC0 fix from Dave
355	*
356	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/14 7/19/11 7:25p farshidf
357	* SW3461-28: remove printf
358	*
359	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/12 7/14/11 10:56p farshidf
360	* SW3461-28: chekc-in fixes from Dave
361	*
362	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/11 7/12/11 4:08p farshidf
363	* SW3461-17: During 2nd tune, the clocks of 6-bit ADC and DCO will be
364	* turned off, which might causes the following issues: 1. LNA AGC will
365	* be freeze 2. SNR degradation due to DCO offset
366	*
367	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/10 6/29/11 12:32p shchang
368	* SW3461-1: replace 6-phase with 8-phase mixer
369	*
370	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/9 6/28/11 6:57p shchang
371	* SW3461-1: fix mixer reset sequence
372	*
373	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/8 6/24/11 4:24p mbsingh
374	* SW3461-1: SD ADC Cal function improvements
375	*
376	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/7 6/24/11 4:10p shchang
377	* SW3461-1: adjust power settings for cable
378	*
379	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/6 6/23/11 5:42p mbsingh
380	* SW3461-1: Remove Sleep's from tuner to reduce tune time
381	*
382	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/5 6/23/11 5:33p mbsingh
383	* SW3461-1: Remove Sleep's from tuner to reduce tune time
384	*
385	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/4 6/22/11 6:49p cbrooks
386	* sw3461-1:Checked tune fix for Dave
387	*
388	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/3 6/21/11 5:34p shchang
389	* SW3461-1: fix DDFS FCW accuracy issue.
390	*
391	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/2 6/20/11 9:20p shchang
392	* SW3461-1: add tracking filter & move AGC-related subroutine to tuner
393	* initialization
394	*
395	* Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/1 6/16/11 6:05p shchang
396	* SW3461-1: add DPM feature
397	*
398	* 29 6/12/11 12:46p farshidf
399	* SW3461-1: clena up
400	*
401	* 28 6/12/11 12:35p farshidf
402	* SW3461-1: code clean up
403	*
404	* 27 6/9/11 6:40p mpovich
405	* SW3461-1: Merge Ver 0.4 Integ. onto main branch.
406	*
407	* SW_System_4_Integ_Test/2 6/9/11 4:48p farshidf
408	* SW3461-1: sync up with 7552 code
409	*
410	* SW_System_4_Integ_Test/1 6/6/11 2:09p mpovich
411	* SW3461-1: Merge disparate branches for test purposes.
412	*
413	* Tnr_Fw_Devel_4/9 6/3/11 1:50p mbsingh
414	* SW3461-1: ifdef out the LNA AGC code
415	*
416	* Tnr_Fw_Devel_4/8 5/26/11 7:24p shchang
417	* SW3461-1: fix AGC power-cycle
418	*
419	* Tnr_Fw_Devel_4/7 5/25/11 3:19p shchang
420	* SW3461-1: increase RFVGA bias for senesitivity
421	*
422	* Tnr_Fw_Devel_4/6 5/25/11 3:07p shchang
423	* SW3461-1: Remonving code .. for now. Need to fix it later
424	*
425	* Tnr_Fw_Devel_4/5 5/25/11 10:03a farshidf
426	* SW3461-6: add the timer Interrupt
427	*
428	* Tnr_Fw_Devel_4/4 5/24/11 5:34p mbsingh
429	* SW3461-1: Implement the LNA AGC cycle ( call back function ) function
430	* for power saving
431	*
432	* Tnr_Fw_Devel_4/3 5/23/11 4:55p mbsingh
433	* SW3461-1: Got Daisy output working in firmware through BBS
434	*
435	* Tnr_Fw_Devel_4/2 5/23/11 4:30p mbsingh
436	* SW3461-1: Got loop through working in firmware through BBS
437	*
438	* Tnr_Fw_Devel_4/1 5/23/11 3:17p mbsingh
439	* SW3461-1: Lower the power consumption of the tuner - LNA AGC take over
440	* point - PHY PLL Optimization
441	*
442	* 26 5/20/11 6:44a mpovich
443	* SW3461-1: rename UFE (BUFE) module to TNR (BTNR).
444	*
445	* TNR_3461_1/1 5/19/11 5:16p mpovich
446	* SW3461-1: Change BUFE module prefix to BTNR
447	*
448	* 25 5/18/11 11:09a farshidf
449	* SW3461-1: merge main
450	*
451	* TNR_3461_1/18 5/17/11 6:17p mbsingh
452	* SW3461-1: Calibrate I and Q channel in parallel
453	*
454	* TNR_3461_1/17 5/16/11 5:16p shchang
455	* change LNA/RF AGC TOP to pass far adjacent scenario
456	*
457	* TNR_3461_1/16 5/3/11 2:58p hfu
458	* To resolve fractional (0.5MHz) tune issue. This solution is a
459	* workaround and the frequency resolution depends on variable M.
460	*
461	* TNR_3461_1/15 4/8/11 2:44p farshidf
462	* SW3461-1: power up the PLL for DS
463	*
464	* TNR_3461_1/14 4/5/11 8:24a jputnam
465	* SW3461-1: Replaced digital I/Q swap with analog fix when 8-phase mixer
466	* is enabled
467	*
468	* TNR_3461_1/13 4/4/11 5:55p jputnam
469	* SW3461-1: Added I/Q swap when 8-phase mixer is used
470	*
471	* TNR_3461_1/12 3/24/11 11:53a jputnam
472	* SW3461-1: Change TNR clock to 540MHz for cable mode
473	*
474	* TNR_3461_1/11 3/21/11 2:45p mbsingh
475	* SW3461-1: Move SD ADC calibration after tune
476	*
477	* TNR_3461_1/10 3/18/11 4:09p farshidf
478	* SW3461-1: merge main
479	*
480	* 20 3/18/11 4:08p farshidf
481	* SW3461-1: merge main
482	*
483	* TNR_3461_1/9 3/17/11 5:36p mbsingh
484	* SW3461-1: Added watchdog reset or mixer PLL lock
485	*
486	* TNR_3461_1/8 3/15/11 5:08p mbsingh
487	* SW3461-1: Enabled 6 bit ADC and LNA AGC
488	*
489	* TNR_3461_1/7 3/15/11 3:38p mbsingh
490	* SW3461-1: Adding RF AGC setup for tuner
491	*
492	* TNR_3461_1/6 3/14/11 8:08p lukose
493	* SW3461-1: Temporarily bypass LNA to get tuner tuned. Will be removed
494	* later
495	*
496	* TNR_3461_1/5 3/14/11 7:41p lukose
497	* SW3461-1: Ported tuner .bbs script. Tuner is tuning
498	*
499	* TNR_3461_1/4 3/14/11 6:27p lukose
500	* SW3461-1: Fix for the DDFS calculation
501	*
502	* TNR_3461_1/3 3/11/11 6:49p mbsingh
503	* SW3461-1: Fixing DCO Setup
504	*
505	* TNR_3461_1/2 3/11/11 6:06p lukose
506	* SXW3461-1: Merging Tuner Changes
507	*
508	* 17 3/10/11 5:35p cbrooks
509	* sw3461-1: New Code
510	*
511	* 16 3/10/11 5:00p mbsingh
512	* sw3461-1: Updating SD ADC Calibration routine based on sd_routine.bss
513	* from Dave
514	*
515	* 15 3/9/11 9:02p cbrooks
516	* sw3461-1:Added LNA level and RFVGA level to status
517	*
518	* 14 3/9/11 3:01p farshidf
519	* SW3461-1: fix the math function
520	*
521	* 13 3/8/11 8:26p cbrooks
522	* sw3461-1:new code
523	*
524	* 12 3/8/11 2:43p cbrooks
525	* sw3461-1:new code
526	*
527	* 11 3/7/11 9:27p cbrooks
528	* sw3461-1:new code
529	*
530	* 9 3/6/11 6:36p cbrooks
531	* sw3461-1:new code
532	*
533	* 7 3/6/11 5:58p cbrooks
534	* SW3461-1:New TNR Code
535	*
536	* 6 3/2/11 4:59p mpovich
537	* SW3461-1: Fix TNR struct compiler bugs. Add HAB related updates for T2
538	* and for TNR.
539	*
540	* Rom_Devel_3461/1 3/2/11 4:24p mpovich
541	* SW3461-1: Fix TNR struct compiler bugs. Add HAB related updates for T2
542	* and for TNR.
543	*
544	* 5 3/1/11 12:59p cbrooks
545	* sw3461-1:new code
546	*
547	* 4 2/28/11 3:38p cbrooks
548	* SW3461-1:new code for tuner
549	*
550	* 3 2/25/11 5:04p shchang
551	* sw3461-1:new code
552	*
553	* 2 2/24/11 3:18p farshidf
554	* SW3461-1: update the code for tuner
555	*
556	* 1 2/24/11 11:27a farshidf
557	* SW3461-1: add the initial Tuner code from Dave
558	*
559	***************************************************************************/
560	#include "bstd.h"
561	#include "bkni.h"
562	#include "btmr.h"
563	#ifndef LEAP_BASED_CODE
564	#include "btnr.h"
565	#include "bdbg.h"
566	#include "btnr_priv.h"
567	#include "btnr_3x7x_priv.h"
568	#endif
569	#include "btnr_global_clk.h"
570	#include "btnr_struct.h"
571	#ifdef LEAP_BASED_CODE
572	#include "btnr_api.h"
573	#include "blna.h"
574	#endif
575	#include "btnr_tune.h"
576	#include "bmth.h"
577	#ifdef SmartTuneEnabled
578	#include "bchp_tm.h"
579	#endif
580
581	#include "bchp_ufe_afe.h"
582	#include "bchp_sdadc.h"
583	#ifndef LEAP_BASED_CODE
584	BDBG_MODULE(btnr_tune);
585	#define POWER2_24 16777216
586	#define POWER2_3 8
587	#define POWER2_16 65536
588	#define POWER2_29 536870912
589	#define POWER2_27 134217728
590	#endif
591	#include "bchp_ufe.h"
592
593
594	#define BTNR_TUNER_CAP_CNTL_TABLE_SIZE 5
595	#define BAST_ENABLE_HW_AUTO_TUNE
596	#define abs(x) ((x)<0?-(x):(x))
597	/#define ENABLE_LNA_AGC_CYCLE/
598
599
600	/*******************************************************************************************
601	*BTNR_P_LNAAGCCycle() This routine keeps LNA AGC and 6 Bit ADC enabled for a small duty
602	*cycle to save power. LNA AGC is slower than RF AGC so slower reaction time is not an issue.
603	*The PI will call the BTNR_P_LNAAGCCycle() every Xmsec (presently 100ms), based on a timer
604	*interrupt
605	*******************************************************************************************/
606	BERR_Code BTNR_P_LNAAGCCycle(BTNR_3x7x_Handle h)
607	{
608	BERR_Code retCode = BERR_SUCCESS;
609
610	#ifdef ENABLE_LNA_AGC_CYCLE
611	/* --- UnFreeze LNA --- */
612	/Power up PHYPLL ch1 & 6-bit ADC. Unfreeze LNA AGC/
613	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
614	temp = temp \| 0x1 ;
615	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
616	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
617	temp = temp \| 0x1 ;
618	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, temp);
619
620	BKNI_Delay(20); /20 usec/
621	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_ADC6B, 0x1);
622	BKNI_Delay(20); /20 usec/
623
624	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_03, AGC_frz, 0x0);
625
626
627	/* --- Sleep X (To control the duty cycle) --- */
628	BKNI_Sleep(20);
629
630	/* --- Freeze LNA --- */
631	/Freeze LNA AGC , Power Down 6-bit ADC & PHYPLL ch1/
632	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_03, AGC_frz, 0x1);
633	BKNI_Delay(20); /20 usec/
634
635	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_ADC6B, 0x0);
636
637	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
638	temp = temp & 0x3E ;
639	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
640	#else
641	BSTD_UNUSED(h);
642	#endif
643
644	/goto label to return error code if something bad happened above/
645	return retCode;
646	}
647
648	/*******************************************************************************************
649	* BTNR_P_Daisy_Control() This routine controls the the Daisy output
650	*The PI will call the BTNR_P_Tuner_Power_Control() when it detects a change in the
651	*h->pTunerParams->BTNR_Daisy_Params.Daisy_Enable THEN call this function
652	*******************************************************************************************/
653	BERR_Code BTNR_P_Daisy_Control(BTNR_3x7x_Handle h)
654	{
655	BERR_Code retCode = BERR_SUCCESS;
656
657	if (h->pTunerParams->BTNR_Daisy_Params.Daisy_Enable == BTNR_Daisy_Params_eEnable)
658	{
659	/anything not handled by BTNR_P_Tuner_Power_Control()/
660
661	if (h->pTunerParams->BTNR_Daisy_Params.Daisy_Source == BTNR_Daisy_Source_eVHF)
662	{
663	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_VHF, 0x1);
664	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_UHF, 0x0);
665	}
666	else if (h->pTunerParams->BTNR_Daisy_Params.Daisy_Source == BTNR_Daisy_Source_eUHF)
667	{
668	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_VHF, 0x0);
669	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_UHF, 0x1);
670	}
671	else if (h->pTunerParams->BTNR_Daisy_Params.Daisy_Source == BTNR_Daisy_Source_eUHF_VHF)
672	{
673	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_VHF, 0x1);
674	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_UHF, 0x1);
675	}
676	}
677	else
678	{
679	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_VHF, 0x0);
680	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DAISY_UHF, 0x0);
681	}
682
683	BDBG_MSG((" BTNR_P_Daisy_Control() Complete\n"));
684
685	/goto label to return error code if something bad happened above/
686	return retCode;
687	}
688
689	/*******************************************************************************************
690	* BTNR_P_LoopThru_Control() This routine controls the LoopThru output
691	*The PI will call the BTNR_P_Tuner_Power_Control() when it detects a change in the
692	*h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Enable THEN call this function
693	*******************************************************************************************/
694
695	BERR_Code BTNR_P_LoopThru_Control(BTNR_3x7x_Handle h)
696	{
697	BERR_Code retCode = BERR_SUCCESS;
698
699	if (h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Enable == BTNR_LoopThru_Params_eEnable)
700	{
701	/anything not handled by BTNR_P_Tuner_Power_Control()/
702	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_LT, 0x1);
703	}
704	else
705	{
706	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_LT, 0x0);
707	}
708
709	BDBG_MSG((" BTNR_P_LoopThru_Control() Complete\n"));
710
711	/goto label to return error code if something bad happened above/
712	return retCode;
713	}
714
715	/*******************************************************************************************
716	* BTNR_P_DPM_Control() This routine controls the LoopThru output
717	*The PI will call the BTNR_P_Tuner_Power_Control() when it detects a change in the
718	*h->pTunerParams->BTNR_DPM_Params.DPM_Enable THEN call this function
719	*******************************************************************************************/
720	BERR_Code BTNR_P_DPM_Control(BTNR_3x7x_Handle h)
721	{
722	BERR_Code retCode = BERR_SUCCESS;
723	uint16_t temp;
724	if (h->pTunerParams->BTNR_DPM_Params.DPM_Enable == BTNR_DPM_Params_eEnable)
725	{
726	BTNR_P_DPMSetFreq(h);
727	}
728	else
729	{
730	/Power down DPM/
731	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DPM_LOBUF_REG, 0x0);
732	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DPM, 0x0);
733	/Power down DPM fx clock/
734	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
735	BDBG_MSG(("BTNR_P_TunerSetFreq: temp=%d",temp));
736	temp = temp & 0x2F ;
737	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
738	}
739	BDBG_MSG((" BTNR_P_DPM_Control() Complete\n"));
740
741	return retCode;
742	}
743	/******************************************************************************
744	BTNR_P_DPMSetFreq()
745	******************************************************************************/
746	void BTNR_P_DPMSetFreq(BTNR_3x7x_Handle h)
747	{
748	/local variables/
749	uint8_t index, M, N;
750	uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, Freq;
751	uint16_t temp;
752	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1) /* #if (BCHP_VER != BCHP_VER_A0) */
753	uint32_t ReadReg;
754	#endif
755
756	/* power up DPM */
757	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DPM_LOBUF_REG, 0x1);
758	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DPM, 0x1);
759
760	/* Enable DPM fx clock */
761	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
762	BDBG_MSG(("BTNR_P_TunerSetFreq: temp=%d",temp));
763	temp = temp \| 0x10 ;
764	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
765	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
766
767	/* Enable divider change on the fly */
768	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m5div, 0x20);
769	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
770	BDBG_MSG(("BTNR_P_TunerSetFreq: temp=%d",temp));
771	temp = temp \| 0x1 ;
772	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, temp);
773	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
774	temp = temp \| 0x10 ;
775	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, temp);
776	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
777
778	/* Enable LO state-machine clock */
779	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
780	temp = temp \| 0x4 ;
781	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
782
783	/* Enable divider change on the fly */
784	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
785	BDBG_MSG(("BTNR_P_TunerSetFreq: temp=%d",temp));
786	temp = temp \| 0x4 ;
787	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, temp);
788	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
789
790	/* Change LO settings */
791	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_02, lP_QPbiasCNT_1p0, 0xC);
792	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_02, lP_QPbiasCNT2_1p0, 0x4);
793	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_VcREF_1p0, 0x15);
794	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_04, lP_mainVbal_1p0, 0x1);
795	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_04, lP_mainIbal_1p0, 0x0);
796
797	/Enable auto tuner/
798	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LO_SMtuner_resetb, 0x0);
799	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x0);
800	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_param_sel, 0x1);
801	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LO_SMtuner_resetb, 0x1);
802
803	/* lookup freq range */
804	for (index = 0; index < BTNR_DPM_LO_TABLE_SIZE; index++)
805	{
806	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= DPM_LO_Freq_Table[index])
807	{
808	/index = BTNR_TUNER_LO_TABLE_SIZE;/
809	break;
810	}
811	}
812
813	BDBG_MSG(("BTNR_P_TunerSetFreq: index%d \n",index));
814
815	/Program the values for LO/
816	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MXR_SR6p8p12p16p, DPM_LO_Table[index].i_MXR_SR6p8p12p16p);
817	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel_div_ratio, DPM_LO_Table[index].i_MIXER_sel_div_ratio);
818	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel, DPM_LO_Table[index].i_MIXER_sel);
819	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_HRM_mode, DPM_LO_Table[index].i_MIXER_HRM_mode);
820	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel_MUX0p6p8p, DPM_LO_Table[index].i_MIXER_sel_MUX0p6p8p);
821	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_fbdivn_1p0, DPM_LO_Table[index].lP_fbdivn_1p0);
822	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_div23_sel_1p0, DPM_LO_Table[index].lP_div23_sel_1p0);
823
824	/Program the values for DPM/
825	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_PreSel, DPM_Table[index].logen_PreSel);
826	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_two, DPM_Table[index].logen_two);
827	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_six, DPM_Table[index].logen_six);
828	BKNI_Sleep(10);
829
830	/* Set the DDFS FCW*/
831	M = DPM_LO_Table[index].M_Factor;
832	N = DPM_LO_Table[index].lP_fbdivn_1p0;
833
834	BDBG_MSG(("BTNR_P_TunerSetFreq: M=%d, N=%d\n",M, N));
835
836	/* FCW = (Fc/RFPLL_FREQ)(M/N)2^37* where Fc is desired frequency
837	* M[2 255], N[4,8,12,16,24,32,64]
838	* FCW = (Fc(M2^23)/N) * (2^14/RFPLL_FREQ) where Fc is desired frequency*/
839	BDBG_MSG((" Rf Freq=%08x\n",h->pTunerParams->BTNR_Acquire_Params.RF_Freq));
840
841	#if 1
842	Freq = (h->pTunerParams->BTNR_Acquire_Params.RF_Freq);
843
844	ulMultA = 0x20;
845	ulMultB = 0;
846	ulNrmHi = 0;
847	ulNrmLo = Freq*M/100;
848
849	BMTH_HILO_64TO64_Mul(ulMultA, ulMultB, ulNrmHi, ulNrmLo, &ulMultA, &ulMultB);
850	BDBG_MSG((" First %08x, %08x\n",ulMultA, ulMultB));
851	BMTH_HILO_64TO64_Div32(ulMultA, ulMultB, ((REFPLL_FREQ/100)*N), &ulNrmHi, &ulNrmLo);
852	BDBG_MSG((" Second %08x, %08x\n",ulNrmHi, ulNrmLo));
853	#endif
854
855	if (ulNrmHi > 0x0000001F)
856	{
857	BDBG_ERR(("DDFS is outside of the 37 bit range in BTNR_P_TunerSetFreq()"));
858	}
859
860	/* Setup DDFS*/
861	/* program fcw[36:5] and fcw[4:0]*/
862	ulNrmHi = (((ulNrmHi<<27) & 0xF8000000) \| ((ulNrmLo>>5) & 0x07FFFFFF)); /Get 32 msb's/
863	ulNrmLo = (ulNrmLo & 0x0000001F); /Get 5 lsb's/
864	/Reset and Release DDFS/
865	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)/* (BCHP_VER == BCHP_VER_A0) / / TO FIX - Fixed*/
866	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7afe );
867	BKNI_Sleep(1);
868	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7aff );
869	#else
870	ReadReg = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02);
871	ReadReg = ReadReg \| 0x7afe ;
872	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, ReadReg);
873	BKNI_Sleep(1);
874	ReadReg = ReadReg \| 0x7aff ;
875	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, ReadReg);
876	#endif
877
878	/Program FCW/
879	BDBG_MSG(("BTNR_P_TunerSetFreq: Hi=%x, Lo=%x\n",ulNrmHi, ulNrmLo));
880	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_DDFS_FCW_02, ulNrmHi); /32 MSB of 37 bit word/
881	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_DDFS_FCW_01, ulNrmLo); /* 5 LSB of 37 bit word*/
882
883	/* De-assert reset/resetb for div23, cml, SR, pre_div */
884	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_rstdiv23_1p0, 0x1);
885	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_cmlDIVRST, 0x1);
886	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_ld_RESET_STRT_1p0, 0x1);
887	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_rstdiv23_1p0, 0x0);
888	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_cmlDIVRST, 0x0);
889	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_ld_RESET_STRT_1p0, 0x0);
890
891	/* Startup DDFS*/
892	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x1);
893	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x0);
894	BKNI_Sleep(1);
895	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x1);
896	BKNI_Sleep(1);
897	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x0);
898
899	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x1);
900	BKNI_Sleep(1);
901	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x0);
902	BKNI_Sleep(1);
903
904	/SR, pre_div /
905	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x1);
906	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x1);
907	BKNI_Delay(20); /20 usec/
908	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x0);
909	BKNI_Delay(20); /20 usec/
910	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x0);
911
912
913	/Power down state machine clock/
914	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
915	BDBG_MSG(("BTNR_P_TunerSetFreq: temp=%d",temp));
916	temp = temp & 0x3B ;
917	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
918	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
919	BDBG_MSG(("BTNR_P_TunerSetFreq: temp=%d",temp));
920
921	/* DPM Settings */
922	/* DPM Amplitude Settings */
923	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, DPM_6dB, 0x1); /enabling 6dB boost/
924	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, DPM_amp0, 0x1); /setting the output power LSB/
925	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, DPM_amp1, 0x1); /setting the output power/
926	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, DPM_amp2, 0x1); /setting the output power MSB/
927	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, sel_I, 0x1); /Setting the mode for upconversion/downconversion. Toggle this bit to change the mode./
928	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, sel_Q, 0x0); /Setting the mode for upconversion/downconversion/
929
930	/* LOGen Settings */
931	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_I_Qneg, 0x0);
932
933	/* assert/de-assert DPM reset/resetb */
934	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_logen_reset, 0x1);
935	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_start, 0x0);
936	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_async_reset, 0x0);
937	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, reset_1p0, 0x0);
938	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_logen_reset, 0x0);
939	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_start, 0x0);
940	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_logen_reset, 0x0);
941	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_logen_start, 0x1);
942	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, reset_1p0, 0x1);
943	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, reset_1p0, 0x0);
944
945	/enable DPM out/
946	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_DPM_switch, 0x1);
947	/* UFE_AFE.TNR0_PWRUP_01.i_pwrup_DAISY_UHF = 1
948	UFE_AFE.TNR0_DS_01.i_DAISY_UHF_DPM_sel = 0*/
949	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_atten, 0x1);
950	BKNI_Sleep(1);
951	/* assert/de-assert mixer reset/resetb */
952	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x1);
953	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x1);
954	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x0);
955	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x0);
956
957	/TEMPORARY CODE - BYPASS LNA - Will be removed when LNA is working/
958	/* BREG_WriteField(h->hRegister,UFE_AFE_TNR0_PWRUP_01, i_pwrup_LNA, 0x0);
959	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_bypass, 0x1);
960	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_pad_en, 0x1);*/
961	}
962
963	/*******************************************************************************************
964	* BTNR_P_Tuner_PowerUpPLL() This routine controls the power up/down of the tuner blocks
965	*******************************************************************************************/
966	BERR_Code BTNR_P_Tuner_PowerUpPLL(BTNR_3x7x_Handle h)
967	{
968	BERR_Code retCode = BERR_SUCCESS;
969	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_1)
970	if (h->pTunerParams->BTNR_Local_Params.RevId == BCHP_VER_B1)
971	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, i_clk_sel, 0x1);
972	else
973	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, i_clk_sel, 0x0);
974	#elif (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_2) /* 3462 A0 */
975	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, i_clk_sel, 0x1);
976	#endif
977	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_01, 0x00030001);
978
979	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
980	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, 0x00298000);
981	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR_PWRUP_01, 0x00006CFF);
982	#elif (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
983	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, 0x002B8000);
984	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR_PWRUP_01, 0x00006806);
985	#endif
986
987	/* BKNI_Sleep(1);*/
988	BDBG_MSG(("BTNR_P_Tuner_PowerUpPLL() Complete\n"));
989	return retCode;
990	}
991	/*******************************************************************************************
992	* BTNR_P_Tuner_Power_Control() This routine controls the power up/down of the tuner blocks
993	*******************************************************************************************/
994	BERR_Code BTNR_P_Tuner_Power_Control(BTNR_3x7x_Handle h)
995	{
996	BERR_Code retCode = BERR_SUCCESS;
997
998	uint32_t temp_UFE_AFE_TNR0_PWRUP_01 = 0;
999	uint32_t temp_UFE_AFE_TNR0_PWRUP_02 = 0;
1000	uint32_t temp_UFE_AFE_TNR_PWRUP_01 = 0;
1001	uint32_t temp_SDADC_CTRL_PWRUP = 0;
1002	/enable LNA bypass switch/
1003	uint8_t temp_i_LNA_bypass = 1;
1004	/disable DPM to daisy switch/
1005	uint8_t temp_i_DAISY_UHF_DPM_sel = 1;
1006	/disable DPM to RFVGA switch/
1007	uint8_t temp_i_DPM_switch = 0;
1008
1009	h->pTunerParams->BTNR_Internal_Params.LNA_Enable = BTNR_Internal_Params_eEnable;
1010
1011	/Set RFPLL and PHYPLL/
1012	/REFPLL_FREQ = REF_FREQ/REF_OUTDIV_m0REF_DIV_fb/REF_DIV_ratio = 1080 MHz*/
1013	BREG_WriteField(h->hRegister, UFE_AFE_TNR_REFPLL_01, REF_DIV_fb, 0x14); /REF_DIV_fb = 20/
1014	BREG_WriteField(h->hRegister, UFE_AFE_TNR_REFPLL_02, REF_DIV_ratio, 0x01); /REF_DIV_ratio = 1/
1015	BREG_WriteField(h->hRegister, UFE_AFE_TNR_REFPLL_03, REF_OUTDIV_m0, 0x01); /REF_OUTDIV_m0 = 1/
1016
1017	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1018	BREG_WriteField(h->hRegister, UFE_AFE_TNR_REFPLL_03, REF_CLK_bypass_enable, 0x1);
1019	#else
1020	BREG_WriteField(h->hRegister, UFE_AFE_TNR_REFPLL_03, REF_CLK_bypass_enable, 0x0);
1021	#endif
1022
1023	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_1)
1024	if (h->pTunerParams->BTNR_Local_Params.RevId == BCHP_VER_B1)
1025	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, i_clk_sel, 0x1);
1026	else
1027	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, i_clk_sel, 0x0);
1028	#elif (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_2) /* 3462 A0 */
1029	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, i_clk_sel, 0x1);
1030	#endif
1031	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_02, ndiv_frac, 0x0);/ndiv_frac = 0/
1032	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, p1div, 0x01); /p1div = 1/
1033	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, ndiv_int, 0x32);/ndiv_int = 50/
1034	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m1div, 0x01); /m1div = 1/
1035	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m2div, 0x02); /m2div = 2/
1036	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m3div, 0x0C); /m3div = 12/
1037	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m4div, 0x1B); /m4div = 27/
1038	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m5div, 0x00); /m5div = 256/
1039	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m6div, 0x05); /m6div = 5/
1040	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, 0x3F);
1041
1042	/optimize PHYPLL/
1043	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_01, kvcox, 0x3);
1044	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_01, Icpx, 0x1F);
1045	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_01, Icpx2, 0x1);
1046	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_01, Rz, 0xF);
1047
1048	/**********************************************************
1049	*tuner power modes
1050	*********************************************************/
1051	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
1052	{
1053	case BTNR_Tuner_Power_Mode_eMini_Power: /Tuner in minimum power mode/
1054	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00030001);
1055	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00208000);
1056	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00000042);
1057	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1058	temp_i_LNA_bypass = 1;
1059	break;
1060	case BTNR_Tuner_Power_Mode_eUHF_Power: /Tuner in UHF input mode/
1061	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0F0F83F5);
1062	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
1063	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0028FAFF);
1064	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00002CFF);
1065	#elif (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1066	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x002BFAFF);
1067	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00006806);
1068	#endif
1069	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1070	temp_i_LNA_bypass = 1;
1071	break;
1072	case BTNR_Tuner_Power_Mode_eVHF_Power: /Tuner in VHF input mode/
1073	if (h->pTunerParams->BTNR_Internal_Params.LNA_Enable == BTNR_Internal_Params_eEnable) /Tuner in VHF input mode: LNA enabled/
1074	{
1075	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0FA383F7);
1076	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
1077	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0029FAFF);
1078	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00006CFF);
1079	#elif (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1080	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x002BFAFF);
1081	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00006806);
1082	#endif
1083	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1084	temp_i_LNA_bypass = 0;
1085	}
1086	else /Tuner in VHF input mode: LNA disabled/
1087	{
1088	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0EA383F5);
1089	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0029FAFF);
1090	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00006CFF);
1091	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1092	temp_i_LNA_bypass = 1;
1093	}
1094	break;
1095	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power: /Tuner in UHF + VHF input mode/
1096	if (h->pTunerParams->BTNR_Internal_Params.LNA_Enable == BTNR_Internal_Params_eEnable) /Tuner in UHF + VHF input mode: LNA enabled/
1097	{
1098	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0F0F83F7);
1099	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0028FAFF);
1100	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00002CFF);
1101	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1102	temp_i_LNA_bypass = 0;
1103	}
1104	else /Tuner in UHF + VHF input mode: LNA disabled/
1105	{
1106	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0E0F83F5);
1107	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0028FAFF);
1108	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00002CFF);
1109	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1110	temp_i_LNA_bypass = 1;
1111	}
1112	break;
1113	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power: /Tuner in VHF input mode/
1114	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0CA10817);
1115	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
1116	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00038000);
1117	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00006CFF);
1118	#elif (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1119	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00038000);
1120	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00004000);
1121	#endif
1122
1123	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1124	temp_i_LNA_bypass = 0;
1125	break;
1126	default:
1127	BDBG_ERR(("ERROR!!! h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode, value received is %d",h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode));
1128	retCode = BERR_INVALID_PARAMETER;
1129	/goto bottom of function to return error code/
1130	goto something_bad_happened;
1131	}
1132
1133	/**********************************************************
1134	*IF ONLY the Daisy is on, tuner is in minimum power mode
1135	*********************************************************/
1136	if (h->pTunerParams->BTNR_Daisy_Params.Daisy_Enable == BTNR_Daisy_Params_eEnable)
1137	{
1138	switch (h->pTunerParams->BTNR_Daisy_Params.Daisy_Source)
1139	{
1140	case BTNR_Daisy_Source_eUHF:
1141	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00039001);
1142	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00208000);
1143	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00000000);
1144	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1145	break;
1146	case BTNR_Daisy_Source_eVHF:
1147	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x0FA30817);
1148	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00218000);
1149	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00006CFF);
1150	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1151	break;
1152	case BTNR_Daisy_Source_eUHF_VHF:
1153	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00031801);
1154	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00208000);
1155	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00000000);
1156	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1157	break;
1158	default:
1159	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Daisy_Params.Daisy_Source, value received is %d",h->pTunerParams->BTNR_Daisy_Params.Daisy_Source));
1160	retCode = BERR_INVALID_PARAMETER;
1161	/goto bottom of function to return error code/
1162	goto something_bad_happened;
1163	}
1164	}
1165	else if (h->pTunerParams->BTNR_Daisy_Params.Daisy_Enable == BTNR_Daisy_Params_eDisable)
1166	{
1167	/do nothing/
1168	}
1169	else
1170	{
1171	BDBG_ERR(("ERROR!!! h->pTunerParams->BTNR_Daisy_Params.Daisy_Enable, value received is %d",h->pTunerParams->BTNR_Daisy_Params.Daisy_Enable));
1172	retCode = BERR_INVALID_PARAMETER;
1173	/goto bottom of function to return error code/
1174	goto something_bad_happened;
1175	}
1176
1177	/***********************************************************
1178	*IF ONLY the LoopThru is on, tuner is in minimum power mode
1179	**********************************************************/
1180	if (h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Enable == BTNR_LoopThru_Params_eEnable)
1181	{
1182	switch (h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Source)
1183	{
1184	case BTNR_LoopThru_Source_eVHF:
1185	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00030401);
1186	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00208000);
1187	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00000000);
1188	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1189	break;
1190	case BTNR_LoopThru_Source_eDAC:
1191	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00430001);
1192	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00208000);
1193	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00000000);
1194	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1195	break;
1196	case BTNR_LoopThru_Source_eVHF_DAC:
1197	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00430401);
1198	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x00208000);
1199	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00000000);
1200	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1201	break;
1202	default:
1203	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Source, value received is %d",h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Source));
1204	retCode = BERR_INVALID_PARAMETER;
1205	/goto bottom of function to return error code/
1206	goto something_bad_happened;
1207	}
1208	}
1209	else if (h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Enable == BTNR_LoopThru_Params_eDisable)
1210	{
1211	/do nothing/
1212	}
1213	else
1214	{
1215	BDBG_ERR(("ERROR!!! h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Enable, value received is %d",h->pTunerParams->BTNR_LoopThru_Params.LoopThru_Enable));
1216	retCode = BERR_INVALID_PARAMETER;
1217	/goto bottom of function to return error code/
1218	goto something_bad_happened;
1219	}
1220
1221	/***********************************************************
1222	*IF ONLY the DPM is on, tuner is in minimum power mode
1223	**********************************************************/
1224	if (h->pTunerParams->BTNR_DPM_Params.DPM_Enable == BTNR_DPM_Params_eEnable)
1225	{
1226	switch(h->pTunerParams->BTNR_DPM_Params.DPM_Target)
1227	{
1228	case BTNR_DPM_Target_eDaisyUHF :
1229	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00037001);
1230	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0030FAFF);
1231	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00002CFF);
1232	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1233	/enable DPM to daisy switch/
1234	temp_i_DAISY_UHF_DPM_sel = 0;
1235	/disable DPM to RFVGA switch/
1236	temp_i_DPM_switch = 0;
1237	break;
1238	case BTNR_DPM_Target_eRFVGA :
1239	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00036001);
1240	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0030FAFF);
1241	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00002CFF);
1242	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1243	/disable DPM to daisy switch/
1244	temp_i_DAISY_UHF_DPM_sel = 1;
1245	/enable DPM to RFVGA switch/
1246	temp_i_DPM_switch = 1;
1247	break;
1248	case BTNR_DPM_Target_eDaisyUHF_RFVGA :
1249	temp_UFE_AFE_TNR0_PWRUP_01 = (temp_UFE_AFE_TNR0_PWRUP_01 \| 0x00037001);
1250	temp_UFE_AFE_TNR0_PWRUP_02 = (temp_UFE_AFE_TNR0_PWRUP_02 \| 0x0030FAFF);
1251	temp_UFE_AFE_TNR_PWRUP_01 = (temp_UFE_AFE_TNR_PWRUP_01 \| 0x00002CFF);
1252	temp_SDADC_CTRL_PWRUP = (temp_SDADC_CTRL_PWRUP \| 0x00000003);
1253	/enable DPM to daisy switch/
1254	temp_i_DAISY_UHF_DPM_sel = 0;
1255	/enable DPM to RFVGA switch/
1256	temp_i_DPM_switch = 1;
1257	break;
1258	default:
1259	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_DPM_Params.DPM_Target, value received is %d",h->pTunerParams->BTNR_DPM_Params.DPM_Target));
1260	retCode = BERR_INVALID_PARAMETER;
1261	/goto bottom of function to return error code/
1262	goto something_bad_happened;
1263	}
1264	}
1265	else if (h->pTunerParams->BTNR_DPM_Params.DPM_Enable == BTNR_DPM_Params_eDisable)
1266	{
1267	/do nothing/
1268	}
1269	else
1270	{
1271	BDBG_ERR(("ERROR!!! h->pTunerParams->BTNR_DPM_Params.DPM_Enable, value received is %d",h->pTunerParams->BTNR_DPM_Params.DPM_Enable));
1272	retCode = BERR_INVALID_PARAMETER;
1273	/goto bottom of function to return error code/
1274	goto something_bad_happened;
1275	}
1276
1277	/***********************************************************
1278	*Write the tuner power values to the chip
1279	**********************************************************/
1280	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_01, temp_UFE_AFE_TNR0_PWRUP_01);
1281	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, temp_UFE_AFE_TNR0_PWRUP_02);
1282	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR_PWRUP_01, temp_UFE_AFE_TNR_PWRUP_01);
1283	BREG_Write32(h->hRegister, BCHP_SDADC_CTRL_PWRUP, temp_SDADC_CTRL_PWRUP);
1284	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_bypass, temp_i_LNA_bypass);
1285	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DS_01, i_DAISY_UHF_DPM_sel, temp_i_DAISY_UHF_DPM_sel);
1286	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DPM_01, i_DPM_switch, temp_i_DPM_switch);
1287
1288	/* De-assert reset/resetb for REFPLL/PHYPLL */
1289	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR_RESETB_01, 0x00000003);
1290	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR_RESET_01, 0xFFFFFFF0);
1291	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, PHYPLL_dreset, 0);
1292	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, PHYPLL_areset, 0);
1293
1294	BDBG_MSG(("BTNR_P_Tuner_Power_Control() Complete\n"));
1295
1296	/goto label to return error code if something bad happened above/
1297	something_bad_happened:
1298	return retCode;
1299	}
1300
1301	/******************************************************************************
1302	BTNR_P_TunerStatusReset() - reset the status structure
1303	******************************************************************************/
1304	BERR_Code BTNR_P_TunerStatusReset(BTNR_3x7x_Handle h)
1305	{
1306	BERR_Code retCode = BERR_SUCCESS;
1307
1308	/* clear the lock status */
1309	h->pTunerStatus->Tuner_Ref_Lock_Status = BTNR_Status_eUnlock;
1310	h->pTunerStatus->Tuner_Mixer_Lock_Status = BTNR_Status_eUnlock;
1311	h->pTunerStatus->Tuner_Phy_Lock_Status = BTNR_Status_eUnlock;
1312	h->pTunerStatus->Tuner_RF_Freq = 0;
1313	h->pTunerStatus->Tuner_PreADC_Gain_x256db = (int16_t)0x8000;
1314	h->pTunerStatus->External_Gain_x256db = (int16_t)0x8000;
1315
1316	return retCode;
1317	}
1318
1319	/*******************************************************************************************************************
1320	* BTNR_P_TunerSetRFSignalPath() This routine sets the tuner LNA, RFVGA & RF filter
1321	******************************************************************************************************************/
1322	static void BTNR_P_TunerSetRFSignalPath(BTNR_3x7x_Handle h)
1323	{
1324	if (h->pTunerParams->BTNR_Internal_Params.LNA_Enable == BTNR_Internal_Params_eDisable)
1325	{
1326	#ifdef LEAP_BASED_CODE
1327	BLNA_P_Init_LNA(h->pLna); /* Initialize external LNA BCM3406 */
1328	BLNA_P_Set_LNA_Boost(h->pLna);
1329	#endif
1330	}
1331	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
1332	{
1333	case BTNR_TunerApplicationMode_eTerrestrial:
1334	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq > 334020000)
1335	{
1336	/Use MOCA Trap/
1337	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, RF_DPD_sel, 1);/* RF peak-detector set to MoCA trap */
1338	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL, 0x0);
1339	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen, 1);
1340	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, 0x0);
1341	}
1342	else if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 334020000)
1343	{
1344	/Use Tracking Filter Trap/
1345	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, RF_DPD_sel, 0);/* RF peak-detector set to tracking filter */
1346	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL, 0x1);
1347	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen, 0);
1348	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, 0x0);
1349	BTNR_P_TunerSetRFFIL(h); /* set bandwidth of RF tracking filter */
1350	}
1351	break;
1352	case BTNR_TunerApplicationMode_eCable:
1353	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq > 502000000)
1354	{
1355	/Use MOCA Trap/
1356	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, RF_DPD_sel, 1);/* RF peak-detector set to MoCA trap */
1357	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL, 0x0);
1358	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen, 1);
1359	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, 0x0);
1360	}
1361	else if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 502000000)
1362	{
1363	/Use Tracking Filter Trap/
1364	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, RF_DPD_sel, 0);/* RF peak-detector set to tracking filter */
1365	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL, 0x1);
1366	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen, 0);
1367	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, 0x0);
1368	BTNR_P_TunerSetRFFIL(h); /* set bandwidth of RF tracking filter */
1369	}
1370	break;
1371	default:
1372	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
1373	}
1374	BDBG_MSG(("BTNR_P_TunerSetRFSignalPath() Complete\n"));
1375	}
1376
1377	/*******************************************************************************************************************
1378	* BTNR_P_TunerSetSignalPathPower() This routine sets the tuner signal path power
1379	******************************************************************************************************************/
1380	static void BTNR_P_TunerSetSignalPathPower(BTNR_3x7x_Handle h)
1381	{
1382	#ifndef BTNR_J83A_SUPPORT
1383	uint8_t temp;
1384	#endif
1385	/enable dither clock/
1386	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x1);
1387	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_freeze_gain, 0x0);
1388	/SDADC attenuator settings/
1389	BREG_WriteField(h->hRegister, SDADC_CTRL_SYS0, i_ctl_adc_gain, 0x1);
1390	/* power settings */
1391	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
1392	{
1393	case BTNR_TunerApplicationMode_eTerrestrial:
1394	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_sf_vcm, 0x1);
1395	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1396	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_SPARE_01, i_LNA_ctrl_bias, 0x1);
1397	#endif
1398	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_sf, 0x4);
1399	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_bias, 0x4);
1400	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_low_I_mode, 0x0);
1401	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_03, i_MIXER_bias_ctrl, 0x0);
1402	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_FGA_bias_ctrl, 0x5);
1403	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_BUF_I_ctrl, 0xA);
1404	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_bias, 0xC);
1405	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg, 0x3);
1406	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_tilt, 0x0);
1407	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_tilt, 0x0);
1408	break;
1409	case BTNR_TunerApplicationMode_eCable:
1410	#ifndef BTNR_J83A_SUPPORT
1411	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_sf_vcm, 0x1);
1412	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1413	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_SPARE_01, i_LNA_ctrl_bias, 0x6);
1414	#endif
1415	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_sf, 0x4);
1416	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_bias, 0x4);
1417	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_low_I_mode, 0x0);
1418	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_03, i_MIXER_bias_ctrl, 0x6);
1419	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_FGA_bias_ctrl, 0x5);
1420	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_BUF_I_ctrl, 0xF);
1421	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_bias, 0x8);
1422	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg, 0x0);
1423	/* SCTE-40 settings */
1424	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq >= 800000000)
1425	{
1426	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_tilt, 0x1);
1427	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_tilt, 0x7);
1428	}
1429	else if ((h->pTunerParams->BTNR_Acquire_Params.RF_Freq >= 300000000) && (h->pTunerParams->BTNR_Acquire_Params.RF_Freq < 800000000))
1430	{
1431	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_tilt, 0x1);
1432	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_tilt, 0x0);
1433	}
1434	else
1435	{
1436	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_tilt, 0x0);
1437	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_tilt, 0x0);
1438	if ((h->pTunerParams->BTNR_Acquire_Params.RF_Freq >= 95000000) && (h->pTunerParams->BTNR_Acquire_Params.RF_Freq < 105000000))
1439	{
1440	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_DCO, 0x0);
1441	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
1442	temp = temp & 0x37 ;
1443	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
1444	}
1445	}
1446	#endif
1447	break;
1448	default:
1449	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
1450	/retCode = BERR_INVALID_PARAMETER;/
1451	/goto bottom of function to return error code/
1452	/goto something_bad_happened;/
1453	}
1454	BDBG_MSG(("BTNR_P_TunerSetSignalPathPower() Complete\n"));
1455	}
1456
1457	/*******************************************************************************************************************
1458	* BTNR_P_TunerSetSignalPathLowPower() This routine sets the tuner signal path power
1459	******************************************************************************************************************/
1460	static void BTNR_P_TunerSetSignalPathLowPower(BTNR_3x7x_Handle h)
1461	{
1462
1463	/SDADC attenuator settings/
1464	BREG_WriteField(h->hRegister, SDADC_CTRL_SYS0, i_ctl_adc_gain, 0x0);
1465	/bias settings/
1466	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_sf_vcm, 0x1);
1467	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1468	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_SPARE_01, i_LNA_ctrl_bias, 0xB);
1469	#endif
1470	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_sf, 0x4);
1471	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_bias, 0x2);
1472	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_low_I_mode, 0x0);
1473	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_03, i_MIXER_bias_ctrl, 0x6);
1474	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_FGA_bias_ctrl, 0x5);
1475	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_BUF_I_ctrl, 0xA);
1476	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_bias, 0xC);
1477	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg, 0x7);
1478	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_tilt, 0x0);
1479	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_tilt, 0x0);
1480	/RFFIL settings/
1481	if ((h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 334020000) && (h->pTunerParams->BTNR_Acquire_Params.RF_Freq > 143160000))
1482	{
1483	/Use MoCA Trap/
1484	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, RF_DPD_sel, 1);/* RF peak-detector set to MoCA trap */
1485	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL, 0x0);
1486	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, 0x0);
1487	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen, 0x1);
1488	}
1489	else if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 143160000)
1490	{
1491	/Use Tracking Filter Trap/
1492	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, RF_DPD_sel, 0);/* RF peak-detector set to tracking filter */
1493	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL, 0x0);
1494	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, 0x1);
1495	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen, 0x0);
1496	}
1497	BDBG_MSG(("BTNR_P_TunerSetSignalPathLowPower() Complete\n"));
1498	}
1499
1500	/******************************************************************************
1501	BTNR_P_TunerStatus() - get the status structure
1502	******************************************************************************/
1503	BERR_Code BTNR_P_TunerStatus(BTNR_3x7x_Handle h)
1504	{
1505	BERR_Code retCode = BERR_SUCCESS;
1506	uint32_t ReadReg0, ReadReg1, ReadReg2, ReadReg3;
1507	int32_t GainReg=0, GainCorrection;
1508	uint8_t PreDivRatio, M, N , ndiv, pdiv;
1509	uint32_t ulMultA, ulMultB, ulDivisor, ulNrmHi, ulNrmLo;
1510	uint16_t temp;
1511
1512	/RefPLL Lock/
1513	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_04, o_REFPLL_lock);
1514	h->pTunerStatus->Tuner_Ref_Lock_Status = (ReadReg0 == 1) ? BTNR_Status_eLock : BTNR_Status_eLock;
1515
1516	/PhyPLL Lock/
1517	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_04, o_PHYPLL_lock);
1518	h->pTunerStatus->Tuner_Phy_Lock_Status = (ReadReg0 == 1) ? BTNR_Status_eLock : BTNR_Status_eLock;
1519
1520	/MixerPLL Lock/
1521	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXRPLL_07, MXRPLL_FREQ_LOCK);
1522	h->pTunerStatus->Tuner_Mixer_Lock_Status = (ReadReg0 == 1) ? BTNR_Status_eLock : BTNR_Status_eLock;
1523
1524	/Ref Freq/
1525	h->pTunerStatus->Tuner_Ref_Freq = REF_FREQ;
1526
1527	/REFPLL_FREQ = REF_FREQ/REF_OUTDIV_m0REF_DIV_fb/REF_DIV_ratio = 1350 MHz*/
1528	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_01, REF_DIV_fb); /REF_DIV_fb/
1529	ReadReg1 = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_02, REF_DIV_ratio); /REF_DIV_ratio/
1530	ReadReg1 = (ReadReg1 >= 1) ? ReadReg1 : 8+ReadReg1;
1531	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_03, REF_OUTDIV_m0); /REF_OUTDIV_m0/
1532
1533	h->pTunerStatus->Tuner_RefPll_Freq = (REF_FREQReadReg0)/(ReadReg1ReadReg2);
1534
1535	/PHYPLL1_FREQ=REF_FREQ(ndiv_int+ndiv_frac/2^24)/p1div]/m1div, m1div is per channel*/
1536	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, ndiv_int); /ndiv_int/
1537	ReadReg1 = (ReadReg1 >= 10) ? ReadReg1 : 512+ReadReg1;
1538	ReadReg1 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_02, ndiv_frac); /ndiv_frac/
1539	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, p1div); /p1div/
1540	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 16+ReadReg2;
1541	ReadReg0 = (REF_FREQ*ReadReg0);
1542	ReadReg1 = (REF_FREQ*ReadReg1)/POWER2_24;
1543	ReadReg0 = (ReadReg0 + ReadReg1)/ReadReg2;
1544
1545	/now for each channels individual divider/
1546	/PHYPLL1_Freq/
1547	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m1div); /m1div/
1548	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 256+ReadReg2;
1549	h->pTunerStatus->Tuner_PhyPll1_Freq = ReadReg0/ReadReg2;
1550	/PHYPLL2_Freq/
1551	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m2div); /m2div/
1552	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 256+ReadReg2;
1553	h->pTunerStatus->Tuner_PhyPll2_Freq = ReadReg0/ReadReg2;
1554	/PHYPLL3_Freq/
1555	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m3div); /m3div/
1556	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 256+ReadReg2;
1557	h->pTunerStatus->Tuner_PhyPll3_Freq = ReadReg0/ReadReg2;
1558	/PHYPLL4_Freq/
1559	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m4div); /m4div/
1560	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 256+ReadReg2;
1561	h->pTunerStatus->Tuner_PhyPll4_Freq = ReadReg0/ReadReg2;
1562	/PHYPLL5_Freq/
1563	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m5div); /m5div/
1564	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 256+ReadReg2;
1565	h->pTunerStatus->Tuner_PhyPll5_Freq = ReadReg0/ReadReg2;
1566	/PHYPLL6_Freq/
1567	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m6div); /m6div/
1568	ReadReg2 = (ReadReg2 >= 1) ? ReadReg2 : 256+ReadReg2;
1569	h->pTunerStatus->Tuner_PhyPll6_Freq = ReadReg0/ReadReg2;
1570
1571	/LNA AGC level/
1572	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_TESTCTRL_00, i_test_LNAAGC, 0x5);
1573	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_LNAAGC_READBUS_00);
1574	ReadReg0 = (ReadReg0>>23) & 0x0000001F;
1575	h->pTunerStatus->Tuner_LNA_Gain_Code = ReadReg0; /This value is used farther down to get gain in db/
1576
1577	/RFVGA AGC level/
1578	ReadReg1 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither);
1579	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x1);
1580	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_raddr, 0x5);
1581	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0);
1582	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 1);
1583	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0);
1584	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_RFAGC_05);
1585
1586	/* turn on dithering if tuner AGC back-off */
1587	h->pTunerStatus->Tuner_RFVGA_Gain_Code = ReadReg0; /This value is used farther down to get gain in db/
1588	if (ReadReg1 == 0)
1589	{
1590	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x0);
1591	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
1592	{
1593	case BTNR_Tuner_Power_Mode_eVHF_Power:
1594	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
1595	if ((h->pTunerStatus->Tuner_RFVGA_Gain_Code != 0xFFFFFFFF) \|\| (h->pTunerStatus->Tuner_LNA_Gain_Code != 0x1D))
1596	{
1597	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x1);
1598	BDBG_MSG(("dithering on"));
1599	}
1600	break;
1601	case BTNR_Tuner_Power_Mode_eUHF_Power:
1602	if (h->pTunerStatus->Tuner_RFVGA_Gain_Code != 0xFFFFFFFF)
1603	{
1604	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x1);
1605	BDBG_MSG(("dithering on"));
1606	}
1607	break;
1608	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
1609	if (h->pTunerStatus->Tuner_LNA_Gain_Code != 0x1D)
1610	{
1611	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x1);
1612	BDBG_MSG(("dithering on"));
1613	}
1614	break;
1615	default:
1616	case BTNR_Tuner_Power_Mode_eMini_Power:
1617	break;
1618	}
1619	}
1620
1621	if (h->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eTerrestrial)
1622	{
1623	if (BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg) == 0x7)
1624	{
1625	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
1626	{
1627	case BTNR_Tuner_Power_Mode_eVHF_Power:
1628	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
1629	if ((((h->pTunerStatus->Tuner_RFVGA_Gain_Code>>16) & 0x0000FFFF) <= 0x6000) \|\| (h->pTunerStatus->Tuner_LNA_Gain_Code != 0x1D))
1630	{
1631	BTNR_P_TunerSetRFSignalPath(h);
1632	BTNR_P_TunerSetSignalPathPower(h);
1633	}
1634	break;
1635	case BTNR_Tuner_Power_Mode_eUHF_Power:
1636	if (((h->pTunerStatus->Tuner_RFVGA_Gain_Code>>16) & 0x0000FFFF) <= 0x6000)
1637	{
1638	BTNR_P_TunerSetRFSignalPath(h);
1639	BTNR_P_TunerSetSignalPathPower(h);
1640	}
1641	break;
1642	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
1643	if (h->pTunerStatus->Tuner_LNA_Gain_Code != 0x1D)
1644	{
1645	BTNR_P_TunerSetRFSignalPath(h);
1646	BTNR_P_TunerSetSignalPathPower(h);
1647	}
1648	break;
1649	default:
1650	case BTNR_Tuner_Power_Mode_eMini_Power:
1651	break;
1652	}
1653	}
1654	else
1655	{
1656	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
1657	{
1658	case BTNR_Tuner_Power_Mode_eVHF_Power:
1659	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
1660	if ((h->pTunerStatus->Tuner_RFVGA_Gain_Code == 0xFFFFFFFF) && (h->pTunerStatus->Tuner_LNA_Gain_Code == 0x1D))
1661	{
1662	BTNR_P_TunerSetSignalPathLowPower(h);
1663	}
1664	break;
1665	case BTNR_Tuner_Power_Mode_eUHF_Power:
1666	if (h->pTunerStatus->Tuner_RFVGA_Gain_Code == 0xFFFFFFFF)
1667	{
1668	BTNR_P_TunerSetSignalPathLowPower(h);
1669	}
1670	break;
1671	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
1672	if (h->pTunerStatus->Tuner_LNA_Gain_Code == 0x1D)
1673	{
1674	BTNR_P_TunerSetSignalPathLowPower(h);
1675	}
1676	break;
1677	default:
1678	case BTNR_Tuner_Power_Mode_eMini_Power:
1679	break;
1680	}
1681	}
1682	}
1683	else if (h->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eCable)
1684	{
1685	if (BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg) == 0x7)
1686	{
1687	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
1688	{
1689	case BTNR_Tuner_Power_Mode_eVHF_Power:
1690	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
1691	case BTNR_Tuner_Power_Mode_eUHF_Power:
1692	if ((ReadReg2 <= 0x5000))
1693	{
1694	BTNR_P_TunerSetRFSignalPath(h);
1695	BTNR_P_TunerSetSignalPathPower(h);
1696	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
1697	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x9);
1698	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x9);
1699	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x9);
1700	}
1701	break;
1702	default:
1703	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
1704	case BTNR_Tuner_Power_Mode_eMini_Power:
1705	break;
1706	}
1707	}
1708	else
1709	{
1710	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
1711	{
1712	case BTNR_Tuner_Power_Mode_eVHF_Power:
1713	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
1714	if ((h->pTunerStatus->Tuner_RFVGA_Gain_Code == 0xFFFFFFFF) && (h->pTunerStatus->Tuner_LNA_Gain_Code == 0x1D))
1715	{
1716	BTNR_P_TunerSetSignalPathLowPower(h);
1717	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
1718	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x7);
1719	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x5);
1720	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x5);
1721	}
1722	break;
1723	case BTNR_Tuner_Power_Mode_eUHF_Power:
1724	if (h->pTunerStatus->Tuner_RFVGA_Gain_Code == 0xFFFFFFFF)
1725	{
1726	BTNR_P_TunerSetSignalPathLowPower(h);
1727	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
1728	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x7);
1729	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x5);
1730	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x5);
1731	}
1732	break;
1733	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
1734	if (h->pTunerStatus->Tuner_LNA_Gain_Code == 0x1D)
1735	{
1736	BTNR_P_TunerSetSignalPathLowPower(h);
1737	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
1738	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x7);
1739	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x5);
1740	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x5);
1741	}
1742	break;
1743	default:
1744	case BTNR_Tuner_Power_Mode_eMini_Power:
1745	break;
1746	}
1747	}
1748	}
1749	/* The following is for the callbacak function to ADS*/
1750	/To get the RF Frequency we need to get the FCW in the DDFS /
1751	/as well as the parameters in the UFE_AFE_TNR0_MXR_01 register/
1752
1753	/Get pre-div ratio/
1754	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel_div_ratio);
1755	PreDivRatio = 1<<ReadReg0;
1756
1757	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_HRM_mode);
1758	ReadReg1 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MXR_SR6p8p12p16p);
1759	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel_MUX0p6p8p);
1760
1761	/GainReg is used later for callback status/
1762	if ((ReadReg0 == 0) && (ReadReg2 == 1))
1763	{
1764	M = PreDivRatio * 1;
1765	GainReg = 6912;
1766	}
1767	else if ((ReadReg0 == 1) && (ReadReg1 == 0) && (ReadReg2 == 2))
1768	{
1769	M = PreDivRatio * 6;
1770	GainReg = 6659; /unit is 256db*/
1771	}
1772	else if ((ReadReg0 == 1) && (ReadReg1 == 1) && (ReadReg2 == 3))
1773	{
1774	M = PreDivRatio * 8;
1775	GainReg = 6528; /unit is 256db*/
1776	}
1777	else if ((ReadReg0 == 1) && (ReadReg1 == 2))
1778	{
1779	M = PreDivRatio * 12;
1780	GainReg = 6528; /unit is 256db*/
1781	}
1782	else if ((ReadReg0 == 1) && (ReadReg1 == 3))
1783	{
1784	M = PreDivRatio * 16;
1785	GainReg = 6528; /unit is 256db*/
1786	}
1787	else
1788	{
1789	BDBG_MSG(("ERROR!!!!! Invalid parameters read fron IC in BTNR_P_TunerStatus()"));
1790	M = 1;
1791	}
1792
1793	N = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_fbdivn_1p0);
1794
1795	/Get FCW/
1796	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_DDFS_FCW_02); /32 MSB of 37 bit word/
1797	ReadReg1 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_DDFS_FCW_01); /* 5 LSB of 37 bit word*/
1798	ReadReg1 = (ReadReg1 & 0x0000001F);
1799
1800	/Fc = (RFPLL_FREQ(temp/ndiv/pdiv)/128)N)FCW/(M2^37)/
1801	/Fc = (RFPLL_FREQ(temp/ndiv/pdiv)/128)N)/2^8FCW/(M2^29)/
1802	/largest N is 24/
1803	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
1804	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_01, REF_DIV_fb);
1805	pdiv = 1;
1806	ndiv = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_02, REF_DIV_ratio);
1807	#elif (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
1808	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, ndiv_int);
1809	pdiv = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, p1div);
1810	ndiv = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m2div);
1811	#endif
1812
1813	ulMultA = REF_FREQ*(temp/ndiv/pdiv);
1814	ulMultB = N;
1815	ulDivisor = 256;
1816	BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
1817	BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
1818
1819	ulMultA = (ReadReg0 & 0xF8000000) >> 27;
1820	ulMultB = ((ReadReg0 & 0x07FFFFFF)<<5) \| (ReadReg1 & 0x0000001F);
1821	ulDivisor = M;
1822	if (ulDivisor == 0)
1823	{
1824	BDBG_ERR(("ERROR!!!!! ulDivisor == 0 in BTNR_P_TunerStatus()"));
1825	}
1826	/BMTH_HILO_64TO64_Div32(ulMultA, ulMultB, ulDivisor, &ulMultA, &ulMultB);/
1827	BMTH_HILO_64TO64_Mul(ulMultA, ulMultB, ulNrmHi, ulNrmLo, &ulMultA, &ulMultB);
1828	BMTH_HILO_64TO64_Div32(ulMultA, ulMultB, ulDivisor, &ulNrmHi, &ulNrmLo);
1829
1830	/Get bits 60:29/
1831	ulNrmLo = (ulNrmHi*POWER2_3 & 0xFFFFFFF8) \| (ulNrmLo/POWER2_29 & 0x0000007);
1832
1833	/Assign value/
1834	h->pTunerStatus->Tuner_RF_Freq = ulNrmLo;
1835
1836	/***********************************************************/
1837	/Get PreADC Gain/
1838	/PreADC Gain = LNA + RFVGA + RFFIL + Mixer_FGA + SDADC_PGA/
1839	/printf("\n\t FGA,SDADC,RFFIl,LNA,RFVGA,LNACorr,RFVGACorr:");/
1840
1841	/Mixer_FGA Gain/
1842	/The GainReg is set above and now must be scaled based on high gain/
1843	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_FGA_HiGain);
1844	GainReg = (ReadReg0 == 0) ? GainReg - 768 : GainReg; /unit is 256db*/
1845	/printf("%d,", GainReg/256);/
1846
1847	/SDADC_PGA Gain is 0, 2, 4, 6 ... up to 14 db/
1848	ReadReg0 = BREG_ReadField(h->hRegister, SDADC_CTRL_SYS0, i_ctl_adc_gain);
1849	GainReg -= 512ReadReg0; /unit is 256db/
1850	/printf("%d,", GainReg/256);/
1851
1852	/RFFIL Gain is either 0 or 2 db/
1853	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_MoCATRAP_swen);
1854	ReadReg1 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en);
1855	ReadReg2 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL_BUF);
1856	ReadReg3 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_pwrup_TRKFIL);
1857
1858	if (((ReadReg0 == 1) && (ReadReg1 == 0) && (ReadReg2 == 1) && (ReadReg3 == 0)) \|\| ((ReadReg0 == 0) && (ReadReg1 == 1) && (ReadReg2 == 1) && (ReadReg3 == 0)))
1859	{
1860	GainReg += 0; /unit is 256db*/
1861	}
1862	else if ((ReadReg0 == 0) && (ReadReg1 == 0) && (ReadReg2 == 1) && (ReadReg3 == 1))
1863	{
1864	GainReg -= 512; /unit is 256db*/
1865	}
1866	else
1867	{
1868	BDBG_ERR(("ERROR!!!!! INVALID COMBINATION OF VALUES RECEIVED IN RFFIL Gain calculation in BTNR_P_TunerStatus())"));
1869	GainReg += 0; /unit is 256db*/
1870	}
1871	/printf("%d,", GainReg/256);/
1872
1873	/LNA Gain/
1874	/This was derived from the Gain curve excel file from David/
1875	/=(290Gain-4080-256Correction)/
1876	/correction is 0 db for 100 MHz, 0.5 db for 200,300,400,500 MHz, 1.5 db for 600,700 MHz, 2.0 db for 800 MHz, 2.5 db for 800,1000 MHz/
1877	ReadReg0 = (int32_t)h->pTunerStatus->Tuner_LNA_Gain_Code;
1878	if (h->pTunerStatus->Tuner_RF_Freq < 150000000)
1879	{
1880	GainCorrection = 0; /unit is 256db*/
1881	}
1882	else if (h->pTunerStatus->Tuner_RF_Freq < 250000000)
1883	{
1884	GainCorrection = -128; /unit is 256db*/
1885	}
1886	else if (h->pTunerStatus->Tuner_RF_Freq < 350000000)
1887	{
1888	GainCorrection = -128; /unit is 256db*/
1889	}
1890	else if (h->pTunerStatus->Tuner_RF_Freq < 450000000)
1891	{
1892	GainCorrection = -128; /unit is 256db*/
1893	}
1894	else if (h->pTunerStatus->Tuner_RF_Freq < 550000000)
1895	{
1896	GainCorrection = -128; /unit is 256db*/
1897	}
1898	else if (h->pTunerStatus->Tuner_RF_Freq < 650000000)
1899	{
1900	GainCorrection = -396; /unit is 256db*/
1901	}
1902	else if (h->pTunerStatus->Tuner_RF_Freq < 750000000)
1903	{
1904	GainCorrection = -396; /unit is 256db*/
1905	}
1906	else if (h->pTunerStatus->Tuner_RF_Freq < 850000000)
1907	{
1908	GainCorrection = -512; /unit is 256db*/
1909	}
1910	else if (h->pTunerStatus->Tuner_RF_Freq < 950000000)
1911	{
1912	GainCorrection = -640; /unit is 256db*/
1913	}
1914	else
1915	{
1916	GainCorrection = -640; /unit is 256db*/
1917	}
1918	GainReg += 256*(int32_t)ReadReg0-2560 + GainCorrection;
1919	/printf("%d,", GainReg/256);/
1920
1921	/RFVGA Gain/
1922	#if 0
1923	/This was derived from the Gain curve excel file from David/
1924	/=IF(B2>43007,(4B2+196608)/256,IF(B2<17404,-3907,(525B2-19005440)/2560))/
1925	ReadReg0 = h->pTunerStatus->Tuner_RFVGA_Gain_Code;
1926	if (ReadReg0 > 43007)
1927	{
1928	GainReg += (4(int32_t)ReadReg0+196608)/256; /unit is 256db/
1929	}
1930	else if (ReadReg0 > 17405)
1931	{
1932	GainReg += (525(int32_t)ReadReg0-19005440)/2560; /unit is 256db/
1933	}
1934	else
1935	{
1936	GainReg += -3907; /unit is 256db*/
1937	}
1938	#endif
1939
1940	/RFVGA Gain/
1941	/This was derived from lab tests/
1942	ReadReg0 = h->pTunerStatus->Tuner_RFVGA_Gain_Code;
1943	ReadReg0 = (ReadReg0>>16) & 0x0000FFFF;
1944	GainReg += -3840;
1945	GainReg += (ReadReg0 > 0xD200) ? 256 : 0;
1946	GainReg += (ReadReg0 > 0xc900) ? 256 : 0;
1947	GainReg += (ReadReg0 > 0xc100) ? 256 : 0;
1948	GainReg += (ReadReg0 > 0xb900) ? 256 : 0;
1949	GainReg += (ReadReg0 > 0xb200) ? 256 : 0;
1950	GainReg += (ReadReg0 > 0xaa00) ? 256 : 0;
1951	GainReg += (ReadReg0 > 0xa000) ? 256 : 0;
1952	GainReg += (ReadReg0 > 0x8f00) ? 256 : 0;
1953	GainReg += (ReadReg0 > 0x6500) ? 256 : 0;
1954	GainReg += (ReadReg0 > 0x5c00) ? 256 : 0;
1955	GainReg += (ReadReg0 > 0x5500) ? 256 : 0;
1956	GainReg += (ReadReg0 > 0x5000) ? 256 : 0;
1957	GainReg += (ReadReg0 > 0x4c00) ? 256 : 0;
1958	GainReg += (ReadReg0 > 0x4800) ? 256 : 0;
1959	GainReg += (ReadReg0 > 0x4400) ? 256 : 0;
1960	GainReg += (ReadReg0 > 0x4000) ? 256 : 0;
1961	GainReg += (ReadReg0 > 0x3c00) ? 256 : 0;
1962	GainReg += (ReadReg0 > 0x3800) ? 256 : 0;
1963	GainReg += (ReadReg0 > 0x3400) ? 256 : 0;
1964	GainReg += (ReadReg0 > 0x3000) ? 256 : 0;
1965	GainReg += (ReadReg0 > 0x2a00) ? 256 : 0;
1966	/printf("%d,", GainReg/256);/
1967
1968	/LNA Bias Correction/
1969	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_SPARE_01, i_LNA_ctrl_bias);
1970	if (ReadReg0 == 1)
1971	{
1972	GainReg -= 1024;
1973	}
1974	/printf("%d,", GainReg/256);/
1975
1976	/RFVGA Bias Correction/
1977	ReadReg0 = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFVGA_01, i_RFVGA_ctrl_rdeg);
1978	if (ReadReg0 == 3)
1979	{
1980	GainReg -= 512;
1981	}
1982	/printf("%d \n", GainReg/256);/
1983
1984	/Assign value/
1985	h->pTunerStatus->Tuner_PreADC_Gain_x256db = (int16_t)GainReg;
1986	/Get External Gain/
1987	/Get LNA Gain/
1988	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_LFSR_SEED);
1989	if ((ReadReg0 == 0) \|\| ((ReadReg0 & 0xFFFF0000)/POWER2_16 == 0x8000))
1990	{
1991	/No external LNA or unknown gain/
1992	GainReg = (ReadReg0 == 0) ? 0 : -32768;
1993	}
1994	else
1995	{
1996	/The LNA Gain is reported in 1/256 db/
1997	/Get the LNA GAIN if Boost and SuperBoost are disabled/
1998	GainReg = (-14 + (ReadReg0 & 0x0000001F))<<8;
1999	if ((ReadReg0 & 0x0000001F) == 0)
2000	{
2001	BDBG_WRN(("WARNING!!! Invalid STG1_GAIN in LNA detected, STG1_GAIN= %d",ReadReg0));
2002	}
2003
2004	/Compenasate if Boost is enabled/
2005	/Check for LNA Boost/
2006	if ((ReadReg0 & 0x00000200) == 0x00000200)
2007	{
2008	GainReg = GainReg + 768;
2009	/Compensate again if SuperBoost is enabled in addition to Boost/
2010	/Check for LNA SuperBoost in 3412 Only/
2011	if ((ReadReg0 & 0xFFFF0000)/POWER2_16 == 0x3412)
2012	{
2013	if ((ReadReg0 & 0x00000400) == 0x00000400)
2014	{
2015	GainReg = GainReg + 768;
2016	}
2017	}
2018	}
2019
2020	/Get tilt/
2021	if ((ReadReg0 & 0x00000100) == 0x00000100)
2022	{
2023	/Compensate gain if tilt is on, a 5 db rise from 500 MHz to 1 GHz/
2024	if ((h->pTunerStatus->Tuner_RF_Freq > 500000000) && (h->pTunerStatus->Tuner_RF_Freq <= 1000000000))
2025	{
2026	GainReg = GainReg + (((h->pTunerStatus->Tuner_RF_Freq-500000000)>>8)5256)/(500000000>>8); /keep in range of 32 bits/
2027	}
2028	else if (h->pTunerStatus->Tuner_RF_Freq > 1000000000)
2029	{
2030	GainReg = GainReg + 1280; /add 5 db/
2031	}
2032	}
2033
2034	}
2035
2036	/Assign value/
2037	h->pTunerStatus->External_Gain_x256db = (int16_t)GainReg;
2038
2039	/Zero these gains for Low-IF mode /
2040	if (h->pTunerParams->BTNR_RF_Input_Mode == BTNR_3x7x_TunerRfInputMode_eLowIf)
2041	{
2042	h->pTunerStatus->Tuner_PreADC_Gain_x256db = 0;
2043	h->pTunerStatus->External_Gain_x256db = 0;
2044	BDBG_MSG(("\n\nPreADC Gain = %d, ExternalGain = %d",h->pTunerStatus->Tuner_PreADC_Gain_x256db,h->pTunerStatus->External_Gain_x256db));
2045	}
2046
2047	return retCode;
2048	}
2049
2050	/*******************************************************************************************
2051	* BTNR_P_TunerInit() This routine initializes the tuner and is only run once
2052	*******************************************************************************************/
2053	BERR_Code BTNR_P_TunerInit(BTNR_3x7x_Handle h)
2054	{
2055	BERR_Code retCode = BERR_SUCCESS;
2056
2057	/* local variables */
2058	uint8_t PLL_Status, LockCount, temp;
2059
2060	/*Initialize the BTNR_Internal_Params_t Structure
2061	these parameters are used locally by BBS to sent parameters into the tuner functions/
2062	h->pTunerParams->BTNR_Internal_Params.LNA_Enable = INIT_BBS_LNA_ENABLE;
2063	h->pTunerParams->BTNR_Internal_Params.RFFIL_Select = INIT_BBS_RFFIL_SELECT;
2064	h->pTunerParams->BTNR_Internal_Params.HRC_Enable = INIT_BBS_HRC_ENABLE;
2065	if (h->pTunerParams->BTNR_RF_Input_Mode == BTNR_3x7x_TunerRfInputMode_eLowIf)
2066	{
2067	h->pTunerParams->BTNR_Internal_Params.SDADC_Input = BTNR_Internal_Params_SDADC_Input_eExtReal;
2068	h->pTunerParams->BTNR_Internal_Params.IF_Freq = h->pTunerParams->BTNR_Acquire_Params.RF_Freq;
2069	} else {
2070	h->pTunerParams->BTNR_Internal_Params.SDADC_Input = INIT_BBS_SDADC_INPUT;
2071	h->pTunerParams->BTNR_Internal_Params.IF_Freq = INIT_BBS_IF_FREQ;
2072	}
2073	/Initialize the BTNR_Local_Params_t Structure/
2074	h->pTunerParams->BTNR_Local_Params.TunerCapCntl = 0;
2075	h->pTunerParams->BTNR_Local_Params.RF_Offset = 0;
2076	h->pTunerParams->BTNR_Local_Params.Symbol_Rate = 0;
2077	h->pTunerParams->BTNR_Local_Params.Total_Mix_After_ADC = (int16_t)0x8000;
2078	h->pTunerParams->BTNR_Local_Params.PostADC_Gain_x256db = (int16_t)0x8000;
2079
2080	/* clear the lock status */
2081	h->pTunerStatus->Tuner_Ref_Lock_Status = BTNR_Status_eUnlock;
2082	h->pTunerStatus->Tuner_Mixer_Lock_Status = BTNR_Status_eUnlock;
2083	h->pTunerStatus->Tuner_Phy_Lock_Status = BTNR_Status_eUnlock;
2084
2085	/Get the REFPLL lock status/
2086	PLL_Status = 0;
2087	LockCount = 0;
2088	while ((PLL_Status == 0) && (LockCount < REF_PLL_LOCK_TIMEOUT_MS))
2089	{
2090	BKNI_Sleep(1);
2091	PLL_Status = BREG_ReadField(h->hRegister,UFE_AFE_TNR_REFPLL_04, o_REFPLL_lock);
2092	switch (PLL_Status)
2093	{
2094	case 0 :
2095	if (BREG_ReadField(h->hRegister, UFE_AFE_TNR_PWRUP_01, REF_PLL_master_PWRUP) == 0)
2096	BDBG_MSG(("REFPLL is NOT used"));
2097	else
2098	BDBG_ERR(("REFPLL is NOT locked"));
2099	break;
2100
2101	case 1 :
2102	BDBG_MSG(("REFPLL is locked"));
2103	break;
2104	default :
2105	BDBG_ERR(("ERROR!!! INVALID Reference PLL Locked Value: value is %d",PLL_Status));
2106	retCode = BERR_INVALID_PARAMETER;
2107	/goto bottom of function to return error code/
2108	goto something_bad_happened;
2109	}
2110	LockCount++;
2111	}
2112
2113	/Get the PHYPLL lock status/
2114	PLL_Status = 0;
2115	LockCount = 0;
2116	while ((PLL_Status == 0) && (LockCount <PHY_PLL_LOCK_TIMEOUT_MS))
2117	{
2118	BKNI_Sleep(1);
2119	/Get the PHYPLL lock status/
2120	PLL_Status = BREG_ReadField(h->hRegister,UFE_AFE_TNR_REFPLL_04, o_PHYPLL_lock);
2121	switch (PLL_Status)
2122	{
2123	case 0 :
2124	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, PHY_PLL_master_PWRUP);
2125	if (temp == 0)
2126	BDBG_ERR(("PHYPLL is NOT used"));
2127	else
2128	BDBG_ERR(("PHYPLL is NOT locked"));
2129	break;
2130	case 1 :
2131	BDBG_MSG(("PHYPLL is locked"));
2132	break;
2133	default :
2134	BDBG_ERR(("ERROR!!! INVALID PHY PLL Locked Value: value is %d",PLL_Status));
2135	retCode = BERR_INVALID_PARAMETER;
2136	/goto bottom of function to return error code/
2137	goto something_bad_happened;
2138	}
2139	LockCount++;
2140	}
2141
2142	/* Initialize SD ADC */
2143	/This Must Be Complete with calibration added/
2144	BREG_WriteField(h->hRegister, SDADC_CTRL_SYS0, i_adcclk_reset, 0x0);
2145	BREG_Write32(h->hRegister, BCHP_SDADC_CTRL_PWRUP, 0x00000003);
2146	BREG_WriteField(h->hRegister, SDADC_CTRL_RESET, i_Ich_reset, 0x0);
2147	BREG_WriteField(h->hRegister, SDADC_CTRL_RESET, i_Qch_reset, 0x0);
2148	/* Swap I/Q on 8/12/16-phase mixer */
2149	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_MIXER_setSR8_Q, 0xf0);
2150	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_MIXER_setSR8_I, 0xc3);
2151	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_03, i_MIXER_setSR12_I, 0xE07);
2152	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_03, i_MIXER_setSR12_Q, 0xFC0);
2153	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_04, i_MIXER_setSR16_I, 0xF00F);
2154	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_04, i_MIXER_setSR16_Q, 0xFF00);
2155	/* set mixer common mode */
2156	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_vcmfb_gen_ctrl, 0x3);
2157
2158	/* set RFAGC clock from REFPLL */
2159	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
2160	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_RFAGC_CLK_sel, 0x0);
2161	#endif
2162	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
2163	#if (BCHP_CHIP == 7552)
2164	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, spare00, 0x1);
2165	#else
2166	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_RFAGC_CLK_sel, 0x1);
2167	#endif
2168	#endif
2169	BTNR_P_TunerSetRFAGC(h);
2170	BTNR_P_TunerSetADC6B(h);
2171	h->pTunerParams->BTNR_Internal_Params.LNA_Enable = BTNR_Internal_Params_eEnable;
2172	if (h->pTunerParams->BTNR_Internal_Params.LNA_Enable == BTNR_Internal_Params_eEnable)
2173	{
2174	BTNR_P_TunerSetLNAAGC(h);
2175	}
2176	if (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode != BTNR_Tuner_Power_Mode_eLna_Daisy_Power)
2177	{
2178	BTNR_P_TunerSetDCO(h);
2179	#ifdef BTNR_ENABLE_SDADC_CAL
2180	BTNR_P_CalFlashSDADC(h);
2181	#endif
2182	}
2183	/Initialization Complete/
2184	BDBG_MSG((" BTNR_P_TunerInit() Complete\n"));
2185
2186	/goto label to return error code if something bad happened above/
2187	something_bad_happened:
2188	return retCode;
2189	}
2190	#ifdef SmartTuneEnabled
2191	/*******************************************************************************************
2192	* BTNR_P_TunerSmartTune()
2193	*******************************************************************************************/
2194	static void BTNR_P_TunerSmartTune(BTNR_3x7x_Handle h)
2195	{
2196	bool ChangeFreqPlan = false;
2197	uint32_t RF_Freq = h->pTunerParams->BTNR_Acquire_Params.RF_Freq;
2198	if (((RF_Freq > (198000000-5000000)) && (RF_Freq < (198000000+5000000))) \|\|
2199	((RF_Freq > (216000000-5000000)) && (RF_Freq < (216000000+5000000))) \|\|
2200	((RF_Freq > (506000000-5000000)) && (RF_Freq < (506000000+5000000))) \|\|
2201	((RF_Freq > (540000000-5000000)) && (RF_Freq < (540000000+5000000))) \|\|
2202	((RF_Freq > (675000000-5000000)) && (RF_Freq < (675000000+5000000))) \|\|
2203	((RF_Freq > (844000000-5000000)) && (RF_Freq < (844000000+5000000)))) {
2204	if (h->pTunerParams->BTNR_Local_Params.SmartTune != BTNR_Local_Params_SmartTune_FreqPlanA) {
2205	h->pTunerParams->BTNR_Local_Params.SmartTune = BTNR_Local_Params_SmartTune_FreqPlanA;
2206	ChangeFreqPlan = true;
2207	}
2208	} else {
2209	if (h->pTunerParams->BTNR_Local_Params.SmartTune != BTNR_Local_Params_SmartTune_FreqPlanDefault) {
2210	h->pTunerParams->BTNR_Local_Params.SmartTune = BTNR_Local_Params_SmartTune_FreqPlanDefault;
2211	ChangeFreqPlan = true;
2212	}
2213	}
2214
2215	if (ChangeFreqPlan) {
2216	/*BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, PHYPLL_dreset, 1);
2217	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, PHYPLL_areset, 1);*/
2218	switch (h->pTunerParams->BTNR_Local_Params.SmartTune) {
2219	case BTNR_Local_Params_SmartTune_FreqPlanDefault :
2220	BDBG_MSG(("SmartTune: Frequency Plan = Default"));
2221	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, ndiv_int, 0x32);/ndiv_int = 50/
2222	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m6div, 0x05); /m6div = 5/
2223	BREG_Write32(h->hRegister, BCHP_TM_SYS_PLL_PDIV, 2);
2224	BREG_Write32(h->hRegister, BCHP_TM_SYS_PLL_NDIV_INT, 80);
2225	BREG_WriteField(h->hRegister, TM_SYS_PLL_CLK_216, DIV, 10);
2226	break;
2227	case BTNR_Local_Params_SmartTune_FreqPlanA :
2228	BDBG_MSG(("SmartTune: Frequency Plan = A"));
2229	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, ndiv_int, 38);/ndiv_int = 38/
2230	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, m6div, 4); /m6div = 4/
2231	BREG_Write32(h->hRegister, BCHP_TM_SYS_PLL_PDIV, 2);
2232	BREG_Write32(h->hRegister, BCHP_TM_SYS_PLL_NDIV_INT, 76);
2233	BREG_WriteField(h->hRegister, TM_SYS_PLL_CLK_216, DIV, 10);
2234	break;
2235	default :
2236	BDBG_ERR(("SmartTune: Frequency Plan Invalid"));
2237	}
2238	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, 0);
2239	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, 0x3f);
2240	/*BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, PHYPLL_dreset, 0);
2241	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, PHYPLL_areset, 0); */
2242	BTNR_P_TunerSetADC6B(h);
2243	}
2244	}
2245	#endif
2246
2247	/*******************************************************************************************************************
2248	* BTNR_P_TunerShiftGearAGC() This routine sets the tuner AGC
2249	******************************************************************************************************************/
2250	static void BTNR_P_TunerShiftGearAGC(BTNR_3x7x_Handle h)
2251	{
2252	uint32_t ReadReg0, ReadReg1;
2253	/LNA AGC bandwidth settings/
2254	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, LNA_Kbw, 0x7);
2255	/RF AGC bandwidth settings/
2256	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x4);
2257	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 26);
2258	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
2259	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
2260	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
2261	/delay 500us/
2262	BKNI_Delay(500);
2263
2264	/LNA AGC level/
2265	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_TESTCTRL_00, i_test_LNAAGC, 0x5);
2266	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_LNAAGC_READBUS_00);
2267	ReadReg0 = (ReadReg0>>23) & 0x0000001F;
2268	BDBG_MSG(("LNA gain = %d",ReadReg0));
2269
2270	/RFVGA AGC level/
2271	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_raddr, 0x5);
2272	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0);
2273	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 1);
2274	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0);
2275	ReadReg1 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_RFAGC_05);
2276	ReadReg1 = (ReadReg1>>16) & 0x0000FFFF;
2277	BDBG_MSG(("RFVGA gain = %d",ReadReg1));
2278
2279	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
2280	{
2281	case BTNR_TunerApplicationMode_eTerrestrial:
2282	/LNA AGC bandwidth settings/
2283	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, LNA_Kbw, 14);
2284	/RF AGC bandwidth settings/
2285	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x4);
2286	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x10);
2287	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
2288	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
2289	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
2290	break;
2291	case BTNR_TunerApplicationMode_eCable:
2292	/LNA AGC bandwidth settings/
2293	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, LNA_Kbw, 0x0);
2294	/RF AGC bandwidth settings/
2295	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x4);
2296	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 12);
2297	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
2298	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
2299	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
2300	break;
2301	default:
2302	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
2303	/retCode = BERR_INVALID_PARAMETER;/
2304	/goto bottom of function to return error code/
2305	/goto something_bad_happened;/
2306	}
2307
2308	BDBG_MSG(("BTNR_P_TunerShiftGearAGC() Complete"));
2309	}
2310
2311	/*******************************************************************************************************************
2312	* BTNR_P_TunerSetSensitivity() This routine sets the tuner for sensitivity
2313	******************************************************************************************************************/
2314	void BTNR_P_TunerSetSensitivity(BTNR_3x7x_Handle h)
2315	{
2316	uint32_t ReadReg0, ReadReg1;
2317
2318	if (h->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eCable)
2319	{
2320	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
2321	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x7);
2322	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x5);
2323	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x5);
2324	}
2325	BKNI_Sleep(100);
2326	BTNR_P_TunerShiftGearAGC(h);
2327	/LNA AGC level/
2328	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_TESTCTRL_00, i_test_LNAAGC, 0x5);
2329	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_LNAAGC_READBUS_00);
2330	ReadReg0 = (ReadReg0>>23) & 0x0000001F;
2331	BDBG_MSG(("LNA gain = %d",ReadReg0));
2332
2333	/RFVGA AGC level/
2334	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_raddr, 0x5);
2335	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0);
2336	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 1);
2337	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0);
2338	ReadReg1 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_RFAGC_05);
2339	ReadReg1 = (ReadReg1>>16) & 0x0000FFFF;
2340	BDBG_MSG(("RFVGA gain = %d",ReadReg1));
2341
2342	if ((ReadReg1 == 0xFFFF) && (ReadReg0 == 0x1D))
2343	{
2344	BTNR_P_TunerSetSignalPathLowPower(h);
2345	/dithering off/
2346	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x0);
2347	}
2348	else
2349	{
2350	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
2351	{
2352	case BTNR_Tuner_Power_Mode_eVHF_Power:
2353	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
2354	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
2355	{
2356	case BTNR_TunerApplicationMode_eTerrestrial:
2357	if ((ReadReg1 <= 0x6000) \|\| (ReadReg0 != 29))
2358	{
2359	BTNR_P_TunerSetRFSignalPath(h);
2360	BTNR_P_TunerSetSignalPathPower(h);
2361	}
2362	break;
2363	case BTNR_TunerApplicationMode_eCable:
2364	if ((ReadReg1 <= 0x5000) \|\| (ReadReg0 <= 23))
2365	{
2366	BTNR_P_TunerSetRFSignalPath(h);
2367	BTNR_P_TunerSetSignalPathPower(h);
2368	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
2369	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x9);
2370	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x9);
2371	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x9);
2372	}
2373	break;
2374	default:
2375	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
2376	/retCode = BERR_INVALID_PARAMETER;/
2377	/goto bottom of function to return error code/
2378	/goto something_bad_happened;/
2379	}
2380	break;
2381	case BTNR_Tuner_Power_Mode_eUHF_Power:
2382	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
2383	{
2384	case BTNR_TunerApplicationMode_eTerrestrial:
2385	if (ReadReg1 <= 0x6000)
2386	{
2387	BTNR_P_TunerSetRFSignalPath(h);
2388	BTNR_P_TunerSetSignalPathPower(h);
2389	}
2390	break;
2391	case BTNR_TunerApplicationMode_eCable:
2392	if (ReadReg1 <= 0x5000)
2393	{
2394	BTNR_P_TunerSetRFSignalPath(h);
2395	BTNR_P_TunerSetSignalPathPower(h);
2396	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
2397	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x9);
2398	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x9);
2399	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x9);
2400	}
2401	break;
2402	default:
2403	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
2404	/retCode = BERR_INVALID_PARAMETER;/
2405	/goto bottom of function to return error code/
2406	/goto something_bad_happened;/
2407	}
2408	break;
2409	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
2410	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
2411	{
2412	case BTNR_TunerApplicationMode_eTerrestrial:
2413	if (ReadReg0 != 29)
2414	{
2415	BTNR_P_TunerSetRFSignalPath(h);
2416	BTNR_P_TunerSetSignalPathPower(h);
2417	}
2418	break;
2419	case BTNR_TunerApplicationMode_eCable:
2420	if (ReadReg0 <= 23)
2421	{
2422	BTNR_P_TunerSetRFSignalPath(h);
2423	BTNR_P_TunerSetSignalPathPower(h);
2424	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
2425	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x9);
2426	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x9);
2427	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x9);
2428	}
2429	break;
2430	default:
2431	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
2432	/retCode = BERR_INVALID_PARAMETER;/
2433	/goto bottom of function to return error code/
2434	/goto something_bad_happened;/
2435	}
2436	break;
2437	default:
2438	case BTNR_Tuner_Power_Mode_eMini_Power:
2439	break;
2440	}
2441	}
2442	BDBG_MSG(("BTNR_P_TunerSetSensitivity() Complete\n"));
2443	}
2444
2445	/*******************************************************************************************
2446	* BTNR_P_TunerTune() This routine tunes the tuner
2447	*******************************************************************************************/
2448	BERR_Code BTNR_P_TunerTune(BTNR_3x7x_Handle h)
2449	{
2450	BERR_Code retCode = BERR_SUCCESS;
2451	uint32_t temp, Freq_pre, Freq_post;
2452
2453	BTNR_P_TunerSetSignalPathLowPower(h);
2454
2455	#ifdef SmartTuneEnabled
2456	BTNR_P_TunerSmartTune(h);
2457	#endif
2458
2459	/set the tuner input pads for testing/
2460	if (h->pTunerParams->BTNR_Internal_Params.SDADC_Input != BTNR_Internal_Params_SDADC_Input_eTuner)
2461	{
2462	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_pad_en, 1); /enable pad switch/
2463	}
2464	else
2465	{
2466	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_pad_en, 0); /disable pad switch/
2467	}
2468
2469
2470	/Main Tuning/
2471	switch (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode)
2472	{
2473	case BTNR_Tuner_Power_Mode_eMini_Power:
2474	case BTNR_Tuner_Power_Mode_eLna_Daisy_Power:
2475	BTNR_P_TunerSetRFSignalPath(h);
2476	BTNR_P_TunerSetSignalPathLowPower(h);
2477	break;
2478	case BTNR_Tuner_Power_Mode_eUHF_Power:
2479	case BTNR_Tuner_Power_Mode_eVHF_Power:
2480	case BTNR_Tuner_Power_Mode_eUHF_VHF_Power:
2481	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXRPLL_07, MXRPLL_FREQ_LOCK);
2482	Freq_pre = (h->pTunerStatus->Tuner_RF_Freq);
2483	Freq_post = (h->pTunerParams->BTNR_Acquire_Params.RF_Freq);
2484	if ((h->pTunerParams->BTNR_TuneType.TuneType == BTNR_TuneType_eMiniTune) \|\| (((((Freq_pre - Freq_post)*(Freq_pre - Freq_post)) <= 0x10) && (h->pTunerParams->BTNR_TuneType.TuneType != BTNR_TuneType_eInitTune)) && (temp ==1)))
2485	{
2486	BTNR_P_TunerSetRFSignalPath(h);
2487	BTNR_P_TunerSetSignalPathLowPower(h);
2488	BTNR_P_TunerSetFGA_IFLPF(h);
2489	}
2490	else
2491	{
2492	BTNR_P_TunerSetRFSignalPath(h);
2493	BTNR_P_TunerSetSignalPathLowPower(h);
2494	BTNR_P_TunerSetFGA_IFLPF(h);
2495	BTNR_P_TunerSetFreq(h);
2496	}
2497
2498	/BTNR_P_TunerSearchCap(h);/
2499	break;
2500
2501	default:
2502	BDBG_ERR(("ERROR!!! h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode, value received is %d",h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode));
2503	retCode = BERR_INVALID_PARAMETER;
2504	/goto bottom of function to return error code/
2505	goto something_bad_happened;
2506	}
2507	BTNR_P_TunerSetSensitivity(h);
2508
2509	#ifdef ENABLE_LNA_AGC_CYCLE
2510	/* Enable LNA AGC Cycle callback timer*/
2511	BTMR_StartTimer(h->hTimer, 1000);
2512	#endif
2513
2514	/* BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_pad_en, 0x1);*/
2515	BDBG_MSG(("BTNR_P_TunerTune() Complete\n"));
2516	/goto label to return error code if something bad happened above/
2517	something_bad_happened:
2518	return retCode;
2519
2520	}
2521
2522
2523	/*******************************************************************************************
2524	* BTNR_P_TunerSetRFFIL() This routine selects the correct RF filter corner frequency
2525	*******************************************************************************************/
2526	void BTNR_P_TunerSetRFFIL(BTNR_3x7x_Handle h)
2527	{
2528	/local variables/
2529	uint8_t i;
2530	uint8_t j;
2531	uint8_t RFTRK_bypass_ctrl;
2532	uint8_t RFTRK_band_ctrl=0;
2533	uint8_t RFTRK_tune_ctrl=0;
2534
2535
2536	/sequence through the LPF_Selection_Table[] from highest freq value to lowest freq value/
2537	/table is in 100 KHz resolution/
2538	/when we get to the entry with a lower freq then the TunerFreq record index and rftrk1 then exit and program/
2539	i = 0;
2540	j = 0;
2541	RFTRK_bypass_ctrl = 0;
2542	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 82000000 )
2543	{
2544	RFTRK_band_ctrl = 0;
2545	RFTRK_tune_ctrl = 17;
2546	}
2547	else if ((h->pTunerParams->BTNR_Acquire_Params.RF_Freq > 82000000) && (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 143160000))
2548	{
2549	RFTRK_band_ctrl = 0;
2550	for (i=0;i<11;i++)
2551	{
2552	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= (uint32_t)((82+i6)1000000)+1160000)
2553	{
2554	RFTRK_tune_ctrl = LPF_Selection_Table[i];
2555	break;
2556	}
2557	}
2558	}
2559	else if ((h->pTunerParams->BTNR_Acquire_Params.RF_Freq > 143160000) && (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 262000000))
2560	{
2561	RFTRK_band_ctrl = 1;
2562	for (i=11;i<31;i++)
2563	{
2564	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= (uint32_t)((82+i6)1000000))
2565	{
2566	RFTRK_tune_ctrl = LPF_Selection_Table[i];
2567	break;
2568	}
2569	}
2570	}
2571	else if ((h->pTunerParams->BTNR_Acquire_Params.RF_Freq > 262000000) && (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= 502000000))
2572	{
2573	RFTRK_band_ctrl = 2;
2574	for (i=31;i<71;i++)
2575	{
2576	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= (uint32_t)((82+i6)1000000))
2577	{
2578	RFTRK_tune_ctrl = LPF_Selection_Table[i];
2579	break;
2580	}
2581	}
2582	}
2583	else
2584	{
2585	BDBG_ERR(("ERROR!!! h->pTunerParams->BTNR_Acquire_Params.RF_Freq, value received is %d",h->pTunerParams->BTNR_Acquire_Params.RF_Freq));
2586	}
2587
2588	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_bypass_en, RFTRK_bypass_ctrl);
2589	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_band_ctrl, RFTRK_band_ctrl);
2590	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFFIL_01, i_TRKFIL_BW_tuning, RFTRK_tune_ctrl);
2591
2592	BDBG_MSG(("RF_Freq = %d\n", h->pTunerParams->BTNR_Acquire_Params.RF_Freq));
2593	BDBG_MSG(("RFTRK_bypass_ctrl = %d RFTRK_band_ctrl = %d RFTRK_tune_ctrl = %d\n", RFTRK_bypass_ctrl, RFTRK_band_ctrl, RFTRK_tune_ctrl));
2594	BDBG_MSG(("BTNR_P_TunerSetRFFIL() Complete\n"));
2595	}
2596
2597
2598	/*******************************************************************************************
2599	* BTNR_P_TunerSetFGA_IFLPF() This routine it to set the IF filter in the tuner
2600	*******************************************************************************************/
2601	void BTNR_P_TunerSetFGA_IFLPF(BTNR_3x7x_Handle h)
2602	{
2603	/local variables/
2604	uint8_t FGA_GAIN;
2605	uint8_t FGA_RC_Ctrl;
2606	uint8_t IFLPF_BW_Sel;
2607	uint8_t IFLPF_WBW_Sel;
2608
2609	/Set FGA gain to high gain for terrestrial, low gain for cable/
2610	if (h->pTunerParams->BTNR_Acquire_Params.Application == BTNR_TunerApplicationMode_eCable)
2611	{
2612	BREG_WriteField(h->hRegister,UFE_AFE_TNR0_MXR_02, i_FGA_HiGain, 0);
2613	FGA_GAIN = 0;
2614	}
2615	{
2616	BREG_WriteField(h->hRegister,UFE_AFE_TNR0_MXR_02, i_FGA_HiGain, 1);
2617	FGA_GAIN = 1;
2618	}
2619
2620	/lookup the IFLPF_BWR_Sel and IFLPF_WBW_Sel values, they are different for each bandwidth 2,4,5,8,10 MHz /
2621	switch (h->pTunerParams->BTNR_Acquire_Params.LPF_Bandwidth)
2622	{
2623	case BTNR_LPF_Bandwidth_e8MHz :
2624	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_8MHz : FGA_RC_CTRL_LOWG_8MHz;
2625	IFLPF_BW_Sel = IFLPF_BW_SEL_8MHz;
2626	IFLPF_WBW_Sel = IFLPF_WBW_SEL_8MHz;
2627	break;
2628	case BTNR_LPF_Bandwidth_e7MHz :
2629	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_7MHz : FGA_RC_CTRL_LOWG_7MHz;
2630	IFLPF_BW_Sel = IFLPF_BW_SEL_7MHz;
2631	IFLPF_WBW_Sel = IFLPF_WBW_SEL_7MHz;
2632	break;
2633	case BTNR_LPF_Bandwidth_e6MHz :
2634	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_6MHz : FGA_RC_CTRL_LOWG_6MHz;
2635	IFLPF_BW_Sel = IFLPF_BW_SEL_6MHz;
2636	IFLPF_WBW_Sel = IFLPF_WBW_SEL_6MHz;
2637	break;
2638	case BTNR_LPF_Bandwidth_e5MHz :
2639	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_5MHz : FGA_RC_CTRL_LOWG_5MHz;
2640	IFLPF_BW_Sel = IFLPF_BW_SEL_5MHz;
2641	IFLPF_WBW_Sel = IFLPF_WBW_SEL_5MHz;
2642	break;
2643	case BTNR_LPF_Bandwidth_e1_7MHz :
2644	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_1_7MHz : FGA_RC_CTRL_LOWG_1_7MHz;;
2645	IFLPF_BW_Sel = IFLPF_BW_SEL_1_7MHz;
2646	IFLPF_WBW_Sel = IFLPF_WBW_SEL_1_7MHz;
2647	break;
2648	case BTNR_LPF_Bandwidth_eVariable :
2649	if ((h->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth > MAX_LPF_VARIABLE_BW) \|\|
2650	(h->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth < MIN_LPF_VARIABLE_BW))
2651	{
2652	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_8MHz : FGA_RC_CTRL_LOWG_8MHz;
2653	IFLPF_BW_Sel = IFLPF_BW_SEL_8MHz;
2654	IFLPF_WBW_Sel = IFLPF_WBW_SEL_8MHz;
2655	BDBG_ERR(("ERROR!!! VARIABLE LPF BANDWIDTH UNSUPPORTED SETTING TO 8 MHZ"));
2656	BDBG_ERR(("ERROR!!! Invalid Tuner_Variable_BW in BTNR_P_TunerSetFGA_IFLPF() , Value is %d", h->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth));
2657	}
2658	else
2659	{
2660	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_8MHz : FGA_RC_CTRL_LOWG_8MHz;
2661	IFLPF_BW_Sel = IFLPF_BW_SEL_8MHz;
2662	IFLPF_WBW_Sel = IFLPF_WBW_SEL_8MHz;
2663	}
2664	break;
2665	default :
2666	FGA_RC_Ctrl = (FGA_GAIN == 1) ? FGA_RC_CTRL_HIGHG_8MHz : FGA_RC_CTRL_LOWG_8MHz;
2667	IFLPF_BW_Sel = IFLPF_BW_SEL_8MHz;
2668	IFLPF_WBW_Sel = IFLPF_WBW_SEL_8MHz;
2669	BDBG_ERR(("ERROR!!! Invalid Tuner_BW selected in BTNR_P_TunerSetFGA_IFLPF() , Value is %d", h->pTunerParams->BTNR_Acquire_Params.LPF_Bandwidth));
2670	break;
2671	}
2672
2673	/write the bandwidth values/
2674	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_02, i_FGA_C_ctrl, FGA_RC_Ctrl);
2675	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_BW, IFLPF_BW_Sel);
2676	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_WBW, IFLPF_WBW_Sel);
2677
2678
2679	BDBG_MSG(("LPF_Bandwidth = %d\n", h->pTunerParams->BTNR_Acquire_Params.LPF_Bandwidth));
2680	BDBG_MSG(("LPF_Variable_Bandwidth = %d\n", h->pTunerParams->BTNR_Acquire_Params.LPF_Variable_Bandwidth));
2681	BDBG_MSG(("i_FGA_C_ctrl = %d", FGA_RC_Ctrl));
2682	BDBG_MSG(("i_LPF_BW = %d", IFLPF_BW_Sel));
2683	BDBG_MSG(("i_LPF_WBW = %d", IFLPF_WBW_Sel));
2684	BDBG_MSG(("BTNR_P_TunerSetFGA_IFLPF() Complete\n"));
2685	}
2686
2687	/******************************************************************************
2688	BTNR_P_TunerSetFreq()
2689	******************************************************************************/
2690	void BTNR_P_TunerSetFreq(BTNR_3x7x_Handle h)
2691	{
2692	/local variables/
2693	uint8_t index, M, N, ndiv, pdiv;
2694	uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, Freq;
2695	uint16_t temp;
2696
2697	/* Enable LO state-machine clock */
2698	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
2699	temp = temp \| 0x4 ;
2700	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
2701
2702	/Optimize LO settings/
2703	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_02, lP_QPbiasCNT_1p0, 0xC);
2704	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_02, lP_QPbiasCNT2_1p0, 0x4);
2705	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_VcREF_1p0, 0x15);
2706	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_04, lP_mainVbal_1p0, 0x1);
2707	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_04, lP_mainIbal_1p0, 0x0);
2708	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, P_divreg1p0_cntl_1p0, 0x3);
2709
2710	/Enable auto tuner/
2711	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LO_SMtuner_resetb, 0x0);
2712	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x0);
2713	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_param_sel, 0x1);
2714	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LO_SMtuner_resetb, 0x1);
2715
2716	/* lookup freq range */
2717	for (index = 0; index < BTNR_TUNER_LO_TABLE_SIZE; index++)
2718	{
2719	if (h->pTunerParams->BTNR_Acquire_Params.RF_Freq <= Tuner_LO_Freq_Table[index])
2720	{
2721	/index = BTNR_TUNER_LO_TABLE_SIZE;/
2722	break;
2723	}
2724	}
2725
2726	BDBG_MSG(("BTNR_P_TunerSetFreq: index%d \n",index));
2727
2728	/Program the values for LO/
2729	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MXR_SR6p8p12p16p, Tuner_LO_Table[index].i_MXR_SR6p8p12p16p);
2730	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel_div_ratio, Tuner_LO_Table[index].i_MIXER_sel_div_ratio);
2731	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel, Tuner_LO_Table[index].i_MIXER_sel);
2732	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_HRM_mode, Tuner_LO_Table[index].i_MIXER_HRM_mode);
2733	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXR_01, i_MIXER_sel_MUX0p6p8p, Tuner_LO_Table[index].i_MIXER_sel_MUX0p6p8p);
2734	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_fbdivn_1p0, Tuner_LO_Table[index].lP_fbdivn_1p0);
2735	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_div23_sel_1p0, Tuner_LO_Table[index].lP_div23_sel_1p0);
2736
2737	/* Set the DDFS FCW*/
2738	M = Tuner_LO_Table[index].M_Factor;
2739	N = Tuner_LO_Table[index].lP_fbdivn_1p0;
2740
2741	BDBG_MSG(("BTNR_P_TunerSetFreq: M=%d, N=%d\n",M, N));
2742
2743	/* FCW = (Fc/RFPLL_FREQ)(M/N)2^37* where Fc is desired frequency
2744	* M[2 255], N[4,8,12,16,24,32,64]
2745	* FCW = ((Fc/100)M)2^37))/(RFPLL_FREQ/100N)) where Fc is desired frequency/
2746	BDBG_MSG((" Rf Freq=%08x\n",h->pTunerParams->BTNR_Acquire_Params.RF_Freq));
2747
2748	#if 1
2749	Freq = (h->pTunerParams->BTNR_Acquire_Params.RF_Freq);
2750
2751	ulMultA = 0x1;
2752	ulMultB = 0;
2753	ulNrmHi = 0;
2754	ulNrmLo = Freq*(M/4);
2755
2756	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)
2757	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_01, REF_DIV_fb);
2758	pdiv = 1;
2759	ndiv = BREG_ReadField(h->hRegister, UFE_AFE_TNR_REFPLL_02, REF_DIV_ratio);
2760	#elif (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1)
2761	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, ndiv_int);
2762	pdiv = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_03, p1div);
2763	ndiv = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_04, m2div);
2764	#endif
2765
2766	BMTH_HILO_64TO64_Mul(ulMultA, ulMultB, ulNrmHi, ulNrmLo, &ulMultA, &ulMultB);
2767	BDBG_MSG((" First %08x, %08x\n",ulMultA, ulMultB));
2768	BMTH_HILO_64TO64_Div32(ulMultA, ulMultB, ( (REF_FREQ(temp/ndiv/pdiv)/128)N ), &ulNrmHi, &ulNrmLo);
2769	BDBG_MSG((" Second %08x, %08x\n",ulNrmHi, ulNrmLo));
2770	#endif
2771
2772	if (ulNrmHi > 0x0000001F)
2773	{
2774	BDBG_ERR(("DDFS is outside of the 37 bit range in BTNR_P_TunerSetFreq()"));
2775	}
2776
2777	/* Setup DDFS*/
2778	/* program fcw[36:5] and fcw[4:0]*/
2779	ulNrmHi = (((ulNrmHi<<27) & 0xF8000000) \| ((ulNrmLo>>5) & 0x07FFFFFF)); /Get 32 msb's/
2780	ulNrmLo = (ulNrmLo & 0x0000001F); /Get 5 lsb's/
2781	/Reset and Release DDFS/
2782	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0) /* (BCHP_VER == BCHP_VER_A0) / / TO FIX - Fixed*/
2783	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7afe );
2784	BKNI_Sleep(1);
2785	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7aff );
2786	#else
2787	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, loddfs_resetn, 0);
2788	BKNI_Sleep(1);
2789	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, loddfs_resetn, 1);
2790	#endif
2791
2792	/Program FCW/
2793	BDBG_MSG(("BTNR_P_TunerSetFreq: Hi=%x, Lo=%x\n",ulNrmHi, ulNrmLo));
2794	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_DDFS_FCW_02, ulNrmHi); /32 MSB of 37 bit word/
2795	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_DDFS_FCW_01, ulNrmLo); /* 5 LSB of 37 bit word*/
2796
2797
2798	/* De-assert reset/resetb for div23, cml, SR, pre_div */
2799	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_rstdiv23_1p0, 0x1);
2800	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_cmlDIVRST, 0x1);
2801	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_ld_RESET_STRT_1p0, 0x1);
2802	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_rstdiv23_1p0, 0x0);
2803	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_cmlDIVRST, 0x0);
2804	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_ld_RESET_STRT_1p0, 0x0);
2805
2806	BKNI_Sleep(1);
2807
2808	/* Startup DDFS*/
2809	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x1);
2810	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x0);
2811	BKNI_Sleep(1);
2812	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x1);
2813	BKNI_Sleep(1);
2814	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_DDFS_01, i_fcw_strb, 0x0);
2815
2816	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x1);
2817	BKNI_Sleep(1);
2818	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x0);
2819
2820	/SR, pre_div /
2821	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x1);
2822	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x1);
2823	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x0);
2824	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x0);
2825	BKNI_Delay(20); /20 usec/
2826	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x1);
2827	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x1);
2828	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_SR_reset, 0x0);
2829	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, MXR_PREDIV_reset, 0x0);
2830	/Power down state machine clock/
2831	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
2832	temp = temp & 0x3B ;
2833	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
2834	/Lock Status/
2835	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXRPLL_07, MXRPLL_FREQ_LOCK);
2836	if (temp == 1)
2837	{
2838	BDBG_MSG(("MIXPLL is locked"));
2839	}
2840	else if (temp == 0)
2841	{
2842	BDBG_MSG(("MIXPLL is NOT locked"));
2843	}
2844	/TEMPORARY CODE - BYPASS LNA - Will be removed when LNA is working/
2845	/* BREG_WriteField(h->hRegister,UFE_AFE_TNR0_PWRUP_01, i_pwrup_LNA, 0x0);
2846	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNA_01, i_LNA_bypass, 0x1);
2847	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LPF_01, i_LPF_pad_en, 0x1);*/
2848	}
2849
2850	/******************************************************************************
2851	BTNR_P_TunerSearchCap() - capacitor binary scan
2852	******************************************************************************/
2853	void BTNR_P_TunerSearchCap(BTNR_3x7x_Handle h)
2854	{
2855	uint16_t temp;
2856	#if (BTNR_P_BCHP_TNR_CORE_VER >= BTNR_P_BCHP_CORE_V_1_1) /* #if (BCHP_VER != BCHP_VER_A0) */
2857	uint32_t ReadReg;
2858	#endif
2859	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
2860	temp = temp \| 0x4 ;
2861	/* enable LO state-machine clock */
2862	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
2863	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, 0x24);
2864
2865	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_04, lP_mainVbal_1p0, 0x1 );
2866	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0) /* (BCHP_VER == BCHP_VER_A0) / / TO FIX - Fixed*/
2867	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7afe );
2868	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7aff );
2869	#else
2870	ReadReg = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02);
2871	ReadReg = ReadReg \| 0x7afe ;
2872	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, ReadReg);
2873	ReadReg = ReadReg \| 0x7aff ;
2874	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, ReadReg);
2875	#endif
2876
2877	/BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_MXRPLL, 0x7aff );/
2878
2879	/* enable auto-tuner - hold reset, disable auto-tune, LO parameters by SM */
2880	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, spare00, 0x0); /* hold reset */
2881	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x0); /* disable auto-tune */
2882	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_param_sel, 0x1);
2883	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, spare00, 0x1); /* release reset */
2884	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LO_SMtuner_resetb, 1);
2885	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, lP_ld_RESET_STRT_1p0, 0);
2886
2887	BKNI_Sleep(10);
2888
2889	/* enable auto-tune state machine */
2890	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x1);
2891	BKNI_Sleep(10);
2892
2893	/* disable auto-tune state machine */
2894	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_05, LO_SMtuner_tune_en, 0x0);
2895
2896	/* turn off LO state-machine clock */
2897	/* BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, 0x4);
2898	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, 0x24);*/
2899	BKNI_Sleep(10);
2900
2901	if (BREG_ReadField(h->hRegister, UFE_AFE_TNR0_MXRPLL_07, MXRPLL_FREQ_LOCK) == 0)
2902	{
2903	/BDBG_MSG(("MXRPLL NOT locked"));/
2904	BDBG_MSG(("Cap Search Done: MXRPLL NOT locked"));
2905	}
2906	}
2907
2908	/*******************************************************************************************************************
2909	* BTNR_P_TunerSetADC6B() This routine sets the tuner 6-bit ADC
2910	******************************************************************************************************************/
2911	void BTNR_P_TunerSetADC6B(BTNR_3x7x_Handle h)
2912	{
2913	uint16_t temp;
2914
2915	/* Powerup Channel 1 */
2916	temp = BREG_ReadField(h->hRegister,UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
2917	temp = temp \| 0x1 ;
2918	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
2919
2920	/* Enable Channel 1 */
2921	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
2922	temp = temp \| 0x1 ;
2923	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, temp);
2924
2925	/* De-assert reset/resetb for 6-bit ADC */
2926	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, ADC6B_resetb, 0);
2927	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, ADC6B_resetb, 1);
2928
2929	BDBG_MSG(("BTNR_P_TunerSetADC6B() Complete\n"));
2930	}
2931
2932	/*******************************************************************************************************************
2933	* BTNR_P_TunerSetLNAAGC() This routine sets the tuner LNA AGC
2934	******************************************************************************************************************/
2935	void BTNR_P_TunerSetLNAAGC(BTNR_3x7x_Handle h)
2936	{
2937	uint32_t ReadReg0;
2938	/BERR_Code retCode = BERR_SUCCESS;/
2939
2940	/* negative edge */
2941	ReadReg0 = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_LNAAGC_02);
2942	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_LNAAGC_02, (ReadReg0 \| 0x80000000));
2943	/* De-assert reset/resetb for LNA AGC */
2944	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LNAAGC_resetb, 0);
2945	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, LNAAGC_resetb, 1);
2946	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_LNAAGC_dsm_srst, 1);
2947	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_LNAAGC_dsm_srst, 0);
2948	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_LNAAGC_agc_srst, 1);
2949	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, i_LNAAGC_agc_srst, 0);
2950
2951	/Program LNA AGC settings/
2952	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
2953	{
2954	case BTNR_TunerApplicationMode_eTerrestrial:
2955	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_ADC6B_03, i_ADCBUF_Rdeg, 0x7);
2956	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0xA);
2957	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, peak_pwr_set_pt, 0x10B66);
2958	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, hi_thresh, 41240);
2959	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, win_len, 0x18);
2960	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, LNA_Kbw, 14);
2961	break;
2962	case BTNR_TunerApplicationMode_eCable:
2963	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_ADC6B_03, i_ADCBUF_Rdeg, 0x7);
2964	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, pd_thresh, 0x6);
2965	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, peak_pwr_set_pt, 0x10B66);
2966	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, hi_thresh, 41240);
2967	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, win_len, 0x16);
2968	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, LNA_Kbw, 14);
2969	break;
2970	default:
2971	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
2972	/retCode = BERR_INVALID_PARAMETER;/
2973	/goto bottom of function to return error code/
2974	/goto something_bad_happened;/
2975	}
2976
2977	/set initial gain/
2978	#if ((BCHP_CHIP==3461))
2979	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, init_LNA_gain, 15);
2980	#else
2981	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_01, init_LNA_gain, 29);
2982	#endif
2983
2984	/unfreeze, un-bypass/
2985	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_03, AGC_byp, 0);
2986	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_03, AGC_frz, 0);
2987	/start LNA AGC/
2988	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, lna_start, 0x0);
2989	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, lna_start, 0x1);
2990
2991	BDBG_MSG(("BTNR_P_TunerSetLNAAGC() Complete\n"));
2992
2993	/goto label to return error code if something bad happened above/
2994	/something_bad_happened:/
2995	/return retCode;/
2996	}
2997
2998	/*******************************************************************************************************************
2999	* BTNR_P_TunerSetRFAGC() This routine sets the tuner RF AGC
3000	******************************************************************************************************************/
3001	void BTNR_P_TunerSetRFAGC(BTNR_3x7x_Handle h)
3002	{
3003	uint32_t ReadReg;
3004	/enable dither clock/
3005	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_clk_dither, 0x1);
3006
3007	/RF AGC init/
3008	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_DAC_LPF_pwrup_RFAGC, 1);
3009	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_RFDPD_pwrup_RFAGC, 1);
3010	#if (BTNR_P_BCHP_TNR_CORE_VER == BTNR_P_BCHP_CORE_V_1_0)/* (BCHP_VER == BCHP_VER_A0) / / TO FIX - Fixed */
3011	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i__BB2DPD_pwrup_RFAGC, 1);
3012	#else
3013	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_BB2DPD_pwrup_RFAGC, 1);
3014	#endif
3015	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_01, i_BB1DPD_pwrup_RFAGC, 1);
3016	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_dsm_sigdel_en, 1);
3017	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, RFAGC_DSM_intg_reset, 1);
3018	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, RFAGC_DSM_resetb, 0);
3019	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, RFAGC_reset, 1);
3020	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, RFAGC_DSM_intg_reset, 0);
3021	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, RFAGC_DSM_resetb, 1);
3022	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESET_01, RFAGC_reset, 0);
3023
3024	/RF AGC settings/
3025
3026	switch (h->pTunerParams->BTNR_Acquire_Params.Application)
3027	{
3028	case BTNR_TunerApplicationMode_eTerrestrial:
3029	/* BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x6);*/
3030	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x8);
3031	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x7);
3032	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x7);
3033
3034	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x4);
3035	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x10);
3036	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3037	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3038	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3039
3040	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x2);
3041	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x2710);
3042	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3043	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3044	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3045
3046	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x1);
3047	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x4B354B35);
3048	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3049	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3050	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3051	break;
3052	case BTNR_TunerApplicationMode_eCable:
3053	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x9);
3054	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x9);
3055	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x9);
3056
3057	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x4);
3058	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x10);
3059	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3060	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3061	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3062
3063	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x2);
3064	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x2710);
3065	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3066	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3067	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3068
3069	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x1);
3070	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x4B354B35);
3071	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3072	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3073	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3074
3075	#ifdef BTNR_J83A_SUPPORT
3076	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_Ios_PRG, 0x7);
3077	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_Ios_PRG, 0x5);
3078	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_Ios_PRG, 0x5);
3079
3080	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x4);
3081	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x10);
3082	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3083	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3084	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3085
3086	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x2);
3087	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x4E2);
3088	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3089	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3090	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3091
3092	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x1);
3093	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0x31BD31BD);
3094	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3095	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3096	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3097	#endif
3098	break;
3099	default:
3100	BDBG_ERR(("ERROR!!! Invalid h->pTunerParams->BTNR_Acquire_Params.Application, value received is %d",h->pTunerParams->BTNR_Acquire_Params.Application));
3101	/retCode = BERR_INVALID_PARAMETER;/
3102	/goto bottom of function to return error code/
3103	/goto something_bad_happened;/
3104	}
3105
3106	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_delay, 0x2);
3107	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, RF_clk_extend, 0x2);
3108	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_sel_IQ, 0x1);
3109	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_delay, 0x2);
3110	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB2_clk_extend, 0x2);
3111	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_sel_IQ, 0x1);
3112	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_delay, 0x2);
3113	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_03, BB1_clk_extend, 0x2);
3114
3115	/RF AGC initial gain settings/
3116	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_freeze_gain, 0x1);
3117	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x5);
3118	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, 0xFFFFFFFF);
3119	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3120	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3121	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3122	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_freeze_gain, 0x0);
3123
3124	/RF AGC close loop settings/
3125	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_raddr, 0x0);
3126	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0x0);
3127	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0x1);
3128	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0x0);
3129
3130	ReadReg = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFAGC_05, o_rdata);
3131
3132	ReadReg = ReadReg & 0xFFF3BDC0;
3133	if (h->pTunerParams->BTNR_TunePowerMode.Tuner_Power_Mode == BTNR_Tuner_Power_Mode_eLna_Daisy_Power)
3134	ReadReg = ReadReg \| 0x0000401A;
3135	else
3136	ReadReg = ReadReg \| 0x0000401B;
3137
3138	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x0);
3139	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, ReadReg);
3140
3141	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3142	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3143	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3144
3145	BDBG_MSG(("BTNR_P_TunerSetRFAGC() Complete\n"));
3146
3147	/goto label to return error code if something bad happened above/
3148	/something_bad_happened:/
3149	/return retCode;/
3150	}
3151
3152	/*******************************************************************************************************************
3153	* BTNR_P_TunerBypassLNAAGC() This routine sets the tuner LNA AGC
3154	******************************************************************************************************************/
3155	void BTNR_P_TunerBypassLNAAGC(BTNR_3x7x_Handle h)
3156	{
3157	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_03, AGC_byp, 0x1);
3158	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_03, LNA_byp_gain, 29);
3159	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, lna_start, 0x0);
3160	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_LNAAGC_00, lna_start, 0x1);
3161	}
3162
3163	/*******************************************************************************************************************
3164	* BTNR_P_TunerBypassRFAGC() This routine sets the tuner RF AGC
3165	******************************************************************************************************************/
3166	void BTNR_P_TunerBypassRFAGC(BTNR_3x7x_Handle h)
3167	{
3168	uint32_t ReadReg;
3169	/RF AGC bypass settings/
3170	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_raddr, 0x0);
3171	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0x0);
3172	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0x1);
3173	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_rload, 0x0);
3174
3175	ReadReg = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_RFAGC_05, o_rdata);
3176
3177	ReadReg = ReadReg & 0xFFF3BDC0;
3178	ReadReg = ReadReg \| 0x0000421B;
3179
3180	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_waddr, 0x0);
3181	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_04, i_wdata, ReadReg);
3182
3183	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3184	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x1);
3185	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_02, i_wload, 0x0);
3186	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RFAGC_01, i_agc_code_bypass, 0x0);
3187	}
3188	/*******************************************************************************************************************
3189	* BTNR_P_TunerSetDCO() This routine sets the tuner DCO
3190	******************************************************************************************************************/
3191	void BTNR_P_TunerSetDCO(BTNR_3x7x_Handle h)
3192	{
3193
3194	uint8_t temp;
3195
3196	/Adjust LDO settings/
3197	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_REG_01, i_REG1p0_ctrl, 3);
3198
3199	/Enable DCO Clock/
3200	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch);
3201	temp = temp \| 0x8 ;
3202	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, temp);
3203
3204	temp = BREG_ReadField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1);
3205	temp = temp \| 0x8 ;
3206	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_PHYPLL_05, load_en_ch6_ch1, temp);
3207
3208	/* De-assert reset/resetb for DCO */
3209	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, i_rstb, 0);
3210	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, i_dco_rstb, 0);
3211	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, i_rstb, 1);
3212	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_RESETB_01, i_dco_rstb, 1);
3213
3214	/gear shifting/
3215	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRDCO_01, i_dco_k0, 16);
3216	BKNI_Sleep(10);
3217	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRDCO_01, i_dco_k0, 8);
3218	BKNI_Sleep(10);
3219
3220	BDBG_MSG(("DCO is running\n"));
3221	}
3222
3223	/******************************************************************************
3224	BTNR_P_CalFlashSDADC() - calibrate SD ADC flash
3225	******************************************************************************/
3226	void BTNR_P_CalFlashSDADC(BTNR_3x7x_Handle h)
3227	{
3228	uint8_t idx;
3229	uint32_t ICalOffset, QCalOffset;
3230	uint8_t statusIch, statusQch=0;
3231
3232	/I Channel Calibration/
3233	BREG_WriteField(h->hRegister, SDADC_CTRL_ICH, i_Ich_flash_resetCal, 0x1);
3234	BREG_WriteField(h->hRegister, SDADC_CTRL_RESET, i_Ich_reset, 0x1);
3235	BREG_WriteField(h->hRegister, SDADC_CTRL_ICH, i_Ich_flash_resetCal, 0x0);
3236	BREG_WriteField(h->hRegister, SDADC_CTRL_ICH, i_Ich_flash_cal_on, 0x1);
3237
3238	/Q Channel Calibration/
3239	BREG_WriteField(h->hRegister, SDADC_CTRL_QCH, i_Qch_flash_resetCal, 0x1);
3240	BREG_WriteField(h->hRegister, SDADC_CTRL_RESET, i_Qch_reset, 0x1);
3241	BREG_WriteField(h->hRegister, SDADC_CTRL_QCH, i_Qch_flash_resetCal, 0x0);
3242	BREG_WriteField(h->hRegister, SDADC_CTRL_QCH, i_Qch_flash_cal_on, 0x1);
3243
3244	for (statusIch=0, idx =0; (idx<2) && ( !(statusIch) \|\| !(statusQch) ) ;idx++){
3245	BKNI_Sleep(1);
3246	statusIch = BREG_ReadField(h->hRegister,SDADC_STATUS_ICH, o_Ich_flash_cal_done);
3247	statusQch = BREG_ReadField(h->hRegister,SDADC_STATUS_QCH, o_Qch_flash_cal_done);
3248	}
3249
3250	switch (statusIch)
3251	{
3252	case 0 : BDBG_MSG(("SDADC I channel calibration NOT done"));
3253	if (idx>99){
3254	BDBG_ERR(("SDADC I channel calibration timeout"));
3255	}
3256	break;
3257	case 1 : BDBG_MSG(("SDADC I channel calibrationis done")); break;
3258	default :BDBG_ERR(("ERROR!!! INVALID SDADC I Channel Calibration Value: value is %d",statusIch)); break;
3259	}
3260
3261	ICalOffset = BREG_ReadField(h->hRegister,SDADC_STATUS_ICH, o_Ich_flash_caldata);
3262	BREG_WriteField(h->hRegister, SDADC_CTRL_ICH, i_ctl_Ich_flash_offset, ICalOffset);
3263	BREG_WriteField(h->hRegister, SDADC_CTRL_ICH, i_Ich_flash_cal_on, 0);
3264
3265	switch (statusQch)
3266	{
3267	case 0 : BDBG_MSG(("SDADC Q channel calibration NOT done"));
3268	if (idx>99){
3269	BDBG_ERR(("SDADC Q channel calibration timeout"));
3270	}
3271	break;
3272	case 1 : BDBG_MSG(("SDADC Q channel calibrationis done")); break;
3273	default :BDBG_ERR(("ERROR!!! INVALID SDADC Q Channel Calibration Value: value is %d",statusQch)); break;
3274	}
3275
3276	QCalOffset = BREG_ReadField(h->hRegister,SDADC_STATUS_QCH, o_Qch_flash_caldata);
3277	BREG_WriteField(h->hRegister, SDADC_CTRL_QCH, i_ctl_Qch_flash_offset, QCalOffset);
3278	BREG_WriteField(h->hRegister, SDADC_CTRL_QCH, i_Qch_flash_cal_on, 0);
3279
3280	BREG_WriteField(h->hRegister, SDADC_CTRL_RESET, i_Ich_reset, 0x0);
3281	BREG_WriteField(h->hRegister, SDADC_CTRL_RESET, i_Qch_reset, 0x0);
3282	}
3283
3284	/******************************************************************************/
3285
3286
3287	#ifdef BTNR_ENABLE_SOFTWARE_TUNE
3288	/******************************************************************************
3289	BTNR_P_TunerSearchCapSoftware() - capacitor binary scan
3290	******************************************************************************/
3291	void BTNR_P_TunerSearchCapSoftware(BTNR_3x7x_Handle h)
3292	{
3293
3294	uint32_t val;
3295	uint32_t tunerCapMask;
3296	uint8_t count1 = 8;
3297
3298
3299
3300	h->pTunerParams->BTNR_Local_Params.TunerCapCntl = 0x100;
3301	while (count1 > 0)
3302	{
3303	tunerCapMask = 1 << count1; /* cap_cntl mask */
3304	h->pTunerParams->BTNR_Local_Params.TunerCapCntl \|= (1 << count1);
3305	BTNR_P_TunerSetCapCntl(h);
3306	BTNR_P_TunerSetCapCntlLoopParams(h);
3307	BKNI_Delay(40); /* 40 us*/
3308	/* read popcap */
3309	val = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_MXRPLL_07);
3310	if (val & 0x80)
3311	h->pTunerParams->BTNR_Local_Params.TunerCapCntl &= ~tunerCapMask; /* cap_cntl <i> = 0 */
3312	else
3313	h->pTunerParams->BTNR_Local_Params.TunerCapCntl \|= tunerCapMask; /* cap_cntl <i> = 1 */
3314	BTNR_P_TunerSetCapCntl(h);
3315	count1--;
3316	}
3317	/* search complete */
3318	BTNR_P_TunerSetCapCntlLoopParams(h);
3319	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_02, lP_QPbiasCNT_1p0, 0x28); /* QP bias control */
3320	BKNI_Delay(40); /* 40 us*/
3321
3322
3323	}
3324	#endif
3325
3326	#ifdef BTNR_ENABLE_SOFTWARE_TUNE
3327	/******************************************************************************
3328	TunerSetcap_cntl() - this function programs cap_cntl, i_cntl
3329	******************************************************************************/
3330	BERR_Code BTNR_P_TunerSetCapCntl(BTNR_3x7x_Handle h)
3331	{
3332	uint32_t val=0;
3333
3334	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_02, lP_cap_cntl_1p0, 0x0); /* VCO cap setting - 9 bits from cap_cntl[8:0] */
3335	val \|= (h->pTunerParams->BTNR_Local_Params.TunerCapCntl << 19) & 0x0FF80000;
3336	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_MXRPLL_02, val);
3337
3338	/* same as VCO cap setting - msb 7 bits for I_cntl[6:0] = cap_cntl[8:2] */
3339	BREG_WriteField(h->hRegister, UFE_AFE_TNR0_MXRPLL_03, lP_I_cntl_1p0, h->pTunerParams->BTNR_Local_Params.TunerCapCntl);
3340	return BERR_SUCCESS;
3341	}
3342	#endif
3343
3344	#ifdef BTNR_ENABLE_SOFTWARE_TUNE
3345	/******************************************************************************
3346	BTNR_P_TunerSetCapCntlLoopParams() - this function programs wben_lf, nbr_lf,
3347	QPbiasCNT2, Kvco_cntl
3348	******************************************************************************/
3349	BERR_Code BTNR_P_TunerSetCapCntlLoopParams(BTNR_3x7x_Handle h)
3350	{
3351	uint32_t val;
3352	uint16_t sval;
3353	uint8_t idx;
3354
3355	static const uint16_t tuner_cap_cntl_table[BTNR_TUNER_CAP_CNTL_TABLE_SIZE] = {
3356	122,
3357	160,
3358	228,
3359	310,
3360	512
3361	};
3362
3363	/* wben_lf = UFE_AFE_TNR0_MXRPLL_01[28] --> bit 12 */
3364	/* nbr_lf = UFE_AFE_TNR0_MXRPLL_01[27:26] --> bits 14:15 */
3365	/* QPbiasCNT2 = UFE_AFE_TNR0_MXRPLL_02[10:6] --> bits 10:6 */
3366	/* Kvco_cntl = UFE_AFE_TNR0_MXRPLL_01[18:16] --> bits 2:0 */
3367	static const uint16_t tuner_cap_cntl_loop_params_table[BTNR_TUNER_CAP_CNTL_TABLE_SIZE] = {
3368	0xC141,
3369	0x4241,
3370	0xC142,
3371	0x4243,
3372	0x4245,
3373	};
3374
3375	for (idx = 0; idx < BTNR_TUNER_CAP_CNTL_TABLE_SIZE; idx++)
3376	{
3377	if (h->pTunerParams->BTNR_Local_Params.TunerCapCntl <= tuner_cap_cntl_table[idx])
3378	break;
3379	}
3380	sval = tuner_cap_cntl_loop_params_table[idx];
3381
3382	val = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_MXRPLL_01);
3383	val &= ~0x1C000000;
3384	val \|= (sval & 0x1000) << 16; /* wben_lf */
3385	val \|= (sval & 0xC000) << 12; /* nbr_lf */
3386	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_MXRPLL_01, val);
3387
3388	val = BREG_Read32(h->hRegister, BCHP_UFE_AFE_TNR0_MXRPLL_02);
3389	val &= ~0x000707C0;
3390	val \|= (sval & 0x0007) << 16; /* Kvco_cntl */
3391	val \|= (sval & 0x07C0); /* QPbiasCNT2 */
3392	BREG_Write32(h->hRegister, BCHP_UFE_AFE_TNR0_MXRPLL_02, val);
3393
3394	return BERR_SUCCESS;
3395	}
3396	#endif
3397
3398
3399

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/tnr/7552/btnr_tune.c

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