Context Navigation

burt.c

Last change on this file was 2, checked in by jglee, 11 years ago
first commit
Property svn:executable set to ``*
File size: 72.2 KB

Line
1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: burt.c $
11	* $brcm_Revision: Hydra_Software_Devel/74 $
12	* $brcm_Date: 3/18/12 6:17p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/urt/7429/burt.c $
19	*
20	* Hydra_Software_Devel/74 3/18/12 6:17p agin
21	* SWNOOS-523: Add 7429 support.
22	*
23	* Hydra_Software_Devel/73 11/7/11 7:40a agin
24	* SWNOOS-497: Relevel 97231 to prerel for B0.
25	*
26	* Hydra_Software_Devel/72 6/21/11 6:45a agin
27	* SW7346-273: Use enum values in switch statement.
28	*
29	* Hydra_Software_Devel/71 2/14/11 4:11p xhuang
30	* SW7358-29: Add 7358/7552 support
31	*
32	* Hydra_Software_Devel/70 2/4/11 2:56p jrubio
33	* SW7344-9: add 7346 and 7344 support
34	*
35	* Hydra_Software_Devel/69 1/26/11 2:26p etrudeau
36	* SWBLURAY-23692: add 7640 support
37	*
38	* Hydra_Software_Devel/68 12/22/10 5:18p rpereira
39	* SW7550-627: Corrected function name of ResetTxRx
40	*
41	* Hydra_Software_Devel/67 12/22/10 4:59p rpereira
42	* SW7550-627: Need a method to flush/reset the RX fifo
43	*
44	* Hydra_Software_Devel/66 11/2/10 5:29p hongtaoz
45	* SW7425-9: added 7425 support;
46	*
47	* Hydra_Software_Devel/65 10/14/10 4:46p nickh
48	* SW7422-74: Add 7422 support
49	*
50	* Hydra_Software_Devel/64 12/13/09 6:45p rpereira
51	* SW7550-41: Fixed compilation issues for 7550
52	*
53	* Hydra_Software_Devel/63 12/7/09 10:17p randyjew
54	* SW7468-6:Add 7468 support
55	*
56	* Hydra_Software_Devel/62 11/9/09 11:57a gmohile
57	* SW7408-1 : Add 7408 support
58	*
59	* Hydra_Software_Devel/61 9/15/09 11:30a rpereira
60	* SW7630-45: Adding 7630 support
61	*
62	* Hydra_Software_Devel/61 9/15/09 11:06a rpereira
63	* SW7630-45: Adding 7630 support
64	*
65	* Hydra_Software_Devel/61 9/15/09 11:05a rpereira
66	* SW7630-45: Adding 7630 support
67	*
68	* Hydra_Software_Devel/61 9/15/09 10:53a rpereira
69	* SW7630-45: Adding 7630 support
70	*
71	* Hydra_Software_Devel/60 9/1/09 6:46p pntruong
72	* SW7550-30: Fixed build errors.
73	*
74	* Hydra_Software_Devel/59 9/1/09 5:54p rpereira
75	* SW7550-30: Added 7550 support
76	*
77	* Hydra_Software_Devel/58 8/20/09 4:28p mward
78	* PR55545: Support 7125.
79	*
80	* Hydra_Software_Devel/57 8/10/09 6:12p jrubio
81	* PR55232: add 7340/73432 support
82	*
83	* Hydra_Software_Devel/56 7/22/09 1:19p maivu
84	* PR 30806: Fix build error with previous checkins for 93549/93556
85	*
86	*
87	* Hydra_Software_Devel/55 7/21/09 5:43p jkim
88	* PR30806: Add the function to set stop bits
89	*
90	* Hydra_Software_Devel/54 4/9/09 4:33p rpereira
91	* PR52971: adding 7635 support
92	*
93	* Hydra_Software_Devel/53 1/31/09 1:08a jrubio
94	* PR51629: add 7336 support
95	*
96	* Hydra_Software_Devel/52 12/2/08 4:17p kaushikb
97	* PR49867: Adding support for 7420
98	*
99	* Hydra_Software_Devel/51 9/4/08 4:55p jkim
100	* PR44823: add a function BURT_Read_Isr()
101	*
102	* Hydra_Software_Devel/50 9/4/08 4:05p jkim
103	* PR45727: remove compiler warning
104	*
105	* Hydra_Software_Devel/49 8/21/08 10:41a fbasso
106	* PR 44545: added support for 7601.
107	*
108	* Hydra_Software_Devel/48 6/12/08 10:16a jkim
109	* PR43200: add break after default label in switch statement and use
110	* BCHP_UARTA_LCR instead of BCHP_UARTB_LCR since offset is used UARTB
111	* and UARTC
112	*
113	* Hydra_Software_Devel/47 4/9/08 10:26a farshidf
114	* PR39194: add support for3548
115	*
116	* Hydra_Software_Devel/46 4/4/08 3:12p farshidf
117	* PR39483: add 3548/3556 support
118	*
119	* Hydra_Software_Devel/45 12/13/07 10:14a brianlee
120	* PR36744: Fixed a bug for 7440.
121	*
122	* Hydra_Software_Devel/44 11/28/07 2:24p farshidf
123	* PR36894: Add 7335 support
124	*
125	* Hydra_Software_Devel/43 11/28/07 1:32p brianlee
126	* PR36744: Added support for uart D for 7440.
127	*
128	* Hydra_Software_Devel/42 11/6/07 5:20p brianlee
129	* PR36744: Fixed compilation warnings.
130	*
131	* Hydra_Software_Devel/41 10/14/07 4:01p jkim
132	* PR14344: Add 7325 support
133	*
134	* Hydra_Software_Devel/40 8/22/07 10:45a jkim
135	* PR14344: add support 7403
136	*
137	* Hydra_Software_Devel/39 7/6/07 3:06p jkim
138	* PR32436: fix compile error when USE_BURT_INT_CALLBACK is defined
139	*
140	* Hydra_Software_Devel/38 5/21/07 4:27p jkim
141	* PR14344: Add 7405 support
142	*
143	* Hydra_Software_Devel/37 4/25/07 4:12p jkim
144	* PR29625: Add three functions, which can be called within ISR.
145	*
146	* Hydra_Software_Devel/36 3/1/07 5:02p jkim
147	* PR26690: add back intMode so that it is backward compatible. Now,
148	* txIntMode and rxIntMode are only used if intMode is set to false.
149	*
150	* Hydra_Software_Devel/35 2/23/07 11:15a jkim
151	* PR26690: remove global variable and make it part of channel handle
152	* structure
153	*
154	* Hydra_Software_Devel/34 1/22/07 11:16a agin
155	* PR26997: merge 3 UART support to trunk.
156	*
157	* Hydra_Software_Devel/33 1/15/07 3:34p jkim
158	* PR26690: separate rx/tx interrupt flag in the structure so that each
159	* interrupt can be enabled indepent of the other
160	*
161	* Hydra_Software_Devel/32 1/10/07 6:34p jkim
162	* PR26690: Add option to use callback instead of event when rx/tx
163	* interrupt is handled
164	*
165	* Hydra_Software_Devel/31 12/12/06 3:04p jkim
166	* PR24640: Preserve error bits in LSR whne LSR is read.
167	*
168	* Hydra_Software_Devel/30 11/9/06 12:55p jkim
169	* PR14344: add support for 7403
170	*
171	* Hydra_Software_Devel/29 9/19/06 5:20p agin
172	* PR24339: Resolve compiler warning for DEBUG=n builds for UPG modules.
173	*
174	* Hydra_Software_Devel/28 9/19/06 3:33p jkim
175	* PR24353: fix compiler error for 7401 C0
176	*
177	* Hydra_Software_Devel/27 9/11/06 4:50p brianlee
178	* PR23187: Added code for 7440.
179	*
180	* Hydra_Software_Devel/26 9/1/06 12:00p ltokuda
181	* PR21692: Update for 7118.
182	*
183	* Hydra_Software_Devel/25 8/9/06 11:11a agin
184	* PR23362: Add 3563 support.
185	*
186	* Hydra_Software_Devel/24 7/19/06 10:25a jkim
187	* PR22662: Cleaned up printf() and asjusted the offset accordingly during
188	* BURT_EnableFifo()
189	*
190	* Hydra_Software_Devel/23 7/18/06 9:24a jkim
191	* PR22662: modified to support UARTC for 7401 B0
192	*
193	* Hydra_Software_Devel/22 6/21/06 9:55a jkim
194	* PR14344: Add support for B0
195	*
196	* Hydra_Software_Devel/21 4/12/06 2:37p brianlee
197	* PR20757: Re-enable RX interrupt even if the FIFO is not empty.
198	*
199	* Hydra_Software_Devel/20 3/21/06 3:06p jkim
200	* PR20326: Add support for 7438
201	*
202	* Hydra_Software_Devel/19 3/14/06 6:06p brianlee
203	* PR14344: Fixed another problem with 7401 UART C.
204	*
205	* Hydra_Software_Devel/18 3/14/06 11:13a brianlee
206	* PR14344: Fixed default uart channel settings for 7401.
207	*
208	* Hydra_Software_Devel/17 3/14/06 10:09a brianlee
209	* PR14344: Changed C++ style comments to C.
210	*
211	* Hydra_Software_Devel/16 3/13/06 11:01a brianlee
212	* PR14344: Fixed the number of uart channels for 7401.
213	*
214	* Hydra_Software_Devel/15 3/1/06 11:28a agin
215	* PR19076: PR19919: Fixed baud rate and data bits calculation.
216	* PR19919: Update uart porting interface code for BCM7400.
217	* PR19076: Support BCM7400.
218	*
219	* Hydra_Software_Devel/PR19076/3 2/28/06 5:44p agin
220	* PR19919: Fixed baud rate and data bits calculation.
221	*
222	* Hydra_Software_Devel/PR19076/2 2/27/06 5:34p agin
223	* PR19919: Update uart porting interface code for BCM7400.
224	*
225	* Hydra_Software_Devel/PR19076/1 1/16/06 7:25p agin
226	* PR19076: Support BCM7400.
227	*
228	* Hydra_Software_Devel/14 10/28/05 2:37p jkim
229	* PR14344: Add 7401 support
230	*
231	* Hydra_Software_Devel/13 5/9/05 11:42a dlwin
232	* PR 14698: Resolve "unused ..." warnings.
233	*
234	* Hydra_Software_Devel/12 3/10/05 9:38a dlwin
235	* PR 14240: Added support for 3560
236	*
237	* Hydra_Software_Devel/11 12/27/04 11:08a brianlee
238	* PR13678: Fixed baudrate register calculation to be more accurate.
239	*
240	* Hydra_Software_Devel/10 6/11/04 11:05a brianlee
241	* PR11179: Set callback to NULL if interrupt is disabled.
242	*
243	* Hydra_Software_Devel/9 5/24/04 10:10a brianlee
244	* PR11179: Check to see if callback is not NULL before destorying it.
245	*
246	* Hydra_Software_Devel/8 3/26/04 4:32p brianlee
247	* PR8971: Remove BDBG_ASSERT() for malloc failure.
248	*
249	* Hydra_Software_Devel/7 12/29/03 3:59p marcusk
250	* PR9117: Updated with changes required to support interrupt ids rather
251	* than strings.
252	*
253	* Hydra_Software_Devel/6 11/4/03 6:54p brianlee
254	* Get rid of enter/leave macros.
255	*
256	* Hydra_Software_Devel/5 9/30/03 11:20a brianlee
257	* Fixed a warning.
258	*
259	* Hydra_Software_Devel/4 9/24/03 2:11p brianlee
260	* Changed the names of header files.
261	*
262	* Hydra_Software_Devel/3 9/19/03 1:58p brianlee
263	* Fixed warnings from Midas build.
264	*
265	* Hydra_Software_Devel/2 9/16/03 6:30p brianlee
266	* Writing to IRQ0_IRQEN register does not require coreoffset.
267	*
268	* Hydra_Software_Devel/1 9/16/03 5:00p brianlee
269	* Initial version.
270	*
271	***************************************************************************/
272	#include "bstd.h"
273	#include "burt.h"
274	#include "burt_priv.h"
275	#include "bchp_uarta.h"
276	#include "bchp_uartb.h"
277
278	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7401) \|\| \
279	(BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| \
280	(BCHP_CHIP==7118) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| \
281	(BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) \|\| (BCHP_CHIP==7601) \|\| \
282	(BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| (BCHP_CHIP==7342) \|\| \
283	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| \
284	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
285	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
286	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
287	#define MAX_URT_CHANNELS 3 /* 3 UARTs */
288	#elif (BCHP_CHIP==7440)
289	#define MAX_URT_CHANNELS 4 /* 4 UARTs for 7440 */
290	#else
291	#define MAX_URT_CHANNELS 2 /* 2 UARTs for 7038/7438/3560/3653/7468 */
292	#endif
293
294	#if (MAX_URT_CHANNELS >= 3)
295	#include "bchp_uartc.h"
296	#endif
297	#if (MAX_URT_CHANNELS >= 4)
298	#include "bchp_uartd.h"
299	#endif
300
301	#include "bchp_irq0.h"
302	#include "bchp_int_id_irq0.h"
303
304	BDBG_MODULE(burt);
305
306	#define DEV_MAGIC_ID ((BERR_URT_ID<<16) \| 0xFACE)
307
308	#define BURT_CHK_RETCODE( rc, func ) \
309	do { \
310	if( (rc = BERR_TRACE(func)) != BERR_SUCCESS ) \
311	{ \
312	goto done; \
313	} \
314	} while(0)
315
316	#define UART_CLOCK_FREQ 27000000 /* 27MHz input clock */
317	#define BITRATE_TO_BAUDRATE( bit ) (((UART_CLOCK_FREQ/8/(bit) + 1)/2) - 1)
318	#define BAUDRATE_TO_BITRATE( baud ) (UART_CLOCK_FREQ / (16 * (baud + 1)))
319
320	#define UART_TX_FIFO_SIZE 32
321
322	/*******************************************************************************
323	*
324	* Private Module Handles
325	*
326	*******************************************************************************/
327
328	typedef struct BURT_P_Handle
329	{
330	uint32_t magicId; /* Used to check if structure is corrupt */
331	BCHP_Handle hChip;
332	BREG_Handle hRegister;
333	BINT_Handle hInterrupt;
334	unsigned int maxChnNo;
335	BURT_ChannelHandle hUrtChn[MAX_URT_CHANNELS];
336	} BURT_P_Handle;
337
338	typedef struct BURT_P_ChannelHandle
339	{
340	uint32_t magicId; /* Used to check if structure is corrupt */
341	BURT_Handle hUrt;
342	uint32_t chnNo;
343	uint32_t coreOffset;
344	BKNI_EventHandle hChnTxEvent;
345	BKNI_EventHandle hChnRxEvent;
346	BINT_CallbackHandle hChnCallback;
347	bool intMode; /* If true, rx/txIntMode is not used. */
348	bool rxIntMode; /* used only if intMode is false */
349	bool txIntMode; /* used only if intMode is false */
350	uint8_t savedLsr; /* OR error bits into here so they are not lost */
351	BINT_CallbackFunc intCallbackFunc ;
352	} BURT_P_ChannelHandle;
353
354	#if (BCHP_CHIP==7118) \|\| (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| \
355	(BCHP_CHIP==7440) \|\| (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| \
356	(BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| \
357	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
358	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
359	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
360	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
361	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
362	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
363	/* chip has some 16550 style UARTS */
364	static void BURT_P_EnableFifo(BURT_ChannelHandle hChn);
365	static uint32_t BURT_P_ReadLsr(BURT_ChannelHandle hChn, uint32_t *pErrLsr);
366	static uint32_t BURT_P_ReadLsr_Isr(BURT_ChannelHandle hChn, uint32_t *pErrLsr);
367	#endif
368
369	/*******************************************************************************
370	*
371	* Default Module Settings
372	*
373	*******************************************************************************/
374	static const BURT_Settings defUrtSettings = NULL;
375
376	static const BURT_ChannelSettings defUrt0ChnSettings =
377	{
378	true,
379	true,
380	115200,
381	BURT_DataBits_eDataBits8,
382	BURT_Parity_eNone,
383	true,
384	false, /* rxIntMode is set to false for backward compatibility. */
385	false, /* txIntMode is set to false for backward compatibility. */
386	BURT_StopBits_eOneBit
387	};
388
389	static const BURT_ChannelSettings defUrt1ChnSettings =
390	{
391	true,
392	true,
393	115200,
394	BURT_DataBits_eDataBits8,
395	BURT_Parity_eNone,
396	true,
397	false, /* rxIntMode is set to false for backward compatibility. */
398	false, /* txIntMode is set to false for backward compatibility. */
399	BURT_StopBits_eOneBit
400	};
401
402	#if (MAX_URT_CHANNELS >= 3)
403	static const BURT_ChannelSettings defUrt2ChnSettings =
404	{
405	true,
406	true,
407	115200,
408	BURT_DataBits_eDataBits8,
409	BURT_Parity_eNone,
410	true,
411	false, /* rxIntMode is set to false for backward compatibility. */
412	false, /* txIntMode is set to false for backward compatibility. */
413	BURT_StopBits_eOneBit
414	};
415	#endif
416
417	#if (MAX_URT_CHANNELS >= 4)
418	static const BURT_ChannelSettings defUrt3ChnSettings =
419	{
420	true,
421	true,
422	115200,
423	BURT_DataBits_eDataBits8,
424	BURT_Parity_eNone,
425	true,
426	false, /* rxIntMode is set to false for backward compatibility. */
427	false, /* txIntMode is set to false for backward compatibility. */
428	BURT_StopBits_eOneBit
429	};
430	#endif
431
432	static const BINT_Id IntId[] =
433	{
434	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438 \|\| BCHP_CHIP==7468 )
435	BCHP_INT_ID_ua_irqen,
436	BCHP_INT_ID_ub_irqen
437	#elif (BCHP_CHIP==3560) \|\| (BCHP_CHIP==3563)
438	BCHP_INT_ID_ua,
439	BCHP_INT_ID_ub
440	#elif (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) \|\| (BCHP_CHIP==7550)
441	BCHP_INT_ID_ua,
442	BCHP_INT_ID_ub,
443	BCHP_INT_ID_uc
444	#elif (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7401) \|\| \
445	(BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| \
446	(BCHP_CHIP==7118) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| \
447	(BCHP_CHIP==7342) \|\| (BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| \
448	(BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| (BCHP_CHIP==7125) \|\| \
449	(BCHP_CHIP==7408) \|\| (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| \
450	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
451	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
452	BCHP_INT_ID_ua_irqen,
453	BCHP_INT_ID_ub_irqen,
454	BCHP_INT_ID_uc_irqen
455	#elif (BCHP_CHIP==7640)
456	BCHP_INT_ID_IRQ0_ua_irqen,
457	BCHP_INT_ID_ub_irqen,
458	BCHP_INT_ID_uc_irqen
459	#elif (BCHP_CHIP==7440)
460	BCHP_INT_ID_ua_irqen,
461	BCHP_INT_ID_ub_irqen,
462	BCHP_INT_ID_uc_irqen,
463	BCHP_INT_ID_ud_irqen
464	#else
465	#error BCHP_CHIP set to unsupported chip.
466	#endif
467
468	};
469	/*******************************************************************************
470	*
471	* Public Module Functions
472	*
473	*******************************************************************************/
474	void BURT_RegisterCallback(
475	BURT_ChannelHandle hChn, /* Device channel handle */
476	BINT_CallbackFunc callbackFunc /* callback function to register */
477	)
478	{
479	BDBG_ASSERT( hChn );
480	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
481
482	hChn->intCallbackFunc = callbackFunc;
483	}
484
485	BERR_Code BURT_Open(
486	BURT_Handle pUrt, / [output] Returns handle */
487	BCHP_Handle hChip, /* Chip handle */
488	BREG_Handle hRegister, /* Register handle */
489	BINT_Handle hInterrupt, /* Interrupt handle */
490	const BURT_Settings pDefSettings / Default settings */
491	)
492	{
493	BERR_Code retCode = BERR_SUCCESS;
494	BURT_Handle hDev;
495	unsigned int chnIdx;
496
497
498	/* Sanity check on the handles we've been given. */
499	BDBG_ASSERT( hChip );
500	BDBG_ASSERT( hRegister );
501	BDBG_ASSERT( hInterrupt );
502	BSTD_UNUSED( pDefSettings );
503
504	/* Alloc memory from the system heap */
505	hDev = (BURT_Handle) BKNI_Malloc( sizeof( BURT_P_Handle ) );
506	if( hDev == NULL )
507	{
508	*pUrt = NULL;
509	retCode = BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
510	BDBG_ERR(("BURT_Open: BKNI_malloc() failed\n"));
511	goto done;
512	}
513
514	hDev->magicId = DEV_MAGIC_ID;
515	hDev->hChip = hChip;
516	hDev->hRegister = hRegister;
517	hDev->hInterrupt = hInterrupt;
518	hDev->maxChnNo = MAX_URT_CHANNELS;
519	for( chnIdx = 0; chnIdx < hDev->maxChnNo; chnIdx++ )
520	{
521	hDev->hUrtChn[chnIdx] = NULL;
522	}
523
524	*pUrt = hDev;
525
526	done:
527	return( retCode );
528	}
529
530	BERR_Code BURT_Close(
531	BURT_Handle hDev /* Device handle */
532	)
533	{
534	BERR_Code retCode = BERR_SUCCESS;
535
536
537	BDBG_ASSERT( hDev );
538	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
539
540	BKNI_Free( (void *) hDev );
541
542	return( retCode );
543	}
544
545	BERR_Code BURT_GetDefaultSettings(
546	BURT_Settings pDefSettings, / [output] Returns default setting */
547	BCHP_Handle hChip /* Chip handle */
548	)
549	{
550	BERR_Code retCode = BERR_SUCCESS;
551
552	BSTD_UNUSED(hChip);
553
554
555	*pDefSettings = defUrtSettings;
556
557	return( retCode );
558	}
559
560	BERR_Code BURT_GetTotalChannels(
561	BURT_Handle hDev, /* Device handle */
562	unsigned int totalChannels / [output] Returns total number downstream channels supported */
563	)
564	{
565	BERR_Code retCode = BERR_SUCCESS;
566
567
568	BDBG_ASSERT( hDev );
569	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
570
571	*totalChannels = hDev->maxChnNo;
572
573	return( retCode );
574	}
575
576	BERR_Code BURT_GetChannelDefaultSettings(
577	BURT_Handle hDev, /* Device handle */
578	unsigned int channelNo, /* Channel number to default setting for */
579	BURT_ChannelSettings pChnDefSettings / [output] Returns channel default setting */
580	)
581	{
582	BERR_Code retCode = BERR_SUCCESS;
583
584	#if !BDBG_DEBUG_BUILD
585	BSTD_UNUSED(hDev);
586	#endif
587
588	BDBG_ASSERT( hDev );
589	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
590
591	switch (channelNo)
592	{
593	case 0:
594	*pChnDefSettings = defUrt0ChnSettings;
595	break;
596
597	case 1:
598	*pChnDefSettings = defUrt1ChnSettings;
599	break;
600
601	#if (MAX_URT_CHANNELS >= 3)
602	case 2:
603	*pChnDefSettings = defUrt2ChnSettings;
604	break;
605	#endif
606
607	#if (MAX_URT_CHANNELS >= 4)
608	case 3:
609	*pChnDefSettings = defUrt3ChnSettings;
610	break;
611	#endif
612
613	default:
614	retCode = BERR_INVALID_PARAMETER;
615	break;
616
617	}
618
619	return( retCode );
620	}
621
622	BERR_Code BURT_OpenChannel(
623	BURT_Handle hDev, /* Device handle */
624	BURT_ChannelHandle phChn, / [output] Returns channel handle */
625	unsigned int channelNo, /* Channel number to open */
626	const BURT_ChannelSettings pChnDefSettings / Channel default setting */
627	)
628	{
629	BERR_Code retCode = BERR_SUCCESS;
630	BURT_ChannelHandle hChnDev;
631	uint32_t lval;
632
633	BDBG_ASSERT( hDev );
634	BDBG_ASSERT( hDev->magicId == DEV_MAGIC_ID );
635
636	hChnDev = NULL;
637
638	if( channelNo < hDev->maxChnNo )
639	{
640	if( hDev->hUrtChn[channelNo] == NULL )
641	{
642	/* Alloc memory from the system heap */
643	hChnDev = (BURT_ChannelHandle) BKNI_Malloc( sizeof( BURT_P_ChannelHandle ) );
644	if( hChnDev == NULL )
645	{
646	*phChn = NULL;
647	retCode = BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
648	BDBG_ERR(("BURT_OpenChannel: BKNI_malloc() failed\n"));
649	goto done;
650	}
651
652	BURT_CHK_RETCODE( retCode, BKNI_CreateEvent( &(hChnDev->hChnTxEvent) ) );
653	BURT_CHK_RETCODE( retCode, BKNI_CreateEvent( &(hChnDev->hChnRxEvent) ) );
654	hChnDev->magicId = DEV_MAGIC_ID;
655	hChnDev->hUrt = hDev;
656	hChnDev->chnNo = channelNo;
657	hDev->hUrtChn[channelNo] = hChnDev;
658	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| \
659	(BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| (BCHP_CHIP==7118) \|\| \
660	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
661	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
662	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
663	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
664	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
665	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
666	switch (channelNo) {
667	default:
668	hChnDev->coreOffset = 0;
669	break;
670	case 1:
671	hChnDev->coreOffset = BCHP_UARTB_RBR - BCHP_UARTA_RBR;
672	break;
673	#if (BCHP_CHIP!=7468)
674	case 2:
675	hChnDev->coreOffset = BCHP_UARTC_RBR - BCHP_UARTA_RBR;
676	break;
677	#if (BCHP_CHIP==7440)
678	case 3:
679	hChnDev->coreOffset = BCHP_UARTD_RBR - BCHP_UARTA_RBR;
680	break;
681	#endif
682	#endif
683	}
684	#elif (BCHP_CHIP==7401 \|\| BCHP_CHIP==7403)
685	if (channelNo == 0)
686	hChnDev->coreOffset = 0;
687	else if (channelNo == 1)
688	hChnDev->coreOffset = BCHP_UARTB_RCVSTAT - BCHP_UARTA_RCVSTAT;
689	else
690	#if (BCHP_VER >= BCHP_VER_B0 \|\| BCHP_CHIP==7403)
691	hChnDev->coreOffset = BCHP_UARTC_RBR - BCHP_UARTA_RCVSTAT;
692	#else
693	hChnDev->coreOffset = BCHP_UARTC_RCVSTAT - BCHP_UARTA_RCVSTAT;
694	#endif
695	#elif (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556)
696	switch (channelNo) {
697	default:
698	hChnDev->coreOffset = 0;
699	case 1:
700	hChnDev->coreOffset = BCHP_UARTB_RCVSTAT - BCHP_UARTA_RCVSTAT;
701	break;
702	case 2:
703	hChnDev->coreOffset = BCHP_UARTC_RCVSTAT - BCHP_UARTA_RCVSTAT;
704	break;
705	}
706	#else
707	hChnDev->coreOffset = (channelNo == 0) ? 0 : (BCHP_UARTB_RCVSTAT - BCHP_UARTA_RCVSTAT);
708	#endif
709
710	BURT_EnableTxInt (hChnDev, false); /* turn off ints */
711	BURT_EnableRxInt (hChnDev, false); /* turn off ints */
712	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
713	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
714	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
715	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
716	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
717	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
718	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
719	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
720	hChnDev->savedLsr = 0;
721	BREG_Write32( hDev->hRegister, (hChnDev->coreOffset + BCHP_UARTA_LCR), 0 );
722	BURT_P_EnableFifo (hChnDev);
723	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
724	if (channelNo == 2)
725	{
726	/* UARTC register definitions are different from UARTA and UARTB.
727	* Do not use coreOffset for UARTC.
728	*/
729	hChnDev->savedLsr = 0;
730	BREG_Write32( hDev->hRegister, BCHP_UARTC_LCR, 0 );
731	BURT_P_EnableFifo (hChnDev);
732	}
733	else
734	{
735	BREG_Write32( hDev->hRegister, (hChnDev->coreOffset + BCHP_UARTA_CONTROL), 0 );
736	}
737	#else
738	BREG_Write32( hDev->hRegister, (hChnDev->coreOffset + BCHP_UARTA_CONTROL), 0 );
739	#endif
740	BURT_P_SetBaudRate (hChnDev, pChnDefSettings->baud);
741	BURT_P_SetDataBits (hChnDev, pChnDefSettings->bits);
742	BURT_P_SetParity (hChnDev, pChnDefSettings->parity);
743	BURT_P_SetStopBits (hChnDev, pChnDefSettings->stopBits);
744	BURT_P_EnableTxRx (hChnDev, pChnDefSettings->txEnable, pChnDefSettings->rxEnable);
745	/*
746	* Enable interrupt for this channel
747	* Initialize callback function to NULL. This callback is
748	* used instead of posting event during interrupt handling.
749	*/
750	hChnDev->intMode = pChnDefSettings->intMode;
751	hChnDev->rxIntMode = pChnDefSettings->rxIntMode;
752	hChnDev->txIntMode = pChnDefSettings->txIntMode;
753	hChnDev->intCallbackFunc = NULL;
754	if ((hChnDev->intMode == true) \|\|
755	(hChnDev->rxIntMode == true) \|\|
756	(hChnDev->txIntMode == true))
757	{
758	/*
759	* Register and enable L2 interrupt.
760	* The same callback is used for tx/rx
761	*/
762	BURT_CHK_RETCODE( retCode, BINT_CreateCallback(
763	&(hChnDev->hChnCallback), hDev->hInterrupt, IntId[channelNo],
764	BURT_P_HandleInterrupt_Isr, (void *) hChnDev, 0x00 ) );
765	BURT_CHK_RETCODE( retCode, BINT_EnableCallback( hChnDev->hChnCallback ) );
766
767	BKNI_EnterCriticalSection();
768
769	/*
770	* Enable URT interrupt in UPG
771	*/
772	lval = BREG_Read32(hDev->hRegister, BCHP_IRQ0_IRQEN);
773	#if (BCHP_CHIP==7038 \|\| BCHP_CHIP==7438 \|\|BCHP_CHIP == 7468)
774	if (channelNo == 0)
775	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ua_irqen, 1);
776	else
777	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ub_irqen, 1);
778	#elif (BCHP_CHIP==3560) \|\| (BCHP_CHIP==3563)
779	if (channelNo == 0)
780	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ua, 1);
781	else
782	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ub, 1);
783	#elif (BCHP_CHIP==3548) \|\| (BCHP_CHIP==3556) \|\| (BCHP_CHIP==7550)
784	if (channelNo == 0)
785	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ua, 1);
786	else if (channelNo == 1)
787	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ub, 1);
788	else if (channelNo == 2)
789	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, uc, 1);
790	#elif (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| \
791	(BCHP_CHIP==7401) \|\| (BCHP_CHIP==7403) \|\| (BCHP_CHIP==7405) \|\| \
792	(BCHP_CHIP==7118) \|\| (BCHP_CHIP==7325) \|\| \
793	(BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| (BCHP_CHIP==7340) \|\| \
794	(BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
795	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7422) \|\| (BCHP_CHIP==7429) \|\| \
796	(BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| (BCHP_CHIP==7344) \|\| \
797	(BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| (BCHP_CHIP==7552) \|\| \
798	(BCHP_CHIP==7231)
799	if (channelNo == 0)
800	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ua_irqen, 1);
801	else if (channelNo == 1)
802	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ub_irqen, 1);
803	else if (channelNo == 2)
804	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, uc_irqen, 1);
805	#if (BCHP_CHIP==7440)
806	else if (channelNo == 3)
807	lval \|= BCHP_FIELD_DATA(IRQ0_IRQEN, ud_irqen, 1);
808	#endif
809
810	#else
811	#error BCHP_CHIP set to unsupported chip.
812	#endif
813
814	BREG_Write32( hDev->hRegister, BCHP_IRQ0_IRQEN, lval );
815
816	/*
817	* Enable RX URT interrupt in URT
818	* DON'T ENABLE TX INT BECAUSE THE FIFO IS EMPTY AND WE'RE GOING TO GET INTERRUPTED RIGHT AWAY.
819	* The caller should enable the interrupt AFTER he writes to the TX FIFO.
820	*/
821	BURT_EnableTxInt (hChnDev, false);
822	if ((hChnDev->intMode == true) \|\|
823	(hChnDev->rxIntMode == true))
824	{
825	BURT_EnableRxInt (hChnDev, true);
826	}
827	BKNI_LeaveCriticalSection();
828	}
829	else
830	{
831	hChnDev->hChnCallback = NULL;
832	}
833
834	*phChn = hChnDev;
835	}
836	else
837	{
838	retCode = BURT_ERR_NOTAVAIL_CHN_NO;
839	}
840	}
841	else
842	{
843	retCode = BERR_INVALID_PARAMETER;
844	}
845
846	done:
847	if( retCode != BERR_SUCCESS )
848	{
849	if( hChnDev != NULL )
850	{
851	BKNI_DestroyEvent( hChnDev->hChnTxEvent );
852	BKNI_DestroyEvent( hChnDev->hChnRxEvent );
853	BKNI_Free( hChnDev );
854	hDev->hUrtChn[channelNo] = NULL;
855	*phChn = NULL;
856	}
857	}
858	return( retCode );
859	}
860
861	BERR_Code BURT_CloseChannel(
862	BURT_ChannelHandle hChn /* Device channel handle */
863	)
864	{
865	BERR_Code retCode = BERR_SUCCESS;
866	BURT_Handle hDev;
867	unsigned int chnNo;
868
869
870	BDBG_ASSERT( hChn );
871	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
872
873	hDev = hChn->hUrt;
874	/*
875	* Disable interrupt for this channel
876	*/
877	BKNI_EnterCriticalSection();
878	BURT_EnableTxInt (hChn, false); /* turn off ints */
879	BURT_EnableRxInt (hChn, false); /* turn off ints */
880	BURT_P_EnableTxRx (hChn, false, false);
881	BKNI_LeaveCriticalSection();
882
883	if (hChn->hChnCallback)
884	{
885	BURT_CHK_RETCODE( retCode, BINT_DisableCallback( hChn->hChnCallback ) );
886	BURT_CHK_RETCODE( retCode, BINT_DestroyCallback( hChn->hChnCallback ) );
887	}
888
889	BKNI_DestroyEvent( hChn->hChnTxEvent );
890	BKNI_DestroyEvent( hChn->hChnRxEvent );
891	chnNo = hChn->chnNo;
892	BKNI_Free( hChn );
893	hDev->hUrtChn[chnNo] = NULL;
894
895	done:
896	return( retCode );
897	}
898
899	BERR_Code BURT_GetDevice(
900	BURT_ChannelHandle hChn, /* Device channel handle */
901	BURT_Handle phDev / [output] Returns Device handle */
902	)
903	{
904	BERR_Code retCode = BERR_SUCCESS;
905
906
907	BDBG_ASSERT( hChn );
908	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
909
910	*phDev = hChn->hUrt;
911
912	return( retCode );
913	}
914
915	BERR_Code BURT_GetTxEventHandle(
916	BURT_ChannelHandle hChn, /* Device channel handle */
917	BKNI_EventHandle phEvent / [output] Returns event handle */
918	)
919	{
920	BERR_Code retCode = BERR_SUCCESS;
921
922
923	BDBG_ASSERT( hChn );
924	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
925
926	*phEvent = hChn->hChnTxEvent;
927
928	return( retCode );
929	}
930
931	BERR_Code BURT_GetRxEventHandle(
932	BURT_ChannelHandle hChn, /* Device channel handle */
933	BKNI_EventHandle phEvent / [output] Returns event handle */
934	)
935	{
936	BERR_Code retCode = BERR_SUCCESS;
937
938
939	BDBG_ASSERT( hChn );
940	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
941
942	*phEvent = hChn->hChnRxEvent;
943
944	return( retCode );
945	}
946
947
948
949	bool BURT_IsRxDataAvailable(
950	BURT_ChannelHandle hChn /* Device channel handle */
951	)
952	{
953	uint32_t lval;
954	BURT_Handle hDev;
955	bool dataAvail;
956
957	BDBG_ASSERT( hChn );
958	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
959
960	hDev = hChn->hUrt;
961
962	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
963	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
964	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
965	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
966	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
967	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
968	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
969	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
970	lval = BURT_P_ReadLsr(hChn, 0);
971	dataAvail = (lval & BCHP_UARTA_LSR_DR_MASK) ? true : false;
972	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
973	/* UARTC register definitions are different from UARTA and UARTB.
974	* Do not use coreOffset for UARTC.
975	*/
976	if (hChn->chnNo == 2)
977	{
978	lval = BURT_P_ReadLsr(hChn, 0);
979	dataAvail = (lval & BCHP_UARTC_LSR_DR_MASK) ? true : false;
980	}
981	else
982	{
983	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
984	dataAvail = (lval & BCHP_UARTA_RCVSTAT_RDA_MASK) ? true : false;
985	}
986	#else
987	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
988	dataAvail = (lval & BCHP_UARTA_RCVSTAT_RDA_MASK) ? true : false;
989	#endif
990
991	return dataAvail;
992	}
993
994
995	bool BURT_IsRxDataAvailable_Isr(
996	BURT_ChannelHandle hChn /* Device channel handle */
997	)
998	{
999	uint32_t lval;
1000	BURT_Handle hDev;
1001	bool dataAvail;
1002
1003	BDBG_ASSERT( hChn );
1004	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1005
1006	hDev = hChn->hUrt;
1007
1008	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1009	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1010	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1011	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1012	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1013	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1014	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1015	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1016	lval = BURT_P_ReadLsr_Isr(hChn, 0);
1017	dataAvail = (lval & BCHP_UARTA_LSR_DR_MASK) ? true : false;
1018	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1019	/* UARTC register definitions are different from UARTA and UARTB.
1020	* Do not use coreOffset for UARTC.
1021	*/
1022	if (hChn->chnNo == 2)
1023	{
1024	lval = BURT_P_ReadLsr_Isr(hChn, 0);
1025	dataAvail = (lval & BCHP_UARTC_LSR_DR_MASK) ? true : false;
1026	}
1027	else
1028	{
1029	lval = BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1030	dataAvail = (lval & BCHP_UARTA_RCVSTAT_RDA_MASK) ? true : false;
1031	}
1032	#else
1033	lval = BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1034	dataAvail = (lval & BCHP_UARTA_RCVSTAT_RDA_MASK) ? true : false;
1035	#endif
1036
1037	return dataAvail;
1038	}
1039
1040
1041	uint32_t BURT_GetAvailTxFifoCnt (
1042	BURT_ChannelHandle hChn /* Device channel handle */
1043	)
1044	{
1045	uint32_t lval, byteCnt;
1046	BURT_Handle hDev;
1047
1048	BDBG_ASSERT( hChn );
1049	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1050
1051	hDev = hChn->hUrt;
1052
1053	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1054	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1055	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1056	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1057	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1058	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1059	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1060	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1061	lval = BURT_P_ReadLsr(hChn, 0);
1062	byteCnt = (lval & BCHP_UARTA_LSR_THRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1063	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1064	/* UARTC register definitions are different from UARTA and UARTB.
1065	* Do not use coreOffset for UARTC.
1066	*/
1067	if (hChn->chnNo == 2)
1068	{
1069	lval = BURT_P_ReadLsr(hChn, 0);
1070	byteCnt = (lval & BCHP_UARTC_LSR_THRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1071	}
1072	else
1073	{
1074	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
1075	byteCnt = (lval & BCHP_UARTA_XMTSTAT_TDRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1076	}
1077	#else
1078	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
1079	byteCnt = (lval & BCHP_UARTA_XMTSTAT_TDRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1080	#endif
1081
1082	return byteCnt;
1083	}
1084
1085
1086	uint32_t BURT_GetAvailTxFifoCnt_Isr(
1087	BURT_ChannelHandle hChn /* Device channel handle */
1088	)
1089	{
1090	uint32_t lval, byteCnt;
1091	BURT_Handle hDev;
1092
1093	BDBG_ASSERT( hChn );
1094	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1095
1096	hDev = hChn->hUrt;
1097
1098	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1099	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1100	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1101	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1102	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1103	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1104	(BCHP_CHIP==7346) \|\| (BCHP_CHIP==7344) \|\| (BCHP_CHIP==7358) \|\| \
1105	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1106
1107	lval = BURT_P_ReadLsr_Isr(hChn, 0);
1108	byteCnt = (lval & BCHP_UARTA_LSR_THRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1109	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1110	/* UARTC register definitions are different from UARTA and UARTB.
1111	* Do not use coreOffset for UARTC.
1112	*/
1113	if (hChn->chnNo == 2)
1114	{
1115	lval = BURT_P_ReadLsr_Isr(hChn, 0);
1116	byteCnt = (lval & BCHP_UARTC_LSR_THRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1117	}
1118	else
1119	{
1120	lval = BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
1121	byteCnt = (lval & BCHP_UARTA_XMTSTAT_TDRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1122	}
1123	#else
1124	lval = BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
1125	byteCnt = (lval & BCHP_UARTA_XMTSTAT_TDRE_MASK) ? UART_TX_FIFO_SIZE : 0;
1126	#endif
1127
1128	return byteCnt;
1129	}
1130
1131
1132	void BURT_EnableTxInt(
1133	BURT_ChannelHandle hChn, /* Device channel handle */
1134	bool enableTxInt /* enable flag for transmitter interrupt */
1135	)
1136	{
1137	uint32_t lval;
1138	BURT_Handle hDev;
1139
1140	hDev = hChn->hUrt;
1141
1142	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1143	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1144	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1145	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1146	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1147	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1148	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1149	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1150	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_IER);
1151	if (enableTxInt)
1152	{
1153	/* Enable TX int */
1154	lval \|= BCHP_UARTA_IER_ETBEI_MASK;
1155	}
1156	else
1157	{
1158	/* Disable TX int */
1159	lval &= ~BCHP_UARTA_IER_ETBEI_MASK;
1160	}
1161	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_IER, lval);
1162	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1163	/* UARTC register definitions are different from UARTA and UARTB.
1164	* Do not use coreOffset for UARTC.
1165	*/
1166	if (hChn->chnNo == 2)
1167	{
1168	lval = BREG_Read32(hDev->hRegister, BCHP_UARTC_IER);
1169	if (enableTxInt)
1170	{
1171	/* Enable TX int */
1172	lval \|= BCHP_UARTC_IER_ETBEI_MASK;
1173	}
1174	else
1175	{
1176	/* Disable TX int */
1177	lval &= ~BCHP_UARTC_IER_ETBEI_MASK;
1178	}
1179	BREG_Write32(hDev->hRegister, BCHP_UARTC_IER, lval);
1180	}
1181	else
1182	{
1183	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
1184	if (enableTxInt)
1185	{
1186	/* Enable TX int */
1187	lval \|= BCHP_UARTA_XMTSTAT_TIE_MASK;
1188	}
1189	else
1190	{
1191	/* Disable TX int */
1192	lval &= ~BCHP_UARTA_XMTSTAT_TIE_MASK;
1193	}
1194	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT, lval);
1195	}
1196	#else
1197	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
1198	if (enableTxInt)
1199	{
1200	/* Enable TX int */
1201	lval \|= BCHP_UARTA_XMTSTAT_TIE_MASK;
1202	}
1203	else
1204	{
1205	/* Disable TX int */
1206	lval &= ~BCHP_UARTA_XMTSTAT_TIE_MASK;
1207	}
1208	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT, lval);
1209	#endif
1210	}
1211
1212	void BURT_EnableRxInt(
1213	BURT_ChannelHandle hChn, /* Device channel handle */
1214	bool enableRxInt /* enable flag for receiver interrupt */
1215	)
1216	{
1217	uint32_t lval;
1218	BURT_Handle hDev;
1219
1220	hDev = hChn->hUrt;
1221
1222
1223	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1224	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1225	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1226	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1227	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1228	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1229	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1230	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1231	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_IER);
1232	if (enableRxInt)
1233	{
1234	/* Enable RX int */
1235	lval \|= BCHP_UARTA_IER_ERBFI_MASK;
1236	}
1237	else
1238	{
1239	/* Disable RX int */
1240	lval &= ~BCHP_UARTA_IER_ERBFI_MASK;
1241	}
1242	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_IER, lval);
1243	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1244	/* UARTC register definitions are different from UARTA and UARTB.
1245	* Do not use coreOffset for UARTC.
1246	*/
1247	if (hChn->chnNo == 2)
1248	{
1249	lval = BREG_Read32(hDev->hRegister, BCHP_UARTC_IER);
1250	if (enableRxInt)
1251	{
1252	/* Enable RX int */
1253	lval \|= BCHP_UARTC_IER_ERBFI_MASK;
1254	}
1255	else
1256	{
1257	/* Disable RX int */
1258	lval &= ~BCHP_UARTC_IER_ERBFI_MASK;
1259	}
1260	BREG_Write32(hDev->hRegister, BCHP_UARTC_IER, lval);
1261	}
1262	else
1263	{
1264	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1265	if (enableRxInt)
1266	{
1267	/* Enable RX int */
1268	lval \|= BCHP_UARTA_RCVSTAT_RIE_MASK;
1269	}
1270	else
1271	{
1272	/* Disable RX int */
1273	lval &= ~BCHP_UARTA_RCVSTAT_RIE_MASK;
1274	}
1275	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT, lval);
1276	}
1277	#else
1278	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1279	if (enableRxInt)
1280	{
1281	/* Enable RX int */
1282	lval \|= BCHP_UARTA_RCVSTAT_RIE_MASK;
1283	}
1284	else
1285	{
1286	/* Disable RX int */
1287	lval &= ~BCHP_UARTA_RCVSTAT_RIE_MASK;
1288	}
1289	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT, lval);
1290	#endif
1291
1292	}
1293
1294	BERR_Code BURT_Read_Isr (
1295	BURT_ChannelHandle hChn, /* Device channel handle */
1296	uint8_t data, / pointer to memory to store data */
1297	uint32_t numBytes, /* number of bytes to read */
1298	uint32_t bytesRead, / [output] number of actual bytes read */
1299	BURT_RxError rxError / [output] receive error code */
1300	)
1301	{
1302	BERR_Code retCode = BERR_SUCCESS;
1303	uint32_t loopCnt = 0;
1304	BURT_Handle hDev;
1305
1306	BDBG_ASSERT( hChn );
1307	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1308
1309	hDev = hChn->hUrt;
1310
1311	while (numBytes && (BURT_IsRxDataAvailable_Isr(hChn)==true))
1312	{
1313	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1314	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1315	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1316	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1317	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1318	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1319	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1320	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1321	*data = (uint8_t)(BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RBR));
1322	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1323	/* UARTC register definitions are different from UARTA and UARTB.
1324	* Do not use coreOffset for UARTC.
1325	*/
1326	if (hChn->chnNo == 2)
1327	{
1328	*data = (uint8_t)(BREG_Read32_isr(hDev->hRegister, BCHP_UARTC_RBR));
1329	}
1330	else
1331	{
1332	*data = (uint8_t)(BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVDATA));
1333	}
1334	#else
1335	*data = (uint8_t)(BREG_Read32_isr(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVDATA));
1336	#endif
1337	data++;
1338	loopCnt++;
1339	numBytes--;
1340	}
1341	bytesRead = loopCnt; / actual bytes read */
1342
1343	*rxError = BURT_GetRxError_Isr(hChn);
1344	if (*rxError != BURT_RxError_eNoError)
1345	{
1346	retCode = BURT_ERR_RX_ERROR;
1347	goto done;
1348	}
1349
1350	done:
1351	return( retCode );
1352	}
1353
1354	BERR_Code BURT_Read (
1355	BURT_ChannelHandle hChn, /* Device channel handle */
1356	uint8_t data, / pointer to memory to store data */
1357	uint32_t numBytes, /* number of bytes to read */
1358	uint32_t bytesRead, / [output] number of actual bytes read */
1359	BURT_RxError rxError / [output] receive error code */
1360	)
1361	{
1362	BERR_Code retCode = BERR_SUCCESS;
1363	uint32_t loopCnt = 0;
1364	BURT_Handle hDev;
1365
1366	BDBG_ASSERT( hChn );
1367	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1368
1369	hDev = hChn->hUrt;
1370
1371	while (numBytes && (BURT_IsRxDataAvailable(hChn)==true))
1372	{
1373	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1374	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1375	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1376	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1377	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1378	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1379	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1380	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1381	*data = (uint8_t)(BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RBR));
1382	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1383	/* UARTC register definitions are different from UARTA and UARTB.
1384	* Do not use coreOffset for UARTC.
1385	*/
1386	if (hChn->chnNo == 2)
1387	{
1388	*data = (uint8_t)(BREG_Read32(hDev->hRegister, BCHP_UARTC_RBR));
1389	}
1390	else
1391	{
1392	*data = (uint8_t)(BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVDATA));
1393	}
1394	#else
1395	*data = (uint8_t)(BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVDATA));
1396	#endif
1397	data++;
1398	loopCnt++;
1399	numBytes--;
1400	}
1401	bytesRead = loopCnt; / actual bytes read */
1402
1403	*rxError = BURT_GetRxError (hChn);
1404	if (*rxError != BURT_RxError_eNoError)
1405	{
1406	retCode = BURT_ERR_RX_ERROR;
1407	goto done;
1408	}
1409
1410	/*
1411	* Re-enable RX interrupt
1412	*/
1413	if ((hChn->intMode) \|\| (hChn->rxIntMode))
1414	BURT_EnableRxInt (hChn, true);
1415
1416	done:
1417	return( retCode );
1418	}
1419
1420	BERR_Code BURT_Write (
1421	BURT_ChannelHandle hChn, /* Device channel handle */
1422	uint8_t data, / pointers to data to send */
1423	uint32_t numBytes /* number of bytes to write */
1424	)
1425	{
1426	BERR_Code retCode = BERR_SUCCESS;
1427	uint32_t fifoAvail, lval;
1428	uint8_t bval;
1429	BURT_Handle hDev;
1430
1431	BDBG_ASSERT( hChn );
1432	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1433
1434	hDev = hChn->hUrt;
1435	if (!numBytes)
1436	goto done;
1437
1438	fifoAvail = BURT_GetAvailTxFifoCnt (hChn);
1439	if (numBytes > fifoAvail)
1440	{
1441	retCode = BURT_ERR_TX_FIFO_NOT_AVAIL;
1442	goto done;
1443	}
1444
1445	while (numBytes--)
1446	{
1447	bval = *data++;
1448	lval = (uint32_t)bval;
1449	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1450	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1451	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1452	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1453	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1454	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1455	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1456	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1457	BREG_Write32 (hDev->hRegister, (hChn->coreOffset + BCHP_UARTA_RBR), lval);
1458	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1459	/* UARTC register definitions are different from UARTA and UARTB.
1460	* Do not use coreOffset for UARTC.
1461	*/
1462	if (hChn->chnNo == 2)
1463	{
1464	BREG_Write32 (hDev->hRegister, BCHP_UARTC_RBR, lval);
1465	}
1466	else
1467	{
1468	BREG_Write32 (hDev->hRegister, (hChn->coreOffset + BCHP_UARTA_XMTDATA), lval);
1469	}
1470	#else
1471	BREG_Write32 (hDev->hRegister, (hChn->coreOffset + BCHP_UARTA_XMTDATA), lval);
1472	#endif
1473	}
1474
1475	/*
1476	* Now that we've stuffed the FIFO, enable the TX int
1477	*/
1478	if ((hChn->intMode) \|\| (hChn->txIntMode))
1479	BURT_EnableTxInt (hChn, true);
1480	done:
1481	return( retCode );
1482	}
1483
1484	BURT_RxError BURT_GetRxError (
1485	BURT_ChannelHandle hChn /* Device channel handle */
1486	)
1487	{
1488	uint32_t lval;
1489	BURT_Handle hDev;
1490	BURT_RxError rxError;
1491
1492	BDBG_ASSERT( hChn );
1493	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1494
1495	hDev = hChn->hUrt;
1496
1497	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1498	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1499	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1500	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1501	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1502	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1503	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1504	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1505	BURT_P_ReadLsr(hChn, &lval);
1506	if( lval & BCHP_UARTA_LSR_OE_MASK )
1507	rxError = BURT_RxError_eReceiverOverRun;
1508	else if( lval & BCHP_UARTA_LSR_FE_MASK )
1509	rxError = BURT_RxError_eReceiverFrameError;
1510	else if( lval & BCHP_UARTA_LSR_PE_MASK )
1511	rxError = BURT_RxError_eReceiverParityError;
1512	else
1513	rxError = BURT_RxError_eNoError;
1514	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1515	/* UARTC register definitions are different from UARTA and UARTB.
1516	* Do not use coreOffset for UARTC.
1517	*/
1518	if (hChn->chnNo == 2)
1519	{
1520	BURT_P_ReadLsr(hChn, &lval);
1521	if( lval & BCHP_UARTC_LSR_OE_MASK )
1522	rxError = BURT_RxError_eReceiverOverRun;
1523	else if( lval & BCHP_UARTC_LSR_FE_MASK )
1524	rxError = BURT_RxError_eReceiverFrameError;
1525	else if( lval & BCHP_UARTC_LSR_PE_MASK )
1526	rxError = BURT_RxError_eReceiverParityError;
1527	else
1528	rxError = BURT_RxError_eNoError;
1529	}
1530	else
1531	{
1532	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1533	if( lval & BCHP_UARTA_RCVSTAT_OVRN_MASK )
1534	rxError = BURT_RxError_eReceiverOverRun;
1535	else if( lval & BCHP_UARTA_RCVSTAT_FE_MASK )
1536	rxError = BURT_RxError_eReceiverFrameError;
1537	else if( lval & BCHP_UARTA_RCVSTAT_PE_MASK )
1538	rxError = BURT_RxError_eReceiverParityError;
1539	else
1540	rxError = BURT_RxError_eNoError;
1541	}
1542	#else
1543	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1544	if( lval & BCHP_UARTA_RCVSTAT_OVRN_MASK )
1545	rxError = BURT_RxError_eReceiverOverRun;
1546	else if( lval & BCHP_UARTA_RCVSTAT_FE_MASK )
1547	rxError = BURT_RxError_eReceiverFrameError;
1548	else if( lval & BCHP_UARTA_RCVSTAT_PE_MASK )
1549	rxError = BURT_RxError_eReceiverParityError;
1550	else
1551	rxError = BURT_RxError_eNoError;
1552	#endif
1553
1554	return rxError;
1555	}
1556
1557
1558	BURT_RxError BURT_GetRxError_Isr (
1559	BURT_ChannelHandle hChn /* Device channel handle */
1560	)
1561	{
1562	uint32_t lval;
1563	BURT_Handle hDev;
1564	BURT_RxError rxError;
1565
1566	BDBG_ASSERT( hChn );
1567	BDBG_ASSERT( hChn->magicId == DEV_MAGIC_ID );
1568
1569	hDev = hChn->hUrt;
1570
1571	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1572	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1573	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1574	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1575	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1576	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1577	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1578	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1579	BURT_P_ReadLsr_Isr(hChn, &lval);
1580	if( lval & BCHP_UARTA_LSR_OE_MASK )
1581	rxError = BURT_RxError_eReceiverOverRun;
1582	else if( lval & BCHP_UARTA_LSR_FE_MASK )
1583	rxError = BURT_RxError_eReceiverFrameError;
1584	else if( lval & BCHP_UARTA_LSR_PE_MASK )
1585	rxError = BURT_RxError_eReceiverParityError;
1586	else
1587	rxError = BURT_RxError_eNoError;
1588	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1589	/* UARTC register definitions are different from UARTA and UARTB.
1590	* Do not use coreOffset for UARTC.
1591	*/
1592	if (hChn->chnNo == 2)
1593	{
1594	lval = BURT_P_ReadLsr_Isr(hChn, 0);
1595	if( lval & BCHP_UARTC_LSR_OE_MASK )
1596	rxError = BURT_RxError_eReceiverOverRun;
1597	else if( lval & BCHP_UARTC_LSR_FE_MASK )
1598	rxError = BURT_RxError_eReceiverFrameError;
1599	else if( lval & BCHP_UARTC_LSR_PE_MASK )
1600	rxError = BURT_RxError_eReceiverParityError;
1601	else
1602	rxError = BURT_RxError_eNoError;
1603	}
1604	else
1605	{
1606	lval = BREG_Read32_isr (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1607	if( lval & BCHP_UARTA_RCVSTAT_OVRN_MASK )
1608	rxError = BURT_RxError_eReceiverOverRun;
1609	else if( lval & BCHP_UARTA_RCVSTAT_FE_MASK )
1610	rxError = BURT_RxError_eReceiverFrameError;
1611	else if( lval & BCHP_UARTA_RCVSTAT_PE_MASK )
1612	rxError = BURT_RxError_eReceiverParityError;
1613	else
1614	rxError = BURT_RxError_eNoError;
1615	}
1616	#else
1617	lval = BREG_Read32_isr (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
1618	if( lval & BCHP_UARTA_RCVSTAT_OVRN_MASK )
1619	rxError = BURT_RxError_eReceiverOverRun;
1620	else if( lval & BCHP_UARTA_RCVSTAT_FE_MASK )
1621	rxError = BURT_RxError_eReceiverFrameError;
1622	else if( lval & BCHP_UARTA_RCVSTAT_PE_MASK )
1623	rxError = BURT_RxError_eReceiverParityError;
1624	else
1625	rxError = BURT_RxError_eNoError;
1626	#endif
1627
1628	return rxError;
1629	}
1630
1631
1632	/*******************************************************************************
1633	*
1634	* Private Module Functions
1635	*
1636	*******************************************************************************/
1637	void BURT_ResetTxRx(
1638	BURT_ChannelHandle hChn /* Device channel handle */
1639	)
1640	{
1641	BURT_Handle hDev;
1642
1643	hDev = hChn->hUrt;
1644
1645	/* reset xmit and rcvr fifo's */
1646	BREG_Write32 (hDev->hRegister, (hChn->coreOffset + BCHP_UARTA_IIR), 7); /* Note: BCHP_UARTA_IIR shares same address as BCHP_UARTA_FCR */
1647	}
1648
1649
1650	void BURT_P_EnableTxRx(
1651	BURT_ChannelHandle hChn, /* Device channel handle */
1652	bool enableTx, /* enable flag for transmitter */
1653	bool enableRx /* enable flag for receiver */
1654	)
1655	{
1656	uint32_t lval;
1657	BURT_Handle hDev;
1658
1659	hDev = hChn->hUrt;
1660
1661	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1662	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1663	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1664	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1665	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1666	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1667	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1668	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1669	BSTD_UNUSED(lval);
1670	BSTD_UNUSED(enableTx);
1671	BSTD_UNUSED(enableRx);
1672
1673	/* Enable fifo, reset xmit and rcvr fifo's */
1674	BREG_Write32 (hDev->hRegister, (hChn->coreOffset + BCHP_UARTA_IIR), 7); /* Note: BCHP_UARTA_IIR shares same address as BCHP_UARTA_FCR */
1675	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1676	/* UARTC register definitions are different from UARTA and UARTB.
1677	* Do not use coreOffset for UARTC.
1678	*/
1679	if (hChn->chnNo == 2)
1680	{
1681	/* Enable fifo, reset xmit and rcvr fifo's */
1682	BREG_Write32 (hDev->hRegister, BCHP_UARTC_IIR, 7); /* Note: BCHP_UARTAC_IIR shares same address as BCHP_UARTC_FCR */
1683	}
1684	else
1685	{
1686	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
1687	if (enableTx)
1688	{
1689	/* Enable TX */
1690	lval \|= BCHP_UARTA_CONTROL_TXE_MASK;
1691	}
1692	else
1693	{
1694	/* Disable TX */
1695	lval &= ~BCHP_UARTA_CONTROL_TXE_MASK;
1696	}
1697	if (enableRx)
1698	{
1699	/* Enable RX */
1700	lval \|= BCHP_UARTA_CONTROL_RXE_MASK;
1701	}
1702	else
1703	{
1704	/* Disable RX */
1705	lval &= ~BCHP_UARTA_CONTROL_RXE_MASK;
1706	}
1707	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
1708	}
1709	#else
1710	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
1711	if (enableTx)
1712	{
1713	/* Enable TX */
1714	lval \|= BCHP_UARTA_CONTROL_TXE_MASK;
1715	}
1716	else
1717	{
1718	/* Disable TX */
1719	lval &= ~BCHP_UARTA_CONTROL_TXE_MASK;
1720	}
1721	if (enableRx)
1722	{
1723	/* Enable RX */
1724	lval \|= BCHP_UARTA_CONTROL_RXE_MASK;
1725	}
1726	else
1727	{
1728	/* Disable RX */
1729	lval &= ~BCHP_UARTA_CONTROL_RXE_MASK;
1730	}
1731	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
1732	#endif
1733	}
1734
1735	void BURT_P_SetBaudRate(
1736	BURT_ChannelHandle hChn, /* Device channel handle */
1737	uint32_t baud
1738	)
1739	{
1740	uint32_t lval, bitRate;
1741	BURT_Handle hDev;
1742
1743	hDev = hChn->hUrt;
1744
1745	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1746	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1747	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1748	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1749	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1750	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1751	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1752	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1753
1754	BSTD_UNUSED(bitRate);
1755
1756	/* Set DLAB bit to write DLL and DLH registers. */
1757	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR);
1758	lval &= ~BCHP_MASK(UARTA_LCR, DLAB);
1759	lval \|= BCHP_FIELD_DATA(UARTA_LCR, DLAB, 1);
1760	BREG_Write32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR, lval);
1761
1762	lval = (uint32_t)(5062500 / baud); /* DLL = 81MHz / (16 * baud) */
1763	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RBR, lval & 0xff); /* Note: BCHP_UARTA_RBR shares same address as BCHP_UARTA_DLL */
1764	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_IER, lval >> 8); /* Note: BCHP_UARTA_IER shares same address as BCHP_UARTA_DLH */
1765
1766	/* Reset DLAB bit. */
1767	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR);
1768	lval &= ~BCHP_MASK(UARTA_LCR, DLAB);
1769	lval \|= BCHP_FIELD_DATA(UARTA_LCR, DLAB, 0);
1770	BREG_Write32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR, lval);
1771	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1772	/* UARTC register definitions are different from UARTA and UARTB.
1773	* Do not use coreOffset for UARTC.
1774	*/
1775	if (hChn->chnNo == 2)
1776	{
1777	/* Set DLAB bit to write DLL and DLH registers. */
1778	lval = BREG_Read32 (hDev->hRegister, BCHP_UARTC_LCR);
1779	lval &= ~BCHP_MASK(UARTC_LCR, DLAB);
1780	lval \|= BCHP_FIELD_DATA(UARTC_LCR, DLAB, 1);
1781	BREG_Write32 (hDev->hRegister, BCHP_UARTC_LCR, lval);
1782
1783	lval = (uint32_t)(5062500 / baud); /* DLL = 81MHz / (16 * baud) */
1784	BREG_Write32(hDev->hRegister, BCHP_UARTC_RBR, lval & 0xff); /* Note: BCHP_UARTC_RBR shares same address as BCHP_UARTC_DLL */
1785	BREG_Write32(hDev->hRegister, BCHP_UARTC_IER, lval >> 8); /* Note: BCHP_UARTC_IER shares same address as BCHP_UARTC_DLH */
1786
1787	/* Reset DLAB bit. */
1788	lval = BREG_Read32 (hDev->hRegister, BCHP_UARTC_LCR);
1789	lval &= ~BCHP_MASK(UARTC_LCR, DLAB);
1790	lval \|= BCHP_FIELD_DATA(UARTC_LCR, DLAB, 0);
1791	BREG_Write32 (hDev->hRegister, BCHP_UARTC_LCR, lval);
1792	}
1793	else
1794	{
1795	bitRate = (uint32_t) BITRATE_TO_BAUDRATE( baud );
1796	lval = bitRate & 0xff;
1797	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_BAUDLO, lval);
1798	lval = (bitRate >> 8) & 0xff;
1799	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_BAUDHI, lval);
1800	}
1801	#else
1802	bitRate = (uint32_t) BITRATE_TO_BAUDRATE( baud );
1803	lval = bitRate & 0xff;
1804	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_BAUDLO, lval);
1805	lval = (bitRate >> 8) & 0xff;
1806	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_BAUDHI, lval);
1807	#endif
1808	}
1809
1810	void BURT_P_SetDataBits(
1811	BURT_ChannelHandle hChn, /* Device channel handle */
1812	BURT_DataBits bits
1813	)
1814	{
1815	uint32_t lval;
1816	BURT_Handle hDev;
1817
1818	hDev = hChn->hUrt;
1819
1820	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1821	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1822	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1823	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1824	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1825	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1826	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1827	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1828	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR);
1829	lval &= ~BCHP_MASK(UARTA_LCR, DLS);
1830	switch(bits)
1831	{
1832	case BURT_DataBits_eDataBits5:
1833	lval \|= BCHP_FIELD_DATA(UARTA_LCR, DLS, 0);
1834	break;
1835	case BURT_DataBits_eDataBits6:
1836	lval \|= BCHP_FIELD_DATA(UARTA_LCR, DLS, 1);
1837	break;
1838	case BURT_DataBits_eDataBits7:
1839	lval \|= BCHP_FIELD_DATA(UARTA_LCR, DLS, 2);
1840	break;
1841	case BURT_DataBits_eDataBits8:
1842	default:
1843	lval \|= BCHP_FIELD_DATA(UARTA_LCR, DLS, 3);
1844	break;
1845	}
1846	BREG_Write32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR, lval);
1847	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1848	/* UARTC register definitions are different from UARTA and UARTB.
1849	* Do not use coreOffset for UARTC.
1850	*/
1851	if (hChn->chnNo == 2)
1852	{
1853	lval = BREG_Read32 (hDev->hRegister, BCHP_UARTC_LCR);
1854	lval &= ~BCHP_MASK(UARTC_LCR, DLS);
1855	switch(bits)
1856	{
1857	case BURT_DataBits_eDataBits5:
1858	lval \|= BCHP_FIELD_DATA(UARTC_LCR, DLS, 0);
1859	break;
1860	case BURT_DataBits_eDataBits6:
1861	lval \|= BCHP_FIELD_DATA(UARTC_LCR, DLS, 1);
1862	break;
1863	case BURT_DataBits_eDataBits7:
1864	lval \|= BCHP_FIELD_DATA(UARTC_LCR, DLS, 2);
1865	break;
1866	case BURT_DataBits_eDataBits8:
1867	default:
1868	lval \|= BCHP_FIELD_DATA(UARTC_LCR, DLS, 3);
1869	break;
1870	}
1871	BREG_Write32 (hDev->hRegister, BCHP_UARTC_LCR, lval);
1872	}
1873	else
1874	{
1875	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
1876	if (bits == BURT_DataBits_eDataBits8)
1877	lval \|= BCHP_UARTA_CONTROL_BITM8_MASK;
1878	else
1879	lval &= ~BCHP_UARTA_CONTROL_BITM8_MASK;
1880	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
1881	}
1882	#else
1883	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
1884	if (bits == BURT_DataBits_eDataBits8)
1885	lval \|= BCHP_UARTA_CONTROL_BITM8_MASK;
1886	else
1887	lval &= ~BCHP_UARTA_CONTROL_BITM8_MASK;
1888	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
1889	#endif
1890	}
1891
1892	void BURT_P_SetParity(
1893	BURT_ChannelHandle hChn, /* Device channel handle */
1894	BURT_Parity parity
1895	)
1896	{
1897	uint32_t lval;
1898	BURT_Handle hDev;
1899
1900	hDev = hChn->hUrt;
1901
1902	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
1903	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
1904	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
1905	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
1906	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
1907	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
1908	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
1909	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
1910	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR);
1911	switch( parity )
1912	{
1913	case BURT_Parity_eNone:
1914	lval &= ~BCHP_MASK(UARTA_LCR, PEN);
1915	lval \|= BCHP_FIELD_DATA(UARTA_LCR, PEN, 0);
1916	break;
1917
1918	case BURT_Parity_eOdd:
1919	lval &= ~(BCHP_MASK(UARTA_LCR, EPS) \|
1920	BCHP_MASK(UARTA_LCR, PEN));
1921	lval \|= BCHP_FIELD_DATA(UARTA_LCR, EPS, 0) \|
1922	BCHP_FIELD_DATA(UARTA_LCR, PEN, 1);
1923	break;
1924
1925	case BURT_Parity_eEven:
1926	lval &= ~(BCHP_MASK(UARTA_LCR, EPS) \|
1927	BCHP_MASK(UARTA_LCR, PEN));
1928	lval \|= BCHP_FIELD_DATA(UARTA_LCR, EPS, 1) \|
1929	BCHP_FIELD_DATA(UARTA_LCR, PEN, 1);
1930	break;
1931	}
1932	BREG_Write32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR, lval);
1933	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
1934	/* UARTC register definitions are different from UARTA and UARTB.
1935	* Do not use coreOffset for UARTC.
1936	*/
1937	if (hChn->chnNo == 2)
1938	{
1939	lval = BREG_Read32 (hDev->hRegister, BCHP_UARTC_LCR);
1940	switch( parity )
1941	{
1942	case BURT_Parity_eNone:
1943	lval &= ~BCHP_MASK(UARTC_LCR, PEN);
1944	lval \|= BCHP_FIELD_DATA(UARTC_LCR, PEN, 0);
1945	break;
1946
1947	case BURT_Parity_eOdd:
1948	lval &= ~(BCHP_MASK(UARTC_LCR, EPS) \|
1949	BCHP_MASK(UARTC_LCR, PEN));
1950	lval \|= BCHP_FIELD_DATA(UARTC_LCR, EPS, 0) \|
1951	BCHP_FIELD_DATA(UARTC_LCR, PEN, 1);
1952	break;
1953
1954	case BURT_Parity_eEven:
1955	lval &= ~(BCHP_MASK(UARTC_LCR, EPS) \|
1956	BCHP_MASK(UARTC_LCR, PEN));
1957	lval \|= BCHP_FIELD_DATA(UARTC_LCR, EPS, 1) \|
1958	BCHP_FIELD_DATA(UARTC_LCR, PEN, 1);
1959	break;
1960	}
1961	BREG_Write32 (hDev->hRegister, BCHP_UARTC_LCR, lval);
1962	}
1963	else
1964	{
1965	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
1966	switch( parity )
1967	{
1968	case BURT_Parity_eNone:
1969	lval &= ~BCHP_UARTA_CONTROL_PAREN_MASK;
1970	break;
1971
1972	case BURT_Parity_eOdd:
1973	lval \|= BCHP_UARTA_CONTROL_PAREN_MASK \| BCHP_UARTA_CONTROL_PODD_MASK;
1974	break;
1975
1976	case BURT_Parity_eEven:
1977	lval \|= BCHP_UARTA_CONTROL_PAREN_MASK;
1978	lval &= ~BCHP_UARTA_CONTROL_PODD_MASK;
1979	break;
1980	}
1981	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
1982	}
1983	#else
1984	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
1985	switch( parity )
1986	{
1987	case BURT_Parity_eNone:
1988	lval &= ~BCHP_UARTA_CONTROL_PAREN_MASK;
1989	break;
1990
1991	case BURT_Parity_eOdd:
1992	lval \|= BCHP_UARTA_CONTROL_PAREN_MASK \| BCHP_UARTA_CONTROL_PODD_MASK;
1993	break;
1994
1995	case BURT_Parity_eEven:
1996	lval \|= BCHP_UARTA_CONTROL_PAREN_MASK;
1997	lval &= ~BCHP_UARTA_CONTROL_PODD_MASK;
1998	break;
1999	}
2000	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
2001	#endif
2002	}
2003
2004	void BURT_P_SetStopBits(
2005	BURT_ChannelHandle hChn, /* Device channel handle */
2006	BURT_StopBits stop_bits
2007	)
2008	{
2009	uint32_t lval;
2010	BURT_Handle hDev;
2011
2012	hDev = hChn->hUrt;
2013
2014	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
2015	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
2016	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
2017	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2018	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
2019	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
2020	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2021	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
2022	lval = BREG_Read32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR);
2023	lval &= ~BCHP_MASK(UARTA_LCR, STOP);
2024	switch(stop_bits)
2025	{
2026	case BURT_StopBits_eOneBit:
2027	lval \|= BCHP_FIELD_DATA(UARTA_LCR, STOP, 0);
2028	break;
2029	case BURT_StopBits_eTwoBit:
2030	lval \|= BCHP_FIELD_DATA(UARTA_LCR, STOP, 1);
2031	break;
2032	default:
2033	lval \|= BCHP_FIELD_DATA(UARTA_LCR, STOP, 0);
2034	break;
2035	}
2036	BREG_Write32 (hDev->hRegister, hChn->coreOffset + BCHP_UARTA_LCR, lval);
2037	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
2038	/* UARTC register definitions are different from UARTA and UARTB.
2039	* Do not use coreOffset for UARTC.
2040	*/
2041	if (hChn->chnNo == 2)
2042	{
2043	lval = BREG_Read32 (hDev->hRegister, BCHP_UARTC_LCR);
2044	lval &= ~BCHP_MASK(UARTC_LCR, STOP);
2045	switch(stop_bits)
2046	{
2047	case BURT_StopBits_eOneBit:
2048	lval \|= BCHP_FIELD_DATA(UARTC_LCR, STOP, 0);
2049	break;
2050	case BURT_StopBits_eTwoBit:
2051	lval \|= BCHP_FIELD_DATA(UARTC_LCR, STOP, 1);
2052	break;
2053	default:
2054	lval \|= BCHP_FIELD_DATA(UARTC_LCR, STOP, 0);
2055	break;
2056	}
2057	BREG_Write32 (hDev->hRegister, BCHP_UARTC_LCR, lval);
2058	}
2059	else
2060	{
2061	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
2062	if (stop_bits == BURT_StopBits_eTwoBit)
2063	lval \|= BCHP_UARTA_CONTROL_STOP2_MASK;
2064	else
2065	lval &= ~BCHP_UARTA_CONTROL_STOP2_MASK;
2066	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
2067	}
2068	#else
2069	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL);
2070	if (stop_bits == BURT_StopBits_eTwoBit)
2071	lval \|= BCHP_UARTA_CONTROL_STOP2_MASK;
2072	else
2073	lval &= ~BCHP_UARTA_CONTROL_STOP2_MASK;
2074	BREG_Write32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_CONTROL, lval);
2075	#endif
2076	}
2077
2078	static void BURT_P_HandleInterrupt_Isr
2079	(
2080	void pParam1, / Device channel handle */
2081	int parm2 /* not used */
2082	)
2083	{
2084	BURT_ChannelHandle hChn;
2085	BURT_Handle hDev;
2086	uint32_t lval;
2087
2088	hChn = (BURT_ChannelHandle) pParam1;
2089	BDBG_ASSERT( hChn );
2090	BSTD_UNUSED( parm2 );
2091
2092	hDev = hChn->hUrt;
2093
2094	/* Check for transmit interrupt */
2095	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
2096	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
2097	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
2098	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2099	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
2100	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
2101	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2102	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
2103	lval = BURT_P_ReadLsr_Isr(hChn, 0);
2104	if (lval & BCHP_UARTA_LSR_TEMT_MASK)
2105	{
2106	BURT_EnableTxInt (hChn, false); /* turn off TX interrupt */
2107	#ifndef USE_BURT_INT_CALLBACK
2108	BKNI_SetEvent( hChn->hChnTxEvent );
2109	#else
2110	if(hChn->intCallbackFunc == NULL)
2111	{
2112	BKNI_SetEvent( hChn->hChnTxEvent );
2113	}
2114	else
2115	{
2116	hChn->intCallbackFunc(pParam1,1); /* tx interrupt callback */
2117	}
2118	#endif
2119	}
2120	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
2121	/* UARTC register definitions are different from UARTA and UARTB.
2122	* Do not use coreOffset for UARTC.
2123	*/
2124	if (hChn->chnNo == 2)
2125	{
2126	lval = BURT_P_ReadLsr_Isr(hChn, 0);
2127	if (lval & BCHP_UARTC_LSR_TEMT_MASK)
2128	{
2129	BURT_EnableTxInt (hChn, false); /* turn off TX interrupt */
2130	#ifndef USE_BURT_INT_CALLBACK
2131	BKNI_SetEvent( hChn->hChnTxEvent );
2132	#else
2133	if(hChn->intCallbackFunc == NULL)
2134	{
2135	BKNI_SetEvent( hChn->hChnTxEvent );
2136	}
2137	else
2138	{
2139	hChn->intCallbackFunc(pParam1,1); /* tx interrupt callback */
2140	}
2141	#endif
2142	}
2143	}
2144	else
2145	{
2146	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
2147	if (lval & BCHP_UARTA_XMTSTAT_TDRE_MASK)
2148	{
2149	BURT_EnableTxInt (hChn, false); /* turn off TX interrupt */
2150	#ifndef USE_BURT_INT_CALLBACK
2151	BKNI_SetEvent( hChn->hChnTxEvent );
2152	#else
2153	if(hChn->intCallbackFunc == NULL)
2154	{
2155	BKNI_SetEvent( hChn->hChnTxEvent );
2156	}
2157	else
2158	{
2159	hChn->intCallbackFunc(pParam1,1); /* tx interrupt callback */
2160	}
2161	#endif
2162	}
2163	}
2164	#else
2165	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_XMTSTAT);
2166	if (lval & BCHP_UARTA_XMTSTAT_TDRE_MASK)
2167	{
2168	BURT_EnableTxInt (hChn, false); /* turn off TX interrupt */
2169	#ifndef USE_BURT_INT_CALLBACK
2170	BKNI_SetEvent( hChn->hChnTxEvent );
2171	#else
2172	if(hChn->intCallbackFunc == NULL)
2173	{
2174	BKNI_SetEvent( hChn->hChnTxEvent );
2175	}
2176	else
2177	{
2178	hChn->intCallbackFunc(pParam1,1); /* tx interrupt callback */
2179	}
2180	#endif
2181	}
2182	#endif
2183
2184	/* Check for receive interrupt */
2185	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
2186	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
2187	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
2188	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2189	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
2190	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
2191	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2192	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
2193	lval = BURT_P_ReadLsr_Isr(hChn, 0);
2194	if (lval & BCHP_UARTA_LSR_DR_MASK)
2195	{
2196	BURT_EnableRxInt (hChn, false); /* turn off RX interrupt */
2197	#ifndef USE_BURT_INT_CALLBACK
2198	BKNI_SetEvent( hChn->hChnRxEvent );
2199	#else
2200	if(hChn->intCallbackFunc == NULL)
2201	{
2202	BKNI_SetEvent( hChn->hChnRxEvent );
2203	}
2204	else
2205	{
2206	hChn->intCallbackFunc(pParam1,0); /* rx interrupt callback */
2207	}
2208	#endif
2209	}
2210	#elif (BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403)
2211	/* UARTC register definitions are different from UARTA and UARTB.
2212	* Do not use coreOffset for UARTC.
2213	*/
2214	if (hChn->chnNo == 2)
2215	{
2216	lval = BURT_P_ReadLsr_Isr(hChn, 0);
2217	if (lval & BCHP_UARTC_LSR_DR_MASK)
2218	{
2219	BURT_EnableRxInt (hChn, false); /* turn off RX interrupt */
2220	#ifndef USE_BURT_INT_CALLBACK
2221	BKNI_SetEvent( hChn->hChnRxEvent );
2222	#else
2223	if(hChn->intCallbackFunc == NULL)
2224	{
2225	BKNI_SetEvent( hChn->hChnRxEvent );
2226	}
2227	else
2228	{
2229	hChn->intCallbackFunc(pParam1,0); /* rx interrupt callback */
2230	}
2231	#endif
2232	}
2233	}
2234	else
2235	{
2236	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
2237	if (lval & BCHP_UARTA_RCVSTAT_RDA_MASK)
2238	{
2239	BURT_EnableRxInt (hChn, false); /* turn off RX interrupt */
2240	#ifndef USE_BURT_INT_CALLBACK
2241	BKNI_SetEvent( hChn->hChnRxEvent );
2242	#else
2243	if(hChn->intCallbackFunc == NULL)
2244	{
2245	BKNI_SetEvent( hChn->hChnRxEvent );
2246	}
2247	else
2248	{
2249	hChn->intCallbackFunc(pParam1,0); /* rx interrupt callback */
2250	}
2251	#endif
2252	}
2253	}
2254	#else
2255	lval = BREG_Read32(hDev->hRegister, hChn->coreOffset + BCHP_UARTA_RCVSTAT);
2256	if (lval & BCHP_UARTA_RCVSTAT_RDA_MASK)
2257	{
2258	BURT_EnableRxInt (hChn, false); /* turn off RX interrupt */
2259	#ifndef USE_BURT_INT_CALLBACK
2260	BKNI_SetEvent( hChn->hChnRxEvent );
2261	#else
2262	if(hChn->intCallbackFunc == NULL)
2263	{
2264	BKNI_SetEvent( hChn->hChnRxEvent );
2265	}
2266	else
2267	{
2268	hChn->intCallbackFunc(pParam1,0); /* rx interrupt callback */
2269	}
2270	#endif
2271	}
2272	#endif
2273
2274	return;
2275	}
2276
2277	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7440) \|\| \
2278	(BCHP_CHIP==7405) \|\| (BCHP_CHIP==7550) \|\| (BCHP_CHIP==7118) \|\| \
2279	(BCHP_CHIP==7401 && BCHP_VER >= BCHP_VER_B0) \|\| (BCHP_CHIP==7403) \|\| \
2280	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
2281	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2282	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
2283	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
2284	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2285	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
2286	void BURT_P_EnableFifo(
2287	BURT_ChannelHandle hChn /* Device channel handle */
2288	)
2289	{
2290	uint32_t fcraddr;
2291	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
2292	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7440) \|\| (BCHP_CHIP==7118) \|\| \
2293	(BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| (BCHP_CHIP==7342) \|\| \
2294	(BCHP_CHIP==7340) \|\| (BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2295	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
2296	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
2297	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2298	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
2299	fcraddr = hChn->coreOffset + BCHP_UARTA_FCR;
2300	BREG_Write32(hChn->hUrt->hRegister, fcraddr,
2301	BCHP_FIELD_DATA(UARTA_FCR, RT, 0) /* first character */
2302	\| BCHP_FIELD_DATA(UARTA_FCR, TET, 0) /* empty */
2303	\| BCHP_FIELD_DATA(UARTA_FCR, FIFOE, 1) /* enable */
2304	);
2305	#else
2306	/* This is for 7401. UARTA and UARTB uses different UARTS than UARTC. */
2307	if (hChn->chnNo != 2) {
2308	return;
2309	}
2310	/* Since UARTC register definitions are different from UARTA and UARTB,
2311	* do not use coreOffset for UARTC.
2312	*/
2313	fcraddr = BCHP_UARTC_FCR;
2314	BREG_Write32(hChn->hUrt->hRegister, fcraddr,
2315	BCHP_FIELD_DATA(UARTC_FCR, RT, 0) /* first character */
2316	\| BCHP_FIELD_DATA(UARTC_FCR, TET, 0) /* empty */
2317	\| BCHP_FIELD_DATA(UARTC_FCR, FIFOE, 1) /* enable */
2318	);
2319	#endif
2320	}
2321	static uint32_t
2322	BURT_P_ReadLsr_Isr(
2323	BURT_ChannelHandle hChn,
2324	uint32_t *pErrLsr
2325	)
2326	{
2327	uint32_t lsraddr;
2328	uint32_t lval;
2329
2330	#if (BCHP_CHIP==7400) \|\| (BCHP_CHIP==7420) \|\| (BCHP_CHIP==7405) \|\| \
2331	(BCHP_CHIP==7550) \|\| (BCHP_CHIP==7325) \|\| (BCHP_CHIP==7335) \|\| \
2332	(BCHP_CHIP==7342) \|\| (BCHP_CHIP==7340) \|\| (BCHP_CHIP==7440) \|\| \
2333	(BCHP_CHIP==7601) \|\| (BCHP_CHIP==7635) \|\| (BCHP_CHIP==7630) \|\| \
2334	(BCHP_CHIP==7125) \|\| (BCHP_CHIP==7408) \|\| (BCHP_CHIP==7468) \|\| \
2335	(BCHP_CHIP==7422) \|\| (BCHP_CHIP==7425) \|\| (BCHP_CHIP==7429) \|\| (BCHP_CHIP==7640) \|\| \
2336	(BCHP_CHIP==7344) \|\| (BCHP_CHIP==7346) \|\| (BCHP_CHIP==7358) \|\| \
2337	(BCHP_CHIP==7552) \|\| (BCHP_CHIP==7231)
2338	lsraddr = hChn->coreOffset + BCHP_UARTA_LSR;
2339	#else
2340	if (hChn->chnNo != 2) {
2341	return 0;
2342	}
2343	/* UARTC register definitions are different from UARTA and UARTB.
2344	* Do not use coreOffset for UARTC.
2345	*/
2346	lsraddr = BCHP_UARTC_LSR;
2347	#endif
2348	lval = BREG_Read32(hChn->hUrt->hRegister, lsraddr);
2349	hChn->savedLsr \|= lval;
2350	if (pErrLsr) {
2351	*pErrLsr = hChn->savedLsr;
2352	hChn->savedLsr = 0;
2353	}
2354	return lval;
2355	}
2356
2357	static uint32_t
2358	BURT_P_ReadLsr(
2359	BURT_ChannelHandle hChn,
2360	uint32_t *pErrLsr
2361	)
2362	{
2363	uint32_t lval;
2364	BKNI_EnterCriticalSection();
2365	lval = BURT_P_ReadLsr_Isr(hChn, pErrLsr);
2366	BKNI_LeaveCriticalSection();
2367	return lval;
2368	}
2369
2370	#endif
2371
2372	/* End of file */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/urt/7552/burt.c

Download in other formats: