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bvbi_gse.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_gse.c $
11	* $brcm_Revision: Hydra_Software_Devel/19 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_gse.c $
19	*
20	* Hydra_Software_Devel/19 2/20/12 2:53p darnstein
21	* SW7425-2434: more detail in error messages.
22	*
23	* Hydra_Software_Devel/18 2/20/12 12:55p darnstein
24	* SW7425-2434: when an unsupported video format is entered, the BDBG
25	* error message should be informative.
26	*
27	* Hydra_Software_Devel/17 10/28/11 2:39p darnstein
28	* SW7435-14: port to 7435. Same software behavior as for 7425.
29	*
30	* Hydra_Software_Devel/16 9/9/11 7:12p darnstein
31	* SW7429-15: trivial adaptation to 7429 chipset.
32	*
33	* Hydra_Software_Devel/15 4/4/11 4:20p darnstein
34	* SWBLURAY-23702: add support for 7640 chipset.
35	*
36	* Hydra_Software_Devel/14 11/30/10 2:28p darnstein
37	* SW7231-22: support 7231 chipset in same way as 7344 and 7346.
38	*
39	* Hydra_Software_Devel/13 11/23/10 1:55p darnstein
40	* SW7552-15: port to 7552 chipset. Same code as for 7358.
41	*
42	* Hydra_Software_Devel/12 11/11/10 5:19p darnstein
43	* SW7344-8: first cut at porting BVBI to 7344.
44	*
45	* Hydra_Software_Devel/11 10/12/10 6:38p darnstein
46	* SW7358-16: initial port to 7358-A0.
47	*
48	* Hydra_Software_Devel/10 9/29/10 11:32a vanessah
49	* SW7425-32: more for auto-test
50	*
51	* Hydra_Software_Devel/9 7/15/10 7:00p darnstein
52	* SW7422-46: very simple updates for 7422 compatibility.
53	*
54	* Hydra_Software_Devel/8 4/22/10 1:46p darnstein
55	* SW7468-24: previous check-in applied to 7420 as well.
56	*
57	* Hydra_Software_Devel/7 4/1/10 3:57p darnstein
58	* SW7468-24: previous check-in applied to 7408 chipset as well.
59	*
60	* Hydra_Software_Devel/6 4/1/10 3:42p darnstein
61	* SW7468-24: the name of a register bitfield is changing. One chip at a
62	* time, apparently.
63	*
64	* Hydra_Software_Devel/5 11/20/09 5:34p darnstein
65	* SW7468-24: correct error type for non-existent hardware feature.
66	*
67	* Hydra_Software_Devel/4 11/20/09 3:43p darnstein
68	* SW7468-24: If chipset cannot do TVG2x output, then flag error if user
69	* asks for it.
70	*
71	* Hydra_Software_Devel/3 11/18/09 3:51p darnstein
72	* SW7468-24: Gemstar options now placed in dedicated data structure.
73	*
74	* Hydra_Software_Devel/2 12/4/08 6:06p darnstein
75	* PR45819: 7420 software will now compile, but not link.
76	*
77	* Hydra_Software_Devel/1 12/3/08 8:02p darnstein
78	* PR45819:
79	*
80	***************************************************************************/
81
82	#include "bstd.h" /* standard types */
83	#include "bdbg.h" /* Dbglib */
84	#include "bkni.h" /* For critical sections */
85	#include "bvbi.h" /* VBI processing, this module. */
86	#include "bvbi_priv.h" /* VBI internal data structures */
87	#if (BVBI_P_NUM_GSE >= 1)
88	#include "bchp_gse_0.h" /* RDB info for primary Gemstar encoder core */
89	#endif
90	#if (BVBI_P_NUM_GSE >= 2)
91	#include "bchp_gse_1.h" /* RDB info for secondary Gemstar encoder core */
92	#endif
93	#if (BVBI_P_NUM_GSE >= 3)
94	#include "bchp_gse_2.h" /* RDB info for tertiary Gemstar encoder core */
95	#endif
96	#if (BVBI_P_NUM_GSE_656 >= 1)
97	#include "bchp_gse_ancil_0.h" /* RDB info for bypass Gemstar encoder core */
98	#endif
99
100
101	BDBG_MODULE(BVBI);
102
103	/* The hardware engineers are changing a typo. It is going to be a bit messy
104	* getting this correct for every single chip */
105	#if (BCHP_CHIP != 7468) && (BCHP_CHIP != 7408) && (BCHP_CHIP != 7420) && \
106	(BCHP_CHIP != 7422) && (BCHP_CHIP != 7425) && (BCHP_CHIP != 7435) && \
107	(BCHP_CHIP != 7344) && (BCHP_CHIP != 7346) && (BCHP_CHIP != 7231) && \
108	(BCHP_CHIP != 7429) && (BCHP_CHIP != 7358) && (BCHP_CHIP != 7552) && \
109	(BCHP_CHIP != 7640)
110	#define BCHP_GSE_0_CONTROL_WAVE_MODE_TVG2X_CEA2020 \
111	BCHP_GSE_0_CONTROL_WAVE_MODE_TVGX2_CEA2020
112	#endif
113
114
115	/***************************************************************************
116	* Forward declarations of static (private) functions
117	***************************************************************************/
118
119	#if (BVBI_P_NUM_GSE >= 1)
120	static void BVBI_P_ProgramNull (
121	BREG_Handle hReg, uint32_t coreOffset,
122	uint32_t ulWritePointer, uint32_t value);
123	static uint32_t P_GetCoreOffset (bool is656, uint8_t hwCoreIndex);
124	#endif
125
126
127	/***************************************************************************
128	* Implementation of supporting GS functions that are not in API
129	***************************************************************************/
130
131	#if (BVBI_P_NUM_GSE >= 1) / { /
132	/***************************************************************************
133	*
134	*/
135	void BVBI_P_GS_Enc_Init (BREG_Handle hReg, bool is656, uint8_t hwCoreIndex)
136	{
137	BDBG_ENTER(BVBI_P_GS_Enc_Init);
138
139	BVBI_P_VIE_SoftReset (hReg, is656, hwCoreIndex, BVBI_P_SELECT_GS);
140
141	BDBG_LEAVE(BVBI_P_GS_Enc_Init);
142	}
143	#endif / } BVBI_P_NUM_GSE /
144
145	BERR_Code BVBI_P_GS_Enc_Program (
146	BREG_Handle hReg,
147	bool is656,
148	uint8_t hwCoreIndex,
149	bool bActive,
150	BFMT_VideoFmt eVideoFormat,
151	BVBI_GSOptions* gsOptions)
152	{
153	/*
154	Programming note: the implementation here assumes that the bitfield layout
155	within registers is the same for all GS encoder cores in the chip.
156
157	If a chip is built that has multiple GS encoder cores that are not
158	identical, then this routine will have to be redesigned.
159	*/
160	#if (BVBI_P_NUM_GSE >= 1) / { /
161
162	uint32_t ulCoreOffset;
163	uint32_t ulGse_controlReg;
164	#if defined(BVBI_P_GSE_VER2)
165	uint32_t waveform = (
166	gsOptions->bTvg2x ?
167	BCHP_GSE_0_CONTROL_WAVE_MODE_TVG2X_CEA2020 :
168	BCHP_GSE_0_CONTROL_WAVE_MODE_GEMSTAR);
169	#endif
170
171	BDBG_ENTER(BVBI_P_GS_Enc_Program);
172
173	/* Figure out which encoder core to use */
174	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
175	if (ulCoreOffset == 0xFFFFFFFF)
176	{
177	/* This should never happen! This parameter was checked by
178	BVBI_Encode_Create() */
179	BDBG_LEAVE(BVBI_P_GS_Enc_Program);
180	return BERR_TRACE(BERR_INVALID_PARAMETER);
181	}
182
183	/* Complain if video format is not supported */
184	switch (eVideoFormat)
185	{
186	case BFMT_VideoFmt_eNTSC:
187	case BFMT_VideoFmt_eNTSC_J:
188	break;
189
190	default:
191	if (bActive)
192	{
193	BDBG_ERR(("BVBI_GSE: video format %d not supported", eVideoFormat));
194	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
195	}
196	}
197	#if !defined(BVBI_P_GSE_VER2)
198	if (gsOptions->bTvg2x)
199	{
200	if (bActive)
201	return BERR_TRACE (BVBI_ERR_HW_UNSUPPORTED);
202	}
203	#endif
204
205	ulGse_controlReg = 0;
206	ulGse_controlReg \|= (
207	BCHP_FIELD_DATA (GSE_0_ACTIVE_LINE_TOP, ACTIVE_LINE,
208	gsOptions->linemask_top) \|
209	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_TOP, PED_LINE5, DISABLE) \|
210	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_TOP, PED_LINE4, DISABLE) \|
211	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_TOP, PED_LINE3, DISABLE) \|
212	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_TOP, PED_LINE2, DISABLE) \|
213	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_TOP, PED_LINE1, DISABLE) \|
214	BCHP_FIELD_DATA (GSE_0_ACTIVE_LINE_TOP, BASE,
215	gsOptions->baseline_top)
216	);
217	BREG_Write32 (
218	hReg, BCHP_GSE_0_ACTIVE_LINE_TOP + ulCoreOffset, ulGse_controlReg);
219
220	ulGse_controlReg = 0;
221	ulGse_controlReg \|= (
222	BCHP_FIELD_DATA (GSE_0_ACTIVE_LINE_BOT, ACTIVE_LINE,
223	gsOptions->linemask_bot) \|
224	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_BOT, PED_LINE5, DISABLE) \|
225	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_BOT, PED_LINE4, DISABLE) \|
226	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_BOT, PED_LINE3, DISABLE) \|
227	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_BOT, PED_LINE2, DISABLE) \|
228	BCHP_FIELD_ENUM (GSE_0_ACTIVE_LINE_BOT, PED_LINE1, DISABLE) \|
229	BCHP_FIELD_DATA (GSE_0_ACTIVE_LINE_BOT, BASE,
230	gsOptions->baseline_bot - 256)
231	);
232	BREG_Write32 (
233	hReg, BCHP_GSE_0_ACTIVE_LINE_BOT + ulCoreOffset, ulGse_controlReg);
234
235	ulGse_controlReg = 0;
236	ulGse_controlReg \|= (
237	BCHP_FIELD_DATA (GSE_0_GAIN_TOP, LINE4, 0x48) \|
238	BCHP_FIELD_DATA (GSE_0_GAIN_TOP, LINE3, 0x48) \|
239	BCHP_FIELD_DATA (GSE_0_GAIN_TOP, LINE2, 0x48) \|
240	BCHP_FIELD_DATA (GSE_0_GAIN_TOP, LINE1, 0x48)
241	);
242	BREG_Write32 (
243	hReg, BCHP_GSE_0_GAIN_TOP + ulCoreOffset, ulGse_controlReg);
244
245	ulGse_controlReg = 0;
246	ulGse_controlReg \|=
247	BCHP_FIELD_DATA (GSE_0_GAIN_EXT_TOP, LINE5, 70);
248	BREG_Write32 (
249	hReg, BCHP_GSE_0_GAIN_EXT_TOP + ulCoreOffset, ulGse_controlReg);
250
251	ulGse_controlReg = 0;
252	ulGse_controlReg \|= (
253	BCHP_FIELD_DATA (GSE_0_GAIN_BOT, LINE4, 70) \|
254	BCHP_FIELD_DATA (GSE_0_GAIN_BOT, LINE3, 70) \|
255	BCHP_FIELD_DATA (GSE_0_GAIN_BOT, LINE2, 70) \|
256	BCHP_FIELD_DATA (GSE_0_GAIN_BOT, LINE1, 70)
257	);
258	BREG_Write32 (
259	hReg, BCHP_GSE_0_GAIN_BOT + ulCoreOffset, ulGse_controlReg);
260
261	ulGse_controlReg = 0;
262	ulGse_controlReg \|=
263	BCHP_FIELD_DATA (GSE_0_GAIN_EXT_BOT, LINE5, 70);
264	BREG_Write32 (
265	hReg, BCHP_GSE_0_GAIN_EXT_BOT + ulCoreOffset, ulGse_controlReg);
266
267	ulGse_controlReg = 0;
268	ulGse_controlReg \|= (
269	BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK3, 0) \|
270	BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK2, 0) \|
271	BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK1, 0) \|
272	BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK0, 0) \|
273	BCHP_FIELD_DATA (GSE_0_NULL, CHARACTER, 0x20)
274	);
275	BREG_Write32 (hReg, BCHP_GSE_0_NULL + ulCoreOffset, ulGse_controlReg);
276
277	ulGse_controlReg = 0;
278	ulGse_controlReg \|= (
279	BCHP_FIELD_DATA (GSE_0_CONTROL, FIFO_FREEZE, 0) \|
280	BCHP_FIELD_DATA (GSE_0_CONTROL, NULL_MODE, 1) \|
281	BCHP_FIELD_ENUM (GSE_0_CONTROL, BIT_WIDTH, NTSC) \|
282	BCHP_FIELD_DATA (GSE_0_CONTROL, DELAY_COUNT, 0x42) \|
283	BCHP_FIELD_ENUM (GSE_0_CONTROL, PARITY_TYPE, EVEN) \|
284	BCHP_FIELD_ENUM (GSE_0_CONTROL, TOP_FLD_PARITY, AUTOMATIC) \|
285	BCHP_FIELD_ENUM (GSE_0_CONTROL, BOT_FLD_PARITY, AUTOMATIC) \|
286	BCHP_FIELD_ENUM (GSE_0_CONTROL, BYTE_SWAP_656_ANCIL,
287	LITTLE_ENDIAN) \|
288	BCHP_FIELD_ENUM (GSE_0_CONTROL, BYTE_SWAP_VIDEO_SAMPLE,
289	LITTLE_ENDIAN) \|
290	BCHP_FIELD_ENUM (GSE_0_CONTROL, SHIFT_DIRECTION, LSB2MSB)
291	);
292	if (bActive)
293	{
294	ulGse_controlReg \|= (
295	#if defined(BVBI_P_GSE_VER2)
296	BCHP_FIELD_DATA (GSE_0_CONTROL, WAVE_MODE, waveform) \|
297	#endif
298	BCHP_FIELD_ENUM (GSE_0_CONTROL, ENABLE, ENABLED) );
299	}
300	else
301	{
302	ulGse_controlReg \|=
303	BCHP_FIELD_ENUM (GSE_0_CONTROL, ENABLE, DISABLED);
304	}
305	BREG_Write32 (hReg, BCHP_GSE_0_CONTROL + ulCoreOffset, ulGse_controlReg);
306
307	BDBG_LEAVE(BVBI_P_GS_Enc_Program);
308	return BERR_SUCCESS;
309
310	#else / } ! BVBI_P_NUM_GSE { /
311
312	BSTD_UNUSED (hReg);
313	BSTD_UNUSED (is656);
314	BSTD_UNUSED (hwCoreIndex);
315	BSTD_UNUSED (bActive);
316	BSTD_UNUSED (eVideoFormat);
317	BSTD_UNUSED (gsOptions);
318
319	return BERR_TRACE (BVBI_ERR_HW_UNSUPPORTED);
320
321	#endif / } BVBI_P_NUM_GSE /
322	}
323
324	uint32_t BVBI_P_GS_Encode_Data_isr (
325	BREG_Handle hReg,
326	bool is656,
327	uint8_t hwCoreIndex,
328	BFMT_VideoFmt eVideoFormat,
329	BAVC_Polarity polarity,
330	BVBI_GSData* pGSData)
331	{
332	#if (BVBI_P_NUM_GSE >= 1) / { /
333
334	uint32_t ulCoreOffset;
335	uint32_t ulRegVal;
336	uint32_t ulRegAddr;
337	uint32_t ulReadPointer;
338	uint32_t ulWritePointer;
339	unsigned int iiLine;
340	unsigned int iLine;
341	unsigned int jLine;
342	unsigned int jjLine;
343	uint32_t lineIndex;
344	uint32_t bankIndex;
345	uint32_t hwActiveLine;
346	uint32_t hwBase;
347	uint32_t baseAdj;
348
349	/* Debug code
350	uint32_t dread_pointer[2];
351	uint32_t dwrite_pointer[2];
352	uint32_t status;
353	*/
354
355	BDBG_ENTER(BVBI_P_GS_Encode_Data_isr);
356
357	/* Size check for field data */
358	if (!pGSData)
359	{
360	return (BVBI_LINE_ERROR_FLDH_CONFLICT);
361	}
362
363	/* Refuse service for data with known errors */
364	if (pGSData->ulErrorLines != 0x0)
365	{
366	return (BVBI_LINE_ERROR_FLDH_CONFLICT);
367	}
368
369	/* Figure out which encoder core to use */
370	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
371	if (ulCoreOffset == 0xFFFFFFFF)
372	{
373	/* This should never happen! This parameter was checked by
374	BVBI_Encode_Create() */
375	BDBG_LEAVE(BVBI_P_GS_Encode_Data_isr);
376	return BERR_TRACE(BERR_INVALID_PARAMETER);
377	}
378
379	/* Complain if video format is not supported */
380	switch (eVideoFormat)
381	{
382	case BFMT_VideoFmt_eNTSC:
383	case BFMT_VideoFmt_eNTSC_J:
384	break;
385
386	default:
387	/* Should not happen */
388	BDBG_ERR(("BVBI_GSE: video format %d not supported", eVideoFormat));
389	return (-1);
390	}
391
392	/* Retrieve GSE configuration */
393	if (polarity == BAVC_Polarity_eTopField)
394	{
395	ulRegAddr = BCHP_GSE_0_ACTIVE_LINE_TOP;
396	baseAdj = 0;
397	}
398	else
399	{
400	ulRegAddr = BCHP_GSE_0_ACTIVE_LINE_BOT;
401	baseAdj = 7;
402	}
403	ulRegAddr += ulCoreOffset;
404	ulRegVal = BREG_Read32 (hReg, ulRegAddr);
405	hwActiveLine =
406	BCHP_GET_FIELD_DATA (ulRegVal, GSE_0_ACTIVE_LINE_TOP, ACTIVE_LINE);
407	hwBase =
408	BCHP_GET_FIELD_DATA (ulRegVal, GSE_0_ACTIVE_LINE_TOP, BASE);
409	hwBase -= baseAdj;
410
411	/* Refuse service if any of the user's data is inconsistent with current
412	* settings */
413	for (iLine = 0 ; iLine < 32 ; ++iLine)
414	{
415	if (pGSData->ulDataLines & (1 << iLine))
416	{
417	/* Equivalent hardware line */
418	if (
419	(iLine < hwBase) \|\|
420	!((hwActiveLine & (1 << (iLine - hwBase))))
421	)
422	{
423	return (BVBI_LINE_ERROR_FLDH_CONFLICT);
424	}
425	}
426	}
427
428	/* Clear status bits */
429	ulRegVal = BREG_Read32 (hReg, BCHP_GSE_0_STATUS + ulCoreOffset);
430	/* Debug code
431	status = ulRegVal;
432	*/
433	ulRegVal &= 0x000003FF;
434	BREG_Write32 (hReg, BCHP_GSE_0_STATUS + ulCoreOffset, ulRegVal);
435	/* TODO: Check GSE_0_STATUS register? */
436
437	/* Get FIFO pointers */
438	ulRegVal = BREG_Read32 (hReg, BCHP_GSE_0_WRPTR + ulCoreOffset);
439	ulWritePointer = BCHP_GET_FIELD_DATA (ulRegVal, GSE_0_WRPTR, VALUE);
440	bankIndex = ulWritePointer & 0x00000003;
441	ulRegVal = BREG_Read32 (hReg, BCHP_GSE_0_RDPTR + ulCoreOffset);
442	ulReadPointer = BCHP_GET_FIELD_DATA (ulRegVal, GSE_0_RDPTR, VALUE);
443
444	/* Debug code
445	dread_pointer[0] = ulReadPointer;
446	dwrite_pointer[0] = ulWritePointer;
447	*/
448
449	/* Check for FIFO full */
450	if (((ulReadPointer & 0x3) == bankIndex ) &&
451	(ulReadPointer != ulWritePointer) )
452	{
453	/* Debug code
454	printf ("\n * Gemstar FIFO full!!! *\n\n");
455	*/
456	return BVBI_LINE_ERROR_GEMSTAR_OVERRUN;
457	}
458
459	/* Handle field misalignment */
460	if (
461	((bankIndex == 0) \|\| (bankIndex == 2)) &&
462	(polarity != BAVC_Polarity_eTopField)
463	)
464	{
465	BVBI_P_ProgramNull (hReg, ulCoreOffset, bankIndex, 1);
466	++ulWritePointer;
467	}
468	else if (
469	((bankIndex == 1) \|\| (bankIndex == 3)) &&
470	(polarity != BAVC_Polarity_eBotField)
471	)
472	{
473	BVBI_P_ProgramNull (hReg, ulCoreOffset, bankIndex, 1);
474	++ulWritePointer;
475	}
476	else
477	{
478	BVBI_P_ProgramNull (hReg, ulCoreOffset, bankIndex, 0);
479	}
480
481	/* Now write the user's data */
482	/* Programming note:
483	* iLine and jLine apply to user's data.
484	* iiLine and jjLine apply to hardware registers
485	*/
486	jjLine = 0;
487	jLine = 0;
488	iiLine = 0;
489	iLine = 0;
490	/* Loop over user data */
491	for ( ; iLine < 32 ; ++iLine)
492	{
493	if (pGSData->ulDataLines & (1 << iLine))
494	{
495	/* Loop over hardware configuration bits */
496	for ( ; iiLine < iLine ; ++iiLine)
497	{
498	if ((hwActiveLine & (1 << (iiLine - hwBase))))
499	++jjLine;
500	}
501	lineIndex = jjLine;
502	ulRegAddr =
503	BCHP_GSE_0_DATA_LINE1_BANK0 + ulCoreOffset +
504	(20 * bankIndex) +
505	( 4 * lineIndex);
506	BREG_Write32 (hReg, ulRegAddr, pGSData->ulData[jLine]);
507	++jLine;
508	}
509	}
510
511	/* Program the write pointer into hardware */
512	++ulWritePointer;
513	ulRegVal = BCHP_FIELD_DATA (GSE_0_WRPTR, VALUE, ulWritePointer);
514	BREG_Write32 (hReg, BCHP_GSE_0_WRPTR + ulCoreOffset, ulRegVal);
515
516	/* Debug code
517	ulRegVal = BREG_Read32 (hReg, BCHP_GSE_0_WRPTR + ulCoreOffset);
518	ulWritePointer = BCHP_GET_FIELD_DATA (ulRegVal, GSE_0_WRPTR, VALUE);
519	dwrite_pointer[1] = ulWritePointer;
520	ulRegVal = BREG_Read32 (hReg, BCHP_GSE_0_RDPTR + ulCoreOffset);
521	dread_pointer[1] = BCHP_GET_FIELD_DATA (ulRegVal, GSE_0_RDPTR, VALUE);
522	printf (
523	"Field %c: status: %03x R/W (%d/%d) --> (%d/%d) data (%08x %08x %08x)\n",
524	((polarity == BAVC_Polarity_eTopField) ? 'T' : 'B'),
525	status,
526	dread_pointer[0], dwrite_pointer[0],
527	dread_pointer[1], dwrite_pointer[1],
528	pGSData->ulData[0], pGSData->ulData[1], pGSData->ulData[2]);
529	*/
530
531	BDBG_LEAVE(BVBI_P_GS_Encode_Data_isr);
532	return 0x0;
533
534	#else / } BVBI_P_NUM_GSE { /
535
536	BSTD_UNUSED (hReg);
537	BSTD_UNUSED (is656);
538	BSTD_UNUSED (hwCoreIndex);
539	BSTD_UNUSED (eVideoFormat);
540	BSTD_UNUSED (polarity);
541	BSTD_UNUSED (pGSData);
542
543	return (-1);
544
545	#endif / } BVBI_P_NUM_GSE /
546	}
547
548	/***************************************************************************
549	*
550	*/
551	BERR_Code BVBI_P_GS_Encode_Enable_isr (
552	BREG_Handle hReg,
553	bool is656,
554	uint8_t hwCoreIndex,
555	BFMT_VideoFmt eVideoFormat,
556	bool bEnable)
557	{
558	#if (BVBI_P_NUM_GSE >= 1) / { /
559
560	uint32_t ulCoreOffset;
561	uint32_t ulGse_controlReg;
562
563	BSTD_UNUSED (eVideoFormat);
564
565	BDBG_ENTER(BVBI_P_GS_Encode_Enable_isr);
566
567	/* Figure out which encoder core to use */
568	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
569	if (ulCoreOffset == 0xFFFFFFFF)
570	{
571	/* This should never happen! This parameter was checked by
572	BVBI_Encode_Create() */
573	BDBG_LEAVE(BVBI_P_GS_Encode_Enable_isr);
574	return BERR_TRACE(BERR_INVALID_PARAMETER);
575	}
576
577	ulGse_controlReg = BREG_Read32 (hReg, BCHP_GSE_0_CONTROL + ulCoreOffset);
578	ulGse_controlReg &= ~(
579	BCHP_MASK (GSE_0_CONTROL, ENABLE ) );
580	if (bEnable)
581	{
582	ulGse_controlReg \|= (
583	BCHP_FIELD_DATA (GSE_0_CONTROL, ENABLE, 1) );
584	}
585	else
586	{
587	ulGse_controlReg \|= (
588	BCHP_FIELD_DATA (GSE_0_CONTROL, ENABLE, 0) );
589	}
590	BREG_Write32 (hReg, BCHP_GSE_0_CONTROL + ulCoreOffset, ulGse_controlReg);
591
592	BDBG_LEAVE(BVBI_P_GS_Encode_Enable_isr);
593	return BERR_SUCCESS;
594
595	#else / } BVBI_P_NUM_GSE { /
596
597	BSTD_UNUSED (hReg);
598	BSTD_UNUSED (is656);
599	BSTD_UNUSED (hwCoreIndex);
600	BSTD_UNUSED (eVideoFormat);
601	BSTD_UNUSED (bEnable);
602
603	return BERR_TRACE (BVBI_ERR_HW_UNSUPPORTED);
604
605	#endif / } BVBI_P_NUM_GSE /
606	}
607
608
609	/***************************************************************************
610	* Static (private) functions
611	***************************************************************************/
612
613	#if (BVBI_P_NUM_GSE >= 1) / { /
614
615	static void BVBI_P_ProgramNull (
616	BREG_Handle hReg, uint32_t coreOffset,
617	uint32_t ulWritePointer, uint32_t value)
618	{
619	uint32_t ulRegAddr = BCHP_GSE_0_NULL + coreOffset;
620	uint32_t ulRegVal = BREG_Read32 (hReg, ulRegAddr);
621
622	switch (ulWritePointer & 0x3)
623	{
624	case 0:
625	ulRegVal &= ~BCHP_MASK (GSE_0_NULL, NULL_ENABLE_BANK0 );
626	ulRegVal \|= BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK0, value);
627	break;
628	case 1:
629	ulRegVal &= ~BCHP_MASK (GSE_0_NULL, NULL_ENABLE_BANK1 );
630	ulRegVal \|= BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK1, value);
631	break;
632	case 2:
633	ulRegVal &= ~BCHP_MASK (GSE_0_NULL, NULL_ENABLE_BANK2 );
634	ulRegVal \|= BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK2, value);
635	break;
636	case 3:
637	ulRegVal &= ~BCHP_MASK (GSE_0_NULL, NULL_ENABLE_BANK3 );
638	ulRegVal \|= BCHP_FIELD_DATA (GSE_0_NULL, NULL_ENABLE_BANK3, value);
639	break;
640	default:
641	/* Should never happen! Programming error! */
642	BDBG_ASSERT (false);
643	break;
644	}
645
646	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
647	}
648
649	/***************************************************************************
650	*
651	*/
652	static uint32_t P_GetCoreOffset (bool is656, uint8_t hwCoreIndex)
653	{
654	uint32_t ulCoreOffset = 0xFFFFFFFF;
655
656	if (is656)
657	{
658	#if (BVBI_P_NUM_GSE_656 >= 1)
659	ulCoreOffset = (BCHP_GSE_ANCIL_0_REVID - BCHP_GSE_0_REVID);
660	#endif
661	}
662	else
663	{
664	switch (hwCoreIndex)
665	{
666	#if (BVBI_P_NUM_GSE >= 1)
667	case 0:
668	ulCoreOffset = 0;
669	break;
670	#endif
671	#if (BVBI_P_NUM_GSE >= 2)
672	case 1:
673	ulCoreOffset = (BCHP_GSE_1_REVID - BCHP_GSE_0_REVID);
674	break;
675	#endif
676	#if (BVBI_P_NUM_GSE >= 3)
677	case 2:
678	ulCoreOffset = (BCHP_GSE_2_REVID - BCHP_GSE_0_REVID);
679	break;
680	#endif
681	default:
682	break;
683	}
684	}
685
686	return ulCoreOffset;
687	}
688
689	#endif / } BVBI_P_NUM_GSE /

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_gse.c

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