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bvbi_sctee.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_sctee.c $
11	* $brcm_Revision: Hydra_Software_Devel/11 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_sctee.c $
19	*
20	* Hydra_Software_Devel/11 2/20/12 2:53p darnstein
21	* SW7425-2434: more detail in error messages.
22	*
23	* Hydra_Software_Devel/10 2/20/12 12:56p darnstein
24	* SW7425-2434: when an unsupported video format is entered, the BDBG
25	* error message should be informative.
26	*
27	* Hydra_Software_Devel/9 7/14/11 1:24p darnstein
28	* SW7420-1994: add an alias for BCHP_SCTE_0_LCR_DATAi_BANK0_CC_DATA_MASK.
29	*
30	* Hydra_Software_Devel/8 10/5/10 5:37p darnstein
31	* SW7405-4916: avoid ASSERT in initialization. Use error code instead.
32	*
33	* Hydra_Software_Devel/7 3/25/10 11:54a darnstein
34	* SW7125-130: add register name work-around to 7340-B0 and 7342-B0.
35	*
36	* Hydra_Software_Devel/6 2/9/10 3:33p darnstein
37	* SW7125-130: extend register name work-around to 7420-B0.
38	*
39	* Hydra_Software_Devel/5 1/18/10 4:35p darnstein
40	* SW7125-130: add register name work-around to 7420-C0.
41	*
42	* Hydra_Software_Devel/4 12/1/09 7:34p darnstein
43	* SW7125-130: Temporarily, change register names for SCTE encoder core.
44	* Only applies to 7125. This will be reversed when the RDB gets
45	* straightened out.
46	*
47	* Hydra_Software_Devel/3 6/24/09 4:58p darnstein
48	* PR56290: BVBI now compiles for 7342 chipset.
49	*
50	* Hydra_Software_Devel/2 12/4/08 6:07p darnstein
51	* PR45819: 7420 software will now compile, but not link.
52	*
53	* Hydra_Software_Devel/1 12/3/08 8:02p darnstein
54	* PR45819:
55	*
56	***************************************************************************/
57
58	#include "bstd.h" /* standard types */
59	#include "bdbg.h" /* Dbglib */
60	#include "bkni.h" /* For critical sections */
61	#include "bvbi.h" /* VBI processing, this module. */
62	#include "bvbi_priv.h" /* VBI internal data structures */
63	#if (BVBI_P_NUM_SCTEE >= 1)
64	#include "bchp_scte_0.h" /* RDB info for primary SCTE encoder core */
65	#endif
66	#if (BVBI_P_NUM_SCTEE >= 2)
67	#include "bchp_scte_1.h" /* RDB info for secondary SCTE encoder core */
68	#endif
69	#if (BVBI_P_NUM_SCTEE >= 3)
70	#include "bchp_scte_2.h" /* RDB info for tertiary SCTE encoder core */
71	#endif
72	/* Currently, there is no 656/SCTE encoder core. */
73
74	/*
75	* This is a temporary measure, only until the RDBs get straightened out.
76	*/
77	#if ( BCHP_CHIP == 7125) \|\| \
78	( BCHP_CHIP == 7420) \|\| \
79	((BCHP_CHIP == 7340) && (BCHP_VER >= BCHP_VER_B0)) \|\| \
80	((BCHP_CHIP == 7342) && (BCHP_VER >= BCHP_VER_B0))
81	#define BCHP_SCTE_0_LCR_CONTROLi_BANK1_ARRAY_BASE \
82	BCHP_SCTE_0_LCR_CONTROL_BANK1i_ARRAY_BASE
83	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE \
84	BCHP_SCTE_0_LCR_CONTROL_BANK0i_ARRAY_BASE
85	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_LINE_OFFSET_MASK \
86	BCHP_SCTE_0_LCR_CONTROL_BANK0i_LINE_OFFSET_MASK
87	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_VBI_DATA_TYPE_MASK \
88	BCHP_SCTE_0_LCR_CONTROL_BANK0i_VBI_DATA_TYPE_MASK
89	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_LINE_OFFSET_SHIFT \
90	BCHP_SCTE_0_LCR_CONTROL_BANK0i_LINE_OFFSET_SHIFT
91	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_VBI_DATA_TYPE_PAM_DATA \
92	BCHP_SCTE_0_LCR_CONTROL_BANK0i_VBI_DATA_TYPE_PAM_DATA
93	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_VBI_DATA_TYPE_SHIFT \
94	BCHP_SCTE_0_LCR_CONTROL_BANK0i_VBI_DATA_TYPE_SHIFT
95	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_VBI_DATA_TYPE_NO_DATA \
96	BCHP_SCTE_0_LCR_CONTROL_BANK0i_VBI_DATA_TYPE_NO_DATA
97	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_reserved0_MASK \
98	BCHP_SCTE_0_LCR_CONTROL_BANK0i_reserved0_MASK
99	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_SHIFT_DIRECTION_MASK \
100	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_SHIFT_DIRECTION_MASK
101	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_BYTE_ORDER_MASK \
102	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_BYTE_ORDER_MASK
103	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_PARITY_TYPE_MASK \
104	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_PARITY_TYPE_MASK
105	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_PARITY_MASK \
106	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_PARITY_MASK
107	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_RUN_IN_MASK \
108	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_RUN_IN_MASK
109	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_NULL_MASK \
110	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_NULL_MASK
111	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_DELAY_COUNT_MASK \
112	BCHP_SCTE_0_LCR_CONTROL_BANK0i_DELAY_COUNT_MASK
113	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_reserved0_SHIFT \
114	BCHP_SCTE_0_LCR_CONTROL_BANK0i_reserved0_SHIFT
115	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_SHIFT_DIRECTION_LSB_FIRST \
116	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_SHIFT_DIRECTION_LSB_FIRST
117	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_SHIFT_DIRECTION_SHIFT \
118	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_SHIFT_DIRECTION_SHIFT
119	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_BYTE_ORDER_LOW_BYTE_FIRST \
120	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_BYTE_ORDER_LOW_BYTE_FIRST
121	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_BYTE_ORDER_SHIFT \
122	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_BYTE_ORDER_SHIFT
123	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_PARITY_TYPE_ODD \
124	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_PARITY_TYPE_ODD
125	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_PARITY_TYPE_SHIFT \
126	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_PARITY_TYPE_SHIFT
127	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_PARITY_ENABLE \
128	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_PARITY_ENABLE
129	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_PARITY_SHIFT \
130	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_PARITY_SHIFT
131	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_RUN_IN_ENABLE \
132	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_RUN_IN_ENABLE
133	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_RUN_IN_SHIFT \
134	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_RUN_IN_SHIFT
135	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_NULL_DISABLE \
136	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_NULL_DISABLE
137	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_CC_NULL_SHIFT \
138	BCHP_SCTE_0_LCR_CONTROL_BANK0i_CC_NULL_SHIFT
139	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_DELAY_COUNT_SHIFT \
140	BCHP_SCTE_0_LCR_CONTROL_BANK0i_DELAY_COUNT_SHIFT
141	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_VBI_DATA_TYPE_CC_DATA \
142	BCHP_SCTE_0_LCR_CONTROL_BANK0i_VBI_DATA_TYPE_CC_DATA
143	#define BCHP_SCTE_0_LCR_DATAi_BANK1_ARRAY_BASE \
144	BCHP_SCTE_0_LCR_DATA_BANK1i_ARRAY_BASE
145	#define BCHP_SCTE_0_LCR_DATAi_BANK0_ARRAY_BASE \
146	BCHP_SCTE_0_LCR_DATA_BANK0i_ARRAY_BASE
147	#define BCHP_SCTE_0_LCR_DATAi_BANK0_CC_DATA_SHIFT \
148	BCHP_SCTE_0_LCR_DATA_BANK0i_CC_DATA_SHIFT
149	#define BCHP_SCTE_0_LCR_DATAi_BANK0_CC_DATA_MASK \
150	BCHP_SCTE_0_LCR_DATA_BANK0i_CC_DATA_MASK
151	#define BCHP_SCTE_0_LCR_CONTROLi_BANK0_VBI_DATA_TYPE_NRTV_DATA \
152	BCHP_SCTE_0_LCR_CONTROL_BANK0i_VBI_DATA_TYPE_NRTV_DATA
153	#endif
154
155	BDBG_MODULE(BVBI);
156
157	/***************************************************************************
158	* Private data
159	***************************************************************************/
160
161	/*
162	* Programming note: this table must be in sync with the enum
163	* BVBI_CSC.
164	*/
165	/* These settings work for CC and SCTE modes. Not for monochrome mode. */
166	static const uint16_t P_csc_coeff_c00[4] = {0x146b, 0x12ec, 0x12d6, 0x1456};
167	static const uint16_t P_csc_coeff_c03[4] = {0xfd73, 0x0042, 0xfd75, 0xfd77};
168	static const uint16_t P_csc_coeff_c11[4] = {0xf6aa, 0xf75a, 0x10f8, 0x13e4};
169	static const uint16_t P_csc_coeff_c12[4] = {0x1441, 0x12c4, 0x0000, 0xfffe};
170	static const uint16_t P_csc_coeff_c13[4] = {0xf515, 0xf5e2, 0xef08, 0xec20};
171	static const uint16_t P_csc_coeff_c21[4] = {0x0e2d, 0x0d23, 0x0000, 0x0003};
172	static const uint16_t P_csc_coeff_c22[4] = {0x0d23, 0x0c2c, 0x17f1, 0x13e3};
173	static const uint16_t P_csc_coeff_c23[4] = {0xe4b0, 0xe6b1, 0xe80e, 0xec18};
174
175	/***************************************************************************
176	* Forward declarations of static (private) functions
177	***************************************************************************/
178
179	#if (BVBI_P_NUM_SCTEE > 0) / { /
180	static uint32_t P_GetCoreOffset (uint8_t hwCoreIndex);
181	static void BVBI_P_ProgramNull (
182	BREG_Handle hReg, uint32_t coreOffset,
183	uint32_t ulWritePointer, uint32_t value);
184	static bool BVBI_P_HasComponentOnly (uint8_t hwCoreIndex);
185	#endif / } BVBI_P_NUM_SCTEE /
186
187	/***************************************************************************
188	* Implementation of supporting SCTE functions that are not in API
189	***************************************************************************/
190
191	/***************************************************************************
192	*
193	*/
194	void BVBI_P_SCTE_Enc_Init (BREG_Handle hReg, uint8_t hwCoreIndex)
195	{
196	#if (BVBI_P_NUM_SCTEE > 0) / { /
197
198	BDBG_ENTER(BVBI_P_SCTE_Enc_Init);
199
200	BVBI_P_VIE_SoftReset (hReg, false, hwCoreIndex, BVBI_P_SELECT_SCTE);
201
202	BDBG_LEAVE(BVBI_P_SCTE_Enc_Init);
203
204	#else / } BVBI_P_NUM_SCTEE { /
205
206	BSTD_UNUSED (hReg);
207	BSTD_UNUSED (hwCoreIndex);
208
209	#endif / } BVBI_P_NUM_SCTEE /
210	}
211
212	/***************************************************************************
213	*
214	*/
215	BERR_Code BVBI_P_SCTE_Enc_Program (
216	BREG_Handle hReg,
217	bool is656,
218	uint8_t hwCoreIndex,
219	bool bActive,
220	BFMT_VideoFmt eVideoFormat,
221	BVBI_SCTE_Type scteType,
222	BVBI_CSC csc,
223	BVBI_CSC coCsc)
224	{
225	/*
226	Programming note: the implementation here assumes that the bitfield layout
227	within registers is the same for all SCTE encoder cores in the chip.
228
229	If a chip is built that has multiple SCTE encoder cores that are not
230	identical, then this routine will have to be redesigned.
231	*/
232	#if (BVBI_P_NUM_SCTEE > 0) / { /
233
234	uint32_t ulCoreOffset;
235	uint32_t ulSctee_controlReg;
236
237	BDBG_ENTER(BVBI_P_SCTE_Enc_Program);
238
239	/* Figure out which encoder core to use */
240	ulCoreOffset = P_GetCoreOffset (hwCoreIndex);
241	if (ulCoreOffset == 0xFFFFFFFF)
242	{
243	/* This should never happen! This parameter was checked by
244	BVBI_Encode_Create() */
245	BDBG_LEAVE(BVBI_P_SCTE_Enc_Program);
246	return BERR_TRACE(BERR_INVALID_PARAMETER);
247	}
248
249	/* Sanity check */
250	if (is656)
251	{
252	if (bActive)
253	{
254	/* No bypass encoder for SCTE */
255	BDBG_LEAVE(BVBI_P_SCTE_Enc_Program);
256	return BERR_TRACE(BERR_INVALID_PARAMETER);
257	}
258	else
259	{
260	/* Do nothing */
261	return BERR_SUCCESS;
262	}
263	}
264
265	/* Complain if video format is not supported */
266	switch (eVideoFormat)
267	{
268	case BFMT_VideoFmt_eNTSC:
269	case BFMT_VideoFmt_eNTSC_J:
270	break;
271
272	default:
273	if (bActive)
274	{
275	BDBG_ERR(("BVBI_SCTEE: video format %d not supported",
276	eVideoFormat));
277	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
278	}
279	}
280
281	/* This makes use of scteType safe */
282	BDBG_ASSERT (
283	BVBI_SCTE_Type_NONE == BCHP_SCTE_0_CONFIG_VBI_MODE_DISABLE );
284	BDBG_ASSERT (
285	BVBI_SCTE_Type_CCONLY == BCHP_SCTE_0_CONFIG_VBI_MODE_CC );
286	BDBG_ASSERT (
287	BVBI_SCTE_Type_CCNRTV == BCHP_SCTE_0_CONFIG_VBI_MODE_SCTE20 );
288	BDBG_ASSERT (
289	BVBI_SCTE_Type_CCPAM == BCHP_SCTE_0_CONFIG_VBI_MODE_SCTE21 );
290	BDBG_ASSERT (
291	BVBI_SCTE_Type_CCMONO == BCHP_SCTE_0_CONFIG_VBI_MODE_MONO_CHROME);
292	BDBG_ASSERT (
293	BVBI_SCTE_Type_LAST == BCHP_SCTE_0_CONFIG_VBI_MODE_MONO_CHROME+1);
294
295	/* If user wants to turn off closed caption processing, just use the
296	enable bit. */
297	if (!bActive)
298	{
299	ulSctee_controlReg =
300	BREG_Read32 ( hReg, BCHP_SCTE_0_CONFIG + ulCoreOffset );
301	ulSctee_controlReg &=
302	~BCHP_MASK (SCTE_0_CONFIG, VBI_MODE );
303	ulSctee_controlReg \|=
304	BCHP_FIELD_ENUM (SCTE_0_CONFIG, VBI_MODE, DISABLE);
305	BREG_Write32 (
306	hReg, BCHP_SCTE_0_CONFIG + ulCoreOffset, ulSctee_controlReg );
307	BDBG_LEAVE(BVBI_P_SCTE_Enc_Program);
308	return BERR_SUCCESS;
309	}
310
311	/* LCR enable registers: let everything through. */
312	BREG_Write32 (hReg, BCHP_SCTE_0_LCR_ENABLE_BANK0 + ulCoreOffset,
313	BCHP_FIELD_DATA (SCTE_0_LCR_ENABLE_BANK0, MASK, 0xFFFFFFFF) );
314	BREG_Write32 (hReg, BCHP_SCTE_0_LCR_ENABLE_BANK1 + ulCoreOffset,
315	BCHP_FIELD_DATA (SCTE_0_LCR_ENABLE_BANK0, MASK, 0xFFFFFFFF) );
316	BREG_Write32 (hReg, BCHP_SCTE_0_LCR_ENABLE_BANK2 + ulCoreOffset,
317	BCHP_FIELD_DATA (SCTE_0_LCR_ENABLE_BANK0, MASK, 0xFFFFFFFF) );
318	BREG_Write32 (hReg, BCHP_SCTE_0_LCR_ENABLE_BANK3 + ulCoreOffset,
319	BCHP_FIELD_DATA (SCTE_0_LCR_ENABLE_BANK0, MASK, 0xFFFFFFFF) );
320
321	ulSctee_controlReg = 0;
322	ulSctee_controlReg \|= (
323	BCHP_FIELD_DATA (SCTE_0_CONFIG, INC_VALUE, 16) \|
324	BCHP_FIELD_DATA (SCTE_0_CONFIG, MOD_VALUE, 429) \|
325	BCHP_FIELD_DATA (SCTE_0_CONFIG, VBI_MODE , scteType) );
326	BREG_Write32 (
327	hReg, BCHP_SCTE_0_CONFIG + ulCoreOffset, ulSctee_controlReg);
328
329	ulSctee_controlReg = 0;
330	ulSctee_controlReg \|= (
331	BCHP_FIELD_DATA (SCTE_0_PADDING_BLANK, Y_VALUE, 16) \|
332	BCHP_FIELD_DATA (SCTE_0_PADDING_BLANK, Cb_VALUE, 128) \|
333	BCHP_FIELD_DATA (SCTE_0_PADDING_BLANK, Cr_VALUE, 128) );
334	BREG_Write32 (
335	hReg, BCHP_SCTE_0_PADDING_BLANK + ulCoreOffset, ulSctee_controlReg);
336
337	ulSctee_controlReg = 0;
338	ulSctee_controlReg \|= (
339	BCHP_FIELD_DATA (SCTE_0_CC_GAIN_OFFSET, OFFSET, 0) \|
340	BCHP_FIELD_DATA (SCTE_0_CC_GAIN_OFFSET, GAIN , 2048) );
341	BREG_Write32 (
342	hReg, BCHP_SCTE_0_CC_GAIN_OFFSET + ulCoreOffset, ulSctee_controlReg);
343
344	ulSctee_controlReg = 0;
345	ulSctee_controlReg \|= (
346	BCHP_FIELD_DATA (SCTE_0_PAM_ADD_GAIN_OFFSET, OFFSET, 0) \|
347	BCHP_FIELD_DATA (SCTE_0_PAM_ADD_GAIN_OFFSET, GAIN , 0) );
348	BREG_Write32 (
349	hReg, BCHP_SCTE_0_PAM_ADD_GAIN_OFFSET + ulCoreOffset,
350	ulSctee_controlReg);
351
352	ulSctee_controlReg = 0;
353	ulSctee_controlReg \|= (
354	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK0, BANK_SKIP, 0) \|
355	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK0, LINE_NUMBER, 10) );
356	BREG_Write32 (
357	hReg, BCHP_SCTE_0_BANK_BASE_BANK0 + ulCoreOffset,
358	ulSctee_controlReg);
359
360	ulSctee_controlReg = 0;
361	ulSctee_controlReg \|= (
362	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK1, BANK_SKIP, 0) \|
363	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK1, LINE_NUMBER, 263+10) );
364	BREG_Write32 (
365	hReg, BCHP_SCTE_0_BANK_BASE_BANK1 + ulCoreOffset,
366	ulSctee_controlReg);
367
368	ulSctee_controlReg = 0;
369	ulSctee_controlReg \|= (
370	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK2, BANK_SKIP, 0) \|
371	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK2, LINE_NUMBER, 10) );
372	BREG_Write32 (
373	hReg, BCHP_SCTE_0_BANK_BASE_BANK2 + ulCoreOffset,
374	ulSctee_controlReg);
375
376	ulSctee_controlReg = 0;
377	ulSctee_controlReg \|= (
378	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK3, BANK_SKIP, 0) \|
379	BCHP_FIELD_DATA (SCTE_0_BANK_BASE_BANK3, LINE_NUMBER, 263+10) );
380	BREG_Write32 (
381	hReg, BCHP_SCTE_0_BANK_BASE_BANK3 + ulCoreOffset,
382	ulSctee_controlReg);
383
384	/* Write start registers: start them at the beginning. */
385	ulSctee_controlReg = 0;
386	ulSctee_controlReg \|= (
387	BCHP_FIELD_DATA (
388	SCTE_0_NRTV_WRITE_PTR_BANK0, PTR_WR_ENABLE, 1) \|
389	BCHP_FIELD_DATA (
390	SCTE_0_NRTV_WRITE_PTR_BANK0, Cb_Cr_WRITE_PTR, 0) \|
391	BCHP_FIELD_DATA (
392	SCTE_0_NRTV_WRITE_PTR_BANK0, Y_WRITE_PTR, 0) );
393	BREG_Write32 (
394	hReg, BCHP_SCTE_0_NRTV_WRITE_PTR_BANK0 + ulCoreOffset,
395	ulSctee_controlReg);
396	BREG_Write32 (
397	hReg, BCHP_SCTE_0_NRTV_WRITE_PTR_BANK1 + ulCoreOffset,
398	ulSctee_controlReg);
399	BREG_Write32 (
400	hReg, BCHP_SCTE_0_NRTV_WRITE_PTR_BANK2 + ulCoreOffset,
401	ulSctee_controlReg);
402	BREG_Write32 (
403	hReg, BCHP_SCTE_0_NRTV_WRITE_PTR_BANK3 + ulCoreOffset,
404	ulSctee_controlReg);
405
406	ulSctee_controlReg = 0;
407	ulSctee_controlReg \|= (
408	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C03_C00, COEFF_C0,
409	P_csc_coeff_c00[csc]) \|
410	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C03_C00, COEFF_C3,
411	P_csc_coeff_c03[csc]) );
412	BREG_Write32 (
413	hReg, BCHP_SCTE_0_CSC_COEFF_C03_C00 + ulCoreOffset,
414	ulSctee_controlReg);
415
416	ulSctee_controlReg = 0;
417	ulSctee_controlReg \|= (
418	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C12_C11, COEFF_C1,
419	P_csc_coeff_c11[csc]) \|
420	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C12_C11, COEFF_C2,
421	P_csc_coeff_c12[csc]) );
422	BREG_Write32 (
423	hReg, BCHP_SCTE_0_CSC_COEFF_C12_C11 + ulCoreOffset,
424	ulSctee_controlReg);
425
426	ulSctee_controlReg = 0;
427	ulSctee_controlReg \|=
428	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C13, COEFF_C3,
429	P_csc_coeff_c13[csc]) ;
430	BREG_Write32 (
431	hReg, BCHP_SCTE_0_CSC_COEFF_C13 + ulCoreOffset,
432	ulSctee_controlReg);
433
434	ulSctee_controlReg = 0;
435	ulSctee_controlReg \|= (
436	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C22_C21, COEFF_C1,
437	P_csc_coeff_c21[csc]) \|
438	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C22_C21, COEFF_C2,
439	P_csc_coeff_c22[csc]) );
440	BREG_Write32 (
441	hReg, BCHP_SCTE_0_CSC_COEFF_C22_C21 + ulCoreOffset,
442	ulSctee_controlReg);
443
444	ulSctee_controlReg = 0;
445	ulSctee_controlReg \|=
446	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C23, COEFF_C3,
447	P_csc_coeff_c23[csc]) ;
448	BREG_Write32 (
449	hReg, BCHP_SCTE_0_CSC_COEFF_C23 + ulCoreOffset,
450	ulSctee_controlReg);
451
452	#ifdef BVBI_P_HAS_SCTEE_CO / { /
453	if ((BVBI_P_HasComponentOnly (hwCoreIndex)) &&
454	(coCsc != BVBI_CSC_NONE ) )
455	{
456	ulSctee_controlReg = 0;
457	ulSctee_controlReg \|= (
458	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C03_C00, COEFF_C0,
459	P_csc_coeff_c00[coCsc]) \|
460	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C03_C00, COEFF_C3,
461	P_csc_coeff_c03[coCsc]) );
462	BREG_Write32 (
463	hReg, BCHP_SCTE_0_CSC_CO_COEFF_C03_C00 + ulCoreOffset,
464	ulSctee_controlReg);
465
466	ulSctee_controlReg = 0;
467	ulSctee_controlReg \|= (
468	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C12_C11, COEFF_C1,
469	P_csc_coeff_c11[coCsc]) \|
470	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C12_C11, COEFF_C2,
471	P_csc_coeff_c12[coCsc]) );
472	BREG_Write32 (
473	hReg, BCHP_SCTE_0_CSC_CO_COEFF_C12_C11 + ulCoreOffset,
474	ulSctee_controlReg);
475
476	ulSctee_controlReg = 0;
477	ulSctee_controlReg \|=
478	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C13, COEFF_C3,
479	P_csc_coeff_c13[coCsc]) ;
480	BREG_Write32 (
481	hReg, BCHP_SCTE_0_CSC_CO_COEFF_C13 + ulCoreOffset,
482	ulSctee_controlReg);
483
484	ulSctee_controlReg = 0;
485	ulSctee_controlReg \|= (
486	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C22_C21, COEFF_C1,
487	P_csc_coeff_c21[coCsc]) \|
488	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C22_C21, COEFF_C2,
489	P_csc_coeff_c22[coCsc]) );
490	BREG_Write32 (
491	hReg, BCHP_SCTE_0_CSC_CO_COEFF_C22_C21 + ulCoreOffset,
492	ulSctee_controlReg);
493
494	ulSctee_controlReg = 0;
495	ulSctee_controlReg \|=
496	BCHP_FIELD_DATA (SCTE_0_CSC_CO_COEFF_C23, COEFF_C3,
497	P_csc_coeff_c23[coCsc]) ;
498	BREG_Write32 (
499	hReg, BCHP_SCTE_0_CSC_CO_COEFF_C23 + ulCoreOffset,
500	ulSctee_controlReg);
501	}
502	#endif / } BVBI_P_HAS_SCTEE_CO /
503
504	ulSctee_controlReg = 0;
505	ulSctee_controlReg \|= (
506	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, LUMA_BLANK,
507	0x00) \|
508	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, CHROMA_BLANK,
509	0x80) );
510	BREG_Write32 (
511	hReg, BCHP_SCTE_0_SHAPER_BLANK_VALUE + ulCoreOffset,
512	ulSctee_controlReg);
513	if ((BVBI_P_HasComponentOnly (hwCoreIndex)) &&
514	(coCsc != BVBI_CSC_NONE ) )
515	{
516	ulSctee_controlReg = 0;
517	ulSctee_controlReg \|= (
518	BCHP_FIELD_DATA (SCTE_0_SHAPER_CO_BLANK_VALUE, LUMA_BLANK,
519	0x00) \|
520	BCHP_FIELD_DATA (SCTE_0_SHAPER_CO_BLANK_VALUE, CHROMA_BLANK,
521	0x80) );
522	BREG_Write32 (
523	hReg, BCHP_SCTE_0_SHAPER_CO_BLANK_VALUE + ulCoreOffset,
524	ulSctee_controlReg);
525	}
526
527	/*
528	* TODO: registers SCTE_0_CSC_MODE, SCTE_0_CSC_MIN_MAX. Default values
529	* suffice.
530	*/
531
532	switch (scteType)
533	{
534	case BVBI_SCTE_Type_CCONLY:
535
536	ulSctee_controlReg = 0;
537	ulSctee_controlReg \|= (
538	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_2, 0) \|
539	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_1, 0) \|
540	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_0, 0) );
541	BREG_Write32 (
542	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_0_2 + ulCoreOffset,
543	ulSctee_controlReg);
544
545	ulSctee_controlReg = 0;
546	ulSctee_controlReg \|= (
547	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_5, 0) \|
548	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_4, 0) \|
549	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_3, 0) );
550	BREG_Write32 (
551	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_3_5 + ulCoreOffset,
552	ulSctee_controlReg);
553
554	ulSctee_controlReg = 0;
555	ulSctee_controlReg \|= (
556	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_8, 0) \|
557	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_7, 0) \|
558	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_6, 0) );
559	BREG_Write32 (
560	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_6_8 + ulCoreOffset,
561	ulSctee_controlReg);
562
563	ulSctee_controlReg = 0;
564	ulSctee_controlReg \|= (
565	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_2, 0) \|
566	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_1, 0) \|
567	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_0, 0) );
568	BREG_Write32 (
569	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_0_2 + ulCoreOffset,
570	ulSctee_controlReg);
571
572	ulSctee_controlReg = 0;
573	ulSctee_controlReg \|= (
574	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_5, 0) \|
575	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_4, 0) \|
576	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_3, 0) );
577	BREG_Write32 (
578	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_3_5 + ulCoreOffset,
579	ulSctee_controlReg);
580
581	ulSctee_controlReg = 0;
582	ulSctee_controlReg \|= (
583	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_8, 0) \|
584	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_7, 0) \|
585	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_6, 0) );
586	BREG_Write32 (
587	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_6_8 + ulCoreOffset,
588	ulSctee_controlReg);
589
590	ulSctee_controlReg = 0;
591	ulSctee_controlReg \|= (
592	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, REPL_COUNT, 0) \|
593	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_OUT_OFFSET, 0) \|
594	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_IN_OFFSET, 0) \|
595	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, CC_ENABLE, 1) );
596	BREG_Write32 (
597	hReg, BCHP_SCTE_0_SHAPER_CONTROL + ulCoreOffset,
598	ulSctee_controlReg);
599
600	break;
601
602	/* This is SCTE 20 mode */
603	case BVBI_SCTE_Type_CCNRTV:
604
605	ulSctee_controlReg = 0;
606	ulSctee_controlReg \|= (
607	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_0, 0x10) \|
608	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_1, 0x30) \|
609	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_2, 0x50) );
610	BREG_Write32 (
611	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_0_2 + ulCoreOffset,
612	ulSctee_controlReg);
613
614	ulSctee_controlReg = 0;
615	ulSctee_controlReg \|= (
616	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_3, 0x70) \|
617	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_4, 0x90) \|
618	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_5, 0xc0) );
619	BREG_Write32 (
620	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_3_5 + ulCoreOffset,
621	ulSctee_controlReg);
622
623	ulSctee_controlReg = 0;
624	ulSctee_controlReg \|= (
625	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_6, 0xd0) \|
626	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_7, 0xe0) \|
627	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_8, 0xf0) );
628	BREG_Write32 (
629	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_6_8 + ulCoreOffset,
630	ulSctee_controlReg);
631
632	ulSctee_controlReg = 0;
633	ulSctee_controlReg \|= (
634	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_0, 0x10) \|
635	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_1, 0x30) \|
636	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_2, 0x50) );
637	BREG_Write32 (
638	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_0_2 + ulCoreOffset,
639	ulSctee_controlReg);
640
641	ulSctee_controlReg = 0;
642	ulSctee_controlReg \|= (
643	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_3, 0x70) \|
644	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_4, 0x90) \|
645	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_5, 0xc0) );
646	BREG_Write32 (
647	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_3_5 + ulCoreOffset,
648	ulSctee_controlReg);
649
650	ulSctee_controlReg = 0;
651	ulSctee_controlReg \|= (
652	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_6, 0xd0) \|
653	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_7, 0xe0) \|
654	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_8, 0xf0) );
655	BREG_Write32 (
656	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_6_8 + ulCoreOffset,
657	ulSctee_controlReg);
658
659	ulSctee_controlReg = 0;
660	ulSctee_controlReg \|= (
661	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, REPL_COUNT, 0) \|
662	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_OUT_OFFSET, 0) \|
663	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_IN_OFFSET, 0) \|
664	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, NRTV_ENABLE, 1) );
665	BREG_Write32 (
666	hReg, BCHP_SCTE_0_SHAPER_CONTROL + ulCoreOffset,
667	ulSctee_controlReg);
668
669	ulSctee_controlReg = 0;
670	ulSctee_controlReg \|= (
671	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, LUMA_BLANK,
672	0x00) \|
673	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, CHROMA_BLANK,
674	0x80) );
675	BREG_Write32 (
676	hReg, BCHP_SCTE_0_SHAPER_BLANK_VALUE + ulCoreOffset,
677	ulSctee_controlReg);
678
679	/* This is SCTE 21 mode */
680	case BVBI_SCTE_Type_CCPAM:
681
682	ulSctee_controlReg = 0;
683	ulSctee_controlReg \|= (
684	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_0, 0x10) \|
685	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_1, 0x30) \|
686	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_2, 0x50) );
687	BREG_Write32 (
688	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_0_2 + ulCoreOffset,
689	ulSctee_controlReg);
690
691	ulSctee_controlReg = 0;
692	ulSctee_controlReg \|= (
693	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_3, 0x70) \|
694	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_4, 0x90) \|
695	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_5, 0xc0) );
696	BREG_Write32 (
697	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_3_5 + ulCoreOffset,
698	ulSctee_controlReg);
699
700	ulSctee_controlReg = 0;
701	ulSctee_controlReg \|= (
702	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_6, 0xd0) \|
703	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_7, 0xe0) \|
704	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_8, 0xf0) );
705	BREG_Write32 (
706	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_6_8 + ulCoreOffset,
707	ulSctee_controlReg);
708
709	ulSctee_controlReg = 0;
710	ulSctee_controlReg \|= (
711	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_0, 0x10) \|
712	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_1, 0x30) \|
713	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_2, 0x50) );
714	BREG_Write32 (
715	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_0_2 + ulCoreOffset,
716	ulSctee_controlReg);
717
718	ulSctee_controlReg = 0;
719	ulSctee_controlReg \|= (
720	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_3, 0x70) \|
721	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_4, 0x90) \|
722	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_5, 0xc0) );
723	BREG_Write32 (
724	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_3_5 + ulCoreOffset,
725	ulSctee_controlReg);
726
727	ulSctee_controlReg = 0;
728	ulSctee_controlReg \|= (
729	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_6, 0xd0) \|
730	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_7, 0xe0) \|
731	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_8, 0xf0) );
732	BREG_Write32 (
733	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_6_8 + ulCoreOffset,
734	ulSctee_controlReg);
735
736	ulSctee_controlReg = 0;
737	ulSctee_controlReg \|= (
738	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, REPL_COUNT, 0) \|
739	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_OUT_OFFSET, 0) \|
740	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_IN_OFFSET, 0) \|
741	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, PAM_ENABLE, 1) );
742	BREG_Write32 (
743	hReg, BCHP_SCTE_0_SHAPER_CONTROL + ulCoreOffset,
744	ulSctee_controlReg);
745
746	ulSctee_controlReg = 0;
747	ulSctee_controlReg \|= (
748	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, LUMA_BLANK,
749	0x00) \|
750	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, CHROMA_BLANK,
751	0x80) );
752	BREG_Write32 (
753	hReg, BCHP_SCTE_0_SHAPER_BLANK_VALUE + ulCoreOffset,
754	ulSctee_controlReg);
755
756	break;
757
758	case BVBI_SCTE_Type_CCMONO:
759
760	ulSctee_controlReg = 0;
761	ulSctee_controlReg \|= (
762	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_0, 0x10) \|
763	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_1, 0x30) \|
764	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_0_2, COEFF_2, 0x50) );
765	BREG_Write32 (
766	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_0_2 + ulCoreOffset,
767	ulSctee_controlReg);
768
769	ulSctee_controlReg = 0;
770	ulSctee_controlReg \|= (
771	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_3, 0x70) \|
772	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_4, 0x90) \|
773	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_3_5, COEFF_5, 0xc0) );
774	BREG_Write32 (
775	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_3_5 + ulCoreOffset,
776	ulSctee_controlReg);
777
778	ulSctee_controlReg = 0;
779	ulSctee_controlReg \|= (
780	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_6, 0xd0) \|
781	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_7, 0xe0) \|
782	BCHP_FIELD_DATA (SCTE_0_SHAPER_LUMA_COEFF_6_8, COEFF_8, 0xf0) );
783	BREG_Write32 (
784	hReg, BCHP_SCTE_0_SHAPER_LUMA_COEFF_6_8 + ulCoreOffset,
785	ulSctee_controlReg);
786
787	ulSctee_controlReg = 0;
788	ulSctee_controlReg \|= (
789	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_0, 0x10) \|
790	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_1, 0x30) \|
791	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_0_2, COEFF_2, 0x50) );
792	BREG_Write32 (
793	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_0_2 + ulCoreOffset,
794	ulSctee_controlReg);
795
796	ulSctee_controlReg = 0;
797	ulSctee_controlReg \|= (
798	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_3, 0x70) \|
799	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_4, 0x90) \|
800	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_3_5, COEFF_5, 0xc0) );
801	BREG_Write32 (
802	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_3_5 + ulCoreOffset,
803	ulSctee_controlReg);
804
805	ulSctee_controlReg = 0;
806	ulSctee_controlReg \|= (
807	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_6, 0xd0) \|
808	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_7, 0xe0) \|
809	BCHP_FIELD_DATA (SCTE_0_SHAPER_CHROMA_COEFF_6_8, COEFF_8, 0xf0) );
810	BREG_Write32 (
811	hReg, BCHP_SCTE_0_SHAPER_CHROMA_COEFF_6_8 + ulCoreOffset,
812	ulSctee_controlReg);
813
814	ulSctee_controlReg = 0;
815	ulSctee_controlReg \|= (
816	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, REPL_COUNT, 0) \|
817	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_OUT_OFFSET, 0) \|
818	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, SHAPE_IN_OFFSET, 0) \|
819	BCHP_FIELD_DATA (SCTE_0_SHAPER_CONTROL, PAM_ENABLE, 1) );
820	BREG_Write32 (
821	hReg, BCHP_SCTE_0_SHAPER_CONTROL + ulCoreOffset,
822	ulSctee_controlReg);
823
824	ulSctee_controlReg = 0;
825	ulSctee_controlReg \|= (
826	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, LUMA_BLANK,
827	0x00) \|
828	BCHP_FIELD_DATA (SCTE_0_SHAPER_BLANK_VALUE, CHROMA_BLANK,
829	0x80) );
830	BREG_Write32 (
831	hReg, BCHP_SCTE_0_SHAPER_BLANK_VALUE + ulCoreOffset,
832	ulSctee_controlReg);
833
834	/*
835	* Override CSC settings for monochrome data!
836	*/
837	ulSctee_controlReg = 0;
838	ulSctee_controlReg \|= (
839	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C03_C00, COEFF_C0, 0x800) \|
840	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C03_C00, COEFF_C3, 0x000) );
841	BREG_Write32 (
842	hReg, BCHP_SCTE_0_CSC_COEFF_C03_C00 + ulCoreOffset,
843	ulSctee_controlReg);
844
845	ulSctee_controlReg = 0;
846	ulSctee_controlReg \|= (
847	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C12_C11, COEFF_C1, 0x800) \|
848	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C12_C11, COEFF_C2, 0x000) );
849	BREG_Write32 (
850	hReg, BCHP_SCTE_0_CSC_COEFF_C12_C11 + ulCoreOffset,
851	ulSctee_controlReg);
852
853	ulSctee_controlReg = 0;
854	ulSctee_controlReg \|=
855	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C13, COEFF_C3, 0x000) ;
856	BREG_Write32 (
857	hReg, BCHP_SCTE_0_CSC_COEFF_C13 + ulCoreOffset,
858	ulSctee_controlReg);
859
860	ulSctee_controlReg = 0;
861	ulSctee_controlReg \|= (
862	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C22_C21, COEFF_C1, 0x000) \|
863	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C22_C21, COEFF_C2, 0x800) );
864	BREG_Write32 (
865	hReg, BCHP_SCTE_0_CSC_COEFF_C22_C21 + ulCoreOffset,
866	ulSctee_controlReg);
867
868	ulSctee_controlReg = 0;
869	ulSctee_controlReg \|=
870	BCHP_FIELD_DATA (SCTE_0_CSC_COEFF_C23, COEFF_C3, 0x000) ;
871	BREG_Write32 (
872	hReg, BCHP_SCTE_0_CSC_COEFF_C23 + ulCoreOffset,
873	ulSctee_controlReg);
874
875	break;
876
877	default:
878	BDBG_LEAVE(BVBI_P_SCTE_Enc_Program);
879	return BERR_TRACE(BERR_INVALID_PARAMETER);
880	break;
881	}
882
883	/*
884	* TODO: configure SCTE_0_NRTV_SAMPLE_ORDER register. Default values
885	* suffice.
886	*/
887
888	BDBG_LEAVE(BVBI_P_SCTE_Enc_Program);
889	return BERR_SUCCESS;
890
891	#else / } ! BVBI_P_NUM_SCTEE { /
892
893	BSTD_UNUSED (hReg);
894	BSTD_UNUSED (is656);
895	BSTD_UNUSED (hwCoreIndex);
896	BSTD_UNUSED (bActive);
897	BSTD_UNUSED (eVideoFormat);
898	BSTD_UNUSED (scteType);
899	BSTD_UNUSED (csc);
900	BSTD_UNUSED (coCsc);
901
902	return BERR_TRACE (BVBI_ERR_HW_UNSUPPORTED);
903
904	#endif / } BVBI_P_NUM_SCTEE /
905	}
906
907	/***************************************************************************
908	*
909	*/
910	uint32_t BVBI_P_SCTE_Encode_Data_isr (
911	BREG_Handle hReg,
912	BMEM_Handle hMem,
913	bool is656,
914	uint8_t hwCoreIndex,
915	BFMT_VideoFmt eVideoFormat,
916	BAVC_Polarity polarity,
917	BVBI_SCTE_Type scteType,
918	BVBI_P_SCTE_Data* pData,
919	BVBI_LineBuilder_Handle hTopScteNrtv[2],
920	BVBI_LineBuilder_Handle hBotScteNrtv[2],
921	BVBI_LineBuilder_Handle hTopScteMono[2],
922	BVBI_LineBuilder_Handle hBotScteMono[2],
923	uint8_t** pSctePamData
924	)
925	{
926	#if (BVBI_P_NUM_SCTEE > 0) / { /
927
928	BVBI_LineBuilder_Handle *hScteNrtv;
929	BVBI_LineBuilder_Handle *hScteMono;
930	BERR_Code eErr;
931	uint32_t hardware_offset;
932	uint32_t ulCoreOffset;
933	uint32_t ulRegVal;
934	uint32_t ulRegAddr;
935	uint32_t ulReadPointer;
936	uint32_t ulWritePointer;
937	uint32_t sourceIndex;
938	uint32_t bankIndex;
939	uint32_t regBankOffset;
940	uint32_t regLineOffset;
941	uint32_t dataValue;
942	int lineIndex;
943	int iBulk;
944	int nrtv_sequence_number[2] = {0, 0};
945	uint8_t* bulkNrtvData[2] = {0, 0};
946	int line_number[2];
947
948	/* Debug code
949	uint32_t dread_pointer[2];
950	uint32_t dwrite_pointer[2];
951	*/
952
953	BDBG_ENTER(BVBI_P_SCTE_Encode_Data_isr);
954
955	/* Size check for field data */
956	if (!pData)
957	{
958	BDBG_LEAVE(BVBI_P_SCTE_Encode_Data_isr);
959	return (BVBI_LINE_ERROR_FLDH_CONFLICT);
960	}
961
962	/* Figure out which encoder core to use */
963	ulCoreOffset = P_GetCoreOffset (hwCoreIndex);
964	if (is656 \|\| (ulCoreOffset == 0xFFFFFFFF))
965	{
966	/* This should never happen! This parameter was checked by
967	BVBI_Encode_Create() */
968	ulCoreOffset = 0;
969	BDBG_ASSERT (ulCoreOffset);
970	}
971
972	/* Complain if video format is not supported */
973	switch (eVideoFormat)
974	{
975	case BFMT_VideoFmt_eNTSC:
976	case BFMT_VideoFmt_eNTSC_J:
977	break;
978
979	default:
980	/* Should not happen */
981	BDBG_ERR(("BVBI_SCTEE: video format %d not supported", eVideoFormat));
982	BDBG_ASSERT (0);
983	break;
984	}
985
986	/* Verify SCTE type */
987	/* TODO: handle monochrome data */
988	switch (scteType)
989	{
990	case BVBI_SCTE_Type_CCONLY:
991	case BVBI_SCTE_Type_CCNRTV:
992	case BVBI_SCTE_Type_CCPAM:
993	/* case BVBI_SCTE_Type_CCMONO: */
994	break;
995	default:
996	BDBG_LEAVE(BVBI_P_SCTE_Encode_Data_isr);
997	return BERR_SUCCESS;
998	break;
999	}
1000
1001	/* Clear linecount underflow conditions */
1002	ulRegVal = BREG_Read32 (hReg, BCHP_SCTE_0_FIFO_STATUS + ulCoreOffset);
1003	ulRegVal \|= (
1004	BCHP_FIELD_DATA (SCTE_0_FIFO_STATUS, UNDERFLOW_0, 1) \|
1005	BCHP_FIELD_DATA (SCTE_0_FIFO_STATUS, UNDERFLOW_1, 1) );
1006	BREG_Write32 (hReg, BCHP_SCTE_0_FIFO_STATUS + ulCoreOffset, ulRegVal);
1007
1008	/* TODO: clear other status bits? */
1009
1010	/* Get FIFO pointers */
1011	ulRegVal = BREG_Read32 (hReg, BCHP_SCTE_0_BANK_CONTROL + ulCoreOffset);
1012	ulWritePointer =
1013	BCHP_GET_FIELD_DATA (ulRegVal, SCTE_0_BANK_CONTROL, WRITE_PTR);
1014	bankIndex = ulWritePointer & 0x00000003;
1015	ulRegVal = BREG_Read32 (hReg, BCHP_SCTE_0_FIFO_STATUS + ulCoreOffset);
1016	ulReadPointer =
1017	BCHP_GET_FIELD_DATA (ulRegVal, SCTE_0_FIFO_STATUS, READ_PTR);
1018
1019	/* Debug code
1020	dread_pointer[0] = ulReadPointer;
1021	dwrite_pointer[0] = ulWritePointer;
1022	*/
1023
1024	/* Check for FIFO full */
1025	if (((ulReadPointer & 0x3) == bankIndex ) &&
1026	(ulReadPointer != ulWritePointer) )
1027	{
1028	/* Debug code
1029	printf ("\n * SCTE FIFO full!!! *\n\n");
1030	*/
1031
1032	return BVBI_LINE_ERROR_SCTE_OVERRUN;
1033	}
1034
1035	/* Choose bulk data stores based on field polarity */
1036	if (polarity == BAVC_Polarity_eTopField)
1037	{
1038	hScteNrtv = hTopScteNrtv;
1039	hScteMono = hTopScteMono;
1040	}
1041	else
1042	{
1043	hScteNrtv = hBotScteNrtv;
1044	hScteMono = hBotScteMono;
1045	}
1046
1047	/* Handle field misalignment */
1048	if (
1049	((bankIndex == 0) \|\| (bankIndex == 2)) &&
1050	(polarity != BAVC_Polarity_eTopField)
1051	)
1052	{
1053	BVBI_P_ProgramNull (hReg, ulCoreOffset, bankIndex, 1);
1054	++ulWritePointer;
1055	}
1056	else if (
1057	((bankIndex == 1) \|\| (bankIndex == 3)) &&
1058	(polarity != BAVC_Polarity_eBotField)
1059	)
1060	{
1061	BVBI_P_ProgramNull (hReg, ulCoreOffset, bankIndex, 1);
1062	++ulWritePointer;
1063	}
1064	else
1065	{
1066	BVBI_P_ProgramNull (hReg, ulCoreOffset, bankIndex, 0);
1067	}
1068
1069	/* Set DMA length to zero. This default will be overridden if PAM, NRTV, or
1070	* monochrome data is present.
1071	*/
1072	regBankOffset =
1073	BCHP_SCTE_0_CH0_DMA_LENGTH_BANK1 -
1074	BCHP_SCTE_0_CH0_DMA_LENGTH_BANK0;
1075	ulRegAddr = BCHP_SCTE_0_CH0_DMA_LENGTH_BANK0 + ulCoreOffset +
1076	(regBankOffset * bankIndex);
1077	ulRegVal = 0;
1078	ulRegVal \|= (
1079	BCHP_FIELD_DATA (
1080	SCTE_0_CH0_DMA_LENGTH_BANK0, FIELD_NUM, 1) \|
1081	BCHP_FIELD_DATA (
1082	SCTE_0_CH0_DMA_LENGTH_BANK0, RESET, 0) \|
1083	BCHP_FIELD_DATA (
1084	SCTE_0_CH0_DMA_LENGTH_BANK0, LENGTH, 0) );
1085	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1086
1087	regBankOffset =
1088	BCHP_SCTE_0_CH1_DMA_LENGTH_BANK1 -
1089	BCHP_SCTE_0_CH1_DMA_LENGTH_BANK0;
1090	ulRegAddr = BCHP_SCTE_0_CH1_DMA_LENGTH_BANK0 + ulCoreOffset +
1091	(regBankOffset * bankIndex);
1092	ulRegVal = 0;
1093	ulRegVal \|= (
1094	BCHP_FIELD_DATA (
1095	SCTE_0_CH1_DMA_LENGTH_BANK0, RESET, 0) \|
1096	BCHP_FIELD_DATA (
1097	SCTE_0_CH1_DMA_LENGTH_BANK0, LENGTH, 0) );
1098	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1099
1100	/* Program the line control registers to some sensible defaults */
1101	for (lineIndex = 0 ; lineIndex < BVBI_SCTE_MAX_ITEMS ; ++lineIndex)
1102	{
1103	regBankOffset =
1104	BCHP_SCTE_0_LCR_CONTROLi_BANK1_ARRAY_BASE -
1105	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE;
1106	regLineOffset = 4;
1107	ulRegAddr =
1108	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE + ulCoreOffset +
1109	(regBankOffset * bankIndex) + (regLineOffset * lineIndex);
1110	ulRegVal = BREG_Read32 (hReg, ulRegAddr);
1111	ulRegVal &= ~(
1112	BCHP_MASK (SCTE_0_LCR_CONTROLi_BANK0, LINE_OFFSET ) \|
1113	BCHP_MASK (SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE) );
1114	ulRegVal \|=
1115	BCHP_FIELD_DATA (
1116	SCTE_0_LCR_CONTROLi_BANK0, LINE_OFFSET, lineIndex);
1117	if (scteType == BVBI_SCTE_Type_CCPAM)
1118	{
1119	ulRegVal \|=
1120	BCHP_FIELD_ENUM (
1121	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE, PAM_DATA);
1122	}
1123	else
1124	{
1125	ulRegVal \|=
1126	BCHP_FIELD_ENUM (
1127	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE, NO_DATA);
1128	}
1129	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1130	}
1131
1132	/* Debug code: research a particular problem.
1133	for (lineIndex = 4 ; lineIndex < BVBI_SCTE_MAX_ITEMS ; ++lineIndex)
1134	{
1135	if ((lineIndex == 8) \|\| (lineIndex == 11))
1136	continue;
1137	regBankOffset =
1138	BCHP_SCTE_0_LCR_CONTROLi_BANK1_ARRAY_BASE -
1139	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE;
1140	regLineOffset = 4;
1141	ulRegAddr =
1142	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE + ulCoreOffset +
1143	(regBankOffset * bankIndex) + (regLineOffset * lineIndex);
1144	ulRegVal = BREG_Read32 (hReg, ulRegAddr);
1145	ulRegVal &= ~(
1146	BCHP_MASK (SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE) \|
1147	BCHP_MASK (SCTE_0_LCR_CONTROLi_BANK0, DELAY_COUNT ) );
1148	ulRegVal \|= (
1149	BCHP_FIELD_ENUM (SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE,
1150	NRTV_DATA) \|
1151	BCHP_FIELD_DATA (SCTE_0_LCR_CONTROLi_BANK0, DELAY_COUNT ,
1152	0x30) );
1153	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1154	}
1155	*/
1156
1157	/* Commit the line-oriented data to hardware */
1158	for (sourceIndex = 0 ; sourceIndex < pData->line_count ; ++sourceIndex)
1159	{
1160	BVBI_P_SCTE_Line_Data* lineData = &(pData->pLine[sourceIndex]);
1161	lineIndex = lineData->line_number - 10;
1162	if (lineData->eType == BVBI_SCTE_Type_CCONLY)
1163	{
1164	if ((scteType == BVBI_SCTE_Type_CCONLY) \|\|
1165	(scteType == BVBI_SCTE_Type_CCNRTV) \|\|
1166	(scteType == BVBI_SCTE_Type_CCPAM ) \|\|
1167	(scteType == BVBI_SCTE_Type_CCMONO) )
1168	{
1169	/*
1170	* Process one line of CC data
1171	*/
1172	BVBI_P_SCTE_CC_Line_Data* pScteCcData = &(lineData->d.CC);
1173
1174	/* Debug code
1175	printf (" Programming LCR bank %d, line %d\n",
1176	bankIndex, lineIndex);
1177	*/
1178
1179	/* Locate and program the LCR control register */
1180	regBankOffset =
1181	BCHP_SCTE_0_LCR_CONTROLi_BANK1_ARRAY_BASE -
1182	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE;
1183	regLineOffset = 4;
1184	ulRegAddr =
1185	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE +
1186	ulCoreOffset +
1187	(regBankOffset * bankIndex) +
1188	(regLineOffset * lineIndex);
1189	ulRegVal = BREG_Read32 (hReg, ulRegAddr);
1190	ulRegVal &= ~(
1191	BCHP_MASK (
1192	SCTE_0_LCR_CONTROLi_BANK0, reserved0 ) \|
1193	BCHP_MASK (
1194	SCTE_0_LCR_CONTROLi_BANK0, CC_SHIFT_DIRECTION) \|
1195	BCHP_MASK (
1196	SCTE_0_LCR_CONTROLi_BANK0, CC_BYTE_ORDER ) \|
1197	BCHP_MASK (
1198	SCTE_0_LCR_CONTROLi_BANK0, CC_PARITY_TYPE ) \|
1199	BCHP_MASK (
1200	SCTE_0_LCR_CONTROLi_BANK0, CC_PARITY ) \|
1201	BCHP_MASK (
1202	SCTE_0_LCR_CONTROLi_BANK0, CC_RUN_IN ) \|
1203	BCHP_MASK (
1204	SCTE_0_LCR_CONTROLi_BANK0, CC_NULL ) \|
1205	BCHP_MASK (
1206	SCTE_0_LCR_CONTROLi_BANK0, DELAY_COUNT ) \|
1207	BCHP_MASK (
1208	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE ) );
1209	ulRegVal \|= (
1210	BCHP_FIELD_DATA (
1211	SCTE_0_LCR_CONTROLi_BANK0, reserved0 ,
1212	0x0) \|
1213	BCHP_FIELD_ENUM (
1214	SCTE_0_LCR_CONTROLi_BANK0, CC_SHIFT_DIRECTION,
1215	LSB_FIRST) \|
1216	BCHP_FIELD_ENUM (
1217	SCTE_0_LCR_CONTROLi_BANK0, CC_BYTE_ORDER ,
1218	LOW_BYTE_FIRST) \|
1219	BCHP_FIELD_ENUM (
1220	SCTE_0_LCR_CONTROLi_BANK0, CC_PARITY_TYPE ,
1221	ODD) \|
1222	BCHP_FIELD_ENUM (
1223	SCTE_0_LCR_CONTROLi_BANK0, CC_PARITY ,
1224	ENABLE) \|
1225	BCHP_FIELD_ENUM (
1226	SCTE_0_LCR_CONTROLi_BANK0, CC_RUN_IN ,
1227	ENABLE) \|
1228	BCHP_FIELD_ENUM (
1229	SCTE_0_LCR_CONTROLi_BANK0, CC_NULL ,
1230	DISABLE) \|
1231	BCHP_FIELD_DATA (
1232	SCTE_0_LCR_CONTROLi_BANK0, DELAY_COUNT ,
1233	0x24) \|
1234	BCHP_FIELD_ENUM (
1235	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE ,
1236	CC_DATA) );
1237	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1238
1239	/* Locate and program the LCR Data register */
1240	regBankOffset =
1241	BCHP_SCTE_0_LCR_DATAi_BANK1_ARRAY_BASE -
1242	BCHP_SCTE_0_LCR_DATAi_BANK0_ARRAY_BASE;
1243	regLineOffset = 4;
1244	ulRegAddr =
1245	BCHP_SCTE_0_LCR_DATAi_BANK0_ARRAY_BASE + ulCoreOffset +
1246	(regBankOffset * bankIndex) +
1247	(regLineOffset * lineIndex);
1248	dataValue =
1249	(pScteCcData->cc_data_2 << 8) \| pScteCcData->cc_data_1;
1250	ulRegVal = 0x0;
1251	ulRegVal \|=
1252	BCHP_FIELD_DATA (SCTE_0_LCR_DATAi_BANK0, CC_DATA,
1253	dataValue);
1254	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1255	}
1256	}
1257	else if (lineData->eType == BVBI_SCTE_Type_CCNRTV)
1258	{
1259	if (scteType == BVBI_SCTE_Type_CCNRTV)
1260	{
1261	/*
1262	* Process one section of one line of NRTV data
1263	*/
1264	BVBI_P_SCTE_NTRV_Line_Data* pScteNrtvData = &(lineData->d.NRTV);
1265
1266	/* Accumulate section */
1267	for (iBulk = 0 ; iBulk < 2 ; ++iBulk)
1268	{
1269	eErr = BVBI_LineBuilder_Put (
1270	hScteNrtv[iBulk],
1271	pData->nrtv_data[iBulk],
1272	32,
1273	32 * (pScteNrtvData->segment_number - 1),
1274	pScteNrtvData->sequence_number,
1275	lineData->line_number);
1276	if (eErr != BERR_SUCCESS)
1277	return BVBI_LINE_ERROR_SCTE_NODATA;
1278	}
1279
1280	/* Point to the assembled NRTV data, if any */
1281	for (iBulk = 0 ; iBulk < 2 ; ++iBulk)
1282	{
1283	eErr = BVBI_LineBuilder_Get (
1284	hScteNrtv[iBulk], &bulkNrtvData[iBulk],
1285	&nrtv_sequence_number[iBulk], &line_number[iBulk]);
1286	if (eErr != BERR_SUCCESS)
1287	return BVBI_LINE_ERROR_SCTE_NODATA;
1288	}
1289
1290	/* A few sanity checks */
1291	if (nrtv_sequence_number[0] != nrtv_sequence_number[1])
1292	return BVBI_LINE_ERROR_SCTE_NODATA;
1293	if (line_number[0] != line_number[1])
1294	return BVBI_LINE_ERROR_SCTE_NODATA;
1295
1296	/* Debug code
1297	printf (
1298	"Programming LCR bank %d, line %d, seg. no. %d "
1299	"seq. no. (%d %d)\n",
1300	bankIndex, lineIndex, pScteNrtvData->segment_number,
1301	nrtv_sequence_number[0], nrtv_sequence_number[1]);
1302	*/
1303
1304	/* Locate and program the LCR control register */
1305	regBankOffset =
1306	BCHP_SCTE_0_LCR_CONTROLi_BANK1_ARRAY_BASE -
1307	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE;
1308	regLineOffset = 4;
1309	ulRegAddr =
1310	BCHP_SCTE_0_LCR_CONTROLi_BANK0_ARRAY_BASE +
1311	ulCoreOffset +
1312	(regBankOffset * bankIndex) +
1313	(regLineOffset * lineIndex);
1314	ulRegVal = BREG_Read32 (hReg, ulRegAddr);
1315	ulRegVal &= ~(
1316	BCHP_MASK (
1317	SCTE_0_LCR_CONTROLi_BANK0, reserved0 ) \|
1318	BCHP_MASK (
1319	SCTE_0_LCR_CONTROLi_BANK0, DELAY_COUNT ) \|
1320	BCHP_MASK (
1321	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE ) );
1322	ulRegVal \|= (
1323	BCHP_FIELD_DATA (
1324	SCTE_0_LCR_CONTROLi_BANK0, reserved0 ,
1325	0x0) \|
1326	BCHP_FIELD_DATA (
1327	SCTE_0_LCR_CONTROLi_BANK0, DELAY_COUNT ,
1328	0x30) );
1329	if (nrtv_sequence_number[0] == 0)
1330	{
1331	ulRegVal \|=
1332	BCHP_FIELD_ENUM (
1333	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE ,
1334	NO_DATA);
1335	}
1336	else
1337	{
1338	ulRegVal \|=
1339	BCHP_FIELD_ENUM (
1340	SCTE_0_LCR_CONTROLi_BANK0, VBI_DATA_TYPE ,
1341	NRTV_DATA);
1342	}
1343	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1344	}
1345	}
1346	}
1347
1348	/* Transfer persistent NRTV data, if any. */
1349	if ((scteType == BVBI_SCTE_Type_CCNRTV) && (nrtv_sequence_number[0] != 0))
1350	{
1351
1352	/* Write start registers: start them at the beginning. */
1353	regBankOffset =
1354	BCHP_SCTE_0_NRTV_WRITE_PTR_BANK1 -
1355	BCHP_SCTE_0_NRTV_WRITE_PTR_BANK0;
1356	ulRegAddr =
1357	BCHP_SCTE_0_NRTV_WRITE_PTR_BANK0 + ulCoreOffset +
1358	(regBankOffset * bankIndex);
1359	ulRegVal = 0;
1360	ulRegVal \|= (
1361	BCHP_FIELD_DATA (
1362	SCTE_0_NRTV_WRITE_PTR_BANK0, PTR_WR_ENABLE, 0) \|
1363	BCHP_FIELD_DATA (
1364	SCTE_0_NRTV_WRITE_PTR_BANK0, Cb_Cr_WRITE_PTR, 0) \|
1365	BCHP_FIELD_DATA (
1366	SCTE_0_NRTV_WRITE_PTR_BANK0, Y_WRITE_PTR, 0) );
1367	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1368
1369	/* Program DMA addresses */
1370	regBankOffset =
1371	BCHP_SCTE_0_CH0_DMA_ADDR_BANK1 -
1372	BCHP_SCTE_0_CH0_DMA_ADDR_BANK0;
1373	ulRegAddr =
1374	BCHP_SCTE_0_CH0_DMA_ADDR_BANK0 + ulCoreOffset +
1375	(regBankOffset * bankIndex);
1376	eErr = BERR_TRACE (BMEM_ConvertAddressToOffset (
1377	hMem, bulkNrtvData[0], &hardware_offset));
1378	BDBG_ASSERT (eErr == BERR_SUCCESS);
1379	/* Debug code
1380	printf ("Programmed bank %d DMA CH0 address %08x "
1381	"(read pointer was %d)\n",
1382	bankIndex, hardware_offset, ulReadPointer);
1383	printf ("CH0:\n");
1384	for (ulRegVal = 0 ; ulRegVal < 704 ; ++ulRegVal)
1385	printf ("%02x ", bulkNrtvData[0][ulRegVal]);
1386	printf ("\n");
1387	*/
1388	ulRegVal = 0;
1389	ulRegVal \|=
1390	BCHP_FIELD_DATA (SCTE_0_CH0_DMA_ADDR_BANK0, START_ADDR,
1391	hardware_offset);
1392	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1393
1394	ulRegAddr =
1395	BCHP_SCTE_0_CH1_DMA_ADDR_BANK0 + ulCoreOffset +
1396	(regBankOffset * bankIndex);
1397	eErr = BERR_TRACE (BMEM_ConvertAddressToOffset (
1398	hMem, bulkNrtvData[1], &hardware_offset));
1399	BDBG_ASSERT (eErr == BERR_SUCCESS);
1400	/* Debug code
1401	printf ("Programmed bank %d DMA CH1 address %08x "
1402	"(read pointer was %d)\n",
1403	bankIndex, hardware_offset, ulReadPointer);
1404	printf ("CH1:\n");
1405	for (ulRegVal = 0 ; ulRegVal < 704 ; ++ulRegVal)
1406	printf ("%02x ", bulkNrtvData[1][ulRegVal]);
1407	printf ("\n");
1408	*/
1409	ulRegVal = 0;
1410	ulRegVal \|=
1411	BCHP_FIELD_DATA (SCTE_0_CH1_DMA_ADDR_BANK0, START_ADDR,
1412	hardware_offset);
1413	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1414
1415	/* Debug code
1416	printf (" Programming DMA addresses %08x %08x\n",
1417	bulkNrtvData[0], bulkNrtvData[1]);
1418	*/
1419
1420	/* Program DMA length, etc. */
1421	regBankOffset =
1422	BCHP_SCTE_0_CH0_DMA_LENGTH_BANK1 -
1423	BCHP_SCTE_0_CH0_DMA_LENGTH_BANK0;
1424	ulRegAddr = BCHP_SCTE_0_CH0_DMA_LENGTH_BANK0 + ulCoreOffset +
1425	(regBankOffset * bankIndex);
1426	ulRegVal = 0;
1427	ulRegVal \|= (
1428	BCHP_FIELD_DATA (
1429	SCTE_0_CH0_DMA_LENGTH_BANK0, FIELD_NUM, 1) \|
1430	BCHP_FIELD_DATA (
1431	SCTE_0_CH0_DMA_LENGTH_BANK0, RESET, 1) \|
1432	BCHP_FIELD_DATA (
1433	SCTE_0_CH0_DMA_LENGTH_BANK0, LENGTH, 720) );
1434	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1435
1436	regBankOffset =
1437	BCHP_SCTE_0_CH1_DMA_LENGTH_BANK1 -
1438	BCHP_SCTE_0_CH1_DMA_LENGTH_BANK0;
1439	ulRegAddr = BCHP_SCTE_0_CH1_DMA_LENGTH_BANK0 + ulCoreOffset +
1440	(regBankOffset * bankIndex);
1441	ulRegVal = 0;
1442	ulRegVal \|= (
1443	BCHP_FIELD_DATA (
1444	SCTE_0_CH1_DMA_LENGTH_BANK0, RESET, 1) \|
1445	BCHP_FIELD_DATA (
1446	SCTE_0_CH1_DMA_LENGTH_BANK0, LENGTH, 720) );
1447	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1448	}
1449
1450	/* Program PAM registers */
1451	if ((pData->pam_data_count != 0) && (scteType == BVBI_SCTE_Type_CCPAM))
1452	{
1453	uint8_t* sourceArray;
1454	int dma_length;
1455	int field_index = pData->field_number;
1456	int reset = (bankIndex == 0) ? 1 : 0;
1457	BERR_Code eErr = BERR_SUCCESS;
1458
1459	/* Swap PAM bulk data between field handle and VEC encoder handle */
1460	P_SWAP (*pSctePamData, pData->pam_data, sourceArray);
1461	dma_length = pData->pam_data_count;
1462
1463	regBankOffset =
1464	BCHP_SCTE_0_CH0_DMA_ADDR_BANK1 -
1465	BCHP_SCTE_0_CH0_DMA_ADDR_BANK0;
1466	ulRegAddr =
1467	BCHP_SCTE_0_CH0_DMA_ADDR_BANK0 + ulCoreOffset +
1468	(regBankOffset * bankIndex);
1469	eErr = BERR_TRACE (BMEM_ConvertAddressToOffset (
1470	hMem, *pSctePamData, &hardware_offset));
1471	BDBG_ASSERT (eErr == BERR_SUCCESS);
1472	ulRegVal = 0;
1473	ulRegVal \|=
1474	BCHP_FIELD_DATA (SCTE_0_CH0_DMA_ADDR_BANK0, START_ADDR,
1475	hardware_offset);
1476	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1477
1478	regBankOffset =
1479	BCHP_SCTE_0_CH0_DMA_LENGTH_BANK1 -
1480	BCHP_SCTE_0_CH0_DMA_LENGTH_BANK0;
1481	ulRegAddr = BCHP_SCTE_0_CH0_DMA_LENGTH_BANK0 + ulCoreOffset +
1482	(regBankOffset * bankIndex);
1483	ulRegVal = 0;
1484	ulRegVal \|= (
1485	BCHP_FIELD_DATA (
1486	SCTE_0_CH0_DMA_LENGTH_BANK0, FIELD_NUM, field_index) \|
1487	BCHP_FIELD_DATA (
1488	SCTE_0_CH0_DMA_LENGTH_BANK0, RESET, reset) \|
1489	BCHP_FIELD_DATA (
1490	SCTE_0_CH0_DMA_LENGTH_BANK0, LENGTH, dma_length) );
1491	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1492
1493	/* Debug code
1494	printf ("PAM length: register %08x, value %08x\n", ulRegAddr, ulRegVal);
1495	*/
1496	}
1497
1498	/* TODO: monochrome data. */
1499
1500	/* Program the write pointer into hardware */
1501	++ulWritePointer;
1502	ulWritePointer &= 0x7;
1503	ulRegVal =
1504	BCHP_FIELD_DATA (SCTE_0_BANK_CONTROL, WRITE_PTR, ulWritePointer);
1505	BREG_Write32 (hReg, BCHP_SCTE_0_BANK_CONTROL + ulCoreOffset, ulRegVal);
1506
1507	/* Debug code
1508	ulRegVal = BREG_Read32 (hReg, BCHP_SCTE_0_BANK_CONTROL + ulCoreOffset);
1509	ulWritePointer =
1510	BCHP_GET_FIELD_DATA (ulRegVal, SCTE_0_BANK_CONTROL, WRITE_PTR);
1511	dwrite_pointer[1] = ulWritePointer;
1512	ulRegVal = BREG_Read32 (hReg, BCHP_SCTE_0_FIFO_STATUS + ulCoreOffset);
1513	dread_pointer[1] =
1514	BCHP_GET_FIELD_DATA (ulRegVal, SCTE_0_FIFO_STATUS, READ_PTR);
1515	printf ("Programming complete: R/W pointers now %d/%d\n",
1516	dread_pointer[1], dwrite_pointer[1]);
1517	printf (
1518	"Field %c: R/W (%d/%d) --> (%d/%d)\n",
1519	((polarity == BAVC_Polarity_eTopField) ? 'T' : 'B'),
1520	dread_pointer[0], dwrite_pointer[0],
1521	dread_pointer[1], dwrite_pointer[1]);
1522	*/
1523
1524	BDBG_LEAVE(BVBI_P_SCTE_Encode_Data_isr);
1525	return 0x0;
1526
1527	#else / } ! BVBI_P_NUM_SCTEE { /
1528
1529	BSTD_UNUSED (hMem);
1530	BSTD_UNUSED (hReg);
1531	BSTD_UNUSED (is656);
1532	BSTD_UNUSED (hwCoreIndex);
1533	BSTD_UNUSED (eVideoFormat);
1534	BSTD_UNUSED (polarity);
1535	BSTD_UNUSED (scteType);
1536	BSTD_UNUSED (pData);
1537	BSTD_UNUSED (pSctePamData);
1538	BSTD_UNUSED (hTopScteNrtv);
1539	BSTD_UNUSED (hBotScteNrtv);
1540	BSTD_UNUSED (hTopScteMono);
1541	BSTD_UNUSED (hBotScteMono);
1542
1543	return (-1);
1544
1545	#endif / } BVBI_P_NUM_SCTEE /
1546	}
1547
1548	/***************************************************************************
1549	*
1550	*/
1551	BERR_Code BVBI_P_SCTE_Encode_Enable_isr (
1552	BREG_Handle hReg,
1553	bool is656,
1554	uint8_t hwCoreIndex,
1555	BFMT_VideoFmt eVideoFormat,
1556	BVBI_SCTE_Type scteType,
1557	bool bEnable)
1558	{
1559	#if (BVBI_P_NUM_SCTEE > 0) / { /
1560
1561	uint32_t ulCoreOffset;
1562	uint32_t ulSctee_controlReg;
1563
1564	BSTD_UNUSED (eVideoFormat);
1565
1566	BDBG_ENTER(BVBI_P_SCTE_Encode_Enable_isr);
1567
1568	/* Figure out which encoder core to use */
1569	ulCoreOffset = P_GetCoreOffset (hwCoreIndex);
1570	if (is656 \|\| (ulCoreOffset == 0xFFFFFFFF))
1571	{
1572	/* This should never happen! This parameter was checked by
1573	BVBI_Encode_Create() */
1574	BDBG_LEAVE(BVBI_P_SCTE_Encode_Enable_isr);
1575	return BERR_TRACE(BERR_INVALID_PARAMETER);
1576	}
1577
1578	ulSctee_controlReg =
1579	BREG_Read32 (hReg, BCHP_SCTE_0_CONFIG + ulCoreOffset);
1580	ulSctee_controlReg &= ~(
1581	BCHP_MASK (SCTE_0_CONFIG, VBI_MODE) );
1582	if (bEnable)
1583	{
1584	ulSctee_controlReg \|= (
1585	BCHP_FIELD_DATA (SCTE_0_CONFIG, VBI_MODE, scteType) );
1586	}
1587	else
1588	{
1589	ulSctee_controlReg \|= (
1590	BCHP_FIELD_ENUM (SCTE_0_CONFIG, VBI_MODE, DISABLE) );
1591	}
1592	BREG_Write32 (
1593	hReg, BCHP_SCTE_0_CONFIG + ulCoreOffset, ulSctee_controlReg);
1594
1595	BDBG_LEAVE(BVBI_P_SCTE_Encode_Enable_isr);
1596	return BERR_SUCCESS;
1597
1598	#else / } ! BVBI_P_NUM_SCTEE { /
1599
1600	BSTD_UNUSED (hReg);
1601	BSTD_UNUSED (is656);
1602	BSTD_UNUSED (hwCoreIndex);
1603	BSTD_UNUSED (eVideoFormat);
1604	BSTD_UNUSED (scteType);
1605	BSTD_UNUSED (bEnable);
1606
1607	return BERR_TRACE (BVBI_ERR_HW_UNSUPPORTED);
1608
1609	#endif / } BVBI_P_NUM_SCTEE /
1610	}
1611
1612
1613	/***************************************************************************
1614	* Static (private) functions
1615	***************************************************************************/
1616
1617
1618	/***************************************************************************
1619	*
1620	*/
1621	#if (BVBI_P_NUM_SCTEE > 0) / { /
1622	static void BVBI_P_ProgramNull (
1623	BREG_Handle hReg, uint32_t coreOffset,
1624	uint32_t ulWritePointer, uint32_t value)
1625	{
1626	uint32_t ulRegAddr;
1627	uint32_t ulRegVal = BCHP_FIELD_DATA (SCTE_0_CC_NULL_BANK0, VALUE, value);
1628
1629	switch (ulWritePointer & 0x3)
1630	{
1631	case 0:
1632	ulRegAddr = BCHP_SCTE_0_CC_NULL_BANK0;
1633	break;
1634	case 1:
1635	ulRegAddr = BCHP_SCTE_0_CC_NULL_BANK1;
1636	break;
1637	case 2:
1638	ulRegAddr = BCHP_SCTE_0_CC_NULL_BANK2;
1639	break;
1640	case 3:
1641	ulRegAddr = BCHP_SCTE_0_CC_NULL_BANK3;
1642	break;
1643	default:
1644	/* Should never happen! Programming error! */
1645	BDBG_ASSERT (false);
1646	ulRegAddr = BCHP_SCTE_0_CC_NULL_BANK0;
1647	break;
1648	}
1649	ulRegAddr += coreOffset;
1650
1651	BREG_Write32 (hReg, ulRegAddr, ulRegVal);
1652	}
1653	#endif / } BVBI_P_NUM_SCTEE /
1654
1655	#if (BVBI_P_NUM_SCTEE > 0) / { /
1656	/***************************************************************************
1657	*
1658	*/
1659	static bool BVBI_P_HasComponentOnly (uint8_t hwCoreIndex)
1660	{
1661	bool retval;
1662
1663	switch (hwCoreIndex)
1664	{
1665	case 0:
1666	#if (BCHP_CHIP == 7400)
1667	retval = false;
1668	#elif (BCHP_CHIP == 7405)
1669	retval = false;
1670	#else
1671	retval = false;
1672	#endif
1673	break;
1674
1675	#if (BVBI_P_NUM_SCTEE >= 2)
1676	case 1:
1677	#if (BCHP_CHIP == 7400)
1678	retval = true;
1679	#else
1680	retval = false;
1681	#endif
1682	break;
1683	#endif
1684	#if (BVBI_P_NUM_SCTEE >= 2)
1685	case BAVC_VbiPath_eVec2:
1686	#if (BCHP_CHIP == 7400)
1687	retval = false;
1688	#else
1689	retval = false;
1690	#endif
1691	break;
1692	#endif
1693	default:
1694	/* This should never happen! This parameter was checked by
1695	BVBI_Encode_Create() */
1696	BDBG_ASSERT(0);
1697	retval = false;
1698	break;
1699	}
1700
1701	return retval;
1702	}
1703	#endif / } BVBI_P_NUM_SCTEE /
1704
1705	#if (BVBI_P_NUM_SCTEE > 0) / { /
1706	/***************************************************************************
1707	*
1708	*/
1709	static uint32_t P_GetCoreOffset (uint8_t hwCoreIndex)
1710	{
1711	uint32_t ulCoreOffset = 0xFFFFFFFF;
1712
1713	switch (hwCoreIndex)
1714	{
1715	#if (BVBI_P_NUM_SCTEE >= 1)
1716	case 0:
1717	ulCoreOffset = 0;
1718	break;
1719	#endif
1720	#if (BVBI_P_NUM_SCTEE >= 2)
1721	case 1:
1722	ulCoreOffset = (BCHP_SCTE_1_REVID - BCHP_SCTE_0_REVID);
1723	break;
1724	#endif
1725	#if (BVBI_P_NUM_SCTEE >= 3)
1726	case 2:
1727	ulCoreOffset = (BCHP_SCTE_2_REVID - BCHP_SCTE_0_REVID);
1728	break;
1729	#endif
1730	default:
1731	break;
1732	}
1733
1734	return ulCoreOffset;
1735	}
1736	#endif / } BVBI_P_NUM_SCTEE /

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_sctee.c

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