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bvbi_top.c

Last change on this file was 2, checked in by jglee, 11 years ago
first commit
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_top.c $
11	* $brcm_Revision: Hydra_Software_Devel/4 $
12	* $brcm_Date: 2/20/12 12:55p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7400/bvbi_top.c $
19	*
20	* Hydra_Software_Devel/4 2/20/12 12:55p darnstein
21	* SW7425-2434: when an unsupported video format is entered, the BDBG
22	* error message should be informative.
23	*
24	* Hydra_Software_Devel/3 12/21/09 7:05p darnstein
25	* SW7550-120: Add support for SECAM variants.
26	*
27	* Hydra_Software_Devel/2 12/3/08 7:57p darnstein
28	* PR45819: New, more modular form of most BVBI source files.
29	*
30	* Hydra_Software_Devel/23 6/26/08 7:51p darnstein
31	* PR40710: update for 50 Hz HDTV video formats.
32	*
33	* Hydra_Software_Devel/22 4/2/08 7:55p darnstein
34	* PR38956: VBI software compiles now.
35	*
36	* Hydra_Software_Devel/21 1/2/08 2:28p darnstein
37	* PR32758: PAL VBI decoding starts very late in each video field. This is
38	* to give the TTD core lots of time to do its job. I might be able to
39	* reduce the delay later.
40	*
41	* Hydra_Software_Devel/20 4/9/07 8:26p darnstein
42	* PR23254: Fix programming of top level decoder core for second VDEC.
43	*
44	* Hydra_Software_Devel/19 1/2/07 4:20p darnstein
45	* PR26872: Mechanically add SECAM to all cases where PAL formats are
46	* accepted.
47	*
48	* Hydra_Software_Devel/18 11/20/06 5:53p darnstein
49	* PR20428: Fix silly typos in previous checkin.
50	*
51	* Hydra_Software_Devel/17 11/16/06 4:41p darnstein
52	* PR20428: Change the way interrupts for progressive video input is
53	* handled. This might have to be revisited.
54	*
55	* Hydra_Software_Devel/16 11/2/06 5:21p darnstein
56	* PR23178: Merge back to main branch.
57	*
58	* Hydra_Software_Devel/Refsw_Devel_3563/1 11/2/06 3:19p darnstein
59	* PR23178: adapt to recent changes in the 3563 branch of BVDC.
60	*
61	* Hydra_Software_Devel/15 8/18/06 6:51p darnstein
62	* PR23178: basic compile on 93563 is possible.
63	*
64	* Hydra_Software_Devel/14 3/9/06 2:02p darnstein
65	* PR 20088: streamline the way that existence of EXT_656_TOP chip core is
66	* handled.
67	*
68	* Hydra_Software_Devel/13 9/23/05 2:47p darnstein
69	* PR13750: Proper use of BERR_TRACE and BERR_CODEs.
70	*
71	* Hydra_Software_Devel/12 9/19/05 2:57p darnstein
72	* PR17151: Check for chip name where needed. Also, convert to new scheme
73	* for testing chip revisions (BCHP_VER).
74	*
75	* Hydra_Software_Devel/11 4/13/05 8:38p darnstein
76	* PR 14720: Modify #defines to account for 7038-B2 and 7038-C0 chip
77	* revisions. Compiles OK now. But untested!
78	*
79	* Hydra_Software_Devel/10 3/17/05 6:39p darnstein
80	* PR 14426: use new _0 names for VDEC cores.
81	*
82	* Hydra_Software_Devel/9 3/17/05 6:27p darnstein
83	* PR 14426: use new _0 names for VDEC cores.
84	*
85	* Hydra_Software_Devel/8 3/9/05 3:44p darnstein
86	* PR 11440: fix errors involving ITU-R 656 input and output.
87	*
88	* Hydra_Software_Devel/7 1/5/05 4:27p jasonh
89	* PR 13700: Fixed VBI compile issues for 7038 C0.
90	*
91	* Hydra_Software_Devel/6 7/16/04 7:07p darnstein
92	* PR 9080: merge in 656 input and output work. Some testing and debugging
93	* remains to be done.
94	*
95	* Hydra_Software_Devel/I656/1 7/8/04 7:45p darnstein
96	* ITU-R 656 decoding of VBI seems to be ready for bring up. Expect bugs.
97	*
98	* Hydra_Software_Devel/5 5/24/04 5:08p jasonh
99	* PR 11189: Merge down from B0 to main-line
100	*
101	* Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/19/04 2:45p darnstein
102	* PR 9080: Compilation is possible with 7038 B0. Correct execution is not
103	* likely.
104	*
105	* Hydra_Software_Devel/4 4/2/04 6:42p darnstein
106	* PR 9080: Allow NTSC-J video format.
107	*
108	* Hydra_Software_Devel/3 3/26/04 1:50p darnstein
109	* PR 9080: Adjust which line interrupt fires on. I don't think this is
110	* the optimal setting.
111	*
112	* Hydra_Software_Devel/2 3/18/04 10:41a darnstein
113	* PR 9080: first working version.
114	*
115	* Hydra_Software_Devel/1 12/19/03 5:04p darnstein
116	* PR 9080: initial version.
117	*
118	***************************************************************************/
119	#include "bstd.h" /* standard types */
120	#include "bdbg.h" /* Dbglib */
121	#include "bvbi.h" /* VBI processing, this module. */
122	#include "bkni.h" /* For critical sections */
123	#include "bvbi_priv.h" /* VBI internal data structures */
124
125	#if (BVBI_P_NUM_VDEC >= 1) / { /
126
127	#include "bchp_vd_top_0.h" /* RDB info for VD_TOP_0 registers */
128	#ifdef BVBI_P_HAS_FE_BE
129	#include "bchp_vdec_be_0.h"
130	#if (BVBI_P_NUM_VDEC >= 2)
131	#include "bchp_vdec_be_1.h"
132	#endif
133	#endif
134	#ifdef BVBI_P_HAS_EXT_656
135	#include "bchp_ext_656_top_0.h"
136	#endif
137
138	BDBG_MODULE(BVBI);
139
140
141	/***************************************************************************
142	* Forward declarations of static (private) functions
143	***************************************************************************/
144
145
146	/***************************************************************************
147	* Implementation of "BVBI_" API functions
148	***************************************************************************/
149
150
151	/***************************************************************************
152	* Implementation of supporting VD_TOP functions that are not in API
153	***************************************************************************/
154
155
156	BERR_Code BVBI_P_VDTOP_Dec_Program (
157	BREG_Handle hReg,
158	BAVC_SourceId eSource,
159	BFMT_VideoFmt eVideoFormat)
160	{
161	/*
162	Programming note: the implementation here assumes that the bitfield layout
163	within registers is the same for all VD_TOP cores in the chip.
164
165	If a chip is built that has multiple VD_TOP decoder cores that are not
166	identical, then this routine will have to be redesigned.
167	*/
168	uint32_t ulOffset;
169	uint32_t ulReg;
170	uint32_t topLine;
171	uint32_t botLine;
172
173	BDBG_ENTER(BVBI_P_VDTOP_Dec_Program);
174
175	/* Figure out which decoder core to use */
176	switch (eSource)
177	{
178	case BAVC_SourceId_eVdec0:
179	ulOffset = 0;
180	break;
181	#if (BVBI_P_NUM_VDEC > 1)
182	case BAVC_SourceId_eVdec1:
183	#ifdef BVBI_P_HAS_FE_BE
184	ulOffset = BCHP_VDEC_BE_1_BE_REV_ID - BCHP_VDEC_BE_0_BE_REV_ID;
185	#else
186	ulOffset = BCHP_VD_TOP_1_VD_REV_ID - BCHP_VD_TOP_0_VD_REV_ID;
187	#endif
188	break;
189	#endif
190	default:
191	/* This should never happen! This parameter was checked by
192	BVBI_Decode_Create() */
193	BDBG_LEAVE(BVBI_P_VDTOP_Dec_Program);
194	return BERR_TRACE(BERR_INVALID_PARAMETER);
195	break;
196	}
197
198	/* Prepare to program the interrupt control register */
199	#ifdef BVBI_P_HAS_FE_BE
200	ulReg =
201	BREG_Read32 ( hReg, BCHP_VDEC_BE_0_VDEC_INTERRUPT + ulOffset );
202	#else
203	ulReg =
204	BREG_Read32 ( hReg, BCHP_VD_TOP_0_vd_vdec_interrupt + ulOffset );
205	#endif
206
207	/* Select video format */
208	switch (eVideoFormat)
209	{
210	case BFMT_VideoFmt_eNTSC:
211	case BFMT_VideoFmt_eNTSC_J:
212	topLine = 30;
213	botLine = 30;
214	break;
215
216	case BFMT_VideoFmt_e1080i:
217	case BFMT_VideoFmt_e1080i_50Hz:
218	topLine = 23;
219	botLine = 23;
220	break;
221
222	case BFMT_VideoFmt_e720p:
223	case BFMT_VideoFmt_e720p_50Hz:
224	topLine = 30;
225	botLine = 30;
226	break;
227
228	case BFMT_VideoFmt_e480p:
229	topLine = 45;
230	botLine = 45;
231	break;
232
233	case BFMT_VideoFmt_ePAL_B:
234	case BFMT_VideoFmt_ePAL_B1:
235	case BFMT_VideoFmt_ePAL_D:
236	case BFMT_VideoFmt_ePAL_D1:
237	case BFMT_VideoFmt_ePAL_G:
238	case BFMT_VideoFmt_ePAL_H:
239	case BFMT_VideoFmt_ePAL_K:
240	case BFMT_VideoFmt_ePAL_I:
241	case BFMT_VideoFmt_ePAL_M:
242	case BFMT_VideoFmt_ePAL_N:
243	case BFMT_VideoFmt_ePAL_NC:
244	case BFMT_VideoFmt_eSECAM_L:
245	case BFMT_VideoFmt_eSECAM_B:
246	case BFMT_VideoFmt_eSECAM_G:
247	case BFMT_VideoFmt_eSECAM_D:
248	case BFMT_VideoFmt_eSECAM_K:
249	case BFMT_VideoFmt_eSECAM_H:
250	topLine = 100;
251	botLine = 100;
252	break;
253
254	default:
255	BDBG_LEAVE(BVBI_P_VDTOP_Dec_Program);
256	BDBG_ERR(("video format %d not supported", eVideoFormat));
257	return BERR_TRACE (BERR_NOT_SUPPORTED);
258	break;
259	}
260
261	/* Finish programming the interrupt control register */
262	#ifdef BVBI_P_HAS_FE_BE / { /
263	ulReg &= ~(
264	BCHP_MASK (VDEC_BE_0_VDEC_INTERRUPT, FIELD_1 ) \|
265	BCHP_MASK (VDEC_BE_0_VDEC_INTERRUPT, FIELD_0 )
266	);
267	ulReg \|= (
268	BCHP_FIELD_DATA(VDEC_BE_0_VDEC_INTERRUPT, FIELD_1, botLine) \|
269	BCHP_FIELD_DATA(VDEC_BE_0_VDEC_INTERRUPT, FIELD_0, topLine)
270	);
271	BREG_Write32 (hReg, BCHP_VDEC_BE_0_VDEC_INTERRUPT + ulOffset, ulReg);
272	#else / } BVBI_P_HAS_FE_BE { /
273	ulReg &= ~(
274	BCHP_MASK (VD_TOP_0_vd_vdec_interrupt, field_1 ) \|
275	BCHP_MASK (VD_TOP_0_vd_vdec_interrupt, field_0 )
276	);
277	ulReg \|= (
278	BCHP_FIELD_DATA(VD_TOP_0_vd_vdec_interrupt, field_0, topLine) \|
279	BCHP_FIELD_DATA(VD_TOP_0_vd_vdec_interrupt, field_1, botLine)
280	);
281	BREG_Write32 (hReg, BCHP_VD_TOP_0_vd_vdec_interrupt + ulOffset, ulReg);
282	#endif / } BVBI_P_HAS_FE_BE /
283
284	BDBG_LEAVE(BVBI_P_VDTOP_Dec_Program);
285	return BERR_SUCCESS;
286	}
287
288	BERR_Code BVBI_P_VDTOP_Dec_Reset (
289	BREG_Handle hReg,
290	BAVC_SourceId eSource,
291	uint32_t whichStandard)
292	{
293	/*
294	Programming note: the implementation here assumes that the bitfield layout
295	within registers is the same for all VD_TOP cores in the chip.
296
297	If a chip is built that has multiple VD_TOP decoder cores that are not
298	identical, then this routine will have to be redesigned.
299	*/
300	uint32_t ulOffset;
301	uint32_t ulReg = 0x0;
302
303	BDBG_ENTER(BVBI_P_VDTOP_Dec_Reset);
304
305	/* Figure out which decoder core to use */
306	switch (eSource)
307	{
308	case BAVC_SourceId_eVdec0:
309	ulOffset = 0;
310	break;
311	#if (BVBI_P_NUM_VDEC > 1)
312	case BAVC_SourceId_eVdec1:
313	ulOffset = BCHP_VD_TOP_0_VBI1_RESET - BCHP_VD_TOP_0_VBI0_RESET;
314	break;
315	#endif
316	default:
317	/* This should never happen! This parameter was checked by
318	BVBI_Decode_Create() */
319	BDBG_LEAVE(BVBI_P_VDTOP_Dec_Reset);
320	return BERR_TRACE(BERR_INVALID_PARAMETER);
321	break;
322	}
323
324	/* Prepare to reset cores of user's choosing */
325	if ((whichStandard & BVBI_P_SELECT_CC) != 0x0)
326	ulReg \|= BCHP_VD_TOP_0_VBI0_RESET_CCD_MASK;
327	if ((whichStandard & BVBI_P_SELECT_CGMSA) != 0x0)
328	ulReg \|= BCHP_VD_TOP_0_VBI0_RESET_CGMSA_MASK;
329	if ((whichStandard & BVBI_P_SELECT_CGMSB) != 0x0)
330	ulReg \|= BCHP_VD_TOP_0_VBI0_RESET_CGMSA_MASK;
331	if ((whichStandard & BVBI_P_SELECT_TT) != 0x0)
332	ulReg \|= BCHP_VD_TOP_0_VBI0_RESET_TTX_MASK;
333	if ((whichStandard & BVBI_P_SELECT_WSS) != 0x0)
334	ulReg \|= BCHP_VD_TOP_0_VBI0_RESET_WSS_MASK;
335	if ((whichStandard & BVBI_P_SELECT_GS) != 0x0)
336	ulReg \|= BCHP_VD_TOP_0_VBI0_RESET_GSD_MASK;
337
338	/* Write the register twice to effect reset */
339	BREG_Write32 (hReg, BCHP_VD_TOP_0_VBI0_RESET + ulOffset, ulReg);
340	BREG_Write32 (hReg, BCHP_VD_TOP_0_VBI0_RESET + ulOffset, 0x00000000);
341
342	BDBG_LEAVE(BVBI_P_VDTOP_Dec_Reset);
343	return BERR_SUCCESS;
344	}
345
346
347	BERR_Code BVBI_P_VDTOP_656_Dec_Program (
348	BREG_Handle hReg,
349	BAVC_SourceId eSource,
350	BFMT_VideoFmt eVideoFormat)
351	{
352	/*
353	Programming note: the implementation here assumes that the bitfield layout
354	within registers is the same for all VD_TOP cores in the chip.
355
356	If a chip is built that has multiple VBI_VD_TOP decoder cores that are not
357	identical, then this routine will have to be redesigned.
358	*/
359	uint32_t ulOffset;
360	uint32_t ulReg;
361	uint32_t topLine;
362	uint32_t botLine;
363
364	BDBG_ENTER(BVBI_P_VDTOP_656_Dec_Program);
365
366	/* Figure out which decoder core to use */
367	switch (eSource)
368	{
369	case BAVC_SourceId_e656In0:
370	ulOffset = 0;
371	break;
372	#if (BVBI_P_NUM_VDEC > 1)
373	case BAVC_SourceId_eVdec1:
374	#ifdef BVBI_P_HAS_FE_BE
375	ulOffset = BCHP_VDEC_BE_1_BE_REV_ID - BCHP_VDEC_BE_0_BE_REV_ID;
376	#else
377	ulOffset = BCHP_VD_TOP_1_VD_REV_ID - BCHP_VD_TOP_0_VD_REV_ID;
378	#endif
379	break;
380	#endif
381	default:
382	/* This should never happen! This parameter was checked by
383	BVBI_Decode_Create() */
384	BDBG_LEAVE(BVBI_P_VDTOP_656_Dec_Program);
385	return BERR_TRACE(BERR_INVALID_PARAMETER);
386	break;
387	}
388
389	/* Prepare to program the interrupt control register */
390	ulReg =
391	#ifdef BVBI_P_HAS_EXT_656
392	BREG_Read32 ( hReg, BCHP_EXT_656_TOP_0_ext_656_interrupt + ulOffset );
393	#else
394	BREG_Read32 ( hReg, BCHP_VD_TOP_0_vd_656_interrupt + ulOffset );
395	#endif
396
397	/* Select video format */
398	switch (eVideoFormat)
399	{
400	case BFMT_VideoFmt_eNTSC:
401	case BFMT_VideoFmt_eNTSC_J:
402	/* NTSC specific settings */
403	topLine = 34;
404	botLine = 34;
405	break;
406
407	case BFMT_VideoFmt_e1080i:
408	case BFMT_VideoFmt_e1080i_50Hz:
409	topLine = 27;
410	botLine = 27;
411	break;
412
413	case BFMT_VideoFmt_e720p:
414	case BFMT_VideoFmt_e720p_50Hz:
415	topLine = 0;
416	botLine = 34;
417	break;
418
419	case BFMT_VideoFmt_e480p:
420	topLine = 0;
421	botLine = 49;
422	break;
423
424	case BFMT_VideoFmt_ePAL_B:
425	case BFMT_VideoFmt_ePAL_B1:
426	case BFMT_VideoFmt_ePAL_D:
427	case BFMT_VideoFmt_ePAL_D1:
428	case BFMT_VideoFmt_ePAL_G:
429	case BFMT_VideoFmt_ePAL_H:
430	case BFMT_VideoFmt_ePAL_K:
431	case BFMT_VideoFmt_ePAL_I:
432	case BFMT_VideoFmt_ePAL_M:
433	case BFMT_VideoFmt_ePAL_N:
434	case BFMT_VideoFmt_ePAL_NC:
435	case BFMT_VideoFmt_eSECAM_L:
436	case BFMT_VideoFmt_eSECAM_B:
437	case BFMT_VideoFmt_eSECAM_G:
438	case BFMT_VideoFmt_eSECAM_D:
439	case BFMT_VideoFmt_eSECAM_K:
440	case BFMT_VideoFmt_eSECAM_H:
441	topLine = 100;
442	botLine = 100;
443	break;
444
445	default:
446	BDBG_LEAVE(BVBI_P_VDTOP_656_Dec_Program);
447	BDBG_ERR(("video format %d not supported", eVideoFormat));
448	return BERR_TRACE (BERR_NOT_SUPPORTED);
449	break;
450	}
451
452	/* Finish programming the interrupt control register */
453	#ifdef BVBI_P_HAS_EXT_656
454	ulReg &= ~(
455	BCHP_MASK (EXT_656_TOP_0_ext_656_interrupt, field_1 ) \|
456	BCHP_MASK (EXT_656_TOP_0_ext_656_interrupt, field_0 )
457	);
458	ulReg \|= (
459	BCHP_FIELD_DATA(EXT_656_TOP_0_ext_656_interrupt, field_1, botLine) \|
460	BCHP_FIELD_DATA(EXT_656_TOP_0_ext_656_interrupt, field_0, topLine)
461	);
462	BREG_Write32 (hReg, BCHP_EXT_656_TOP_0_ext_656_interrupt + ulOffset, ulReg);
463	#else
464	ulReg &= ~(
465	BCHP_MASK (VD_TOP_0_vd_656_interrupt, field_1 ) \|
466	BCHP_MASK (VD_TOP_0_vd_656_interrupt, field_0 )
467	);
468	ulReg \|= (
469	BCHP_FIELD_DATA(VD_TOP_0_vd_656_interrupt, field_1, botLine) \|
470	BCHP_FIELD_DATA(VD_TOP_0_vd_656_interrupt, field_0, topLine)
471	);
472	BREG_Write32 (hReg, BCHP_VD_TOP_0_vd_656_interrupt + ulOffset, ulReg);
473	#endif
474
475
476	BDBG_LEAVE(BVBI_P_VDTOP_656_Dec_Program);
477	return BERR_SUCCESS;
478	}
479
480	/***************************************************************************
481	* Static (private) functions
482	***************************************************************************/
483
484	#endif / } (BVBI_P_NUM_VDEC >= 1) /
485
486	/* End of file */

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_top.c

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