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bvbi_vpse.c

Last change on this file was 2, checked in by jglee, 11 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_vpse.c $
11	* $brcm_Revision: Hydra_Software_Devel/6 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_vpse.c $
19	*
20	* Hydra_Software_Devel/6 2/20/12 2:53p darnstein
21	* SW7425-2434: more detail in error messages.
22	*
23	* Hydra_Software_Devel/5 2/20/12 12:56p darnstein
24	* SW7425-2434: when an unsupported video format is entered, the BDBG
25	* error message should be informative.
26	*
27	* Hydra_Software_Devel/4 12/21/09 7:02p darnstein
28	* SW7550-120: Add support for SECAM variants.
29	*
30	* Hydra_Software_Devel/3 3/27/09 7:43p darnstein
31	* PR53635: Remove internal ConfigForOthers code. It is obsolete, and it
32	* was causing a problem (this PR).
33	*
34	* Hydra_Software_Devel/2 12/4/08 6:07p darnstein
35	* PR45819: 7420 software will now compile, but not link.
36	*
37	* Hydra_Software_Devel/1 12/3/08 8:03p darnstein
38	* PR45819:
39	*
40	***************************************************************************/
41
42	#include "bstd.h" /* standard types */
43	#include "bdbg.h" /* Dbglib */
44	#include "bkni.h" /* For critical sections */
45	#include "bvbi.h" /* VBI processing, this module. */
46	#include "bvbi_priv.h" /* VBI internal data structures */
47	#if (BVBI_P_NUM_WSE >= 1)
48	#include "bchp_wse_0.h" /* RDB info for primary WSE core */
49	#endif
50	#if (BVBI_P_NUM_WSE >= 2)
51	#include "bchp_wse_1.h" /* RDB info for secondary WSE core */
52	#endif
53	#if (BVBI_P_NUM_WSE >= 3)
54	#include "bchp_wse_2.h" /* RDB info for tertiary WSE core */
55	#endif
56
57	BDBG_MODULE(BVBI);
58
59
60	/***************************************************************************
61	* Forward declarations of static (private) functions
62	***************************************************************************/
63	static uint32_t P_GetCoreOffset (uint8_t hwCoreIndex);
64
65
66	/***************************************************************************
67	* Implementation of supporting VPS functions that are not in API
68	***************************************************************************/
69
70
71	/***************************************************************************
72	*
73	*/
74	void BVBI_P_VPS_Enc_Init (BREG_Handle hReg, uint8_t hwCoreIndex)
75	{
76	uint32_t ulCoreOffset;
77	uint32_t ulControlReg;
78	uint32_t ulActiveLine;
79
80	BDBG_ENTER(BVBI_P_VPS_Enc_Init);
81
82	/* No reset here. There is a reset in BVBI_P_WSS_Enc_Init(),though. */
83
84	/* Determine which core to access */
85	ulCoreOffset = P_GetCoreOffset (hwCoreIndex);
86	if (ulCoreOffset == 0xFFFFFFFF)
87	{
88	/* This should never happen! This parameter was checked by
89	BVBI_Encode_Create() */
90	BDBG_ASSERT (0);
91	}
92
93	ulActiveLine = 16 - 1;
94
95	BKNI_EnterCriticalSection();
96
97	/* Program the control register */
98	ulControlReg = BREG_Read32 (hReg, BCHP_WSE_0_vps_control + ulCoreOffset);
99	ulControlReg &= ~(
100	BCHP_MASK (WSE_0_vps_control, vps_bit_order ) \|
101	BCHP_MASK (WSE_0_vps_control, invert_data ) \|
102	BCHP_MASK (WSE_0_vps_control, active_line ) \|
103	BCHP_MASK (WSE_0_vps_control, start_delay ) \|
104	BCHP_MASK (WSE_0_vps_control, enable ) );
105	ulControlReg \|= (
106	BCHP_FIELD_ENUM (WSE_0_vps_control, vps_bit_order, msb_to_lsb) \|
107	BCHP_FIELD_ENUM (WSE_0_vps_control, invert_data, Off) \|
108	BCHP_FIELD_DATA (WSE_0_vps_control, active_line, ulActiveLine) \|
109	BCHP_FIELD_DATA (WSE_0_vps_control, start_delay, 1) \|
110	BCHP_FIELD_DATA (WSE_0_vps_control, enable, 0) );
111	BREG_Write32 (hReg, BCHP_WSE_0_vps_control + ulCoreOffset, ulControlReg);
112
113	BKNI_LeaveCriticalSection();
114
115	BDBG_LEAVE(BVBI_P_VPS_Enc_Init);
116	}
117
118	BERR_Code BVBI_P_VPS_Enc_Program (
119	BREG_Handle hReg,
120	bool is656,
121	uint8_t hwCoreIndex,
122	bool bActive,
123	BFMT_VideoFmt eVideoFormat)
124	{
125	/*
126	Programming note: the implementation here assumes that the bitfield layout
127	within registers is the same for all VPS encoder cores in the chip.
128
129	If a chip is built that has multiple VPS encoder cores that are not
130	identical, then this routine will have to be redesigned.
131	*/
132	BERR_Code eErr;
133
134	BDBG_ENTER(BVBI_P_VPS_Enc_Program);
135
136	/* Take care of a special case for 656 programming */
137	#if (BVBI_P_NUM_WSE_656 >= 1)
138	if (is656)
139	{
140	BDBG_LEAVE(BVBI_P_VPS_Enc_Program);
141	if (bActive)
142	{
143	/* No bypass encoder for VPS */
144	return BERR_TRACE(BERR_INVALID_PARAMETER);
145	}
146	else
147	{
148	return BERR_SUCCESS;
149	}
150	}
151	#endif
152
153	/* Complain if video format is not supported */
154	switch (eVideoFormat)
155	{
156	case BFMT_VideoFmt_ePAL_B:
157	case BFMT_VideoFmt_ePAL_B1:
158	case BFMT_VideoFmt_ePAL_D:
159	case BFMT_VideoFmt_ePAL_D1:
160	case BFMT_VideoFmt_ePAL_G:
161	case BFMT_VideoFmt_ePAL_H:
162	case BFMT_VideoFmt_ePAL_K:
163	case BFMT_VideoFmt_ePAL_I:
164	case BFMT_VideoFmt_ePAL_M:
165	case BFMT_VideoFmt_ePAL_N:
166	case BFMT_VideoFmt_ePAL_NC:
167	case BFMT_VideoFmt_eSECAM_L:
168	case BFMT_VideoFmt_eSECAM_B:
169	case BFMT_VideoFmt_eSECAM_G:
170	case BFMT_VideoFmt_eSECAM_D:
171	case BFMT_VideoFmt_eSECAM_K:
172	case BFMT_VideoFmt_eSECAM_H:
173	break;
174
175	default:
176	if (bActive)
177	{
178	BDBG_ERR(("BVBI_VPSE: video format %d not supported",
179	eVideoFormat));
180	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
181	}
182	}
183
184	BKNI_EnterCriticalSection();
185	eErr = BERR_TRACE (BVBI_P_VPS_Encode_Enable_isr (
186	hReg, is656, hwCoreIndex, BFMT_VideoFmt_ePAL_G, bActive));
187	BKNI_LeaveCriticalSection();
188	if (eErr != BERR_SUCCESS)
189	goto done;
190
191	done:
192	BDBG_LEAVE(BVBI_P_VPS_Enc_Program);
193	return eErr;
194	}
195
196	uint32_t BVBI_P_VPS_Encode_Data_isr (
197	BREG_Handle hReg,
198	bool is656,
199	uint8_t hwCoreIndex,
200	BAVC_Polarity polarity,
201	BVBI_VPSData *pVPSData)
202	{
203	uint32_t ulCoreOffset;
204	uint32_t ulWssReg;
205	uint32_t ulVpsReg;
206	uint32_t ulErrInfo = 0;
207
208	BDBG_ENTER(BVBI_P_VPS_Encode_Data_isr);
209
210	/* Size check for field data */
211	if (!pVPSData)
212	{
213	return (BVBI_LINE_ERROR_FLDH_CONFLICT);
214	}
215
216	/* VPS is for top field only */
217	if (polarity != BAVC_Polarity_eTopField)
218	{
219	return (BVBI_LINE_ERROR_PARITY_CONFLICT);
220	}
221
222	/* Get register offset */
223	ulCoreOffset = P_GetCoreOffset (hwCoreIndex);
224
225	/* Sanity check */
226	if (is656 \|\| (ulCoreOffset == 0xFFFFFFFF))
227	{
228	/* This should never happen! This parameter was checked by
229	BVBI_Encode_Create() */
230	BDBG_ASSERT(0);
231	}
232
233	/* Some of the data goes to the WSS data register */
234	ulWssReg = BREG_Read32 (hReg, BCHP_WSE_0_wss_data + ulCoreOffset);
235	ulWssReg &= ~(
236	BCHP_MASK (WSE_0_wss_data, vps_byte_5 ) \|
237	BCHP_MASK (WSE_0_wss_data, vps_byte_11 ) );
238	ulWssReg \|= (
239	BCHP_FIELD_DATA (WSE_0_wss_data, vps_byte_5,
240	(uint32_t)pVPSData->ucByte05 ) \|
241	BCHP_FIELD_DATA (WSE_0_wss_data, vps_byte_11,
242	(uint32_t)pVPSData->ucByte11 ) );
243	BREG_Write32 (hReg, BCHP_WSE_0_wss_data + ulCoreOffset, ulWssReg);
244
245	/* The rest of the data goes right into the VPS data register */
246	ulVpsReg = BREG_Read32 (hReg, BCHP_WSE_0_vps_data_1 + ulCoreOffset);
247	ulVpsReg &= ~(
248	BCHP_MASK (WSE_0_vps_data_1, vps_byte_12 ) \|
249	BCHP_MASK (WSE_0_vps_data_1, vps_byte_13 ) \|
250	BCHP_MASK (WSE_0_vps_data_1, vps_byte_14 ) \|
251	BCHP_MASK (WSE_0_vps_data_1, vps_byte_15 ) );
252	ulVpsReg \|= (
253	BCHP_FIELD_DATA (WSE_0_vps_data_1, vps_byte_12,
254	(uint32_t)pVPSData->ucByte12 ) \|
255	BCHP_FIELD_DATA (WSE_0_vps_data_1, vps_byte_13,
256	(uint32_t)pVPSData->ucByte13 ) \|
257	BCHP_FIELD_DATA (WSE_0_vps_data_1, vps_byte_14,
258	(uint32_t)pVPSData->ucByte14 ) \|
259	BCHP_FIELD_DATA (WSE_0_vps_data_1, vps_byte_15,
260	(uint32_t)pVPSData->ucByte15 ) );
261	BREG_Write32 (hReg, BCHP_WSE_0_vps_data_1 + ulCoreOffset, ulVpsReg);
262
263	BDBG_LEAVE(BVBI_P_VPS_Encode_Data_isr);
264	return ulErrInfo;
265	}
266
267	/***************************************************************************
268	*
269	*/
270	BERR_Code BVBI_P_VPS_Encode_Enable_isr (
271	BREG_Handle hReg,
272	bool is656,
273	uint8_t hwCoreIndex,
274	BFMT_VideoFmt eVideoFormat,
275	bool bEnable)
276	{
277	uint32_t ulCoreOffset;
278	uint32_t ulVps_controlReg;
279
280	/* TODO: handle progressive video */
281	BSTD_UNUSED (eVideoFormat);
282
283	BDBG_ENTER(BVBI_P_VPS_Encode_Enable_isr);
284
285	/* Figure out which encoder core to use */
286	ulCoreOffset = P_GetCoreOffset (hwCoreIndex);
287	if (ulCoreOffset == 0xFFFFFFFF)
288	{
289	/* This should never happen! This parameter was checked by
290	BVBI_Encode_Create() */
291	BDBG_LEAVE(BVBI_P_VPS_Encode_Enable_isr);
292	return BERR_TRACE(BERR_INVALID_PARAMETER);
293	}
294
295	/* No VPS over ITU-R 656 */
296	if (is656)
297	{
298	if (bEnable)
299	{
300	/* No bypass encoder for VPS */
301	BDBG_LEAVE(BVBI_P_VPS_Encode_Enable_isr);
302	return BERR_TRACE(BERR_INVALID_PARAMETER);
303	}
304	else
305	{
306	/* Do nothing */
307	return BERR_SUCCESS;
308	}
309	}
310
311	ulVps_controlReg =
312	BREG_Read32 (hReg, BCHP_WSE_0_vps_control + ulCoreOffset);
313	ulVps_controlReg &= ~(
314	BCHP_MASK (WSE_0_vps_control, enable ) );
315	if (bEnable)
316	{
317	ulVps_controlReg \|= (
318	BCHP_FIELD_DATA (WSE_0_vps_control, enable, 1) );
319	}
320	else
321	{
322	ulVps_controlReg \|= (
323	BCHP_FIELD_DATA (WSE_0_vps_control, enable, 0) );
324	}
325	BREG_Write32 (
326	hReg, BCHP_WSE_0_vps_control + ulCoreOffset, ulVps_controlReg);
327
328	BDBG_LEAVE(BVBI_P_VPS_Encode_Enable_isr);
329	return BERR_SUCCESS;
330	}
331
332
333	/***************************************************************************
334	* Static (private) functions
335	***************************************************************************/
336
337	/***************************************************************************
338	*
339	*/
340	static uint32_t P_GetCoreOffset (uint8_t hwCoreIndex)
341	{
342	uint32_t ulCoreOffset = 0xFFFFFFFF;
343
344	switch (hwCoreIndex)
345	{
346	#if (BVBI_P_NUM_WSE >= 1)
347	case 0:
348	ulCoreOffset = 0;
349	break;
350	#endif
351	#if (BVBI_P_NUM_WSE >= 2)
352	case 1:
353	ulCoreOffset = (BCHP_WSE_1_control - BCHP_WSE_0_control);
354	break;
355	#endif
356	#if (BVBI_P_NUM_WSE >= 3)
357	case 2:
358	ulCoreOffset = (BCHP_WSE_2_control - BCHP_WSE_0_control);
359	break;
360	#endif
361	default:
362	break;
363	}
364
365	return ulCoreOffset;
366	}

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_vpse.c

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