source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vdc/7552/bvdc.c

Last change on this file was 2, checked in by jglee, 11 years ago

first commit
  • Property svn:executable set to *
File size: 60.3 KB
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1/***************************************************************************
2 *     Copyright (c) 2003-2012, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bvdc.c $
11 * $brcm_Revision: Hydra_Software_Devel/293 $
12 * $brcm_Date: 2/8/12 10:05a $
13 *
14 * Module Description:
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/portinginterface/vdc/7038/bvdc.c $
19 *
20 * Hydra_Software_Devel/293   2/8/12 10:05a pntruong
21 * SW7360-3: Initial support.
22 *
23 * Hydra_Software_Devel/292   1/13/12 2:51p tdo
24 * SW7358-159 , SW7418-55 : Default DAC auto detection ON for
25 * 7231/7344/7346Bx
26 *
27 * Hydra_Software_Devel/291   1/12/12 4:33p yuxiaz
28 * SW7552-181: Adjust buffer size based on alignment.
29 *
30 * Hydra_Software_Devel/290   11/23/11 4:24p tdo
31 * SW7435-9: Add support for CMP4-5, GFD4-5, MFD3, VFD5
32 *
33 * Hydra_Software_Devel/289   11/23/11 11:30a tdo
34 * SW7435-9: add support for 7435A0 in VDC
35 *
36 * Hydra_Software_Devel/288   11/18/11 2:27p pntruong
37 * SW7425-1727: Corrected the default bandgap default values.
38 *
39 * Hydra_Software_Devel/287   11/8/11 9:57p tdo
40 * SW7358-159: No ouput on composite port for B0.  Enable DAC auto
41 * detection for chipsets with the older DAC detection logic
42 *
43 * Hydra_Software_Devel/286   11/4/11 3:23p pntruong
44 * SW7231-387: Enabled hddvi for b0 build.
45 *
46 * Hydra_Software_Devel/285   11/1/11 2:38p pntruong
47 * SW7231-387: Enabled hddvi for b0 build.
48 *
49 * Hydra_Software_Devel/284   10/14/11 2:23p tdo
50 * SW7425-1416, SW7358-159: Add feature to control automatic DAC
51 * detection.  Default is currently OFF until it's fully functional.
52 *
53 * Hydra_Software_Devel/283   10/6/11 4:12p pntruong
54 * SW7429-16: Initial support.
55 *
56 * Hydra_Software_Devel/282   9/22/11 3:32p pntruong
57 * SW3548-3090: Pruned ununsed code.
58 *
59 * Hydra_Software_Devel/281   9/6/11 3:34p tdo
60 * SW7425-979:  Change init value for Dac gain adj for 7425B0/7346B0
61 *
62 * Hydra_Software_Devel/280   8/25/11 3:55p pntruong
63 * SW7425-1191: Rollback.  The acquire/release is more efficience to be
64 * handle in nexus, where the done event is already known.
65 *
66 * Hydra_Software_Devel/279   8/25/11 9:23a vanessah
67 * SW7425-1191:sg pwr management
68 *
69 * Hydra_Software_Devel/278   8/4/11 7:20p tdo
70 * SW7425-979: Add support for 7425B0 DAC name change
71 *
72 * Hydra_Software_Devel/277   7/11/11 2:16p tdo
73 * SW7420-1971: Video Pause seen when VEC alignment is going on.  Add flag
74 * to keep BVN connected while doing alignment.
75 *
76 * Hydra_Software_Devel/276   6/8/11 2:55p pntruong
77 * SW7346-276: Corrected populating the bandgap field.
78 *
79 * Hydra_Software_Devel/275   6/7/11 11:44a pntruong
80 * SW7400-3034, SW7400-2808: Better guarded checks, and refactored
81 * duplicate codes.
82 *
83 * Hydra_Software_Devel/274   2/28/11 10:16a vanessah
84 * SW7422-280: change the default setting
85 *
86 * Hydra_Software_Devel/273   2/25/11 4:15p yuxiaz
87 * SW7408-210: Fixed segfault in BVDC_Standby.
88 *
89 * Hydra_Software_Devel/272   2/17/11 6:31p jtna
90 * SW7420-1456: update BCHP_PWR pm code
91 *
92 * Hydra_Software_Devel/271   2/16/11 7:12p jtna
93 * SW7420-1456: fix typo
94 *
95 * Hydra_Software_Devel/270   2/16/11 5:29p pntruong
96 * SW7420-1456: Control the top level for vdc.
97 *
98 * Hydra_Software_Devel/269   2/9/11 3:58p yuxiaz
99 * SW7400-2882: Ported multi-buffing event logging scheme to VDC. Move
100 * related APIs to bvdc_dbg.h
101 *
102 * Hydra_Software_Devel/268   2/9/11 3:35p pntruong
103 * SW7420-1456: Initial standby power management that used chp's pm
104 * functionalities.
105 *
106 * Hydra_Software_Devel/267   12/14/10 5:32p pntruong
107 * SW7231-2: Removed BCHP_CHIP spot fixes.  Programmed bandgap adjustment
108 * number from API.  Programmed power management for bandgap power down.
109 * Need to add for individual dac.
110 *
111 * Hydra_Software_Devel/266   11/17/10 11:02p hongtaoz
112 * SW7422-13: 7422 has no 656in source;
113 *
114 * Hydra_Software_Devel/265   11/16/10 3:05p hongtaoz
115 * SW7425-33: added gfd3 support and vscl detection;
116 *
117 * Hydra_Software_Devel/264   11/15/10 5:59p pntruong
118 * SW7231-2: Initial support to make 7231 compile.
119 *
120 * Hydra_Software_Devel/263   11/12/10 3:55p pntruong
121 * SW7425-31: Takes bvn yuv into account for hddvi input.  Fixed bad debug
122 * register read on non-mfd source.  Updated scratch registers
123 * availabliity.
124 *
125 * Hydra_Software_Devel/262   11/11/10 7:27p albertl
126 * SW7125-364: Fixed BVDC_P_CbIsDirty and added assert to check bitfields
127 * in dirty bits fit within union integer representation.  Fixed naming
128 * of dirty bits.
129 *
130 * Hydra_Software_Devel/261   11/8/10 4:58p yuxiaz
131 * SW7552-7: Add initial support for 7552.
132 *
133 * Hydra_Software_Devel/260   10/20/10 4:10p yuxiaz
134 * SW7420-1190: Put back generic VDC drian buffer for mosaic mode. Only
135 * allocate drain buffer in window if it does not use main VDC heap.
136 *
137 * Hydra_Software_Devel/259   10/19/10 4:06p yuxiaz
138 * SW7420-1190: Make mosaic scratch buffer to be per window base.
139 *
140 * Hydra_Software_Devel/258   10/19/10 1:44p pntruong
141 * SW7425-31: Initial support for hddvi.
142 *
143 * Hydra_Software_Devel/257   10/18/10 10:05a yuxiaz
144 * SW7422-39: Added BAVC_SourceId_eMpeg2 support in VDC.
145 *
146 * Hydra_Software_Devel/256   10/11/10 11:33a jessem
147 * SW7420-173: Added support for using VFD as  a  source.
148 *
149 * Hydra_Software_Devel/255   9/29/10 11:40a tdo
150 * SW7425-33: VDC: Add the 4th Compositor Support for 7422/7425
151 *
152 * Hydra_Software_Devel/254   9/13/10 4:33p yuxiaz
153 * SW7358-4: Added initial VDC support for 7358.
154 *
155 * Hydra_Software_Devel/253   9/8/10 3:09p hongtaoz
156 * SW7425-13: disabled 7425 HDDVI source tempoarily;
157 *
158 * Hydra_Software_Devel/252   8/30/10 4:14p tdo
159 * SW7425-11, SW7425-13: Add 7425 support for VDC
160 *
161 * Hydra_Software_Devel/251   8/26/10 5:22p tdo
162 * SW7422-57: Add simple vdc support
163 *
164 * Hydra_Software_Devel/250   8/6/10 11:41a rpan
165 * SW7400-2882: Integrated the multi-buffering event logging scheme.
166 *
167 * Hydra_Software_Devel/249   7/7/10 1:11p pntruong
168 * SW35230-575: Corrected the alignment pameter for mem alloc.
169 *
170 * Hydra_Software_Devel/248   6/23/10 4:59p rpan
171 * SW7400-2808: Stop enabling BVN while aligning VECs.
172 *
173 * Hydra_Software_Devel/247   5/7/10 7:07p albertl
174 * SW7125-364: Changed dirty bits to use union structure to avoid type-pun
175 * warnings.
176 *
177 * Hydra_Software_Devel/246   4/19/10 10:10p tdo
178 * SW3548-2814: Improvements to VDC ulBlackMagic. Move
179 * BDBG_OBJECT_ID_DECLARE private header files instead of .c.
180 *
181 * Hydra_Software_Devel/245   4/7/10 11:22a tdo
182 * SW3548-2814: Improvements to VDC ulBlackMagic.  Rename TLA
183 *
184 * Hydra_Software_Devel/244   4/5/10 3:57p tdo
185 * SW3548-2814: Improvements to VDC ulBlackMagic
186 *
187 * Hydra_Software_Devel/243   3/31/10 6:41p albertl
188 * SW7420-674: Changed bandgap defaults to twenty-six for all chips.
189 *
190 * Hydra_Software_Devel/242   1/6/10 3:59p tdo
191 * SW7420-535: Change TMR code to use shared timer.  Remove direct
192 * register access.
193 *
194 * Hydra_Software_Devel/241   1/6/10 3:50p tdo
195 * SW7420-535: Change TMR code to use shared timer
196 *
197 * Hydra_Software_Devel/240   11/19/09 10:15a pntruong
198 * SW7408-13: Initial check in to get 7408 build.
199 *
200 * Hydra_Software_Devel/239   11/17/09 2:43p rpan
201 * SW7468-20: 7468 work.
202 *
203 * Hydra_Software_Devel/238   10/23/09 5:16p pntruong
204 * SW7340-54, SW7342-48, SW7340-57, SW7340-56, SW7125-36: Temporary don't
205 * enable clock gating.
206 *
207 * Hydra_Software_Devel/237   9/24/09 9:20p tdo
208 * SW7125-27: Fix FORWARDING_NULL coverity
209 *
210 * Hydra_Software_Devel/236   9/24/09 4:01p tdo
211 * SW7125-27 : Disable vecSwap for new chipsets with orthogonal VEC to
212 * temporarily fix the issue with hdsd simul on 7125 and 7342
213 *
214 * Hydra_Software_Devel/235   8/25/09 7:25p albertl
215 * SW7125-10: Initial 7125 support.
216 *
217 * Hydra_Software_Devel/234   8/21/09 2:37p tdo
218 * PR57734: Add capability for display to handle DACs re-assignment
219 *
220 * Hydra_Software_Devel/233   8/12/09 11:56a pntruong
221 * PR55225: Corrected the 656 input.
222 *
223 * Hydra_Software_Devel/232   8/5/09 9:48a pntruong
224 * PR55812: Fixed bandgap initialization.
225 *
226 * Hydra_Software_Devel/231   6/25/09 12:10p rpan
227 * PR56137, PR56138, PR56139, PR56166, PR56167, PR56168: Support for
228 * various orthogonal VEC configurations.
229 *
230 * Hydra_Software_Devel/230   6/19/09 5:46p darnstein
231 * PR55225: add support for 7342 chipset.
232 *
233 * Hydra_Software_Devel/229   6/18/09 5:52p syang
234 * PR 55812: add 7550 support
235 *
236 * Hydra_Software_Devel/228   6/11/09 4:02p darnstein
237 * PR55219: fill in some details for 7340 chipset.
238 *
239 * Hydra_Software_Devel/227   6/5/09 3:08p pntruong
240 * PR54615: [M+T][LCD][VIDEO] Pink gargabe blinks on DTV.  Ensured that
241 * the window shutdown process go thru upon destroy.
242 *
243 * Hydra_Software_Devel/226   4/17/09 11:56a pntruong
244 * PR54064: Refactored common code for defered callback til bvn shutdown.
245 * Improved readability and extensibility of dirty bits.
246 *
247 * Hydra_Software_Devel/225   3/16/09 10:42p tdo
248 * PR45785, PR45789: Merge from MCVP branch
249 *
250 * Hydra_Software_Devel/7420_mcvp/5   3/13/09 5:22p tdo
251 * PR45785, PR45789: merge from main branch on 3/13/09
252 *
253 * Hydra_Software_Devel/224   3/13/09 3:13p albertl
254 * PR51648: Added debug messages showing default bandgap settings.
255 *
256 * Hydra_Software_Devel/7420_mcvp/4   2/18/09 11:55a syang
257 * PR 45785, PR 45789: merge from main branch on 2/18/09
258 *
259 * Hydra_Software_Devel/223   2/17/09 2:33p rpan
260 * PR52001: Added 7420 DAC connection state for power management.
261 *
262 * Hydra_Software_Devel/7420_mcvp/3   2/11/09 11:30a tdo
263 * PR 45785, PR 45789: merge from main branch on 2/11/09
264 *
265 * Hydra_Software_Devel/222   2/10/09 4:47p rpan
266 * PR52001: Added 7420 DAC power management.
267 *
268 * Hydra_Software_Devel/7420_mcvp/2   1/29/09 4:29p syang
269 * PR 45785, PR 45789: merge from main branch on 1/29/09
270 *
271 * Hydra_Software_Devel/221   1/27/09 8:57p tdo
272 * PR51627: add VDC 7336 PI support
273 *
274 * Hydra_Software_Devel/7420_mcvp/1   1/23/09 11:28p syang
275 * PR 45785, PR 45789: add PI support for new the new module  MCVP
276 * (MCTF+MCDI)
277 *
278 * Hydra_Software_Devel/220   12/3/08 7:53p pntruong
279 * PR45817: Added hddvi support.
280 *
281 * Hydra_Software_Devel/219   11/24/08 5:02p rpan
282 * PR45804: Move VEC reset to display module.
283 *
284 * Hydra_Software_Devel/218   11/17/08 5:01p darnstein
285 * PR45819: fix error in previous check-in (include file name).
286 *
287 * Hydra_Software_Devel/217   11/17/08 4:10p darnstein
288 * PR45819: Update scratch register trickery to support ITU-R 656 output,
289 * in addition to analog output.
290 *
291 * Hydra_Software_Devel/216   11/7/08 6:40p albertl
292 * PR48740: Fixed #ifdef accidentally surrounding return statement.
293 *
294 * Hydra_Software_Devel/215   11/7/08 5:24p albertl
295 * PR48740: Fixed compiler warnings when debug is turned off.
296 *
297 * Hydra_Software_Devel/214   10/29/08 3:59p darnstein
298 * PR45819: Correct usage of scratch registers for VBI.
299 *
300 * Hydra_Software_Devel/213   10/9/08 5:27p syang
301 * PR 46891: add _isr to the name of func used in _isr context
302 *
303 * Hydra_Software_Devel/212   9/29/08 1:32p yuxiaz
304 * PR47370: Use BVDC_P_BUF_MSG for buffer related messages.
305 *
306 * Hydra_Software_Devel/211   9/29/08 12:56p pntruong
307 * PR47072: Moving 3563 vdc dedicated branch.
308 *
309 * Hydra_Software_Devel/210   9/26/08 1:32p pntruong
310 * PR46515: Adapted to new power management.
311 *
312 * Hydra_Software_Devel/209   9/22/08 9:39a syang
313 * PR 41898:  again more error message for the  win apply time out case
314 *
315 * Hydra_Software_Devel/208   9/19/08 2:52p syang
316 * PR 41898:  add more error message for the  win apply time out case
317 *
318 * Hydra_Software_Devel/207   9/16/08 10:48p pntruong
319 * PR46118: Removed pointless code.
320 *
321 * Hydra_Software_Devel/206   9/15/08 9:16p pntruong
322 * PR46514: Upon destroyed and disabled slot disable adc if not used.
323 *
324 * Hydra_Software_Devel/204   9/5/08 4:43p tdo
325 * PR46484: Bringup appframework for7420
326 *
327 * Hydra_Software_Devel/203   9/4/08 8:29p pntruong
328 * PR46502: Moving 7403 vdc dedicated branch.
329 *
330 * Hydra_Software_Devel/202   9/4/08 12:33p tdo
331 * PR43508, PR43509: Fix initial IREF_ADJ value for TDAC and QDAC for 7400
332 *
333 * Hydra_Software_Devel/201   8/29/08 2:25p darnstein
334 * PR46118: Adapt to pointless name changes in VBI_ENC registers.
335 *
336 * Hydra_Software_Devel/200   7/23/08 7:26p tdo
337 * PR43508, PR43509: Fix compiling errors
338 *
339 * Hydra_Software_Devel/199   7/23/08 7:00p tdo
340 * PR43508, PR43509: Mapping individual bandgap adjustment for each DAC
341 *
342 * Hydra_Software_Devel/198   6/16/08 2:45p darnstein
343 * PR43509: Add more generic video DAC adjustment defaults: by DAC
344 * version.
345 *
346 * Hydra_Software_Devel/197   6/16/08 2:29p darnstein
347 * PR43509: Provide Video DAC bandgap adjustment option for 7325 and 7335
348 * chips.
349 *
350 * Hydra_Software_Devel/196   6/16/08 2:16p darnstein
351 * PR43509: Provide adjustments to DAC bandgap for 3548 and 3556.
352 *
353 * Hydra_Software_Devel/195   6/16/08 1:46p darnstein
354 * PR43509: Add bandgap adjust default for 7405 chipset.
355 *
356 * Hydra_Software_Devel/194   6/16/08 1:28p darnstein
357 * PR43509: Provide separate adjustments to TDAC and QDAC bandgap
358 * settings.
359 *
360 * Hydra_Software_Devel/193   6/16/08 1:10p darnstein
361 * PR43509: Provide separate adjustments to TDAC and QDAC bandgap
362 * settings.
363 *
364 * Hydra_Software_Devel/192   6/13/08 8:39p darnstein
365 * PR43509: Update last checkin for 3563.
366 *
367 * Hydra_Software_Devel/191   6/13/08 8:27p darnstein
368 * PR43509: I got confused with a register name.
369 *
370 * Hydra_Software_Devel/190   6/13/08 8:13p darnstein
371 * PR43509: Switch to scheme: specify default bandgap adjustment by
372 * chipset.
373 *
374 * Hydra_Software_Devel/189   6/13/08 7:50p darnstein
375 * PR43509: fix a numeric error in last check-in.
376 *
377 * Hydra_Software_Devel/188   6/13/08 6:05p darnstein
378 * PR43509: Video DAC bandgap adjustment can be made using new member of
379 * struct BVDC_Settings.
380 *
381 * Hydra_Software_Devel/187   6/11/08 10:27a tdo
382 * PR43119: Use atomic register access
383 *
384 * Hydra_Software_Devel/186   6/7/08 8:25p albertl
385 * PR39336, PR39163:  Fixed bugs in second compositor support.  Added
386 * dirty bits mechanism to compositor for colorclip.
387 *
388 * Hydra_Software_Devel/185   5/2/08 4:00p rpan
389 * PR39421: Set 3548/3556 'cmpb' to true.
390 *
391 * Hydra_Software_Devel/184   3/25/08 3:17p syang
392 * PR 40431: add complete assert for critical section protection among src
393 * _isr, dsp _isr, and ApplyChanges
394 *
395 * Hydra_Software_Devel/183   3/7/08 9:13p pntruong
396 * PR37836, PR39921: Added more helpful info for out of vdc heap to ease
397 * debugging.
398 *
399 * Hydra_Software_Devel/182   3/5/08 1:41p tdo
400 * PR39417: VDC PI support 3556
401 *
402 * Hydra_Software_Devel/181   2/21/08 4:59p pntruong
403 * PR39244: Need drain debugging hooked up to HD_DVI, VDEC, and 656in.
404 * Improved code readability.
405 *
406 * Hydra_Software_Devel/180   2/13/08 3:10p pntruong
407 * PR39421: Removed unused code to improve readability.
408 *
409 * Hydra_Software_Devel/179   2/5/08 2:42p yuxiaz
410 * PR34712: Added H.264 support through MPEG feeder on 3548.
411 *
412 * Hydra_Software_Devel/178   11/19/07 3:49p tdo
413 * PR36898: Add VDC PI support for 7335
414 *
415 * Hydra_Software_Devel/177   10/30/07 7:08p pntruong
416 * PR34239: Allow dynamically loading of vec custom timing.
417 *
418 * Hydra_Software_Devel/176   10/23/07 11:14a yuxiaz
419 * PR29569, PR36290: Add FGT support on 7405.
420 *
421 * Hydra_Software_Devel/PR29569/3   10/22/07 5:15p yuxiaz
422 * PR29569: More FGT work.
423 *
424 * Hydra_Software_Devel/PR29569/2   10/19/07 11:30a yuxiaz
425 * PR29569: Merge from mainline.
426 *
427 * Hydra_Software_Devel/175   10/12/07 10:05a pntruong
428 * PR36058: Fixed compositor/display coupling in custom display setup.
429 *
430 * Hydra_Software_Devel/174   10/11/07 6:06p syang
431 * PR 35036: coverity fix
432 *
433 * Hydra_Software_Devel/173   10/8/07 2:35p pntruong
434 * PR34855: Initial VDC bringup.
435 *
436 * Hydra_Software_Devel/172   9/21/07 4:35p yuxiaz
437 * PR34523: Add 7325 support for VDC.
438 *
439 * Hydra_Software_Devel/171   9/4/07 5:23p jessem
440 * PR 34590: Changed s_stDefaultSettings' pixel format to use
441 * BVDC_P_CAP_PIXEL_FORMAT_8BIT422 instead.
442 *
443 * Hydra_Software_Devel/170   8/7/07 4:21p yuxiaz
444 * PR27644: BVDC_P_CheckDefSettings only checks when the buffer count is
445 * not zero.
446 *
447 * Hydra_Software_Devel/169   7/23/07 10:13a pntruong
448 * PR31869: [VDEC] snow noise blink between normal snow noise and black
449 * screen.
450 *
451 * Hydra_Software_Devel/168   4/24/07 1:45p yuxiaz
452 * PR27644: Added 7405 support.
453 *
454 * Hydra_Software_Devel/167   4/2/07 6:10p darnstein
455 * PR29426: Activate 656 input for 7403-A0 chip. I separated the cases for
456 * 7401 and 7403 chips.
457 *
458 * Hydra_Software_Devel/166   2/23/07 6:26p tdo
459 * PR 27970: Share LPB and FCH if source is the same to eliminate the out
460 * of resource error when number of LPB and FCH are limited
461 *
462 * Hydra_Software_Devel/165   2/16/07 9:37a pntruong
463 * PR15284, PR27951: Graphics shimmering on HD path when video is scaled
464 * down (PIG).  HW fixed.  Removed software work-around to avoid bvb
465 * error interrupts from window surface.  Make bvdc dbg more portable.
466 *
467 * Hydra_Software_Devel/164   1/24/07 9:04p albertl
468 * PR22237:  Updated BMEM calls to use new BMEM_Heap functions.
469 *
470 * Hydra_Software_Devel/163   1/22/07 11:12a pntruong
471 * PR22579: Bringup of HD_DVI input (dual core).  Redo hddvi code.
472 *
473 * Hydra_Software_Devel/162   1/9/07 4:45p tdo
474 * PR 26924: Add support for 7403 VCXO so that it won't be reset by VEC
475 * core reset
476 *
477 * Hydra_Software_Devel/161   1/8/07 10:59p pntruong
478 * PR22577: Initial vdc bringup.  Added flag to indicate if mad reset is
479 * supported.
480 *
481 * Hydra_Software_Devel/160   12/18/06 11:17p pntruong
482 * PR22577: Merged back to mainline.
483 *
484 ***************************************************************************/
485#include "bstd.h"                /* standard types */
486#include "bdbg.h"                /* Dbglib */
487#include "bkni.h"                /* malloc */
488#include "btmr.h"                /* timer */
489
490#ifdef BCHP_PWR_SUPPORT
491#include "bchp_pwr.h"
492#endif
493
494/* Note: Tricky here!  bavc.h needs bchp_gfd_x.h defininitions.
495 * The check here is to see if chips has more than one gfx feeder. */
496#include "bchp_gfd_0.h"
497#include "bchp_gfd_1.h"
498
499#include "bvdc.h"                /* Video display */
500#include "bvdc_priv.h"           /* VDC internal data structures */
501#include "bvdc_common_priv.h"
502#include "bvdc_vnet_priv.h"
503#include "bvdc_compositor_priv.h"
504#include "bvdc_display_priv.h"
505#include "bvdc_source_priv.h"
506#include "bvdc_bufferheap_priv.h"
507#include "bvdc_displayfmt_priv.h"
508#include "bvdc_fgt_priv.h"
509#include "bvdc_window_priv.h"  /* only for err msg as time out */
510#include "bvdc_display_priv.h"
511
512#include "bchp_fmisc.h"
513#include "bchp_mmisc.h"
514#include "bchp_bmisc.h"
515#include "bchp_timer.h"
516
517#if BVDC_P_SUPPORT_DMISC
518#include "bchp_dmisc.h"
519#endif
520
521
522/* bDisableComponentVDEC mode registers */
523#if (BVDC_P_SUPPORT_VDEC)
524#include "bchp_ifd_top.h"
525#include "bvdc_vdec_priv.h"  /* power up/down, and reset */
526#endif
527
528BDBG_MODULE(BVDC);
529BDBG_OBJECT_ID(BVDC_VDC);
530
531/* This table used to indicate which DACs belong to each group. 0 for unused DAC */
532static const uint32_t s_aulDacGrouping[BVDC_MAX_DACS] =
533{
534#if (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_0)
535        1, 1, 1, 1, 0, 0, 0
536#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_1)
537    1, 1, 1, 2, 2, 2, 0
538#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_2)
539        /* TODO: Need to confirm if TDAC = DAC[0-2] and QDAC = DAC[3-6] or
540           TDAC = DAC[4-6] and QDAC = DAC[0-3] */
541        1, 1, 1, 2, 2, 2, 2
542#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_3)
543        1, 1, 1, 2, 2, 2, 0
544#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_4)
545        1, 1, 1, 2, 2, 2, 0
546#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_5)
547        1, 1, 1, 0, 0, 0, 0
548#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_6)
549        1, 1, 1, 2, 2, 2, 2
550#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_7)
551        1, 1, 1, 2, 2, 2, 0
552#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_8)
553        1, 1, 1, 1, 0, 0, 0
554#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_9)
555        1, 1, 1, 1, 0, 0, 0
556#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_10)
557        1, 1, 1, 1, 0, 0, 0
558#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_11)
559        1, 1, 1, 1, 0, 0, 0
560#else
561#error "Unknown chip!  Not yet supported in VDC."
562#endif
563};
564
565/* Default settings. */
566static const BVDC_Settings s_stDefaultSettings =
567{
568        BFMT_VideoFmt_e1080i,
569        BAVC_FrameRateCode_e59_94,                /* Most HDMI monitors support 60Hz */
570        BAVC_MatrixCoefficients_eItu_R_BT_709, /* default HD color matrix */
571        BAVC_MatrixCoefficients_eSmpte_170M,   /* default SD color matrix */
572        true,                                  /* VEC swap, cmp_0 -> vec_1 */
573        false,                                 /* support S-Video and Component VDEC */
574        false,                                 /* do not support FGT */
575
576        /* Memory controller setttins. */
577        {
578                /* Double HD Buffer settings */
579                BVDC_P_MAX_2HD_BUFFER_COUNT,           /* default 2HD buffer count */
580                BVDC_P_CAP_PIXEL_FORMAT_8BIT422,       /* default capture Pixel format */
581                BFMT_VideoFmt_e1080p_30Hz,             /* 2HD buffer is 1080p */
582                0,                                     /* no additional lines for 2HD buffer */
583                BVDC_P_DEFAULT_2HD_PIP_BUFFER_COUNT,   /* default 1/4 2HD buffer count */
584
585                /* HD buffer settings */
586                BVDC_P_MAX_HD_BUFFER_COUNT,            /* default HD buffer count */
587                BVDC_P_CAP_PIXEL_FORMAT_8BIT422,                 /* default capture Pixel format */
588                BFMT_VideoFmt_e1080i,                  /* HD buffer is 1080i */
589                0,                                     /* no additional lines for HD buffer */
590                BVDC_P_DEFAULT_HD_PIP_BUFFER_COUNT,    /* default 1/4 HD buffer count */
591
592                /* SD buffer settings */
593                BVDC_P_MAX_SD_BUFFER_COUNT,            /* default SD buffer count */
594                BVDC_P_CAP_PIXEL_FORMAT_8BIT422,       /* default capture Pixel format */
595                BFMT_VideoFmt_ePAL_G,                  /* default SD buffer is PAL */
596                0,                                     /* no additional lines for SD buffer */
597                BVDC_P_DEFAULT_SD_PIP_BUFFER_COUNT     /* default 1/4 SD buffer count */
598        },
599
600        /* New Video DAC bandgap adjust */
601        {
602#if (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_0)
603                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
604                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
605                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
606                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
607                0,
608                0,
609                0
610#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_1)
611                BCHP_MISC_TDAC0_CTRL_REG_BG_PTATADJ_NORM,
612                BCHP_MISC_TDAC0_CTRL_REG_BG_PTATADJ_NORM,
613                BCHP_MISC_TDAC0_CTRL_REG_BG_PTATADJ_NORM,
614                BCHP_MISC_TDAC1_CTRL_REG_BG_PTATADJ_NORM,
615                BCHP_MISC_TDAC1_CTRL_REG_BG_PTATADJ_NORM,
616                BCHP_MISC_TDAC1_CTRL_REG_BG_PTATADJ_NORM,
617                0
618#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_2)
619        /* TODO: Need to confirm if TDAC = DAC[0-2] and QDAC = DAC[3-6] or
620           TDAC = DAC[4-6] and QDAC = DAC[0-3] */
621                BCHP_MISC_TDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
622                BCHP_MISC_TDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
623                BCHP_MISC_TDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
624                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
625                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
626                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
627                BCHP_MISC_QDAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX
628#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_3)
629                BCHP_MISC_TDAC0_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
630                BCHP_MISC_TDAC0_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
631                BCHP_MISC_TDAC0_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
632                BCHP_MISC_TDAC1_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
633                BCHP_MISC_TDAC1_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
634                BCHP_MISC_TDAC1_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
635                0
636#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_4)
637                BCHP_MISC_TDAC0_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
638                BCHP_MISC_TDAC0_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
639                BCHP_MISC_TDAC0_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
640                BCHP_MISC_TDAC1_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
641                BCHP_MISC_TDAC1_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
642                BCHP_MISC_TDAC1_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
643                0
644#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_5)
645                BCHP_MISC_DAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
646                BCHP_MISC_DAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
647                BCHP_MISC_DAC_BG_CTRL_REG_IREF_ADJ_TWENTY_SIX,
648                0,
649                0,
650                0,
651                0
652#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_6)
653                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
654                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
655                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
656                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX,
657                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX,
658                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX,
659                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX
660#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_7)
661                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
662                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
663                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
664                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX,
665                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX,
666                BCHP_MISC_DAC_BG_CTRL_1_IREF_ADJ_TWENTY_SIX,
667                0
668#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_8)
669                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
670                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
671                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
672                BCHP_MISC_DAC_BG_CTRL_0_IREF_ADJ_TWENTY_SIX,
673                0,
674                0,
675                0
676#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_9)
677                244,
678                244,
679                244,
680                244,
681                0,
682                0,
683                0
684#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_10)
685                244,
686                244,
687                244,
688                244,
689                0,
690                0,
691                0
692#elif (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_11)
693                244,
694                244,
695                244,
696                244,
697                0,
698                0,
699                0
700#else
701#error "Unknown chip!  Not yet supported in VDC."
702#endif
703        },
704        BVDC_Mode_eAuto,
705};
706
707/* Here is a little consistency check */
708#if (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_1)
709        #if (BCHP_MISC_TDAC0_CTRL_REG_BG_PTATADJ_NORM != \
710                 BCHP_MISC_TDAC0_CTRL_REG_BG_CTATADJ_NORM)
711                #error bandgap constants not equal
712        #endif
713#endif
714
715/* Available features
716 * INDEX: by compositor id, window id source id */
717static const BVDC_P_Features s_VdcFeatures =
718{
719#if (BCHP_CHIP==7400)
720        false,
721        /* cmp0   cmp1   cmp2   cmp3   cmp4   cmp5 */
722        {  true,  true,  true,  false, false, false },
723
724        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0    dvi1   ds 0   vfd0  vfd1  vfd2  vfd3  vfd4   vfd5 */
725        {  true,  true,  false, false, false, false, true,  true,  true,  true,  true,  false, false, false, false,  false, false, true, true, true, true, false, false },
726#elif (BCHP_CHIP==7420)
727        false,
728        /* cmp0   cmp1   cmp2   cmp3   cmp4   cmp5 */
729        {  true,  true,  true,  false, false, false },
730
731        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2  vfd3  vfd4   vfd5  */
732        {  true,  true,  false, false, false, false, true,  true,  true,  true,  true,  false, false, false, true,  false, false, true, true, true, true, false, false },
733#elif (BCHP_CHIP==7422) || (BCHP_CHIP==7425)
734        false,
735        /* cmp0   cmp1   cmp2   cmp3   cmp4   cmp5  */
736        {  true,  true,  true,  true,  false, false  },
737
738        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2  vfd3  vfd4   vfd5  */
739        {  true,  true,  true,  false, false, false, false, false, true,  true,  true,  true,  false, false, true,  false, false, true, true, true, true, true, false },
740#elif (BCHP_CHIP==7435)
741        false,
742        /* cmp0   cmp1   cmp2   cmp3   cmp4   cmp5  */
743        {  true,  true,  true,  true,  true,  true  },
744
745        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2  vfd3  vfd4   vfd5  */
746        {  true,  true,  true,  true,  false, false, false, false, true,  true,  true,  true,  true,  true,  true,  false, false, true, true, true, true, true, true  },
747#elif (BCHP_CHIP==7405)
748        false,
749        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
750        {  true,  true,  false, false, false, false },
751
752        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2  vfd3  vfd4   vfd5  */
753        {  true,  true,  false, false, false, false, true,  false, true,  true,  false, false, false, false, false, false, false, true, true, true, true, false, false },
754
755#elif (BCHP_CHIP==7325) || (BCHP_CHIP==7335) || (BCHP_CHIP==7336)
756        false,
757        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
758        {  true,  true,  false, false, false, false },
759
760        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2   vfd3   vfd4   vfd5  */
761        {  true,  false, false, false, false, false, false, false, true,  true,  false, false, false, false, false, false, false, true, true, false, false, false, false },
762
763#elif (BCHP_CHIP==7340) || (BCHP_CHIP==7342) || (BCHP_CHIP==7550) || \
764          (BCHP_CHIP==7358) || (BCHP_CHIP==7552) || (BCHP_CHIP==7360)
765        false,
766        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
767        {  true,  true,  false, false, false, false },
768
769        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2   vfd3   vfd4   vfd5  */
770        {  true,  false, false, false, false, false, false, false, true,  true,  false, false, false, false, false, false, false, true, true, false, false, false, false },
771
772#elif (BCHP_CHIP==7344) || (BCHP_CHIP==7346)
773        false,
774        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
775        {  true,  true,  false, false, false, false },
776
777        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2   vfd3   vfd4   vfd5  */
778        {  true,  true,  false, false, false, false, false, false, true, true,   false, false, false, false, false, false, false, true, true, false, false, false, false },
779
780#elif (BCHP_CHIP==7231) && (BCHP_VER == BCHP_VER_A0)
781        false,
782        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
783        {  true,  true,  false, false, false, false },
784
785        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2   vfd3   vfd4   vfd5  */
786        {  true,  true,  false, false, false, false, false,  false, true, true,  false, false, false, false, false, false, false, true, true, false, false, false, false },
787
788#elif (BCHP_CHIP==7231) || (BCHP_CHIP==7429)
789        false,
790        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
791        {  true,  true,  false, false, false, false },
792
793        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0  dvi1   ds 0   vfd0  vfd1  vfd2   vfd3   vfd4   vfd5  */
794        {  true,  true,  false, false, false, false, false,  false, true, true,  false, false, false, false, true, false, false, true, true, false, false, false, false },
795
796#elif (BCHP_CHIP==7125) || (BCHP_CHIP==7468) || (BCHP_CHIP==7408)
797        false,
798        /* cmp0   cmp1   cmpb   cmp3   cmp4   cmp5 */
799        {  true,  true,  false, false, false, false },
800
801        /* mpg0   mpg1   mpg2   mpg3   vdec0  vdec1  656_0  656_1  gfx0   gfx1   gfx2   gfx3   gfx4   gfx5   dvi0   dvi1   ds 0   vfd0  vfd1  vfd2   vfd3   vfd4   vfd5  */
802        {  true,  false, false, false, false, false, false, false, true,  true,  false, false, false, false, false, false, false, true, true, false, false, false, false },
803
804#else
805#error "Unknown chip!  Not yet supported in VDC."
806#endif
807};
808
809
810/***************************************************************************
811 * This function does a soft-reset of each VDC modules.
812 */
813static void BVDC_P_PrintHeapInfo
814        ( const BVDC_Heap_Settings        *pHeap )
815{
816        const BFMT_VideoInfo *pFmtInfo;
817
818        pFmtInfo = BFMT_GetVideoFormatInfoPtr(pHeap->eBufferFormat_2HD);
819        BVDC_P_BUF_MSG(("--------2HD---------"));
820        BVDC_P_BUF_MSG(("ulBufferCnt     = %d", pHeap->ulBufferCnt_2HD));
821        BVDC_P_BUF_MSG(("ulBufferCnt_Pip = %d", pHeap->ulBufferCnt_2HD_Pip));
822        BVDC_P_BUF_MSG(("eBufferFormat   = %s", pFmtInfo->pchFormatStr));
823        BVDC_P_BUF_MSG(("ePixelFormat    = %s", BPXL_ConvertFmtToStr(pHeap->ePixelFormat_2HD)));
824
825        pFmtInfo = BFMT_GetVideoFormatInfoPtr(pHeap->eBufferFormat_HD);
826        BVDC_P_BUF_MSG(("---------HD---------"));
827        BVDC_P_BUF_MSG(("ulBufferCnt     = %d", pHeap->ulBufferCnt_HD));
828        BVDC_P_BUF_MSG(("ulBufferCnt_Pip = %d", pHeap->ulBufferCnt_HD_Pip));
829        BVDC_P_BUF_MSG(("eBufferFormat   = %s", pFmtInfo->pchFormatStr));
830        BVDC_P_BUF_MSG(("ePixelFormat    = %s", BPXL_ConvertFmtToStr(pHeap->ePixelFormat_HD)));
831
832        pFmtInfo = BFMT_GetVideoFormatInfoPtr(pHeap->eBufferFormat_SD);
833        BVDC_P_BUF_MSG(("---------SD---------"));
834        BVDC_P_BUF_MSG(("ulBufferCnt     = %d", pHeap->ulBufferCnt_SD));
835        BVDC_P_BUF_MSG(("ulBufferCnt_Pip = %d", pHeap->ulBufferCnt_SD_Pip));
836        BVDC_P_BUF_MSG(("eBufferFormat   = %s", pFmtInfo->pchFormatStr));
837        BVDC_P_BUF_MSG(("ePixelFormat    = %s", BPXL_ConvertFmtToStr(pHeap->ePixelFormat_SD)));
838
839        return;
840}
841
842
843/***************************************************************************
844 *
845 */
846static void BVDC_P_ResetBvn
847        ( BVDC_P_Context                  *pVdc )
848{
849        bool bFreeRun;
850        uint32_t ulReg;
851
852        /* Note we can not use the SUN_TOP_CTRL_SW_RESET, because it would
853         * also reset the RDC, and MEMC memory controller. */
854#if (BVDC_P_SUPPORT_CLOCK_GATING)
855        bFreeRun = false;
856#else
857        bFreeRun = true;
858#endif
859
860        /* Reset BVN front-end, middle-end, and back-end modules.
861         * To reset write a 1 to a bit, and then write a 0.*/
862        /*---------------------------*/
863        /* FRONT-END & MIDDLE BLOCKS */
864        /*---------------------------*/
865        ulReg = 0xffffffff;
866        ulReg &= ~(
867#if BVDC_P_SUPPORT_NEW_SW_INIT
868        BCHP_MASK(FMISC_SW_INIT, RDC ));
869        BREG_Write32(pVdc->hRegister, BCHP_FMISC_SW_INIT, ulReg);
870        BREG_Write32(pVdc->hRegister, BCHP_FMISC_SW_INIT, 0);
871#else
872#if BVDC_P_SUPPORT_FMISC_PFRI
873                BCHP_MASK(FMISC_SOFT_RESET, MEMC_PFRI )  |
874#endif
875#if BVDC_P_SUPPORT_FMISC_MEMC
876                BCHP_MASK(FMISC_SOFT_RESET, MEMC_IOBUF ) |
877                BCHP_MASK(FMISC_SOFT_RESET, MEMC_RBUS )  |
878                BCHP_MASK(FMISC_SOFT_RESET, MEMC_CORE)   |
879#endif
880                BCHP_MASK(FMISC_SOFT_RESET, RDC ) );
881        BREG_Write32(pVdc->hRegister, BCHP_FMISC_SOFT_RESET, ulReg);
882        BREG_Write32(pVdc->hRegister, BCHP_FMISC_SOFT_RESET, 0);
883#endif
884
885#ifdef BCHP_FMISC_BVNF_CLOCK_CTRL
886        BREG_Write32(pVdc->hRegister, BCHP_FMISC_BVNF_CLOCK_CTRL,
887                BCHP_FIELD_DATA(FMISC_BVNF_CLOCK_CTRL, CLK_FREE_RUN_MODE, bFreeRun));
888#endif
889
890        /*---------------*/
891        /* MAD BLOCKS    */
892        /*---------------*/
893#if BVDC_P_SUPPORT_DMISC
894        ulReg = 0xffffffff;
895        BREG_Write32(pVdc->hRegister, BCHP_DMISC_SOFT_RESET, ulReg);
896        BREG_Write32(pVdc->hRegister, BCHP_DMISC_SOFT_RESET, 0);
897#endif
898
899#ifdef BCHP_DMISC_BVND_MAD_0_CLOCK_CTRL
900        BREG_Write32(pVdc->hRegister, BCHP_DMISC_BVND_MAD_0_CLOCK_CTRL,
901                BCHP_FIELD_DATA(DMISC_BVND_MAD_0_CLOCK_CTRL, CLK_FREE_RUN_MODE, bFreeRun));
902#endif
903
904        /*---------------*/
905        /* MIDDLE BLOCKS */
906        /*---------------*/
907        ulReg = 0xffffffff;
908#if BVDC_P_SUPPORT_NEW_SW_INIT
909        BREG_Write32(pVdc->hRegister, BCHP_MMISC_SW_INIT, ulReg);
910        BREG_Write32(pVdc->hRegister, BCHP_MMISC_SW_INIT, 0);
911#else
912        BREG_Write32(pVdc->hRegister, BCHP_MMISC_SOFT_RESET, ulReg);
913        BREG_Write32(pVdc->hRegister, BCHP_MMISC_SOFT_RESET, 0);
914#endif
915
916#ifdef BCHP_MMISC_BVNM_CLOCK_CTRL
917        BREG_Write32(pVdc->hRegister, BCHP_MMISC_BVNM_CLOCK_CTRL,
918                BCHP_FIELD_DATA(MMISC_BVNM_CLOCK_CTRL, CLK_FREE_RUN_MODE, bFreeRun));
919#endif
920
921        /*------------------*/
922        /* BACK-END BLOCKS */
923        /*------------------*/
924        ulReg = 0xffffffff;
925#if BVDC_P_SUPPORT_NEW_SW_INIT
926        BREG_Write32(pVdc->hRegister, BCHP_BMISC_SW_INIT, ulReg);
927        BREG_Write32(pVdc->hRegister, BCHP_BMISC_SW_INIT, 0);
928#else
929        BREG_Write32(pVdc->hRegister, BCHP_BMISC_SOFT_RESET, ulReg);
930        BREG_Write32(pVdc->hRegister, BCHP_BMISC_SOFT_RESET, 0);
931#endif
932
933#ifdef BCHP_BMISC_BVNB_CLOCK_CTRL
934        BREG_Write32(pVdc->hRegister, BCHP_BMISC_BVNB_CLOCK_CTRL,
935                BCHP_FIELD_DATA(BMISC_BVNB_CLOCK_CTRL, CLK_FREE_RUN_MODE, bFreeRun));
936#endif
937
938        return;
939}
940
941
942/***************************************************************************
943 * This function does a soft-reset of each VDC modules.
944 */
945static void BVDC_P_SoftwareReset
946        ( BVDC_P_Context                  *pVdc )
947{
948        /* Reset all BVN modules in BVN_Front, BVN_Middle, BVN_Back */
949        BVDC_P_ResetBvn(pVdc);
950
951        /* Reset all Vec modules in Sundry, and initialize vec Misc regs. */
952        BVDC_P_ResetVec(pVdc);
953
954#if (BVDC_P_SUPPORT_VDEC)
955        BVDC_P_Vdec_Reset(pVdc->hRegister);
956#endif
957
958        return;
959}
960
961/***************************************************************************
962 * Check VDC default settings.
963 *
964 * 1) SD buffer format is SD
965 * 2) HD buffer format is HD
966 * 3) 2HD buffer format is  HD
967 * 4) SD buffer < HD buffer
968 * 5) HD buffer < 2HD buffer
969 * 6) VBI lines
970 *
971 */
972static BERR_Code BVDC_P_CheckDefSettings
973        ( const BVDC_Heap_Settings         *pHeapSettings )
974{
975        BERR_Code  eStatus = BERR_SUCCESS;
976        uint32_t   ulWidth, ulHeight;
977        uint32_t   ulSDBufSize, ulHDBufSize, ul2HDBufSize;
978        const BVDC_P_FormatInfo  *pVdcFmt;
979
980        /* 1) SD buffer format is SD */
981        pVdcFmt = BVDC_P_GetFormatInfoPtr_isr(
982                BFMT_GetVideoFormatInfoPtr(pHeapSettings->eBufferFormat_SD));
983        if( (!pVdcFmt->bSd) &&
984            (pHeapSettings->ulBufferCnt_SD || pHeapSettings->ulBufferCnt_SD_Pip))
985        {
986                BDBG_ERR(("SD buffer format is not SD"));
987                return BERR_TRACE(BERR_INVALID_PARAMETER);
988        }
989
990        /* 2) HD buffer format is HD */
991        pVdcFmt = BVDC_P_GetFormatInfoPtr_isr(
992                BFMT_GetVideoFormatInfoPtr(pHeapSettings->eBufferFormat_HD));
993        if( (!pVdcFmt->bHd) &&
994            (pHeapSettings->ulBufferCnt_HD || pHeapSettings->ulBufferCnt_HD_Pip))
995        {
996                BDBG_ERR(("HD buffer format is not HD"));
997                return BERR_TRACE(BERR_INVALID_PARAMETER);
998        }
999
1000        /* 3) 2Hd buffer format is HD */
1001        pVdcFmt = BVDC_P_GetFormatInfoPtr_isr(
1002                BFMT_GetVideoFormatInfoPtr(pHeapSettings->eBufferFormat_2HD));
1003        if( (!pVdcFmt->bHd) &&
1004            (pHeapSettings->ulBufferCnt_2HD || pHeapSettings->ulBufferCnt_2HD_Pip))
1005        {
1006                BDBG_ERR(("2HD buffer format is not HD"));
1007                return BERR_TRACE(BERR_INVALID_PARAMETER);
1008        }
1009
1010        /* Get SD, HD, 2HD buffer size */
1011        ulSDBufSize = BVDC_P_BufferHeap_GetHeapSize(
1012                BFMT_GetVideoFormatInfoPtr(pHeapSettings->eBufferFormat_SD),
1013                pHeapSettings->ePixelFormat_SD, 0, false, NULL, &ulWidth, &ulHeight);
1014        ulHDBufSize = BVDC_P_BufferHeap_GetHeapSize(
1015                BFMT_GetVideoFormatInfoPtr(pHeapSettings->eBufferFormat_HD),
1016                pHeapSettings->ePixelFormat_HD, 0, false, NULL, &ulWidth, &ulHeight);
1017        ul2HDBufSize = BVDC_P_BufferHeap_GetHeapSize(
1018                BFMT_GetVideoFormatInfoPtr(pHeapSettings->eBufferFormat_2HD),
1019                pHeapSettings->ePixelFormat_2HD, 0, false, NULL, &ulWidth, &ulHeight);
1020
1021        /* 4) SD buffer < HD buffer */
1022        if( (!(ulSDBufSize < ulHDBufSize)) &&
1023            (pHeapSettings->ulBufferCnt_SD || pHeapSettings->ulBufferCnt_SD_Pip) &&
1024            (pHeapSettings->ulBufferCnt_HD || pHeapSettings->ulBufferCnt_HD_Pip))
1025        {
1026                BDBG_ERR(("HD buffer (0x%d) is not bigger than SD buffer (0x%x)",
1027                        ulHDBufSize, ulSDBufSize));
1028                return BERR_TRACE(BERR_INVALID_PARAMETER);
1029        }
1030
1031        /* 5) HD buffer < 2HD buffer */
1032        if( (!(ulHDBufSize < ul2HDBufSize)) &&
1033            (pHeapSettings->ulBufferCnt_HD || pHeapSettings->ulBufferCnt_HD_Pip) &&
1034            (pHeapSettings->ulBufferCnt_2HD || pHeapSettings->ulBufferCnt_2HD_Pip))
1035        {
1036                BDBG_ERR(("2HD buffer is not bigger than HD buffer"));
1037                return BERR_TRACE(BERR_INVALID_PARAMETER);
1038        }
1039
1040        /* 6) VBI lines */
1041        if((pHeapSettings->ulAdditionalLines_HD > BVDC_ADDITIONAL_VBI_LINES_MAX_HD)  ||
1042           (pHeapSettings->ulAdditionalLines_2HD > BVDC_ADDITIONAL_VBI_LINES_MAX_HD) ||
1043           (pHeapSettings->ulAdditionalLines_SD >
1044           (VIDEO_FORMAT_IS_NTSC(pHeapSettings->eBufferFormat_SD) ?
1045            BVDC_ADDITIONAL_VBI_LINES_MAX_NTSC : BVDC_ADDITIONAL_VBI_LINES_MAX_PAL)))
1046        {
1047                BDBG_ERR(("Default setting requests more vbi lines pass-through lines than max allowed"));
1048                return BERR_TRACE(BERR_INVALID_PARAMETER);
1049        }
1050
1051        return eStatus;
1052}
1053
1054/***************************************************************************
1055 * Check VDC DAC bandgap default settings.
1056 */
1057static BERR_Code BVDC_P_CheckBandgapDefSettings
1058        ( const BVDC_Settings             *pDefSettings )
1059{
1060        BERR_Code  eStatus = BERR_SUCCESS;
1061        uint32_t   id;
1062
1063        for(id = 0; id < BVDC_MAX_DACS; id++)
1064        {
1065                BDBG_MSG(("DAC %d BG setting = %d", id + 1, pDefSettings->aulDacBandGapAdjust[id]));
1066        }
1067
1068        for(id = 1; id < BVDC_MAX_DACS; id++)
1069        {
1070                if(s_aulDacGrouping[id] != 0 &&
1071                   s_aulDacGrouping[id-1] == s_aulDacGrouping[id] &&
1072                   pDefSettings->aulDacBandGapAdjust[id-1] != pDefSettings->aulDacBandGapAdjust[id])
1073                {
1074                        BDBG_ERR(("BG setting for DAC %d = %d should be same as DAC %d = %d",
1075                                id, pDefSettings->aulDacBandGapAdjust[id],
1076                                id - 1, pDefSettings->aulDacBandGapAdjust[id-1]));
1077                        return BERR_TRACE(BERR_INVALID_PARAMETER);
1078                }
1079        }
1080
1081        return eStatus;
1082}
1083
1084/***************************************************************************
1085 *
1086 */
1087BERR_Code BVDC_GetDefaultSettings
1088        ( BVDC_Settings                   *pDefSettings )
1089{
1090        BDBG_ENTER(BVDC_GetDefaultSettings);
1091
1092        if(pDefSettings)
1093        {
1094                *pDefSettings = s_stDefaultSettings;
1095
1096#if BVDC_P_ORTHOGONAL_VEC
1097                /* Temporarily disable  bVecSwap for new chipsets with orthogonal VEC */
1098                /* so that DISP_0 (main display) can be created with CMP_0 because    */
1099                /* currently the HD_SRC is assumed to be with the VEC that connects   */
1100                /* to CMP_0.  This can be removed after the assumption is removed     */
1101                pDefSettings->bVecSwap = false;
1102#endif
1103        }
1104
1105        BDBG_LEAVE(BVDC_GetDefaultSettings);
1106        return BERR_SUCCESS;
1107}
1108
1109/***************************************************************************
1110 *
1111 */
1112BERR_Code BVDC_GetMaxCompositorCount
1113        ( const BVDC_Handle                hVdc,
1114          uint32_t                        *pulCompositorCount )
1115{
1116        BDBG_ENTER(BVDC_GetMaxCompositorCount);
1117        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1118
1119        /* set return value */
1120        if(pulCompositorCount)
1121        {
1122                *pulCompositorCount = BVDC_P_MAX_COMPOSITOR_COUNT;
1123        }
1124
1125        BDBG_LEAVE(BVDC_GetMaxCompositorCount);
1126        return BERR_SUCCESS;
1127}
1128
1129
1130/***************************************************************************
1131 * BVDC_Open()
1132 *
1133 */
1134BERR_Code BVDC_Open
1135        ( BVDC_Handle                     *phVdc,
1136          BCHP_Handle                      hChip,
1137          BREG_Handle                      hRegister,
1138          BMEM_Heap_Handle                 hMemory,
1139          BINT_Handle                      hInterrupt,
1140          BRDC_Handle                      hRdc,
1141          BTMR_Handle                      hTmr,
1142          const BVDC_Settings             *pDefSettings )
1143{
1144        BVDC_P_Context *pVdc = NULL;
1145        BERR_Code eStatus;
1146        BTMR_Settings sTmrSettings;
1147        uint32_t i;
1148        uint32_t ulCmpCount = 0;
1149
1150        BDBG_ENTER(BVDC_Open);
1151        BDBG_ASSERT(phVdc);
1152        BDBG_ASSERT(hChip);
1153        BDBG_ASSERT(hRegister);
1154        BDBG_ASSERT(hMemory);
1155        BDBG_ASSERT(hInterrupt);
1156        BDBG_ASSERT(hRdc);
1157
1158        /* The handle will be NULL if create fails. */
1159        *phVdc = NULL;
1160
1161        /* check VDC settings */
1162        if(pDefSettings)
1163        {
1164                BVDC_P_PrintHeapInfo(&pDefSettings->stHeapSettings);
1165                eStatus = BERR_TRACE(BVDC_P_CheckDefSettings(&pDefSettings->stHeapSettings));
1166                if( eStatus != BERR_SUCCESS )
1167                {
1168                        goto BVDC_Open_Done;
1169                }
1170
1171                eStatus = BERR_TRACE(BVDC_P_CheckBandgapDefSettings(pDefSettings));
1172                if( eStatus != BERR_SUCCESS )
1173                {
1174                        goto BVDC_Open_Done;
1175                }
1176        }
1177
1178        /* (1) Alloc the main VDC context. */
1179        pVdc = (BVDC_P_Context*)(BKNI_Malloc(sizeof(BVDC_P_Context)));
1180        if(NULL == pVdc)
1181        {
1182                eStatus = BERR_OUT_OF_SYSTEM_MEMORY;
1183                goto BVDC_Open_Done;
1184        }
1185
1186        /* Clear out the context and set defaults. */
1187        BKNI_Memset((void*)pVdc, 0x0, sizeof(BVDC_P_Context));
1188        BDBG_OBJECT_SET(pVdc, BVDC_VDC);
1189
1190        /* Store the hChip, hRegister, hMemory, and hRdc for later use. */
1191        pVdc->hChip      = hChip;
1192        pVdc->hRegister  = hRegister;
1193        pVdc->hMemory    = hMemory;
1194        pVdc->hInterrupt = hInterrupt;
1195        pVdc->hRdc       = hRdc;
1196        pVdc->hTmr       = hTmr;
1197
1198        /* (1.1) Power managment */
1199#ifdef BCHP_PWR_RESOURCE_VDC
1200        BCHP_PWR_AcquireResource(pVdc->hChip, BCHP_PWR_RESOURCE_VDC);
1201#endif
1202
1203        /* (2) Initalize and start timer */
1204        BTMR_GetDefaultTimerSettings(&sTmrSettings);
1205        sTmrSettings.type = BTMR_Type_eSharedFreeRun;
1206        sTmrSettings.cb_isr = NULL;
1207        sTmrSettings.pParm1 = NULL;
1208        sTmrSettings.parm2 = 0;
1209        sTmrSettings.exclusive = true;
1210
1211        eStatus = BTMR_CreateTimer(hTmr, &pVdc->hTimer, &sTmrSettings);
1212        if (eStatus != BERR_SUCCESS)
1213        {
1214                goto BVDC_Open_Done;
1215        }
1216
1217        /* Take in feature, this should be the centralize place to discover about
1218         * chip information and features. */
1219        pVdc->pFeatures = &s_VdcFeatures;
1220
1221        /* Take in default settings. */
1222        pVdc->stSettings = (pDefSettings) ? *pDefSettings : s_stDefaultSettings;
1223
1224        /* Do we need to swap the CMP/VEC. */
1225        pVdc->bSwapVec = (
1226                (pVdc->stSettings.bVecSwap) &&
1227                (pVdc->pFeatures->abAvailCmp[BVDC_CompositorId_eCompositor1]));
1228
1229        /* (3) Allocate Buffer Heap (VDC Internal) */
1230        BVDC_P_BufferHeap_Create(pVdc, &pVdc->hBufferHeap, pVdc->hMemory,
1231                &pVdc->stSettings.stHeapSettings);
1232
1233        /* (4-1) create FGT noise pattern table */
1234        if(pVdc->stSettings.bEnableFgt)
1235        {
1236                pVdc->pucFgtPatTblAddr = BMEM_Heap_AllocAligned(hMemory,
1237                        BVDC_P_FGT_NOISE_PIXEL_PATTERN_TABLE_SIZE,
1238                        BVDC_P_HEAP_MEMORY_ALIGNMENT, 0);
1239                if(!pVdc->pucFgtPatTblAddr)
1240                {
1241                        BDBG_ERR(("Not enough device memory"));
1242                        BDBG_ASSERT(0);
1243                        return BERR_TRACE(BERR_OUT_OF_DEVICE_MEMORY);
1244                }
1245
1246                /* load table */
1247                BVDC_P_Fgt_LoadPatTable(pVdc->pucFgtPatTblAddr);
1248        }
1249
1250        /* (4-2) Create resource */
1251        BVDC_P_Resource_Create(&pVdc->hResource,  pVdc);
1252
1253        /* (5) Alloc context for compositor/display. */
1254        for(i  = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT; i++)
1255        {
1256                if(pVdc->pFeatures->abAvailCmp[i])
1257                {
1258                        BVDC_P_Compositor_Create(pVdc, &pVdc->ahCompositor[i], (BVDC_CompositorId)i);
1259                        pVdc->ahCompositor[i]->ulCmpCount = ulCmpCount; /* count number of the compositors */
1260                        BVDC_P_Display_Create(pVdc, &pVdc->ahDisplay[i], (BVDC_DisplayId)i);
1261                        pVdc->ahDisplay[i]->ulDisplayCnt  = ulCmpCount++;/* count number of displays */
1262                }
1263        }
1264
1265        /* (6) Alloc context for gfx and vfd sources. */
1266        for(i  = 0; i < BVDC_P_MAX_SOURCE_COUNT; i++)
1267        {
1268                if(pVdc->pFeatures->abAvailSrc[i])
1269                {
1270                        BVDC_P_Source_Create(pVdc, &pVdc->ahSource[i], (BAVC_SourceId)i, pVdc->hResource);
1271                }
1272        }
1273
1274        /* (7) Put Hardware into a known state. */
1275        BVDC_P_SoftwareReset((BVDC_Handle)pVdc);
1276
1277        /* (8) Register BVN error recovery handler. */
1278#if (BVDC_SUPPORT_BVN_DEBUG)
1279        eStatus = BVDC_P_CreateErrCb(pVdc);
1280        if(BERR_SUCCESS != eStatus)
1281                goto BVDC_Open_Done;
1282#endif
1283
1284        /* (9) allocate drain buffer (2 pixels deep) for mosaic mode support */
1285#if BVDC_P_SUPPORT_MOSAIC_MODE
1286        pVdc->pvVdcNullBufAddr = BMEM_Heap_AllocAligned(pVdc->hMemory,
1287                16, /* 2 pixels wide, in case 10-bit 4:2:2 capture rounding; */
1288                4,  /* 16 bytes aligned for capture engine */
1289                0   /* no boundary */);
1290        BERR_TRACE(BMEM_Heap_ConvertAddressToOffset(pVdc->hMemory, pVdc->pvVdcNullBufAddr,
1291                &pVdc->ulVdcNullBufOffset));
1292#endif
1293
1294        /* (10) Initialize all DACs to unused */
1295#if BVDC_P_ORTHOGONAL_VEC
1296        for (i = 0; i < BVDC_P_MAX_DACS; i++ )
1297        {
1298                pVdc->aDacOutput[i] = BVDC_DacOutput_eUnused;
1299        }
1300        pVdc->aulDacGrouping = s_aulDacGrouping;
1301#if (BVDC_P_SUPPORT_TDAC_VER == BVDC_P_SUPPORT_TDAC_VER_10)
1302        /* Default Auto = Off */
1303        pVdc->bDacDetectionEnable = (pVdc->stSettings.eDacDetection == BVDC_Mode_eOn) ? true : false;
1304#else
1305        /* Default Auto = On */
1306        pVdc->bDacDetectionEnable = (pVdc->stSettings.eDacDetection == BVDC_Mode_eOff) ? false : true;
1307#endif
1308#endif
1309
1310        /* All done. now return the new fresh context to user. */
1311        *phVdc = (BVDC_Handle)pVdc;
1312
1313BVDC_Open_Done:
1314        BDBG_LEAVE(BVDC_Open);
1315
1316        if ((BERR_SUCCESS != eStatus) && (NULL != pVdc))
1317        {
1318#ifdef BCHP_PWR_RESOURCE_VDC
1319                BCHP_PWR_ReleaseResource(pVdc->hChip, BCHP_PWR_RESOURCE_VDC);
1320#endif
1321                BDBG_OBJECT_DESTROY(pVdc, BVDC_VDC);
1322                BKNI_Free((void*)pVdc);
1323        }
1324
1325        return BERR_TRACE(eStatus);
1326}
1327
1328
1329/***************************************************************************
1330 *
1331 */
1332BERR_Code BVDC_Close
1333        ( BVDC_Handle                      hVdc )
1334{
1335        uint32_t i;
1336        BERR_Code eStatus = BERR_SUCCESS;
1337
1338        BDBG_ENTER(BVDC_Close);
1339
1340        /* Return if trying to free a NULL handle. */
1341        if(!hVdc)
1342        {
1343                goto done;
1344        }
1345
1346        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1347
1348        /* [9] free drain buffer */
1349#if BVDC_P_SUPPORT_MOSAIC_MODE
1350        BMEM_Heap_Free(hVdc->hMemory, hVdc->pvVdcNullBufAddr);
1351#endif
1352
1353        /* [8] Un-Register BVN error recovery handler. */
1354#if (BVDC_SUPPORT_BVN_DEBUG)
1355        BVDC_P_DestroyErrCb(hVdc);
1356#endif
1357
1358        /* [7] Make sure we disable capture before we exit so that it would
1359         * not write to memory that potential contain heap bookeeping
1360         * next time we create. */
1361        BVDC_P_ResetBvn(hVdc);
1362
1363#if (BVDC_P_SUPPORT_VDEC)
1364        BVDC_P_Vdec_Reset(hVdc->hRegister);
1365#endif
1366
1367        /* [6] Free sources handles. */
1368        for(i  = 0; i < BVDC_P_MAX_SOURCE_COUNT; i++)
1369        {
1370                if(hVdc->pFeatures->abAvailSrc[i])
1371                {
1372                        BVDC_P_Source_Destroy(hVdc->ahSource[i]);
1373                }
1374        }
1375
1376        /* [5] Free compositor handles . */
1377        for(i  = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT; i++)
1378        {
1379                if(hVdc->pFeatures->abAvailCmp[i])
1380                {
1381                        BVDC_P_Display_Destroy(hVdc->ahDisplay[i]);
1382                        BVDC_P_Compositor_Destroy(hVdc->ahCompositor[i]);
1383                }
1384        }
1385
1386        /* [4-2] destroy resource */
1387        BVDC_P_Resource_Destroy(hVdc->hResource);
1388
1389        /* [4-1] Free FGT memory */
1390        if(hVdc->stSettings.bEnableFgt)
1391        {
1392                BMEM_Free(hVdc->hMemory, hVdc->pucFgtPatTblAddr);
1393        }
1394
1395        /* [3] Release Buffer Heap */
1396        BVDC_P_BufferHeap_Destroy(hVdc->hBufferHeap);
1397
1398        /* [2] Destroy Timer */
1399        eStatus = BTMR_DestroyTimer(hVdc->hTimer);
1400        if (eStatus != BERR_SUCCESS)
1401        {
1402                return BERR_TRACE(eStatus);
1403        }
1404
1405        /* [1.1] Power managment */
1406#ifdef BCHP_PWR_RESOURCE_VDC
1407        BCHP_PWR_ReleaseResource(hVdc->hChip, BCHP_PWR_RESOURCE_VDC);
1408#endif
1409
1410        /* [1] Release main context.   User will be responsible for destroying
1411         * compositors, sources, windows, and displays prior. */
1412        BDBG_OBJECT_DESTROY(hVdc, BVDC_VDC);
1413        BKNI_Free((void*)hVdc);
1414
1415done:
1416        BDBG_LEAVE(BVDC_Close);
1417        return eStatus;
1418}
1419
1420/***************************************************************************
1421 *
1422 */
1423void BVDC_GetDefaultStandbySettings
1424        ( BVDC_StandbySettings            *pStandbypSettings )
1425{
1426        BSTD_UNUSED(pStandbypSettings);
1427        return;
1428}
1429
1430/***************************************************************************
1431 *
1432 */
1433BERR_Code BVDC_Standby
1434        ( BVDC_Handle                      hVdc,
1435          const BVDC_StandbySettings      *pStandbypSettings )
1436{
1437        uint32_t i, j;
1438        bool bActive = false;
1439        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1440
1441        BSTD_UNUSED(pStandbypSettings);
1442
1443        for(i = 0; i < BVDC_P_MAX_SOURCE_COUNT && !bActive; i++)
1444        {
1445                bActive |= BVDC_P_STATE_IS_ACTIVE(hVdc->ahSource[i]);
1446                BDBG_MSG(("hVdc->ahSource[%d]=%d", i, BVDC_P_STATE_IS_ACTIVE(hVdc->ahSource[i])));
1447        }
1448
1449        for(i = 0; i < BVDC_P_MAX_DISPLAY_COUNT && !bActive; i++)
1450        {
1451                bActive |= BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i]);
1452                BDBG_MSG(("hVdc->ahDisplay[%d]=%d", i, BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i])));
1453        }
1454
1455        for(i = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT && !bActive; i++)
1456        {
1457                bActive |= BVDC_P_STATE_IS_ACTIVE(hVdc->ahCompositor[i]);
1458                BDBG_MSG(("hVdc->ahCompositor[%d]=%d", i, BVDC_P_STATE_IS_ACTIVE(hVdc->ahCompositor[i])));
1459
1460                if(hVdc->pFeatures->abAvailCmp[i])
1461                {
1462                        for(j = 0; j < BVDC_P_MAX_WINDOW_COUNT && !bActive; j++)
1463                        {
1464                                bActive |= BVDC_P_STATE_IS_ACTIVE(hVdc->ahCompositor[i]->ahWindow[j]);
1465                                BDBG_MSG(("hVdc->ahCompositor[%d]->ahWindow[%d]=%d",
1466                                        i, j, BVDC_P_STATE_IS_ACTIVE(hVdc->ahCompositor[i]->ahWindow[j])));
1467                        }
1468                }
1469        }
1470
1471        BDBG_MSG(("Power Standby %s ready!", !bActive ? "is" : "is not"));
1472
1473#ifdef BCHP_PWR_RESOURCE_VDC
1474        if(bActive) {
1475                BDBG_ERR(("Cannot enter standby due to VDC in use"));
1476                return BERR_UNKNOWN;
1477        }
1478        /* if we get to this point, then nothing is in use and we can power down */
1479        if(!hVdc->bStandby)
1480        {
1481                BCHP_PWR_ReleaseResource(hVdc->hChip, BCHP_PWR_RESOURCE_VDC);
1482                hVdc->bStandby = true;
1483                BDBG_MSG(("Entering standby mode!"));
1484        }
1485#endif
1486
1487        return BERR_SUCCESS;
1488}
1489
1490/***************************************************************************
1491 *
1492 */
1493BERR_Code BVDC_Resume
1494        ( BVDC_Handle                      hVdc )
1495{
1496        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1497
1498#ifdef BCHP_PWR_RESOURCE_VDC
1499        if(!hVdc->bStandby)
1500        {
1501                BDBG_ERR(("Not in standby"));
1502                return BERR_UNKNOWN;
1503        }
1504        else
1505        {
1506                BCHP_PWR_AcquireResource(hVdc->hChip, BCHP_PWR_RESOURCE_VDC);
1507                hVdc->bStandby = false;
1508                BDBG_MSG(("Leaving standby mode!"));
1509        }
1510#endif
1511
1512        return BERR_SUCCESS;
1513}
1514
1515
1516/***************************************************************************
1517 *
1518 */
1519#if (BDBG_DEBUG_BUILD)
1520static void BVDC_P_CheckDisplayAlignAdjustedStatus
1521        ( BVDC_Handle                      hVdc )
1522{
1523        uint32_t k;
1524
1525        BDBG_ENTER(BVDC_P_CheckDisplayAlignAdjustStatus);
1526        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1527
1528        for (k = 0; k < BVDC_P_MAX_COMPOSITOR_COUNT; k++)
1529        {
1530                /* Bypass the inactive ones. */
1531                if(!hVdc->ahDisplay[k] || !hVdc->ahDisplay[k]->hCompositor)
1532                {
1533                        continue;
1534                }
1535
1536                if (hVdc->ahDisplay[k]->bAlignAdjusting)
1537                {
1538                        BDBG_ERR(("Display %d is in the process of VEC alignment", k));
1539                }
1540        }
1541
1542        BDBG_ENTER(BVDC_P_CheckDisplayAlignAdjustStatus);
1543        return;
1544}
1545#endif
1546
1547/***************************************************************************
1548 *
1549 */
1550static BERR_Code BVDC_P_CheckApplyChangesStatus
1551        ( BVDC_Handle                      hVdc )
1552{
1553        uint32_t i, j;
1554        BERR_Code eStatus = BERR_SUCCESS;
1555
1556        BDBG_ENTER(BVDC_P_CheckApplyChangesStatus);
1557        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1558
1559        /* Active various debug message at runtime */
1560#if (BDBG_DEBUG_BUILD)
1561        {
1562                uint32_t ulReg = BREG_Read32(hVdc->hRegister, BCHP_BMISC_SCRATCH_0);
1563                hVdc->bForcePrint = (ulReg & (1 << 0)); /* BMISC_SCRATCH_0[00:00] */
1564                                                        /* BMISC_SCRATCH_0[31:01] - avail */
1565        }
1566#endif
1567
1568        for(i = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT; i++)
1569        {
1570                /* Bypass the inactive ones. */
1571                if(!hVdc->ahDisplay[i] || !hVdc->ahDisplay[i]->hCompositor)
1572                {
1573                        continue;
1574                }
1575
1576                BDBG_OBJECT_ASSERT(hVdc->ahDisplay[i], BVDC_DSP);
1577                BDBG_OBJECT_ASSERT(hVdc->ahDisplay[i]->hCompositor, BVDC_CMP);
1578
1579                /* Wait for compositor/display to be applied/destroyed. */
1580                if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i]) &&
1581                   BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i]->hCompositor) &&
1582                   hVdc->ahDisplay[i]->bSetEventPending)
1583                {
1584                        BDBG_MSG(("Waiting for Display%d to be applied", hVdc->ahDisplay[i]->eId));
1585                        eStatus = BKNI_WaitForEvent(hVdc->ahDisplay[i]->hAppliedDoneEvent,
1586                                BVDC_P_MAX_VEC_APPLY_WAIT_TIMEOUT);
1587                        if(BERR_TIMEOUT == eStatus)
1588                        {
1589                                BDBG_ERR(("Display%d apply times out", hVdc->ahDisplay[i]->eId));
1590                                return BERR_TRACE(eStatus);
1591                        }
1592                }
1593
1594                /* Wait for window to applied/destroy */
1595                for(j = 0; j < BVDC_P_MAX_WINDOW_COUNT; j++)
1596                {
1597                        if((BVDC_P_STATE_IS_SHUTDOWNPENDING(hVdc->ahDisplay[i]->hCompositor->ahWindow[j]) ||
1598                            BVDC_P_STATE_IS_SHUTDOWNRUL(hVdc->ahDisplay[i]->hCompositor->ahWindow[j]) ||
1599                            BVDC_P_STATE_IS_SHUTDOWN(hVdc->ahDisplay[i]->hCompositor->ahWindow[j]) ||
1600                            BVDC_P_STATE_IS_INACTIVE(hVdc->ahDisplay[i]->hCompositor->ahWindow[j])) &&
1601                           (hVdc->ahDisplay[i]->hCompositor->ahWindow[j]->bSetDestroyEventPending))
1602                        {
1603                                BVDC_Window_Handle hWindow = hVdc->ahDisplay[i]->hCompositor->ahWindow[j];
1604                                BDBG_OBJECT_ASSERT(hWindow, BVDC_WIN);
1605                                BDBG_MSG(("Waiting for window%d to be destroyed", hWindow->eId));
1606                                eStatus = BKNI_WaitForEvent(hWindow->hDestroyDoneEvent,
1607                                        BVDC_P_MAX_DESTROY_WAIT_TIMEOUT);
1608                                if(BERR_TIMEOUT == eStatus)
1609                                {
1610#if (BDBG_DEBUG_BUILD)
1611                                        const BVDC_P_Window_DirtyBits  *pDirty = &(hWindow->stCurInfo.stDirty);
1612                                        const BVDC_P_VnetMode  *pVntMd = &(hWindow->stVnetMode);
1613                                        BVDC_P_CheckDisplayAlignAdjustedStatus(hVdc);
1614                                        BDBG_ERR(("Window%d destroy times out", hWindow->eId));
1615                                        BDBG_ERR(("VnetMode 0x%08lx, readerState %d, writerState %d",
1616                                                *(uint32_t *) pVntMd, hWindow->stCurInfo.eReaderState, hWindow->stCurInfo.eWriterState));
1617                                        BDBG_ERR(("   bShutDown %d, bRecfgVnet %d, bSrcPending %d, dirty 0x%08lx",
1618                                                pDirty->stBits.bShutdown, pDirty->stBits.bReConfigVnet, pDirty->stBits.bSrcPending, pDirty->aulInts[0]));
1619#endif
1620                                        return BERR_TRACE(eStatus);
1621                                }
1622                        }
1623                        else if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i]->hCompositor->ahWindow[j]) &&
1624                                hVdc->ahDisplay[i]->hCompositor->ahWindow[j]->bSetAppliedEventPending)
1625                        {
1626                                BVDC_Window_Handle hWindow = hVdc->ahDisplay[i]->hCompositor->ahWindow[j];
1627                                BDBG_OBJECT_ASSERT(hWindow, BVDC_WIN);
1628                                BDBG_MSG(("Waiting for window%d to be applied", hWindow->eId));
1629                                eStatus = BKNI_WaitForEvent(hWindow->hAppliedDoneEvent,
1630                                        BVDC_P_MAX_APPLY_WAIT_TIMEOUT);
1631                                if(BERR_TIMEOUT == eStatus)
1632                                {
1633#if (BDBG_DEBUG_BUILD)
1634                                        const BVDC_P_Window_DirtyBits *pDirty = &(hWindow->stCurInfo.stDirty);
1635                                        const BVDC_P_VnetMode  *pVntMd = &(hWindow->stVnetMode);
1636                                        BVDC_P_CheckDisplayAlignAdjustedStatus(hVdc);
1637                                        BDBG_ERR(("Window%d apply times out", hWindow->eId));
1638                                        BDBG_ERR(("VnetMode 0x%08lx, readerState %d, writerState %d",
1639                                                *(uint32_t *) pVntMd, hWindow->stCurInfo.eReaderState, hWindow->stCurInfo.eWriterState));
1640                                        BDBG_ERR(("   bShutDown %d, bRecfgVnet %d, bSrcPending %d, dirty 0x%08lx",
1641                                                pDirty->stBits.bShutdown, pDirty->stBits.bReConfigVnet, pDirty->stBits.bSrcPending, pDirty->aulInts[0]));
1642#endif
1643                                        return BERR_TRACE(eStatus);
1644                                }
1645                        }
1646                }
1647        }
1648
1649        for(i = 0; i < BVDC_P_MAX_SOURCE_COUNT; i++)
1650        {
1651                if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahSource[i]) &&
1652                   hVdc->ahSource[i]->bUserAppliedChanges)
1653                {
1654                        BDBG_OBJECT_ASSERT(hVdc->ahSource[i], BVDC_SRC);
1655                        BDBG_MSG(("Waiting for Source%d to be applied", hVdc->ahSource[i]->eId));
1656                        eStatus = BKNI_WaitForEvent(hVdc->ahSource[i]->hAppliedDoneEvent,
1657                                BVDC_P_MAX_APPLY_WAIT_TIMEOUT);
1658                        if(BERR_TIMEOUT == eStatus)
1659                        {
1660#if (BDBG_DEBUG_BUILD)
1661                                BVDC_P_CheckDisplayAlignAdjustedStatus(hVdc);
1662                                BDBG_ERR(("Source%d apply times out", hVdc->ahSource[i]->eId));
1663#endif
1664                                return BERR_TRACE(eStatus);
1665                        }
1666                }
1667        }
1668
1669        BDBG_LEAVE(BVDC_P_CheckApplyChangesStatus);
1670        return eStatus;
1671}
1672
1673
1674/***************************************************************************
1675 * BVDC_AbortChanges
1676 *
1677 */
1678BERR_Code BVDC_AbortChanges
1679        ( BVDC_Handle                      hVdc )
1680{
1681        uint32_t i;
1682
1683        BDBG_ENTER(BVDC_AbortChanges);
1684        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1685
1686        for(i = 0; i < BVDC_P_MAX_SOURCE_COUNT; i++)
1687        {
1688                if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahSource[i]) ||
1689                   BVDC_P_STATE_IS_CREATE(hVdc->ahSource[i]) ||
1690                   BVDC_P_STATE_IS_DESTROY(hVdc->ahSource[i]))
1691                {
1692                        BVDC_P_Source_AbortChanges(hVdc->ahSource[i]);
1693                }
1694        }
1695
1696        for(i = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT; i++)
1697        {
1698                if((BVDC_P_STATE_IS_ACTIVE(hVdc->ahCompositor[i]) &&
1699                    BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i])) ||
1700                   (BVDC_P_STATE_IS_CREATE(hVdc->ahCompositor[i]) &&
1701                    BVDC_P_STATE_IS_CREATE(hVdc->ahDisplay[i])) ||
1702                   (BVDC_P_STATE_IS_DESTROY(hVdc->ahCompositor[i]) &&
1703                    BVDC_P_STATE_IS_DESTROY(hVdc->ahDisplay[i])))
1704                {
1705                        BVDC_P_Display_AbortChanges(hVdc->ahDisplay[i]);
1706                        BVDC_P_Compositor_AbortChanges(hVdc->ahCompositor[i]);
1707                }
1708        }
1709
1710        BDBG_LEAVE(BVDC_AbortChanges);
1711        return BERR_SUCCESS;
1712}
1713
1714
1715/***************************************************************************
1716 * BVDC_ApplyChanges
1717 *
1718 * Validate/Apply User's new changes.  This function will not result in
1719 * RUL building, but rather taken the new changes.  The ISR will be
1720 * responsible for building the RUL.
1721 */
1722BERR_Code BVDC_ApplyChanges
1723        ( BVDC_Handle                      hVdc )
1724{
1725        uint32_t i;
1726        BERR_Code eStatus = BERR_SUCCESS;
1727
1728        BDBG_ENTER(BVDC_ApplyChanges);
1729        BDBG_OBJECT_ASSERT(hVdc, BVDC_VDC);
1730
1731        BDBG_MSG(("-------------ApplyChanges(%d)------------", hVdc->ulApplyCnt++));
1732
1733        /* +------------------+
1734         * | VALIDATE CHANGES |
1735         * +------------------+
1736         * User's new settings reject if we have bad new setting with
1737         * approriate error status.  No new settings will be used.
1738         * Frontend   Things that are going to cause failures should be caught
1739         * here.   Other failures may able to detect early in the set function
1740         * where error checking is not depended on other settings.   Our build
1741         * RULs and ApplyChanges should not failed anymore. */
1742        eStatus = BERR_TRACE(BVDC_P_Source_ValidateChanges(hVdc->ahSource));
1743        if(BERR_SUCCESS != eStatus)
1744        {
1745                return BERR_TRACE(eStatus);
1746        }
1747
1748        eStatus = BERR_TRACE(BVDC_P_Display_ValidateChanges(hVdc->ahDisplay));
1749        if(BERR_SUCCESS != eStatus)
1750        {
1751                return BERR_TRACE(eStatus);
1752        }
1753
1754        eStatus = BERR_TRACE(BVDC_P_Compositor_ValidateChanges(hVdc->ahCompositor));
1755        if(BERR_SUCCESS != eStatus)
1756        {
1757                return BERR_TRACE(eStatus);
1758        }
1759
1760        /* +-------------- +
1761         * | APPLY CHANGES |
1762         * +---------------+
1763         * Apply user's new settings it will be include in the next RUL building*/
1764        BKNI_EnterCriticalSection();
1765        BDBG_ASSERT(0 == hVdc->ulInsideCs);
1766        hVdc->ulInsideCs++;
1767
1768        for(i = 0; i < BVDC_P_MAX_SOURCE_COUNT; i++)
1769        {
1770                if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahSource[i]) ||
1771                   BVDC_P_STATE_IS_CREATE(hVdc->ahSource[i]) ||
1772                   BVDC_P_STATE_IS_DESTROY(hVdc->ahSource[i]))
1773                {
1774                        BVDC_P_Source_ApplyChanges_isr(hVdc->ahSource[i]);
1775                }
1776        }
1777
1778        BVDC_P_Vec_Update_OutMuxes_isr(hVdc);
1779
1780        /* Note, since display has id now, which might be different from compositor
1781           id, we need to loop them separately in case cmp/win logic depends on its
1782           display's context changes; */
1783        for(i = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT; i++)
1784        {
1785                if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahDisplay[i]) ||
1786                   BVDC_P_STATE_IS_CREATE(hVdc->ahDisplay[i]) ||
1787                   BVDC_P_STATE_IS_DESTROY(hVdc->ahDisplay[i]))
1788                {
1789                        BVDC_P_Display_ApplyChanges_isr(hVdc->ahDisplay[i]);
1790                }
1791        }
1792        for(i = 0; i < BVDC_P_MAX_COMPOSITOR_COUNT; i++)
1793        {
1794                if(BVDC_P_STATE_IS_ACTIVE(hVdc->ahCompositor[i]) ||
1795                   BVDC_P_STATE_IS_CREATE(hVdc->ahCompositor[i]) ||
1796                   BVDC_P_STATE_IS_DESTROY(hVdc->ahCompositor[i]))
1797                {
1798                        BVDC_P_Compositor_ApplyChanges_isr(hVdc->ahCompositor[i]);
1799                }
1800        }
1801
1802        hVdc->ulInsideCs--;
1803        BKNI_LeaveCriticalSection();
1804
1805        /* +------------------------------------- +
1806         * | WAIT FOR CHANGES APPLIED (next vsync)|
1807         * +--------------------------------------+
1808         * After the changes are put in RUL in _isr it will set event to notify
1809         * that changes will be hardware on next trigger. */
1810        eStatus = BERR_TRACE(BVDC_P_CheckApplyChangesStatus(hVdc));
1811        if(BERR_SUCCESS != eStatus)
1812        {
1813                return BERR_TRACE(eStatus);
1814        }
1815
1816        BDBG_LEAVE(BVDC_ApplyChanges);
1817        return BERR_SUCCESS;
1818}
1819
1820/* End of File */
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