source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/xpt/7552/bxpt_priv.h

Last change on this file was 2, checked in by jglee, 11 years ago

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1/***************************************************************************
2 *     Copyright (c) 2003-2011, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bxpt_priv.h $
11 * $brcm_Revision: Hydra_Software_Devel/24 $
12 * $brcm_Date: 12/16/11 2:59p $
13 *
14 * Private code for the data transport porting interface.
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/portinginterface/xpt/base2/bxpt_priv.h $
19 *
20 * Hydra_Software_Devel/24   12/16/11 2:59p gmullen
21 * SW7425-1838: Merged to Hydra
22 *
23 * Hydra_Software_Devel/SW7425-1838/1   12/6/11 5:01p gmullen
24 * SW7425-1838: Ported dynamic splicing to base2 files
25 *
26 * Hydra_Software_Devel/23   12/2/11 12:13p jtna
27 * SW7425-1863: refactor xpt standby power management
28 *
29 * Hydra_Software_Devel/22   11/10/11 12:25p jtna
30 * SW7425-1672: merge to hydra
31 *
32 * Hydra_Software_Devel/SW7425-1672/1   11/9/11 5:51p jtna
33 * SW7425-1672: set FORCE_RESYNC flag on descriptors when packetizing ES
34 *
35 * Hydra_Software_Devel/21   11/3/11 3:47p gmullen
36 * SW7425-1323: Fixed B0/B1 binary compatability issue
37 *
38 * Hydra_Software_Devel/20   10/3/11 10:01a gmullen
39 * SW7425-1183: Missing WakeupArmed in xpt handle
40 *
41 * Hydra_Software_Devel/19   9/30/11 3:10p gmullen
42 * SW7425-1183: Merged to Hydra
43 *
44 * Hydra_Software_Devel/SW7425-1183/1   8/30/11 9:05a gmullen
45 * SW7425-1183: Acquire the CLK216 resource when entering standby
46 *
47 * Hydra_Software_Devel/18   9/30/11 12:14p jtna
48 * SW7425-1266: merge BXPT_Rave_AllocCx() and related changes
49 *
50 * Hydra_Software_Devel/17   9/28/11 11:47a gmullen
51 * SW7425-1323: Cached RAVE settings in DRAM to reduce overhead
52 *
53 * Hydra_Software_Devel/16   9/21/11 10:17a gmullen
54 * SW7425-1323: Merged to Hydra
55 *
56 * Hydra_Software_Devel/SW7425-1323/1   9/21/11 10:02a gmullen
57 * SW7425-1323: Potential workaround.
58 *
59 * Hydra_Software_Devel/15   9/12/11 4:36p gmullen
60 * SW7344-193: Merged changes to Hydra
61 *
62 * Hydra_Software_Devel/SW7344-193/1   9/7/11 4:34p gmullen
63 * SW7344-193: Added tri-state logic to jitter API
64 *
65 * Hydra_Software_Devel/14   7/27/11 3:59p gmullen
66 * SW7425-1016: Ported changes to 40nm chips
67 *
68 * Hydra_Software_Devel/SW7425-1016/1   7/27/11 3:08p gmullen
69 * SW7425-1016: Ported fix to 40nm chips
70 *
71 * Hydra_Software_Devel/13   7/13/11 10:04a jtna
72 * SW7231-296: initial non-sram pm work
73 *
74 * Hydra_Software_Devel/12   6/27/11 2:39p gmullen
75 * SW7231-186: Merged power management code to Hydra branch
76 *
77 * Hydra_Software_Devel/SW7231-186/1   6/13/11 5:59p gmullen
78 * SW7231-186: Implemented SRAM save and restore for XPT standby/resume
79 *
80 * Hydra_Software_Devel/11   6/3/11 4:34p gmullen
81 * SW7425-653: Merged changes to Hydra branch
82 *
83 * Hydra_Software_Devel/SW7425-653/1   6/2/11 10:35a gmullen
84 * SW7425-653: Added non-realtime transcoding support
85 *
86 * Hydra_Software_Devel/10   5/16/11 5:08p gmullen
87 * SW7408-284: Added support for jitter adjust in PCR hw to PI
88 *
89 * Hydra_Software_Devel/9   5/12/11 4:59p gmullen
90 * SW7231-128: Merged to mainline
91 *
92 * Hydra_Software_Devel/SW7231-128/1   5/10/11 1:40p gmohile
93 * SW7231-128 : Add power management support
94 *
95 * Hydra_Software_Devel/8   4/15/11 4:49p gmullen
96 * SW7425-313: Merged to mainline
97 *
98 * Hydra_Software_Devel/SW7425-313/1   4/13/11 2:05p gmullen
99 * SW7425-313: Added parser remapping support
100 *
101 * Hydra_Software_Devel/7   4/11/11 9:15a gmullen
102 * SW7346-119: Merged fix to mainline
103 *
104 * Hydra_Software_Devel/SW7346-119/1   4/7/11 3:43p gmullen
105 * SW7346-119: Disable CC checking when enabling all-pass mode. Restore
106 * when exiting all-pass
107 *
108 * Hydra_Software_Devel/6   3/11/11 1:07p gmullen
109 * SW7346-112: Merged to mainline
110 *
111 * Hydra_Software_Devel/SW7346-112/1   3/11/11 9:39a gmullen
112 * SW7346-112: Recalc blockout when packet length is changed
113 *
114 * Hydra_Software_Devel/5   1/17/11 8:54p gmullen
115 * SW7422-115: Removed SvcModeEn from BXPT_Rave_RecordSettings struct and
116 * add SvcMvcEn to BXPT_Rave_IndexerSettings
117 *
118 * Hydra_Software_Devel/SW7422-115/1   1/10/11 1:31p gmullen
119 * SW7422-115: Removed SvcModeEn from BXPT_Rave_RecordSettings struct and
120 * add  SvcMvcEn to BXPT_Rave_IndexerSettings.
121 *
122 * Hydra_Software_Devel/4   10/28/10 2:08p gmullen
123 * SW7422-20: Checkin ported files
124 *
125 * Hydra_Software_Devel/3   10/27/10 1:20p gmullen
126 * SW7422-20: Ported to 7422
127 *
128 * Hydra_Software_Devel/2   10/25/10 5:32p gmullen
129 * SW7422-20: Changed _P_MAX defines to _NUM
130 *
131 * Hydra_Software_Devel/1   10/25/10 2:09p gmullen
132 * SW7425-15: Moved srcs to base2 folder
133 *
134 * Hydra_Software_Devel/1   10/8/10 2:58p gmullen
135 * SW7425-15: Added header files
136 *
137 * Hydra_Software_Devel/57   7/7/10 11:37a gmullen
138 * SW7401-4402: Fixed compilation error for 734x
139 *
140 * Hydra_Software_Devel/56   7/4/10 5:33p gmullen
141 * SW7630-81: Added support for QUICK
142 *
143 * Hydra_Software_Devel/55   4/23/10 11:21a gmullen
144 * SW7405-4254: Route PCR PID channel to RAVE only when stream PCRs are
145 * used.
146 *
147 * Hydra_Software_Devel/54   11/17/09 3:07p gmullen
148 * SW7408-9: Finished adding 7408 support to XPT
149 *
150 * Hydra_Software_Devel/53   11/2/09 10:53a gmullen
151 * SW3548-2589: Use reference counting when deciding to disable PID
152 * channels
153 *
154 * Hydra_Software_Devel/52   10/1/09 11:12a gmullen
155 * SW7405-3102: ResetPacing in Setting struct incorrectly set if pacing is
156 * enabled
157 *
158 * Hydra_Software_Devel/51   9/23/09 2:26p gmullen
159 * SW7405-2994: Merged fix to Hydra_Software_Devel
160 *
161 * Hydra_Software_Devel/SW7405-2994/1   9/8/09 6:56p gmullen
162 * SW7405-2994: Stored MPEG mode setting for CONT_COUNT_IGNORE in module
163 * handle
164 *
165 * Hydra_Software_Devel/50   9/2/09 2:13p piyushg
166 * SW3548-2363: restore SC_OR_MODE for cleaner scrambling detection.
167 * Currently avaibale in 3549B1 and higher chips. Enable in others as
168 * and when RDB is updated.
169 *
170 * Hydra_Software_Devel/49   9/1/09 9:04a gmullen
171 * SW3548-2368: Merged fix to mainline
172 *
173 * Hydra_Software_Devel/SW3548-2368/1   8/23/09 4:09p gmullen
174 * PRSW3548-2368: Created new context type for VCT handling
175 *
176 * Hydra_Software_Devel/48   7/31/09 2:44p gmullen
177 * PR54331: Added 35130 to XPT support.
178 *
179 * Hydra_Software_Devel/47   7/14/09 10:22a piyushg
180 * PR56771: Add XPT PI code for 7342.
181 *
182 * Hydra_Software_Devel/46   7/13/09 10:01a gmullen
183 * PR56760: Added dummy descriptor and wait until dummy desc is consumed.
184 *
185 * Hydra_Software_Devel/45   6/17/09 6:46p gmullen
186 * PR56110: Added support.xpt/7550/uif_image/a0
187 *
188 * Hydra_Software_Devel/44   6/2/09 10:29a gmullen
189 * PR51821: Merged workaround to mainline.
190 *
191 * Hydra_Software_Devel/PR51821/1   5/26/09 8:02p gmullen
192 * PR51821: Added workarounds and warning mesg.
193 *
194 * Hydra_Software_Devel/43   4/7/09 5:25p piyushg
195 * PR52986: Add support for 7635
196 * Added directory element "7635".
197 *
198 * Hydra_Software_Devel/42   1/27/09 1:10p gmullen
199 * PR51625: Added 7336 support
200 *
201 * Hydra_Software_Devel/41   1/9/09 3:41p gmohile
202 * PR 50861 : Add detection of DivX sequence header in s/w rave
203 *
204 * Hydra_Software_Devel/40   12/19/08 1:59p yili
205 * PR42660:IPTV integration
206 *
207 * Hydra_Software_Devel/39   12/15/08 2:36p gmullen
208 * PR48908: Removed power management code from XPT PI.
209 *
210 * Hydra_Software_Devel/38   12/4/08 7:40p vishk
211 * PR 30494: Application does not remove P-skip frames from a few Divx avi
212 * streams.
213 * PR 44712: CBD data missing when ITB size is large (and when softrave is
214 * used).
215 *
216 * Hydra_Software_Devel/37   11/26/08 4:15p gmullen
217 * PR47755: Added support for 7420.
218 *
219 * Hydra_Software_Devel/36   10/28/08 4:19p gmullen
220 * PR46544: Added power management support.
221 *
222 * Hydra_Software_Devel/35   8/18/08 2:57p gmullen
223 * PR45362: Number of playback channels that support muxing should be
224 * programmable.
225 *
226 * Hydra_Software_Devel/34   7/16/08 3:44p gmullen
227 * PR37867: Merged playback mux code to Hydra_Software_Devel
228 *
229 * Hydra_Software_Devel/33   6/16/08 11:56a piyushg
230 * PR39234: Change some comments and API names for setting up
231 * multiple message buffers for same PID channel.
232 *
233 * Hydra_Software_Devel/32   5/30/08 7:25p gmullen
234 * PR43123: Fixed ITB alignment bug in soft RAVE config.
235 *
236 * Hydra_Software_Devel/31   5/7/08 10:47a gmullen
237 * PR42443: Removed call to change band rates when changing parser mode.
238 *
239 * Hydra_Software_Devel/30   3/26/08 11:24a gmullen
240 * PR38954: Added 3548 support to XPT PI.
241 *
242 * Hydra_Software_Devel/29   3/17/08 1:03p gmullen
243 * PR40675: Added support to route all mesg filter data on R-pipe.
244 *
245 * Hydra_Software_Devel/28   3/13/08 6:43p qcheng
246 * PR40402: Add ICAM support to BCM7325 A0
247 *
248 * Hydra_Software_Devel/27   3/7/08 4:54p gmullen
249 * PR38618: Added 7118C0 support
250 *
251 * Hydra_Software_Devel/26   3/6/08 3:47p piyushg
252 * PR39234: Initial checkin for API's to support PID Duplication.
253 *
254 * Hydra_Software_Devel/25   2/28/08 11:24a gmullen
255 * PR37893: Ported soft RAVE to XPT PI.
256 *
257 * Hydra_Software_Devel/24   1/23/08 10:08a gmullen
258 * PR38884: Updated for B0
259 *
260 * Hydra_Software_Devel/23   12/19/07 9:01a gmullen
261 * PR38274: Updated PI for final version of D0 RDB.
262 *
263 * Hydra_Software_Devel/SanJose_CDI_Devel/2   12/17/07 6:43p shuang
264 * PR37867:Merge Jethead patch in order to support DirecTV AM21 project
265 * which ATSC data will input through USB interface.
266 * Merge Magnum Phase 7.0.
267 *
268 * Hydra_Software_Devel/22   11/29/07 3:57p gmullen
269 * PR37062: Removed BAVC_ItbEsType_eDvdMpeg2Video support.
270 * BXPT_Rave_AvSettings.VobMode is now used to indicate VOB streams for
271 * 7401.
272 *
273 * Hydra_Software_Devel/21   11/28/07 11:39a gmullen
274 * PR36900: Added 7335 support
275 *
276 * Hydra_Software_Devel/20   10/30/07 3:11p gmullen
277 * PR35018: Added support for 7325
278 *
279 * Hydra_Software_Devel/19   10/2/07 2:06p katrep
280 * PR35544: Fixed SW RAVE memory leak in XPT.Now XPT tracks the memory
281 * allocated by it.
282 *
283 * Hydra_Software_Devel/18   7/19/07 5:06p gmullen
284 * PR32771: Changed wraparound threshold computation for IP contexts.
285 *
286 * Hydra_Software_Devel/17   7/13/07 4:09p piyushg
287 * PR32218: PACING_START bit is reset whenever
288 * TS_RANGE_ERROR interrupt occurs.
289 *
290 * Hydra_Software_Devel/16   5/17/07 2:17p gmullen
291 * PR30877: Added support for dedicated playback heap handle.
292 *
293 * Hydra_Software_Devel/15   4/27/07 8:44a katrep
294 * PR29959: Added support in RAVE to change the CDB context end pointer
295 * required for DSS,MPEG,TimeStamp support
296 *
297 * Hydra_Software_Devel/14   3/22/07 11:52a gmullen
298 * PR28909: Added Transcoding bool to struct BXPT_Rave_AvSettings
299 *
300 * Hydra_Software_Devel/13   2/14/07 1:10p gmullen
301 * PR27642: Added support for 7405.
302 *
303 * Hydra_Software_Devel/12   2/6/07 7:05p gmullen
304 * PR26217: Added B0 support.
305 *
306 * Hydra_Software_Devel/11   11/27/06 4:24p katrep
307 * PR25431: Added code to detect the lost data ready interrupt and
308 * generate sw callback
309 *
310 * Hydra_Software_Devel/10   11/22/06 4:58p gmullen
311 * PR26109: Updated for 7403.
312 *
313 * Hydra_Software_Devel/9   11/2/06 4:31p gmullen
314 * PR25402: Added support for secure heap to RS and XC buffer code.
315 *
316 * Hydra_Software_Devel/8   8/17/06 6:01p katrep
317 * PR23114: Added Support for 7440 chip
318 *
319 * Hydra_Software_Devel/7   8/4/06 2:11a btan
320 * PR22187: Move hsm out from xpt.
321 *
322 * Hydra_Software_Devel/6   7/24/06 5:04p gmullen
323 * PR20082: Added support for PIC counters.
324 *
325 * Hydra_Software_Devel/5   7/13/06 11:37a katrep
326 * PR20316: Added support to set/unset PSI setting per pid channel basis
327 * as it's supported by new HW arch.PR20315:Also added support for 32
328 * byte filters.Default filter size is 16 bytes.32 Bytes filters can be
329 * enabled at compile time by -DBXPT_FILTER_32
330 *
331 * Hydra_Software_Devel/4   3/31/06 11:30a gmullen
332 * PR20565: Added UseHostPcrs to settings struct.
333 *
334 * Hydra_Software_Devel/3   3/16/06 5:10p gmullen
335 * PR20218: PES SYNC mode not initialized. Fixed and tested.
336 *
337 * Hydra_Software_Devel/2   2/1/06 10:19a gmullen
338 * PR18998: Fixed overflow issue in RAVE ITB/CDB, added support for PB
339 * channels.
340 *
341 * Hydra_Software_Devel/12   1/9/06 11:24a qcheng
342 * PR18909: Add ICAM and keyladder support for 97401
343 *
344 * Hydra_Software_Devel/11   1/6/06 2:22p gmullen
345 * PR18489: Added PID destination workaround for hardware PR 18919.
346 *
347 * Hydra_Software_Devel/9   10/17/05 10:35a gmullen
348 * PR15309: Added TPIT support, BandHoldEn.
349 *
350 * Hydra_Software_Devel/8   10/6/05 11:23a gmullen
351 * PR15309: Fixed audio support.
352 *
353 * Hydra_Software_Devel/7   9/21/05 2:17p gmullen
354 * PR15309: Added support for AAC HE and AC3+ audio, fixed bug in playback
355 * PI, modified RAVE PI to support channel change and reset.
356 *
357 * Hydra_Software_Devel/6   8/18/05 9:59a gmullen
358 * PR15309: Added more DirecTV support.
359 *
360 * Hydra_Software_Devel/5   8/12/05 8:57a gmullen
361 * PR15309: Added PCR, PCR Offset, DirecTV, RAVE video, and ITB/CDB
362 * endianess support. Tested same.
363 *
364 * Hydra_Software_Devel/4   8/4/05 8:14a gmullen
365 * PR15309: Added PCR support.
366 *
367 * Hydra_Software_Devel/3   7/27/05 6:33p gmullen
368 * PR15309: Fixed bug in CheckBuffer() and UpdateReadOffet(). Also updated
369 * register configs.
370 *
371 * Hydra_Software_Devel/2   7/26/05 5:48p gmullen
372 * PR15309: Fixed buffer size issue in bxpt_rave.c and added buffer
373 * shutdown code to other blocks.
374 *
375 * Hydra_Software_Devel/1   7/15/05 9:03a gmullen
376 * PR15309: Inita i
377 *
378 ***************************************************************************/
379
380#ifndef BXPT_PRIV_H__
381#define BXPT_PRIV_H__
382
383#include "breg_mem.h"
384#include "bint.h"
385#include "bmem.h"
386#include "bavc.h"
387#include "bchp.h"
388#include "berr_ids.h"
389#include "bxpt.h"
390#include "bavc.h"
391#include "bxpt_rave.h"
392#include "bxpt_pcr.h"
393
394#if BCHP_PWR_SUPPORT
395#include "bchp_pwr.h"
396    #ifdef BCHP_PWR_RESOURCE_XPT_SRAM
397    #include "bchp_xpt_fe.h"
398    #include "bchp_xpt_msg.h"
399    #endif
400#endif
401
402#ifdef __cplusplus
403extern "C" {
404#endif
405   
406/* Address delta (in bytes) between elements in a register array. */
407#define PARSER_REG_STEPSIZE             ( BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1 - BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1 )
408#define IB_REG_STEPSIZE                 ( BCHP_XPT_FE_IB1_CTRL - BCHP_XPT_FE_IB0_CTRL )
409#define BP_TABLE_STEP                   ( 4 )
410#define RP_TABLE_STEP                   ( 4 )
411#define PID_TABLE_STEP                  ( 4 )
412#define PID_CTRL1_TABLE_STEP            ( 4 )
413#define PID_CTRL2_TABLE_STEP            ( 4 )
414#define FILTER_WORD_STEP                ( 32 )
415#define GEN_FILT_EN_STEP                ( 4 )
416#define PID2BUF_TABLE_STEP              ( 4 )
417#define XPT_REG_SIZE_BITS               ( 32 )
418#define XPT_REG_SIZE_BYTES              ( 4 )
419
420/***************************************************************************
421Summary:
422Used to define the flags inside a linked list descriptor.
423****************************************************************************/
424#define TRANS_DESC_INT_FLAG             ( 1ul << 31 )
425#define TRANS_DESC_FORCE_RESYNC_FLAG    ( 1ul << 30 )
426#define TRANS_DESC_LAST_DESCR_IND       ( 1ul << 0 )
427
428/***************************************************************************
429Summary:
430Used to maintain a list of which message buffers have been allocated by
431porting interface, rather than the caller.
432****************************************************************************/
433
434typedef struct 
435{
436    bool IsAllocated;   /* true if PI allocated the memory. */
437    uint32_t Address;   /* address of the buffer */
438    unsigned OutputMode;    /* Type of filtering this buffer is doing */
439}
440MessageBufferEntry; 
441
442/***************************************************************************
443Summary:
444Used to maintain a list of which PID channels are allocated and what parser
445band and PID are assigned to that channel.
446****************************************************************************/
447
448typedef struct
449{
450    bool IsAllocated;               /* true if allocated. */
451    bool IsPidChannelConfigured;    /* has the Pid and Band values been set. */
452    bool HasMessageBuffer;          /* true if hardware message buffer is associated with this channel. */
453    unsigned int Pid;       
454    unsigned int Band;
455
456    bool EnableRequested;           /* Has a request to enable this PID channel been recieved? */
457#ifdef ENABLE_PLAYBACK_MUX
458        bool MuxEnable;
459        bool HasDestination;
460#endif /*ENABLE_PLAYBACK_MUX*/
461
462    uint32_t MessageBuffercount;
463
464#if BXPT_SW7425_1323_WORKAROUND
465        bool IsPb;
466        bool IsEnabled;
467#endif
468}
469PidChannelTableEntry;
470
471 
472/***************************************************************************
473Summary:
474Used to keep track of which PSI filters have been allocated, and to what
475PID.
476****************************************************************************/
477typedef struct
478{ 
479    bool IsAllocated;       /* Is someone using this? */
480}
481FilterTableEntry;
482
483/***************************************************************************
484Summary:
485Handle for accessing the record API via a channel. Users should not directly
486access the contents of the structure.
487****************************************************************************/
488
489typedef struct BXPT_P_PbHandle
490{
491    BCHP_Handle hChip;              /* [Input] Handle to used chip. */
492    BREG_Handle hRegister;          /* [Input] Handle to access regiters. */
493    BMEM_Handle hMemory;            /* [Input] Handle to memory heap to use. */
494    void *vhXpt;                    /* Pointer to parent transport handle. Requires casting. */
495
496    uint8_t ChannelNo;      /* This channels number. */
497    uint32_t BaseAddr;  /* Address of the first register in this block. */
498    uint32_t LastDescriptor;    /* Address of the last descriptor on the linked list. */
499    bool Opened;
500    bool Running;
501    unsigned int SyncMode;
502    BINT_CallbackHandle hPbIntCallback; /* Callback Handle to service the ISR */
503    bool AlwaysResumeFromLastDescriptor;
504    bool ForceResync;
505   
506    BXPT_PvrDescriptor *DummyDescriptor;
507    uint8_t *DummyBuffer;
508    bool ResetPacingOnTsRangeError;
509    uint32_t BitRate;
510
511    BXPT_PidChannel_CC_Config CcConfigBeforeAllPass;
512    bool IsParserInAllPass;
513
514#if BXPT_HAS_TSMUX
515    unsigned PacingLoadMap;
516    unsigned PacingCount;
517    bool PacingLoadNeeded;
518#endif
519}
520BXPT_P_PbHandle;
521
522/***************************************************************************
523Summary:
524Handle for accessing the remux API via a channel. Users should not directly
525access the contents of the structure.
526****************************************************************************/
527
528typedef struct BXPT_P_RemuxHandle
529{
530    void *vhXpt;            /* Pointer to parent transport handle. Requires casting. */
531
532    BCHP_Handle hChip;              /* [Input] Handle to used chip. */
533    BREG_Handle hRegister;          /* [Input] Handle to access regiters. */
534    BMEM_Handle hMemory;            /* [Input] Handle to memory heap to use. */
535   
536    bool Opened;
537    bool Running;
538
539    uint8_t ChannelNo;      /* This channels number. */
540    uint32_t BaseAddr;  /* Address of the first register in this block. */
541    bool BufferIsAllocated;   
542    void *BufferAddress;
543}
544BXPT_P_RemuxHandle;
545
546/***************************************************************************
547Summary:
548Handle for accessing the packet substution API via a channel. Users should
549not directly access the contents of the structure.
550****************************************************************************/
551
552typedef struct BXPT_P_PacketSubHandle
553{
554    BCHP_Handle hChip;              /* [Input] Handle to used chip. */
555    BREG_Handle hRegister;          /* [Input] Handle to access regiters. */
556    BMEM_Handle hMemory;            /* [Input] Handle to memory heap to use. */
557    void *vhXpt;
558
559    uint8_t ChannelNo;      /* This channels number. */
560    uint32_t BaseAddr;      /* Address of the first register in this block. */
561    uint32_t LastDescriptor;    /* Address of the last descriptor on the linked list. */
562    bool Opened;
563    bool Running;
564}
565BXPT_P_PacketSubHandle;
566
567typedef struct BXPT_P_PcrHandle_Impl
568{
569    BCHP_Handle hChip;              /* [Input] Handle to used chip. */
570    BREG_Handle hRegister;          /* [Input] Handle to access regiters. */
571    void *vhXpt;
572
573    uint8_t ChannelNo;              /* This channels number. */
574    uint32_t RegOffset;            /* reg Offset of the given module. */
575    bool DMode;
576}
577BXPT_P_PcrHandle_Impl;
578
579typedef struct BXPT_P_InterruptCallbackArgs
580{
581    BINT_CallbackFunc   Callback;   /* Callback for this interrupt. */
582    void *Parm1;                    /* User arg for the callback. */
583    int Parm2;                      /* User arg for the callback. */
584}
585BXPT_P_InterruptCallbackArgs;
586
587typedef struct ParserConfig
588{
589    bool SaveShortPsiMsg;       
590    bool SaveLongPsiMsg;       
591    bool PsfCrcDis;             
592    BXPT_PsiMesgModModes PsiMsgMod;
593}
594ParserConfig;
595
596/***************************************************************************
597Summary:
598Handles for accessing and controlling the RAVE and it's contexts.
599****************************************************************************/
600
601typedef struct BXPT_P_IndexerHandle
602{
603    BXPT_RaveIdx ChannelType;
604    void *hChannel;
605    bool Allocated;
606    unsigned NumChannels;
607    void *vhCtx;
608    bool SvcMvcMode;
609}
610BXPT_P_IndexerHandle;
611
612typedef struct StartCodeIndexer
613{
614    BREG_Handle hReg;           
615    BMEM_Handle hMem;           
616    BINT_Handle hInt;
617    uint32_t BaseAddr;
618    unsigned ChannelNo;
619    bool Allocated;
620}
621StartCodeIndexer;
622
623typedef enum brave_itb_types {
624    brave_itb_video_start_code =     0x00,   
625    brave_itb_base_address =         0x20,
626    brave_itb_pts_dts =              0x21,
627    brave_itb_pcr_offset =           0x22, 
628    brave_itb_btp =                  0x23,
629    brave_itb_private_hdr =          0x24,
630    brave_itb_rts =                  0x25,
631    brave_itb_pcr =                  0x26,
632    brave_itb_ip_stream_out =        0x30,
633    brave_itb_termination =          0x70
634} brave_itb_types;
635
636typedef enum eDynamic_splice_btp_marker_commands
637{
638    brave_itb_splice_pts_marker = 0x0B , 
639    brave_itb_splice_start_marker = 0x12,
640    brave_itb_splice_stop_marker = 0x13,
641    brave_itb_splice_transition_marker = 0x14,
642    brave_itb_splice_pcr_offset_marker = 0x15
643}
644eDynamic_splice_btp_marker_command;
645
646typedef enum eDynamic_splice_state
647{
648        SoftRave_SpliceState_Copy = 0,
649        SoftRave_SpliceState_Discard = 1
650}
651eDynamic_splice_state;
652
653typedef struct SoftRaveData
654{
655    uint32_t SrcBaseAddr;
656    unsigned mode;
657    uint32_t last_base_address;
658    uint8_t *src_itb_mem, *dest_itb_mem;
659    uint32_t last_src_itb_valid, last_dst_itb_valid;
660    uint32_t src_itb_base, dest_itb_base;
661       
662    uint32_t last_pts_dts;
663    uint32_t last_sc;
664
665       
666    bool b_frame_found;
667    uint32_t last_dest_valid, flush_cnt;
668    uint32_t* P_frame_pts;
669    brave_itb_types last_entry_type;
670       
671    bool adjust_pts;
672    bool insufficient_itb_info;
673    bool sequence_hdr_found;
674       
675    bool discard_till_next_gop;
676    bool discarding;
677
678    uint32_t splice_start_PTS;
679    uint32_t splice_start_PTS_tolerance;               
680    uint32_t splice_stop_PTS;
681    uint32_t splice_stop_PTS_tolerance;
682    uint32_t splice_monitor_PTS;
683    uint32_t splice_monitor_PTS_tolerance;
684    uint32_t splice_pcr_offset;
685    uint32_t splice_pts_offset;
686    uint32_t splice_last_pcr_offset;
687    bool  SpliceStartPTSFlag;
688    bool  SpliceStopPTSFlag;
689    bool  SpliceMonitorPTSFlag;
690    bool  SpliceModifyPCROffsetFlag;
691    bool  SpliceModifyPTSFlag;
692    eDynamic_splice_state splice_state;
693    uint32_t Splice_Ctx_num;
694    void (*SpliceStopPTSCB) ( void *, uint32_t pts);
695    void (*SpliceStartPTSCB) ( void *,uint32_t pts);
696    void (*SpliceMonitorPTSCB) ( void *, uint32_t pts);
697    void * SpliceStopPTSCBParam;
698    void * SpliceStartPTSCBParam;
699    void * SpliceMonitorPTSCBParam;
700    bool InsertStartPts;
701    bool InsertStopPts;
702    bool StartMarkerInserted;
703    bool StopMarkerInserted;
704
705    unsigned SrcContextIndex;
706    bool SrcIsHeld;
707}
708SoftRaveData;
709
710typedef struct BXPT_P_ContextHandle
711{
712    BREG_Handle hReg;   
713    BCHP_Handle hChp;
714    BMEM_Handle hMem;           
715    BINT_Handle hInt;
716    BMEM_Handle hRHeap;
717    void *vhRave;
718
719    unsigned Type;
720    uint32_t BaseAddr;
721    bool Allocated;
722    unsigned Index; 
723    bool CdbReset; 
724    bool ItbReset; 
725    bool CdbReadReset; 
726    bool ItbReadReset; 
727
728    bool HaveSpliceQueue;
729    unsigned SpliceQueueIdx;
730
731    BAVC_StreamType InputFormat;
732    BAVC_ItbEsType ItbFormat;
733    StartCodeIndexer *hAvScd;
734    int PicCounter;     /* Offset into table of Pic Counter registers */
735    bool Transcoding;
736    uint32_t allocatedCdbBufferSize; /* Total CDB buffer allocated by AllocContext */ 
737    uint32_t usedCdbBufferSize;      /* actual CDB buffer used */ 
738    void *CdbBufferAddr;             /* save the cdb allocated bufffer adddress */ 
739    void *ItbBufferAddr;             /* save the itb allocated buffer address allocated */ 
740    bool externalCdbAlloc;
741    bool externalItbAlloc;
742
743    /* For streaming IP support only. Don't use in AV or REC processing */
744    bool IsMpegTs;      /* True if context is handling MPEG TS, false if DirecTV */
745
746        /* For 7401 only */
747        bool VobMode;
748
749        bool IsSoftContext;
750        SoftRaveData SoftRave; 
751
752    StartCodeIndexer *hVctScd;
753        void *VctNeighbor;
754
755        /* PR57627 :
756    ** SC_OR_MODE is used to select the way scramble control bits are reported.
757    ** 0 = Disable OR-ing of current and previous scramble control bits (Default).
758    ** 1 = Enable OR-ing of current and previous scramble control bits. This is to
759        ** support streams which have mixture of scrambled and unscrambled packets within
760        ** the same PID. In such case, these PIDs will be treated as scramble PIDs.
761        ** By default this is disabled.
762        */
763        bool ScOrMode; 
764
765#if BXPT_SW7425_1323_WORKAROUND
766        bool BandHoldEn;
767        unsigned UpperThreshold;
768#endif
769}
770BXPT_P_ContextHandle;
771
772typedef struct CtxIntData
773{
774    BLST_S_ENTRY( CtxIntData ) Link;
775
776    BINT_CallbackFunc   Callback;   /* Callback for this interrupt. */
777    void *Parm1;                    /* User arg for the callback. */
778    int Parm2;                      /* User arg for the callback. */
779    uint32_t EnableRegAddr;
780    uint32_t StatusRegAddr;
781}
782CtxIntData;
783
784typedef struct TpitIndexer
785{
786    BREG_Handle hReg;           
787    BMEM_Handle hMem;           
788    BINT_Handle hInt;
789    uint32_t BaseAddr;
790    uint32_t PidTableBaseAddr;
791    uint32_t ParseTableBaseAddr;
792    unsigned ChannelNo;
793    bool Allocated;
794}
795TpitIndexer;
796
797typedef struct BXPT_P_RaveHandle   
798{
799    BCHP_Handle hChip;             
800    BREG_Handle hReg;           
801    BMEM_Handle hMem;           
802    BINT_Handle hInt;
803    void *lvXpt;
804    unsigned ChannelNo;             
805
806    BXPT_P_ContextHandle ContextTbl[ BXPT_NUM_RAVE_CONTEXTS ];
807    bool SpliceQueueAllocated[ BXPT_P_NUM_SPLICING_QUEUES ];
808    StartCodeIndexer ScdTable[ BXPT_NUM_SCD ];
809    TpitIndexer TpitTable[ BXPT_NUM_TPIT ];
810    BXPT_P_IndexerHandle IndexerHandles[ BXPT_NUM_SCD + BXPT_NUM_TPIT ];
811    RaveChannelOpenCB chanOpenCB;
812
813#if BXPT_SW7425_1323_WORKAROUND
814        signed PidChanToContextMap[ BXPT_NUM_PID_CHANNELS ];
815        unsigned WatermarkGranularity;
816    bool DoWorkaround;
817#endif
818
819}
820BXPT_P_RaveHandle;
821
822typedef struct RaveChannel
823{
824    void *Handle;
825    bool Allocated;
826}
827RaveChannel;
828
829typedef struct BXPT_P_PcrOffset_Impl
830{
831    BCHP_Handle hChip;             
832    BREG_Handle hReg;           
833    BMEM_Handle hMem;           
834    unsigned int ChannelNo;
835    uint32_t BaseAddr;
836    void *lvXpt;
837    uint32_t CurrentTimeBase;
838    unsigned PidChannelNum;
839    unsigned WhichStc;
840    bool UseHostPcrs;
841}
842BXPT_P_PcrOffset_Impl;
843
844typedef struct PcrOffsetData
845{
846    void *Handle;
847    bool Allocated;
848}
849PcrOffsetData;
850
851/***************************************************************************
852Summary:
853The handle for the transport module. Users should not directly access the
854contents.
855****************************************************************************/
856typedef struct BXPT_P_TransportData
857{
858    BCHP_Handle hChip;              /* [Input] Handle to used chip. */
859    BREG_Handle hRegister;          /* [Input] Handle to access regiters. */
860    BMEM_Handle hMemory;            /* [Input] Handle to memory heap to use. */
861    BINT_Handle hInt;               /* [Input] Handle to interrupt interface to use. */
862
863    /* Handle for secure memory allocations. */
864    BMEM_Handle hRHeap;             
865
866    BINT_CallbackHandle hMsgCb;     /* Callback handle for message interrupts */
867    BINT_CallbackHandle hMsgOverflowCb; /* Callback handle for message overflow interrupts */
868
869    unsigned int MaxPlaybacks;          /* Number of playback blocks we support. */
870    unsigned int MaxPidChannels;        /* Number of PID channels we support. */
871    unsigned int MaxPidParsers;         /* Number of PID parsers we support. */
872    unsigned int MaxInputBands;         /* Max number of input bands we support. */
873    unsigned int MaxFilterBanks;        /* Max number of filter banks */
874    unsigned int MaxFiltersPerBank;     /* Number of filters in each bank. */
875    unsigned int MaxPcrs;               /* Number of PCR blocks */
876    unsigned int MaxPacketSubs;         /* Max number of packet substitution channels. */
877    unsigned int MaxTpitPids;           /* Max number of PIDs handled by each TPIT parser */
878    unsigned int MaxRaveContexts;       /* Max number of RAVE contexts, AV plus record */
879    unsigned int MaxRaveChannels;       /* Max number of RAVE channels (or instances of the RAVE core in XPT). */
880
881#ifdef ENABLE_PLAYBACK_MUX
882    unsigned int NumPlaybackMuxes;      /* Number of playback blocks to be used for muxing. */
883#endif /* ENABLE_PLAYBACK_MUX */
884                                                 
885#if BXPT_HAS_IB_PID_PARSERS
886    ParserConfig IbParserTable[ BXPT_NUM_PID_PARSERS ];
887    bool IsParserInAllPass[ BXPT_NUM_PID_PARSERS ];
888#endif
889
890    ParserConfig PbParserTable[ BXPT_NUM_PLAYBACKS ];
891
892#if BXPT_HAS_MESG_BUFFERS
893    bool PidChannelParserConfigOverride[BXPT_NUM_MESG_BUFFERS]; /* if set the true then PSI setting for this pid
894                                                                     channel can different from the the PSI settings
895                                                                     for the PARSER to which this pid channel belongs */
896
897    MessageBufferEntry MessageBufferTable[ BXPT_NUM_MESG_BUFFERS ];   /* Table of PI allocated buffers */
898    bool MesgBufferIsInitialized[ BXPT_NUM_MESG_BUFFERS ];            /* true if buffer has been configured. */
899
900    FilterTableEntry FilterTable[ BXPT_NUM_FILTER_BANKS ][ BXPT_P_FILTER_TABLE_SIZE ];
901
902    /* Pointers to the interrupt handlers. */
903    BXPT_P_InterruptCallbackArgs MesgIntrCallbacks[ BXPT_NUM_MESG_BUFFERS ];
904    BXPT_P_InterruptCallbackArgs OverflowIntrCallbacks[ BXPT_NUM_MESG_BUFFERS ];
905#endif
906
907#if BXPT_HAS_REMUX                     
908    BXPT_P_RemuxHandle RemuxHandles[ BXPT_NUM_REMULTIPLEXORS ];
909#endif
910
911#if BXPT_HAS_PACKETSUB
912    BXPT_P_PacketSubHandle PacketSubHandles[ BXPT_NUM_PACKETSUBS ]; 
913#endif
914
915    PidChannelTableEntry PidChannelTable[ BXPT_NUM_PID_CHANNELS ];    /* Table of PI allocated PID channels. */
916
917    BXPT_P_PbHandle PlaybackHandles[ BXPT_NUM_PLAYBACKS ];
918
919#if BXPT_HAS_DPCRS
920    BXPT_P_PcrHandle_Impl  *PcrHandles[ BXPT_NUM_PCRS ];
921#endif
922
923    RaveChannel RaveChannels[ BXPT_NUM_RAVE_CHANNELS ];
924    PcrOffsetData PcrOffsets[ BXPT_NUM_PCR_OFFSET_CHANNELS ];
925
926    bool IsLittleEndian;
927        bool Pid2BuffMappingOn;
928        bool MesgDataOnRPipe;
929
930    BMEM_Handle hPbHeap;
931
932    BXPT_PidChannel_CC_Config CcConfigBeforeAllPass[ BXPT_NUM_PID_CHANNELS ];
933
934#if BXPT_HAS_PARSER_REMAPPING
935    BXPT_ParserBandMapping BandMap;
936#endif
937
938    /* TODO: consolidate power-related variables into a struct */
939    bool bStandby; /* true if in standby */
940    bool bS3Standby;
941    bool WakeupEnabled; /* Wakeup packet support enabled */
942
943#ifdef BCHP_PWR_RESOURCE_XPT_SRAM
944    void *SRAM_Backup;
945    void *Reg_Backup;
946    void *vhRave;
947#endif
948
949#ifdef BCHP_PWR_RESOURCE_XPT
950    bool WakeupArmed;
951#endif
952
953    unsigned DpcrRefCount;  /* Number of DPCR channels that have been openned */
954
955    BXPT_PCR_JitterTimestampMode JitterTimestamp[ BXPT_NUM_PCRS ]; 
956    BXPT_PCR_JitterCorrection PbJitterDisable[ BXPT_NUM_PCRS ];
957    BXPT_PCR_JitterCorrection LiveJitterDisable[ BXPT_NUM_PCRS ];
958
959#if BXPT_SW7425_1323_WORKAROUND
960    bool DoWorkaround;
961#endif
962}
963BXPT_P_TransportData;
964
965uint32_t BXPT_P_GetParserCtrlRegAddr(
966        BXPT_Handle hXpt,                               /* [in] Handle for the transport to access. */
967    unsigned ParserNum,
968    unsigned Reg0
969    );
970
971void BXPT_P_ResetTransport( 
972    BREG_Handle hReg         
973    );
974
975void BXPT_P_Interrupt_MsgVector_isr( 
976    BXPT_Handle hXpt,               /* [in] Handle for this transport */
977    int L1Shift         /* [in] Dummy arg. Not used by this interface. */
978    );
979
980void BXPT_P_Interrupt_MsgOverflowVector_isr( 
981    BXPT_Handle hXpt,               /* [in] Handle for this transport */
982    int L1Shift         /* [in] Dummy arg. Not used by this interface. */
983    );
984
985void BXPT_P_Interrupt_MsgSw_isr(
986    BXPT_Handle hXpt,               /* [in] Handle for this transport */
987    int MessageBufferNum            /* [in] Message Buffer */
988    );
989
990BERR_Code BXPT_P_GetGroupSelect( unsigned int Bank, unsigned int *GenGrpSel );
991
992#if BXPT_HAS_PID_CHANNEL_PES_FILTERING
993
994typedef enum
995{
996    BXPT_Spid_eChannelFilterMode_Disable = 0,           /* Disable filter mode */
997    BXPT_Spid_eChannelFilterMode_StreamId = 8,          /* PB packetizer filters data on stream id */
998    BXPT_Spid_eChannelFilterMode_StreamIdRange = 10,    /* PB packetizer filters on hi to lo stream id range */
999    BXPT_Spid_eChannelFilterMode_StreamIdExtension = 12,/* PB packetizer filters on stream id and stream id extension */
1000    BXPT_Spid_eChannelFilterMode_SubStreamId = 14       /* PB packetizer filters on substream id */
1001
1002}BXPT_Spid_eChannelFilterMode;
1003
1004typedef struct BXPT_Spid_eChannelFilter
1005{
1006    BXPT_Spid_eChannelFilterMode Mode; 
1007
1008    union
1009    {
1010        unsigned char StreamId;
1011        struct
1012        {
1013            unsigned char Hi;
1014            unsigned char Lo;
1015        }StreamIdRange;
1016
1017        struct
1018        {
1019            unsigned char Id;
1020            unsigned char Extension;
1021        }StreamIdAndExtension;
1022
1023        struct
1024        {
1025            unsigned char Id;
1026            unsigned char SubStreamId;
1027        }StreamIdAndSubStreamId;
1028    }FilterConfig;
1029   
1030}BXPT_Spid_eChannelFilter;
1031
1032/***************************************************************************
1033Set the configuration for the given secondary PID channel stream filter
1034based on various stream id combinations. Used during DVD playback mode.
1035****************************************************************************/
1036BERR_Code BXPT_Spid_P_ConfigureChannelFilter(BXPT_Handle hXpt,unsigned int ChannelNum,BXPT_Spid_eChannelFilter Filter);
1037
1038/* Enable PID2BUFF support. On by default in this sw base. */
1039void SetPid2BuffMap(BXPT_Handle hXpt);
1040
1041
1042#endif
1043
1044#ifdef __cplusplus
1045}
1046#endif
1047
1048#endif /* #ifndef BXPT_PRIV_H__ */
1049
1050/* end of file */
1051
1052
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