source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/xvd/7552/bxvd_relf.h

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1/***************************************************************************
2 * bxvd_elf.h
3 *
4 * Standard (common) definitions for ELF structures/fields.
5 *
6 * All of this material comes out of the ELF 1.1 Specification.
7 * Metaware ARC-specific definitions are below.
8 *
9 * $brcm_Workfile: bxvd_relf.h $
10 * $brcm_Revision: Hydra_Software_Devel/7 $
11 * $brcm_Date: 2/21/07 1:10p $
12 *
13 * Module Description:
14 *   See module
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/portinginterface/xvd/7401/bxvd_relf.h $
19 *
20 * Hydra_Software_Devel/7   2/21/07 1:10p pblanco
21 * PR26433: Set formatting to standard agreed upon within the XVD group on
22 * 2/20/07.
23 *
24 * Hydra_Software_Devel/6   12/11/06 3:15p pblanco
25 * PR26433: Cleaned up definitions.
26 *
27 * Hydra_Software_Devel/5   8/11/06 1:53p davidp
28 * PR23207: Update ARC copyright statement per Andy Jaros, VP of Sales at
29 * ARC.
30 *
31 * Hydra_Software_Devel/4   6/26/06 9:41a pblanco
32 * PR22302: Checked in Marcin's changes to make all definitions in this
33 * header XVD private.
34 *
35 * Hydra_Software_Devel/3   6/22/06 2:13p pblanco
36 * PR22302: Changed some typedefs to XVD local type names.
37 *
38 * Hydra_Software_Devel/2   6/22/06 1:17p pblanco
39 * PR20017: Incorporate Roy Lewis' changes for BE systems. Verified on LE
40 * Linux and BE VxWorks.
41 *
42 * Hydra_Software_Devel/1   4/4/06 2:03p pblanco
43 * PR20017: Initial check in.
44 *
45 ***************************************************************************/
46#ifndef __ELF_H__
47#define __ELF_H__
48
49typedef unsigned long   Bxvd_Elf32_Addr;
50typedef unsigned short  Bxvd_Elf32_Half;
51typedef unsigned long   Bxvd_Elf32_Off;
52typedef signed   long   Bxvd_Elf32_Sword;
53typedef unsigned long   Bxvd_Elf32_Word;
54
55#define ET_NIDENT       16
56
57typedef struct
58{
59      unsigned char   e_ident[ET_NIDENT];
60      Bxvd_Elf32_Half e_type;
61      Bxvd_Elf32_Half e_machine;
62      Bxvd_Elf32_Word e_version;
63      Bxvd_Elf32_Addr e_entry;
64      Bxvd_Elf32_Off  e_phoff;
65      Bxvd_Elf32_Off  e_shoff;
66      Bxvd_Elf32_Word e_flags;
67      Bxvd_Elf32_Half e_ehsize;
68      Bxvd_Elf32_Half e_phentsize;
69      Bxvd_Elf32_Half e_phnum;
70      Bxvd_Elf32_Half e_shentsize;
71      Bxvd_Elf32_Half e_shnum;
72      Bxvd_Elf32_Half e_shstrndx;
73} Bxvd_Elf32_Ehdr;
74
75        /* e_type definitions */
76#define BXVD_ET_NONE         0       /* No file type         */
77#define BXVD_ET_REL          1       /* Relocatable file     */
78#define BXVD_ET_EXEC         2       /* Executable file      */
79#define BXVD_ET_DYN          3       /* Shared object file   */
80#define BXVD_ET_CORE         4       /* Core file            */
81#define BXVD_ET_LOPROC       0xFF00  /* Processor-specific   */
82#define BXVD_ET_HIPROC       0xFFFF  /* Processor-specific   */
83
84        /* e_machine definitions */
85#define BXVD_EM_NONE         0       /* No machine           */
86#define BXVD_EM_M32          1       /* AT&T WE 32100        */
87#define BXVD_EM_SPARC        2       /* SPARC                */
88#define BXVD_EM_386          3       /* Intel 80386          */
89#define BXVD_EM_68K          4       /* Motorola 68000       */
90#define BXVD_EM_88K          5       /* Motorola 88000       */
91#define BXVD_EM_860          7       /* Intel 80860          */
92#define BXVD_EM_MIPS         8       /* MIPS RS3000          */
93#define BXVD_EM_ARC          45      /* Argonaut Risc Core   */
94
95        /* e_version definitions */
96#define BXVD_EV_NONE         0       /* Invalid version      */
97#define BXVD_EV_CURRENT      1       /* Current version      */
98
99        /* e_ident[] fields */
100#define BXVD_EI_MAG0         0       /* File identification  */
101#define BXVD_EI_MAG1         1       /* File identification  */
102#define BXVD_EI_MAG2         2       /* File identification  */
103#define BXVD_EI_MAG3         3       /* File identification  */
104#define BXVD_EI_CLASS        4       /* File class           */
105#define BXVD_EI_DATA         5       /* Data encoding        */
106#define BXVD_EI_VERSION      6       /* File version         */
107#define BXVD_EI_PAD          7       /* Start of padding     */
108
109#define BXVD_ELFMAG0         0x7F
110#define BXVD_ELFMAG1         'E'
111#define BXVD_ELFMAG2         'L'
112#define BXVD_ELFMAG3         'F'
113
114#define BXVD_ELFCLASSNONE    0       /* Invalid class        */
115#define BXVD_ELFCLASS32      1       /* 32-bit objects       */
116#define BXVD_ELFCLASS64      2       /* 64-bit objects       */
117
118#define BXVD_ELFDATANONE     0       /* Invalid data encoding        */
119#define BXVD_ELFDATA2LSB     1       /* Little-endian encoding       */
120#define BXVD_ELFDATA2MSB     2       /* Big-endian encoding          */
121
122#define BXVD_SHN_UNDEF     0
123#define BXVD_SHN_LORESERVE 0xff00
124#define BXVD_SHN_LOPROC    0xff00
125#define BXVD_SHN_HIPROC    0xff1f
126#define BXVD_SHN_ABS       0xfff1
127#define BXVD_SHN_COMMON    0xfff2
128#define BXVD_SHN_HIRESERVE 0xffff
129
130typedef struct
131{     
132      Bxvd_Elf32_Word  sh_name;      /* Section name (string tbl index)      */
133      Bxvd_Elf32_Word  sh_type;      /* Section type                         */
134      Bxvd_Elf32_Word  sh_flags;     /* Section flags                        */
135      Bxvd_Elf32_Addr  sh_addr;      /* Section virtual addr at execution    */
136      Bxvd_Elf32_Off   sh_offset;    /* Section file offset                  */
137      Bxvd_Elf32_Word  sh_size;      /* Section size in bytes                */
138      Bxvd_Elf32_Word  sh_link;      /* Link to another section              */
139      Bxvd_Elf32_Word  sh_info;      /* Additional section information       */
140      Bxvd_Elf32_Word  sh_addralign; /* Section alignment                    */
141      Bxvd_Elf32_Word  sh_entsize;   /* Entry size if section holds table    */
142} Bxvd_Elf32_Shdr;
143
144#define BXVD_SHT_NULL        0
145#define BXVD_SHT_PROGBITS    1
146#define BXVD_SHT_SYMTAB      2
147#define BXVD_SHT_STRTAB      3
148#define BXVD_SHT_RELA        4
149#define BXVD_SHT_HASH        5
150#define BXVD_SHT_DYNAMIC     6
151#define BXVD_SHT_NOTE        7
152#define BXVD_SHT_NOBITS      8
153#define BXVD_SHT_REL         9
154#define BXVD_SHT_SHLIB       10
155#define BXVD_SHT_DYNSYM      11
156#define BXVD_SHT_LOPROC      0x70000000
157#define BXVD_SHT_HIPROC      0x7FFFFFFF
158#define BXVD_SHT_LOUSER      0x80000000
159#define BXVD_SHT_HIUSER      0xFFFFFFFF
160
161#define BXVD_SHF_WRITE       0x1
162#define BXVD_SHF_ALLOC       0x2
163#define BXVD_SHF_EXECINSTR   0x4
164#define BXVD_SHF_MASKPROC    0xF0000000
165
166
167typedef struct
168{ 
169      Bxvd_Elf32_Word st_name;
170      Bxvd_Elf32_Addr st_value;
171      Bxvd_Elf32_Word st_size;
172      unsigned char   st_info;
173      unsigned char   st_other;
174      Bxvd_Elf32_Half st_shndx;
175} Bxvd_Elf32_Sym;
176
177#define BXVD_ELF32_ST_BIND(i)   ((i) >> 4)
178#define BXVD_ELF32_ST_TYPE(i)   ((i) & 0x0F)
179#define BXVD_ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0x0F))
180
181#define BXVD_STB_LOCAL       0
182#define BXVD_STB_GLOBAL      1
183#define BXVD_STB_WEAK        2
184#define BXVD_STB_LOPROC      13
185#define BXVD_STB_HIPROC      15
186
187#define BXVD_STT_NOTYPE      0
188#define BXVD_STT_OBJECT      1
189#define BXVD_STT_FUNC        2
190#define BXVD_STT_SECTION     3
191#define BXVD_STT_FILE        4
192#define BXVD_STT_LOPROC      13
193#define BXVD_STT_HIPROC      15
194
195typedef struct
196{ 
197      Bxvd_Elf32_Addr r_offset;
198      Bxvd_Elf32_Word r_info;
199} Bxvd_Elf32_Rel;
200
201typedef struct
202{
203      Bxvd_Elf32_Addr  r_offset;
204      Bxvd_Elf32_Word  r_info;
205      Bxvd_Elf32_Sword r_addend;
206} Bxvd_Elf32_Rela;
207
208#define BXVD_ELF32_R_SYM(i)          ((i) >> 8)
209#define BXVD_ELF32_R_TYPE(i)         ((unsigned char)(i))
210#define BXVD_ELF32_R_INFO(s,t)       (((s) << 8) + (unsigned char)(t))
211
212
213typedef struct
214{ 
215      Bxvd_Elf32_Word p_type;
216      Bxvd_Elf32_Off  p_offset;
217      Bxvd_Elf32_Addr p_vaddr;
218      Bxvd_Elf32_Addr p_paddr;
219      Bxvd_Elf32_Word p_filesz;
220      Bxvd_Elf32_Word p_memsz;
221      Bxvd_Elf32_Word p_flags;
222      Bxvd_Elf32_Word p_align;
223} Bxvd_Elf32_Phdr;
224
225#define BXVD_PT_NULL         0
226#define BXVD_PT_LOAD         1
227#define BXVD_PT_DYNAMIC      2
228#define BXVD_PT_INTERP       3
229#define BXVD_PT_NOTE         4
230#define BXVD_PT_SHLIB        5
231#define BXVD_PT_PHDR         6
232#define BXVD_PT_LOPROC       0x70000000
233#define BXVD_PT_HIPROC       0x7FFFFFFF
234
235/*----------------------------------------------------------------------*
236 *                                                                      *
237 * The following is the elf_arc.h file from Metaware.                   *
238 *                                                                      *
239 *----------------------------------------------------------------------*/
240
241
242/*********************************************************************
243 * THE SOFTWARE CONTAINED IN THIS FILE IS LICENSED TO BROADCOMS
244 * CUSTOMERS FOR USE SOLELY IN CONNECTION WITH ARC processors
245 * within BROADCOM'S PRODUCTS.
246 * (C) Copyright 2005; ARC International (ARC);  Santa Cruz, CA 95060
247 * This program is the unpublished property and trade secret of ARC.  It
248 * is to be  utilized  solely  under  license and it is to be maintained
249 * on a confidential basis. The security  and  protection  of  the program
250 * is paramount to maintenance of the trade secret status.  It is to be
251 * protected from disclosure to unauthorized parties, both within the
252 * Licensee company and outside, in a manner not less stringent than that
253 * utilized for Licensee's own proprietary internal information. 
254 *********************************************************************/
255
256/**********************************************************************
257* Relocation types for the ARC ELF object files
258*   A = addend used to compute the relocation
259*   S = The value of the symbol being relocated
260*   P = The place (addr/section offset) of the storage unit being relocated
261*       (computed using r_offset)
262*
263* Relocation Fields (note this is big-endian notation...)
264*   +--------------------------------+
265*   |31          bits31-0           0| word32 data in separate word
266*   +--------------------------------+
267*
268*   +------------------------+
269*   |23      bits23-0       0| bits24 data in separate 3-byte chunk
270*   +------------------------+
271*
272*   +----------------+
273*   |15  bits15-0   0| bits16 data in separate half-word
274*   +----------------+
275*
276*   +-----------+
277*   |7 bits7-0 0| bits8 data in separate byte
278*   +-----------+
279*
280*   +--------------------------------+
281*   |31     |23     bits25-2        0| targ26 data as part of an instruction
282*   +--------------------------------+
283*
284*   +--------------------------------+
285*   |31  |26    bits21-2     7|     0| disp22 data as part of an instruction
286*   +--------------------------------+
287*
288*   +--------------------------------------------+
289*   |31  |26 bits10-1  17| |15 bits20-11 6|     0| disp21h data in instruction
290*   +--------------------------------------------+ (half-word aligned)
291*
292*   +--------------------------------------------+
293*   |31  |26 bits10-2  18| |15 bits20-11 6|     0| disp21w data in instruction
294*   +--------------------------------------------+ (long-word aligned)
295*
296*   +------------------------------------------------------+
297*   |31  |26 bits10-1  17| |15 bits20-11 6|  |3 bits24-21 0| disp25h data
298*   +------------------------------------------------------+ (halfword aligned)
299*
300*   +------------------------------------------------------+
301*   |31  |26 bits10-2  18| |15 bits20-11 6|  |3 bits24-21 0| disp25w data
302*   +------------------------------------------------------+ (longword aligned)
303*
304*   +--------------------------------+
305*   |31                  9| bits8-0 0| disp9 as part of an instruction
306*   +--------------------------------+
307*
308*   +--------------------------------+
309*   |31 |23 bits7-0 16|15 bit8|14   0| disp9ls as part of an instruction
310*   +--------------------------------+
311*
312*   +-------------------+
313*   |15     9| bits8-0 0| disp9s as part of an instruction
314*   +-------------------+
315*
316*   +----------------==-+
317*   |15   11| bits10-0 0| disp13s as part of an instruction (longword aligned)
318*   +----------------==-+
319*
320*********************************************************************/
321
322/*      Relo Type Name        Value    Field    Calculation */
323#define R_ARC_NONE            0x0   /* none     None */
324#define R_ARC_8               0x1   /* bits8    S + A */
325#define R_ARC_16              0x2   /* bits16   S + A */
326#define R_ARC_24              0x3   /* bits24   S + A */
327#define R_ARC_32              0x4   /* word32   S + A */
328#define R_ARC_B26             0x5   /* targ26   (S + A) >> 2   
329                                     *(convert to longword displacement)
330                                     */
331#define R_ARC_B22_PCREL       0x6   /* disp22   (S + A - P) >> 2
332                                     *    (convert to longword displacement)
333                                     */
334#define R_ARC_H30             0x7   /* word32   (S + A) >> 2 */
335#define R_ARC_N8              0x8   /* bits8    S - A */
336#define R_ARC_N16             0x9   /* bits16   S - A */
337#define R_ARC_N24             0xA   /* bits24   S - A */
338#define R_ARC_N32             0xB   /* word32   S - A */
339#define R_ARC_SDA             0xC   /* disp9    S + A */
340#define R_ARC_SECTOFF         0xD   /* word32   (S - <start of section>) + A */
341
342/*************************************************************************
343 * following new relocations defined for the ARCompact ISA
344 *************************************************************************/
345
346/* for conditional branch. Example: bne   printf */
347#define R_ARC_S21H_PCREL  0xE   /* disp21h  (S + A - P) >> 1
348                                 * (convert to halfword displacement)
349                                 */
350
351/* for conditional branch and link. Example: blne  printf */
352#define R_ARC_S21W_PCREL  0xF   /* disp21w  (S + A - P) >> 2
353                                 * (convert to longword displacement)
354                                 */
355
356/* For unconditional branch.  Example: b  printf */
357#define R_ARC_S25H_PCREL  0x10   /* disp25h  (S + A - P) >> 1
358                                  * (convert to halfword displacement)
359                                  */
360
361/* For unconditional branch and link.  Example: bl  printf */
362#define R_ARC_S25W_PCREL  0x11   /* disp25w  (S + A - P) >> 2
363                                  * (convert to longword displacement)
364                                  */
365
366/* for 32-bit Small Data Area fixups.  Example: add   r0, gp, var@sda */
367#define R_ARC_SDA32       0x12   /* word32   (S + A) - _SDA_BASE_ */
368
369/* for small data fixups on loads and stores.  Examples:
370 *     ldb   r0,  [gp, var@sda]   ; R_ARC_SDA_LDST
371 *     stw   r0,  [gp, var@sda]   ; R_ARC_SDA_LDST1
372 *     ld    r0,  [gp, var@sda]   ; R_ARC_SDA_LDST2
373 */
374#define R_ARC_SDA_LDST   0x13   /* disp9ls (S + A - _SDA_BASE_)  (s9 range) */
375#define R_ARC_SDA_LDST1  0x14   /* disp9ls (S+A-_SDA_BASE_) >> 1 (s10 range) */
376#define R_ARC_SDA_LDST2  0x15   /* disp9ls (S+A-_SDA_BASE_) >> 2 (s11 range) */
377
378/* for 16-bit load gp-relative instruction. Example:
379 *     ldb_s  r0, [gp, var@sda]   ; R_ARC_SDA16_LD
380 *     ldw_s  r0, [gp, var@sda]   ; R_ARC_SDA16_LD1
381 *     ld_s   r0, [gp, var@sda]   ; R_ARC_SDA16_LD2
382 */
383#define R_ARC_SDA16_LD   0x16   /* disp9s  (S + A - _SDA_BASE)   (s9 range) */
384#define R_ARC_SDA16_LD1  0x17   /* disp9s  (S+A-_SDA_BASE_) >> 1 (s10 range) */
385#define R_ARC_SDA16_LD2  0x18   /* disp9s  (S+A-_SDA_BASE_) >> 2 (s11 range) */
386
387/* for 16-bit branch-and-link.  Example: bl_s  printf */
388#define R_ARC_S13_PCREL      0x19   /* disp13s  (S + A - P) >> 2 */
389
390/* for 32-bit alignment of the fixup value.  Examples:
391 *     mov   r0,  var@l
392 *     ld    r0, [pcl, lab - .@l]
393 */
394#define R_ARC_W              0x1a   /* word32   (S + A) & ~3   (word-align) */
395
396/*
397 * The following relocations are to support middle-endian storage, whereby
398 * a 32-bit word is stored in two halfwords, with bits 31-16 stored first
399 * in memory and bits 15-0 stored adjacently.  The individual half-words are
400 * stored in the native endian of the machine.  This is how all instructions
401 * and LIMMs are stored in the ARCompact architecture.
402 */
403#define R_ARC_32_ME          0x1b   /* Like ARC_32, but stored in ME format */
404#define R_ARC_N32_ME         0x1c   /* Like N32, but stored in ME format */
405#define R_ARC_SECTOFF_ME     0x1d   /* Like SECTOFF, but stored in ME format */
406#define R_ARC_SDA32_ME       0x1e   /* Like SDA32, but stored in ME format */
407#define R_ARC_W_ME           0x1f   /* Like W, but stored in ME format */
408#define R_ARC_H30_ME         0x20   /* Like H30, but stored in ME format */
409
410/*************************************************************************/
411
412/*
413 * for ARC4 ld/st instructions, allows a section-relative offset in the
414 * range 0-255 (the positive portion of the shimm range).  The base
415 * register must be loaded with the base address of the section. Example:
416 * ld   r0, [r20, var@sectoff_u8]
417 */
418
419#define R_ARC_SECTOFF_U8     0x21   / disp9 (S + A - <start of section>) */
420
421/* ARC4. range -256 to 255.  The base register must be loaded with base of
422 * section + 256. Example:
423 *   ld   r0, [r20, var@sectoff_s9]
424 */
425#define R_ARC_SECTOFF_S9  0x22   /* disp9 (S + A - <start of section> - 256) */
426
427/*
428 * Same semantics as R_ARC_SECTOFF_U8 above, but for ARCompact ISA
429 * Note, however that the assembler encodes these loads and stores with
430 * address scaling (.as) turned on so that the range for half-words is
431 * 0-510 and the range for full 32-bit word accesses is 0-1020
432 * The range for byte accesses remains 0-255
433 *    ldb  r0, [r20, var@sectoff_u8]   ; R_AC_SECTOFF_U8
434 *    stw  r0, [r20, var@sectoff_u8]   ; R_AC_SECTOFF_U8_1
435 *    ld   r0, [r20, var@sectoff_u8]   ; R_AC_SECTOFF_U8_2
436 */
437#define R_AC_SECTOFF_U8   0x23   /* disp9ls (S + A - <start of section>) */
438#define R_AC_SECTOFF_U8_1 0x24   /* disp9ls (S +A - <start of section>) >> 1 */
439#define R_AC_SECTOFF_U8_2 0x25   /* disp9ls (S +A - <start of section>) >> 2 */
440
441/*
442 * Same semantics as R_ARC_SECTOFF_S9 above, but for ARCompact ISA
443 * Note, however that the assembler encodes these loads and stores with
444 * address scaling (.as) turned on so that the range for half-words is
445 * -256-510 and the range for full 32-bit word accesses is -256-1020
446 * The range for byte accesses remains -256-255
447 *    ldb  r0, [r20, var@sectoff_s9]   ; R_AC_SECTOFF_S9
448 *    stw  r0, [r20, var@sectoff_s9]   ; R_AC_SECTOFF_S9_1
449 *    ld   r0, [r20, var@sectoff_s9]   ; R_AC_SECTOFF_S9_2
450 */
451#define R_AC_SECTOFF_S9   0x26   /* disp9ls (S + A - <start of section>) */
452#define R_AC_SECTOFF_S9_1 0x27   /* disp9ls (S +A - <start of section>) >> 1 */
453#define R_AC_SECTOFF_S9_2 0x28   /* disp9ls (S +A - <start of section>) >> 2 */
454
455/* X/Y memory relocations */
456#define R_ARC_SECTOFF_ME_1   0x29   /* word32  ((S - <start of section>) + A)
457                                     * >> 1 [ME format]
458                                     */
459
460#define R_ARC_SECTOFF_ME_2   0x2a   /* word32  ((S - <start of section>) + A)
461                                     * >> 2 [ME format]
462                                     */
463
464#define R_ARC_SECTOFF_1      0x2b   /* word32  ((S - <start of section>) + A)
465                                     * >> 1
466                                     */
467
468#define R_ARC_SECTOFF_2      0x2c   /* word32  ((S - <start of section>) + A)
469                                     * >> 2
470                                     */
471
472#endif
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