| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle |
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| 7 | * Copyright (C) 1999 by Silicon Graphics, Inc. |
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| 8 | * Copyright (C) 2001 MIPS Technologies, Inc. |
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| 9 | * Copyright (C) 2002 Maciej W. Rozycki |
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| 10 | * |
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| 11 | * Some useful macros for MIPS assembler code |
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| 12 | * |
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| 13 | * Some of the routines below contain useless nops that will be optimized |
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| 14 | * away by gas in -O mode. These nops are however required to fill delay |
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| 15 | * slots in noreorder mode. |
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| 16 | */ |
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| 17 | #ifndef __ASM_ASM_H |
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| 18 | #define __ASM_ASM_H |
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| 19 | |
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| 20 | #include <asm/sgidefs.h> |
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| 21 | |
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| 22 | #ifndef CAT |
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| 23 | #ifdef __STDC__ |
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| 24 | #define __CAT(str1,str2) str1##str2 |
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| 25 | #else |
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| 26 | #define __CAT(str1,str2) str1/**/str2 |
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| 27 | #endif |
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| 28 | #define CAT(str1,str2) __CAT(str1,str2) |
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| 29 | #endif |
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| 30 | |
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| 31 | /* |
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| 32 | * PIC specific declarations |
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| 33 | * Not used for the kernel but here seems to be the right place. |
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| 34 | */ |
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| 35 | #ifdef __PIC__ |
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| 36 | #define CPRESTORE(register) \ |
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| 37 | .cprestore register |
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| 38 | #define CPADD(register) \ |
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| 39 | .cpadd register |
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| 40 | #define CPLOAD(register) \ |
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| 41 | .cpload register |
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| 42 | #else |
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| 43 | #define CPRESTORE(register) |
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| 44 | #define CPADD(register) |
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| 45 | #define CPLOAD(register) |
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| 46 | #endif |
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| 47 | |
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| 48 | /* |
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| 49 | * LEAF - declare leaf routine |
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| 50 | */ |
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| 51 | #define LEAF(symbol) \ |
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| 52 | .globl symbol; \ |
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| 53 | .align 2; \ |
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| 54 | .type symbol,@function; \ |
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| 55 | .ent symbol,0; \ |
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| 56 | symbol: .frame sp,0,ra |
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| 57 | |
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| 58 | /* |
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| 59 | * NESTED - declare nested routine entry point |
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| 60 | */ |
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| 61 | #define NESTED(symbol, framesize, rpc) \ |
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| 62 | .globl symbol; \ |
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| 63 | .align 2; \ |
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| 64 | .type symbol,@function; \ |
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| 65 | .ent symbol,0; \ |
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| 66 | symbol: .frame sp, framesize, rpc |
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| 67 | |
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| 68 | /* |
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| 69 | * END - mark end of function |
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| 70 | */ |
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| 71 | #define END(function) \ |
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| 72 | .end function; \ |
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| 73 | .size function,.-function |
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| 74 | |
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| 75 | /* |
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| 76 | * EXPORT - export definition of symbol |
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| 77 | */ |
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| 78 | #define EXPORT(symbol) \ |
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| 79 | .globl symbol; \ |
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| 80 | symbol: |
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| 81 | |
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| 82 | /* |
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| 83 | * FEXPORT - export definition of a function symbol |
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| 84 | */ |
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| 85 | #define FEXPORT(symbol) \ |
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| 86 | .globl symbol; \ |
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| 87 | .type symbol,@function; \ |
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| 88 | symbol: |
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| 89 | |
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| 90 | /* |
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| 91 | * ABS - export absolute symbol |
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| 92 | */ |
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| 93 | #define ABS(symbol,value) \ |
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| 94 | .globl symbol; \ |
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| 95 | symbol = value |
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| 96 | |
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| 97 | #define PANIC(msg) \ |
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| 98 | .set push; \ |
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| 99 | .set reorder; \ |
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| 100 | PTR_LA a0,8f; \ |
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| 101 | jal panic; \ |
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| 102 | 9: b 9b; \ |
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| 103 | .set pop; \ |
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| 104 | TEXT(msg) |
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| 105 | |
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| 106 | /* |
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| 107 | * Print formatted string |
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| 108 | */ |
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| 109 | #define PRINT(string) \ |
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| 110 | .set push; \ |
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| 111 | .set reorder; \ |
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| 112 | PTR_LA a0,8f; \ |
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| 113 | jal printk; \ |
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| 114 | .set pop; \ |
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| 115 | TEXT(string) |
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| 116 | |
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| 117 | #define TEXT(msg) \ |
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| 118 | .pushsection .data; \ |
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| 119 | 8: .asciiz msg; \ |
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| 120 | .popsection; |
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| 121 | |
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| 122 | /* |
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| 123 | * Build text tables |
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| 124 | */ |
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| 125 | #define TTABLE(string) \ |
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| 126 | .pushsection .text; \ |
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| 127 | .word 1f; \ |
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| 128 | .popsection \ |
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| 129 | .pushsection .data; \ |
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| 130 | 1: .asciiz string; \ |
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| 131 | .popsection |
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| 132 | |
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| 133 | /* |
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| 134 | * MIPS IV pref instruction. |
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| 135 | * Use with .set noreorder only! |
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| 136 | * |
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| 137 | * MIPS IV implementations are free to treat this as a nop. The R5000 |
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| 138 | * is one of them. So we should have an option not to use this instruction. |
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| 139 | */ |
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| 140 | #ifdef CONFIG_CPU_HAS_PREFETCH |
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| 141 | |
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| 142 | #define PREF(hint,addr) \ |
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| 143 | .set push; \ |
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| 144 | .set mips4; \ |
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| 145 | pref hint,addr; \ |
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| 146 | .set pop |
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| 147 | |
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| 148 | #define PREFX(hint,addr) \ |
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| 149 | .set push; \ |
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| 150 | .set mips4; \ |
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| 151 | prefx hint,addr; \ |
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| 152 | .set pop |
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| 153 | |
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| 154 | #else /* !CONFIG_CPU_HAS_PREFETCH */ |
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| 155 | |
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| 156 | #define PREF(hint,addr) |
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| 157 | #define PREFX(hint,addr) |
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| 158 | |
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| 159 | #endif /* !CONFIG_CPU_HAS_PREFETCH */ |
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| 160 | |
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| 161 | /* |
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| 162 | * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. |
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| 163 | */ |
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| 164 | #if (_MIPS_ISA == _MIPS_ISA_MIPS1) |
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| 165 | #define MOVN(rd,rs,rt) \ |
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| 166 | .set push; \ |
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| 167 | .set reorder; \ |
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| 168 | beqz rt,9f; \ |
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| 169 | move rd,rs; \ |
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| 170 | .set pop; \ |
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| 171 | 9: |
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| 172 | #define MOVZ(rd,rs,rt) \ |
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| 173 | .set push; \ |
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| 174 | .set reorder; \ |
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| 175 | bnez rt,9f; \ |
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| 176 | move rd,rs; \ |
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| 177 | .set pop; \ |
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| 178 | 9: |
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| 179 | #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ |
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| 180 | #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) |
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| 181 | #define MOVN(rd,rs,rt) \ |
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| 182 | .set push; \ |
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| 183 | .set noreorder; \ |
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| 184 | bnezl rt,9f; \ |
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| 185 | move rd,rs; \ |
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| 186 | .set pop; \ |
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| 187 | 9: |
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| 188 | #define MOVZ(rd,rs,rt) \ |
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| 189 | .set push; \ |
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| 190 | .set noreorder; \ |
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| 191 | beqzl rt,9f; \ |
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| 192 | move rd,rs; \ |
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| 193 | .set pop; \ |
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| 194 | 9: |
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| 195 | #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ |
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| 196 | #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ |
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| 197 | (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) |
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| 198 | #define MOVN(rd,rs,rt) \ |
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| 199 | movn rd,rs,rt |
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| 200 | #define MOVZ(rd,rs,rt) \ |
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| 201 | movz rd,rs,rt |
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| 202 | #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ |
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| 203 | |
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| 204 | /* |
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| 205 | * Stack alignment |
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| 206 | */ |
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| 207 | #if (_MIPS_SIM == _MIPS_SIM_ABI32) |
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| 208 | #define ALSZ 7 |
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| 209 | #define ALMASK ~7 |
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| 210 | #endif |
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| 211 | #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) |
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| 212 | #define ALSZ 15 |
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| 213 | #define ALMASK ~15 |
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| 214 | #endif |
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| 215 | |
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| 216 | /* |
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| 217 | * Macros to handle different pointer/register sizes for 32/64-bit code |
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| 218 | */ |
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| 219 | |
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| 220 | /* |
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| 221 | * Size of a register |
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| 222 | */ |
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| 223 | #ifdef __mips64 |
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| 224 | #define SZREG 8 |
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| 225 | #else |
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| 226 | #define SZREG 4 |
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| 227 | #endif |
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| 228 | |
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| 229 | /* |
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| 230 | * Use the following macros in assemblercode to load/store registers, |
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| 231 | * pointers etc. |
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| 232 | */ |
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| 233 | #if (_MIPS_SIM == _MIPS_SIM_ABI32) |
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| 234 | #define REG_S sw |
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| 235 | #define REG_L lw |
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| 236 | #define REG_SUBU subu |
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| 237 | #define REG_ADDU addu |
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| 238 | #endif |
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| 239 | #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) |
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| 240 | #define REG_S sd |
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| 241 | #define REG_L ld |
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| 242 | #define REG_SUBU dsubu |
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| 243 | #define REG_ADDU daddu |
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| 244 | #endif |
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| 245 | |
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| 246 | /* |
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| 247 | * How to add/sub/load/store/shift C int variables. |
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| 248 | */ |
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| 249 | #if (_MIPS_SZINT == 32) |
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| 250 | #define INT_ADD add |
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| 251 | #define INT_ADDU addu |
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| 252 | #define INT_ADDI addi |
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| 253 | #define INT_ADDIU addiu |
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| 254 | #define INT_SUB sub |
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| 255 | #define INT_SUBU subu |
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| 256 | #define INT_L lw |
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| 257 | #define INT_S sw |
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| 258 | #define INT_SLL sll |
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| 259 | #define INT_SLLV sllv |
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| 260 | #define INT_SRL srl |
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| 261 | #define INT_SRLV srlv |
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| 262 | #define INT_SRA sra |
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| 263 | #define INT_SRAV srav |
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| 264 | #endif |
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| 265 | |
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| 266 | #if (_MIPS_SZINT == 64) |
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| 267 | #define INT_ADD dadd |
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| 268 | #define INT_ADDU daddu |
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| 269 | #define INT_ADDI daddi |
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| 270 | #define INT_ADDIU daddiu |
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| 271 | #define INT_SUB dsub |
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| 272 | #define INT_SUBU dsubu |
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| 273 | #define INT_L ld |
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| 274 | #define INT_S sd |
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| 275 | #define INT_SLL dsll |
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| 276 | #define INT_SLLV dsllv |
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| 277 | #define INT_SRL dsrl |
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| 278 | #define INT_SRLV dsrlv |
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| 279 | #define INT_SRA dsra |
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| 280 | #define INT_SRAV dsrav |
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| 281 | #endif |
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| 282 | |
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| 283 | /* |
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| 284 | * How to add/sub/load/store/shift C long variables. |
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| 285 | */ |
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| 286 | #if (_MIPS_SZLONG == 32) |
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| 287 | #define LONG_ADD add |
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| 288 | #define LONG_ADDU addu |
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| 289 | #define LONG_ADDI addi |
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| 290 | #define LONG_ADDIU addiu |
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| 291 | #define LONG_SUB sub |
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| 292 | #define LONG_SUBU subu |
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| 293 | #define LONG_L lw |
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| 294 | #define LONG_S sw |
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| 295 | #define LONG_SLL sll |
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| 296 | #define LONG_SLLV sllv |
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| 297 | #define LONG_SRL srl |
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| 298 | #define LONG_SRLV srlv |
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| 299 | #define LONG_SRA sra |
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| 300 | #define LONG_SRAV srav |
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| 301 | |
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| 302 | #define LONG .word |
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| 303 | #define LONGSIZE 4 |
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| 304 | #define LONGMASK 3 |
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| 305 | #define LONGLOG 2 |
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| 306 | #endif |
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| 307 | |
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| 308 | #if (_MIPS_SZLONG == 64) |
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| 309 | #define LONG_ADD dadd |
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| 310 | #define LONG_ADDU daddu |
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| 311 | #define LONG_ADDI daddi |
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| 312 | #define LONG_ADDIU daddiu |
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| 313 | #define LONG_SUB dsub |
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| 314 | #define LONG_SUBU dsubu |
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| 315 | #define LONG_L ld |
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| 316 | #define LONG_S sd |
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| 317 | #define LONG_SLL dsll |
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| 318 | #define LONG_SLLV dsllv |
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| 319 | #define LONG_SRL dsrl |
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| 320 | #define LONG_SRLV dsrlv |
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| 321 | #define LONG_SRA dsra |
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| 322 | #define LONG_SRAV dsrav |
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| 323 | |
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| 324 | #define LONG .dword |
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| 325 | #define LONGSIZE 8 |
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| 326 | #define LONGMASK 7 |
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| 327 | #define LONGLOG 3 |
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| 328 | #endif |
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| 329 | |
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| 330 | /* |
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| 331 | * How to add/sub/load/store/shift pointers. |
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| 332 | */ |
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| 333 | #if (_MIPS_SZPTR == 32) |
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| 334 | #define PTR_ADD add |
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| 335 | #define PTR_ADDU addu |
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| 336 | #define PTR_ADDI addi |
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| 337 | #define PTR_ADDIU addiu |
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| 338 | #define PTR_SUB sub |
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| 339 | #define PTR_SUBU subu |
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| 340 | #define PTR_L lw |
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| 341 | #define PTR_S sw |
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| 342 | #define PTR_LA la |
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| 343 | #define PTR_SLL sll |
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| 344 | #define PTR_SLLV sllv |
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| 345 | #define PTR_SRL srl |
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| 346 | #define PTR_SRLV srlv |
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| 347 | #define PTR_SRA sra |
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| 348 | #define PTR_SRAV srav |
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| 349 | |
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| 350 | #define PTR_SCALESHIFT 2 |
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| 351 | |
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| 352 | #define PTR .word |
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| 353 | #define PTRSIZE 4 |
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| 354 | #define PTRLOG 2 |
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| 355 | #endif |
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| 356 | |
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| 357 | #if (_MIPS_SZPTR == 64) |
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| 358 | #define PTR_ADD dadd |
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| 359 | #define PTR_ADDU daddu |
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| 360 | #define PTR_ADDI daddi |
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| 361 | #define PTR_ADDIU daddiu |
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| 362 | #define PTR_SUB dsub |
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| 363 | #define PTR_SUBU dsubu |
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| 364 | #define PTR_L ld |
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| 365 | #define PTR_S sd |
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| 366 | #define PTR_LA dla |
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| 367 | #define PTR_SLL dsll |
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| 368 | #define PTR_SLLV dsllv |
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| 369 | #define PTR_SRL dsrl |
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| 370 | #define PTR_SRLV dsrlv |
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| 371 | #define PTR_SRA dsra |
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| 372 | #define PTR_SRAV dsrav |
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| 373 | |
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| 374 | #define PTR_SCALESHIFT 3 |
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| 375 | |
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| 376 | #define PTR .dword |
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| 377 | #define PTRSIZE 8 |
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| 378 | #define PTRLOG 3 |
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| 379 | #endif |
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| 380 | |
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| 381 | /* |
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| 382 | * Some cp0 registers were extended to 64bit for MIPS III. |
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| 383 | */ |
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| 384 | #if (_MIPS_SIM == _MIPS_SIM_ABI32) |
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| 385 | #define MFC0 mfc0 |
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| 386 | #define MTC0 mtc0 |
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| 387 | #endif |
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| 388 | #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) |
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| 389 | #define MFC0 dmfc0 |
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| 390 | #define MTC0 dmtc0 |
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| 391 | #endif |
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| 392 | |
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| 393 | #define SSNOP sll zero,zero,1 |
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| 394 | |
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| 395 | #endif /* __ASM_ASM_H */ |
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