source: svn/trunk/newcon3bcm2_21bu/toolchain/mips-linux-uclibc/include/asm/pgtable-32.h @ 2

Last change on this file since 2 was 2, checked in by jglee, 11 years ago

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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_PGTABLE_32_H
10#define _ASM_PGTABLE_32_H
11
12#include <asm/addrspace.h>
13#include <asm/page.h>
14
15#include <linux/linkage.h>
16#include <asm/cachectl.h>
17#include <asm/fixmap.h>
18
19/*
20 * - add_wired_entry() add a fixed TLB entry, and move wired register
21 */
22extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
23                               unsigned long entryhi, unsigned long pagemask);
24
25/*
26 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
27 *      starting at the top and working down. This is for populating the
28 *      TLB before trap_init() puts the TLB miss handler in place. It
29 *      should be used only for entries matching the actual page tables,
30 *      to prevent inconsistencies.
31 */
32extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
33                               unsigned long entryhi, unsigned long pagemask);
34
35
36/* Basically we have the same two-level (which is the logical three level
37 * Linux page table layout folded) page tables as the i386.  Some day
38 * when we have proper page coloring support we can have a 1% quicker
39 * tlb refill handling mechanism, but for now it is a bit slower but
40 * works even with the cache aliasing problem the R4k and above have.
41 */
42
43/* PMD_SHIFT determines the size of the area a second-level page table can map */
44#ifdef CONFIG_64BIT_PHYS_ADDR
45#define PMD_SHIFT       21
46#else
47#define PMD_SHIFT       22
48#endif
49#define PMD_SIZE        (1UL << PMD_SHIFT)
50#define PMD_MASK        (~(PMD_SIZE-1))
51
52/* PGDIR_SHIFT determines what a third-level page table entry can map */
53#define PGDIR_SHIFT     PMD_SHIFT
54#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
55#define PGDIR_MASK      (~(PGDIR_SIZE-1))
56
57/*
58 * Entries per page directory level: we use two-level, so
59 * we don't really have any PMD directory physically.
60 */
61#ifdef CONFIG_64BIT_PHYS_ADDR
62#define PGD_ORDER       1
63#define PMD_ORDER       0
64#define PTE_ORDER       0
65#else
66#define PGD_ORDER       0
67#define PMD_ORDER       0
68#define PTE_ORDER       0
69#endif
70
71#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
72#define PTRS_PER_PMD    1
73#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
74
75#define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
76#define FIRST_USER_ADDRESS      0
77
78#define VMALLOC_START     KSEG2
79
80#ifdef CONFIG_HIGHMEM
81# define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
82#else
83# define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
84#endif
85
86#ifdef CONFIG_64BIT_PHYS_ADDR
87#define pte_ERROR(e) \
88        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
89#else
90#define pte_ERROR(e) \
91        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
92#endif
93#define pmd_ERROR(e) \
94        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
95#define pgd_ERROR(e) \
96        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
97
98extern void load_pgd(unsigned long pg_dir);
99
100extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
101
102/*
103 * Empty pgd/pmd entries point to the invalid_pte_table.
104 */
105static inline int pmd_none(pmd_t pmd)
106{
107        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
108}
109
110#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
111
112static inline int pmd_present(pmd_t pmd)
113{
114        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
115}
116
117static inline void pmd_clear(pmd_t *pmdp)
118{
119        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
120}
121
122/*
123 * The "pgd_xxx()" functions here are trivial for a folded two-level
124 * setup: the pgd is never bad, and a pmd always exists (as it's folded
125 * into the pgd entry)
126 */
127static inline int pgd_none(pgd_t pgd)           { return 0; }
128static inline int pgd_bad(pgd_t pgd)            { return 0; }
129static inline int pgd_present(pgd_t pgd)        { return 1; }
130static inline void pgd_clear(pgd_t *pgdp)       { }
131
132#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
133#define pte_page(x)             pfn_to_page(pte_pfn(x))
134#define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
135static inline pte_t
136pfn_pte(unsigned long pfn, pgprot_t prot)
137{
138        pte_t pte;
139        pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
140        pte.pte_low = pgprot_val(prot);
141        return pte;
142}
143
144#else
145
146#define pte_page(x)             pfn_to_page(pte_pfn(x))
147
148#ifdef CONFIG_CPU_VR41XX
149#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
150#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
151#else
152#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
153#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
154#endif
155#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
156
157#define __pgd_offset(address)   pgd_index(address)
158#define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
159
160/* to find an entry in a kernel page-table-directory */
161#define pgd_offset_k(address) pgd_offset(&init_mm, address)
162
163#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
164
165/* to find an entry in a page-table-directory */
166#define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
167
168/* Find an entry in the second-level page table.. */
169static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
170{
171        return (pmd_t *) dir;
172}
173
174/* Find an entry in the third-level page table.. */
175#define __pte_offset(address)                                           \
176        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
177#define pte_offset(dir, address)                                        \
178        ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address))
179#define pte_offset_kernel(dir, address) \
180        ((pte_t *) pmd_page_kernel(*(dir)) +  __pte_offset(address))
181
182#define pte_offset_map(dir, address)                                    \
183        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
184#define pte_offset_map_nested(dir, address)                             \
185        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
186#define pte_unmap(pte) ((void)(pte))
187#define pte_unmap_nested(pte) ((void)(pte))
188
189#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
190
191/* Swap entries must have VALID bit cleared. */
192#define __swp_type(x)           (((x).val >> 10) & 0x1f)
193#define __swp_offset(x)         ((x).val >> 15)
194#define __swp_entry(type,offset)        \
195        ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
196
197/*
198 * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset
199 * into this range:
200 */
201#define PTE_FILE_MAX_BITS       27
202
203#define pte_to_pgoff(_pte) \
204        ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 ))
205
206#define pgoff_to_pte(off) \
207        ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE })
208
209#else
210
211/* Swap entries must have VALID and GLOBAL bits cleared. */
212#define __swp_type(x)           (((x).val >> 8) & 0x1f)
213#define __swp_offset(x)         ((x).val >> 13)
214#define __swp_entry(type,offset)        \
215                ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
216
217/*
218 * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
219 * into this range:
220 */
221#define PTE_FILE_MAX_BITS       27
222
223#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
224        /* fixme */
225#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
226#define pgoff_to_pte(off) \
227        ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
228
229#else
230#define pte_to_pgoff(_pte) \
231        ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
232
233#define pgoff_to_pte(off) \
234        ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
235#endif
236
237#endif
238
239#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
240#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
241
242#endif /* _ASM_PGTABLE_32_H */
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