source: svn/newcon3bcm2_21bu/dst/dhl/src/devices/dtqs22ddp101b/MxL601_TunerApi.h

Last change on this file was 76, checked in by megakiss, 10 years ago

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1/*******************************************************************************
2 *
3 * FILE NAME          : MxL601_TunerApi.h
4 *
5 * AUTHOR             : Sunghoon Park
6 *                      Dong Liu
7 *
8 * DATE CREATED       : 07/10/2011
9 *                      11/26/2011
10 *
11 * DESCRIPTION        : This file is header file for MxL601_TunerApi.cpp
12 *
13 *******************************************************************************
14 *                Copyright (c) 2011, MaxLinear, Inc.
15 ******************************************************************************/
16
17#ifndef __MXL601_TUNER_API_H__
18#define __MXL601_TUNER_API_H__
19
20/******************************************************************************
21    Include Header Files
22    (No absolute paths - paths handled by make file)
23******************************************************************************/
24
25#include "MaxLinearDataTypes.h"
26#include "MxL601_TunerCfg.h"
27
28/******************************************************************************
29    Macros
30******************************************************************************/
31
32#define  MXL_VERSION_SIZE         4   
33
34/******************************************************************************
35    User-Defined Types (Typedefs)
36******************************************************************************/
37
38/* Command Types  */
39typedef enum
40{ 
41  // For API_ConfigDevice interface
42  MXL_DEV_SOFT_RESET_CFG = 0,
43  MXL_DEV_OVERWRITE_DEFAULT_CFG,
44  MXL_DEV_XTAL_SET_CFG,
45  MXL_DEV_POWER_MODE_CFG,
46  MXL_DEV_IF_OUT_CFG,
47  MXL_DEV_GPO_CFG,         
48
49  // For API_GetDeviceStatus interface
50  MXL_DEV_ID_VERSION_REQ,
51  MXL_DEV_GPO_STATE_REQ,             
52
53  // For API_ConfigTuner interface
54  MXL_TUNER_MODE_CFG,
55  MXL_TUNER_POWER_UP_CFG,
56  MXL_TUNER_START_TUNE_CFG,
57  MXL_TUNER_AGC_CFG,
58  MXL_TUNER_CHAN_TUNE_CFG,
59  MXL_TUNER_SPUR_SHIFT_ADJ_CFG,
60  MXL_TUNER_FINE_TUNE_CFG,
61  MXL_TUNER_ENABLE_FINE_TUNE_CFG,
62  MXL_TUNER_HLFRF_CFG,
63  MXL_TUNER_TELETEXT_SPUR_CFG,
64
65  // For API_GetTunerStatus interface
66  MXL_TUNER_SIGNAL_TYPE_REQ,
67  MXL_TUNER_LOCK_STATUS_REQ, 
68  MXL_TUNER_AGC_LOCK_REQ, 
69  MXL_TUNER_RX_PWR_REQ,
70  MXL_TUNER_AFC_CORRECTION_REQ,
71
72  MAX_NUM_COMMAND
73} MXL_CMD_TYPE_E;
74
75/* MXL_DEV_SOFT_RESET_CFG  */
76typedef struct
77{
78  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
79} MXL_RESET_CFG_T, *PMXL_RESET_CFG_T;
80
81/* MXL_DEV_OVERWRITE_DEFAULT_CFG */
82typedef struct
83{
84  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
85  MXL_BOOL SingleSupply_3_3V;   /* IN, Single Supply 3.3v */
86} MXL_OVERWRITE_DEFAULT_CFG_T, *PMXL_OVERWRITE_DEFAULT_CFG_T;
87
88/* MXL_DEV_XTAL_SET_CFG  */
89typedef enum
90{
91  XTAL_16MHz = 0,
92  XTAL_24MHz = 1,
93  XTAL_FREQ_NA = 99
94} MXL_XTAL_FREQ_E;
95
96typedef struct
97{
98  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
99  MXL_XTAL_FREQ_E XtalFreqSel;  /* IN, XTAL Frequency, refers above */
100  UINT8 XtalCap;                /* IN, XTAL capacity, 1 LSB = 1pF, maximum is 31pF */
101  MXL_BOOL ClkOutEnable;        /* IN, enable or disable clock out */
102  MXL_BOOL ClkOutDiv;           /* IN, indicate if XTAL frequency is dived by 4 or not */
103  MXL_BOOL SingleSupply_3_3V;   /* IN, Single Supply 3.3v */
104  MXL_BOOL XtalSharingMode;     /* IN, XTAL sharing mode. default Master, MXL_ENABLE to config Slave mode */
105} MXL_XTAL_SET_CFG_T, *PMXL_XTAL_SET_CFG_T;
106
107/* MXL_DEV_POWER_MODE_CFG  */
108typedef enum
109{
110  MXL_PWR_MODE_SLEEP = 0,
111  MXL_PWR_MODE_ACTIVE,
112  MXL_PWR_MODE_STANDBY
113} MXL_PWR_MODE_E;
114
115typedef struct
116{
117  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
118  MXL_PWR_MODE_E PowerMode;     /* IN, power saving mode */
119} MXL_PWR_MODE_CFG_T, *PMXL_PWR_MODE_CFG_T;
120
121/* MXL_DEV_IF_OUT_CFG  */
122typedef enum
123{
124  IF_PATH1 = 1,
125  IF_PATH2 = 2
126} MXL_IF_PATH_E;
127
128typedef enum
129{
130  IF_3_65MHz  = 0,
131  IF_4MHz     = 1,
132  IF_4_1MHz   = 2,
133  IF_4_15MHz  = 3,
134  IF_4_5MHz   = 4, 
135  IF_4_57MHz  = 5,
136  IF_5MHz     = 6,
137  IF_5_38MHz  = 7, 
138  IF_6MHz     = 8,
139  IF_6_28MHz  = 9,
140  IF_7_2MHz   = 10, 
141  IF_8_25MHz  = 11,
142  IF_35_25MHz = 12,
143  IF_36MHz    = 13, 
144  IF_36_15MHz = 14, 
145  IF_36_65MHz = 15,
146  IF_44MHz    = 16,
147  IF_FREQ_NA  = 99
148} MXL_IF_FREQ_E;
149
150typedef struct
151{
152  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
153  MXL_IF_FREQ_E IFOutFreq;      /* IN, band width of IF out signal */
154  UINT32 ManualIFOutFreqInKHz;  /* IN, IF out frequency selection when ManualIFOutCtrl = 0*/
155  MXL_BOOL ManualFreqSet;       /* IN, IF out frequency is set by manual or not */
156  MXL_BOOL IFInversion;         /* IN, IF spectrum is inverted or not */
157  UINT8 GainLevel;              /* IN, IF out gain level */
158  MXL_IF_PATH_E PathSel;        /* IN, define which path is selected */
159}MXL_IF_OUT_CFG_T, *PMXL_IF_OUT_CFG_T;
160
161/* MXL_DEV_GPO_CFG  */
162typedef enum
163{
164  GPO1 = 0,
165  GPO2 = 1,
166  GPO3 = 2
167} MXL_GPO_ID_E;
168
169typedef enum
170{
171  PORT_LOW = 0,
172  PORT_HIGH = 1,
173  PORT_AUTO_CTRL = 2
174} MXL_GPO_STATE_E;
175
176typedef struct
177{
178  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
179  MXL_GPO_ID_E GPOId;           /* IN, GPO port number. 0 for GPO0, 1 for GPO1, and 2 for GPO2 */
180  MXL_GPO_STATE_E GPOState;     /* IN, configuration. */
181} MXL_GPO_CFG_T, *PMXL_GPO_CFG_T;
182
183/* MXL_DEV_ID_VERSION_REQ */
184typedef struct
185{
186  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
187  UINT8 ChipId;                       /* OUT, Device chip ID information  */
188  UINT8 ChipVersion;                  /* OUT, Device chip revision  */
189  UINT8 MxLWareVer[MXL_VERSION_SIZE]; /* OUT, MxLWare version information */   
190} MXL_DEV_INFO_T, *PMXL_DEV_INFO_T;
191
192/* MXL_DEV_GPO_STATE_REQ  */
193typedef struct
194{
195  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */   
196  MXL_GPO_STATE_E GPO1;               /* OUT, GPO0 status */
197  MXL_GPO_STATE_E GPO2;               /* OUT, GPO1 status */
198  MXL_GPO_STATE_E GPO3;               /* OUT, GPO2 status */       
199} MXL_GPO_INFO_T, *PMXL_GPO_INFO_T;
200
201/* MXL_TUNER_MODE_CFG */
202typedef enum
203{
204  ANA_NTSC_MODE = 0x0,
205  ANA_PAL_BG = 0x01,
206  ANA_PAL_I = 0x02,
207  ANA_PAL_D = 0x03,
208  ANA_SECAM_I = 0x04,
209  ANA_SECAM_L = 0x05,
210  DIG_DVB_C = 0x06, 
211  DIG_ISDBT_ATSC = 0x07,
212  DIG_DVB_T = 0x08,
213  DIG_J83B = 0x09,
214  MXL_SIGNAL_NA = 99
215} MXL_SIGNAL_MODE_E;
216
217typedef struct
218{
219  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
220  MXL_SIGNAL_MODE_E SignalMode;       /* IN , Tuner application mode */
221  UINT32 IFOutFreqinKHz;              /* IN, IF Frequency in KHz */
222  MXL_XTAL_FREQ_E XtalFreqSel;        /* XTAL Frequency, refers above */
223  UINT8 IFOutGainLevel;               /* IF out gain level */
224} MXL_TUNER_MODE_CFG_T, *PMXL_TUNER_MODE_CFG_T;
225
226/* MXL_TUNER_POWER_UP_CFG */
227typedef struct
228{
229  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
230  MXL_BOOL Enable;                    /* IN , enable or disable all sections of main path */
231} MXL_POWER_UP_CFG_T, *PMXL_POWER_UP_CFG_T;
232
233/* MXL_TUNER_START_TUNE_CFG */ 
234typedef struct
235{
236  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
237  MXL_BOOL StartTune;                 /* IN , sequence set, 0 means start sequence, 1 means finish */
238} MXL_START_TUNE_CFG_T, *PMXL_START_TUNE_CFG_T;
239
240/* MXL_TUNER_AGC_CFG */ 
241typedef enum
242{
243  AGC2 = 0,
244  AGC1 = 1
245} MXL_AGC_ID_E;
246
247typedef enum
248{
249  AGC_SELF = 0,
250  AGC_EXTERNAL = 1
251} MXL_AGC_TYPE_E;
252
253typedef struct
254{
255  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
256  MXL_AGC_ID_E AgcSel;                /* IN, AGC selection, AGC1 or AGC2 */
257  MXL_AGC_TYPE_E AgcType;             /* IN, AGC mode selection, self or closed loop */
258  UINT8 SetPoint;                     /* IN, AGC attack point set value */
259  MXL_BOOL AgcPolarityInverstion;     /* IN, Config AGC Polarity inversion */
260} MXL_AGC_SET_CFG_T, *PMXL_AGC_SET_CFG_T;
261
262/* MXL_TUNER_CHAN_TUNE_CFG */
263typedef enum
264{
265  ANA_TV_DIG_CABLE_BW_6MHz = 0x00,    /* Analog TV and Digital Cable Mode 6MHz */ 
266  ANA_TV_DIG_CABLE_BW_7MHz = 0x01,    /* Analog TV and Digital Cable Mode 7MHz */
267  ANA_TV_DIG_CABLE_BW_8MHz = 0x02,    /* Analog TV and Digital Cable Mode 8MHz */
268  DIG_TERR_BW_6MHz = 0x20,            /* Digital Terrestrial Mode 6MHz */
269  DIG_TERR_BW_7MHz = 0x21,            /* Digital Terrestrial Mode 7MHz */
270  DIG_TERR_BW_8MHz = 0x22             /* Digital Terrestrial Mode 8MHz */
271} MXL_BW_E;
272
273typedef enum
274{
275  VIEW_MODE = 0, 
276  SCAN_MODE
277} MXL_TUNE_TYPE_E;
278
279typedef enum
280{
281  MXL_NTSC_CARRIER_NA = 0,
282  MXL_NTSC_CARRIER_HRC = 1,
283  MXL_NTSC_CARRIER_IRC = 2
284} MXL_NTSC_CARRIERS_E;
285
286typedef struct
287{
288  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
289  MXL_TUNE_TYPE_E TuneType;           /* IN, Tune mode, view mode or channel scan mode */
290  MXL_BW_E BandWidth;                 /* IN, band width in MHz */
291  UINT32 FreqInHz;                    /* IN, Radio Frequency in Hz */
292  MXL_SIGNAL_MODE_E SignalMode;       /* IN , Tuner application mode */
293  MXL_XTAL_FREQ_E XtalFreqSel;        /* IN, Xtal frequency */
294  MXL_NTSC_CARRIERS_E NtscCarrier;    /* IN, NTSC Carriers HRC or IRC (used for tunning NTSC channels only) */
295  UINT32 IFOutFreqinKHz;              /* IN, IF Frequency in KHz */
296} MXL_TUNER_TUNE_CFG_T, *PMXL_TUNER_TUNE_CFG_T;
297
298/* MXL_TUNER_SPUR_SHIFT_ADJ_CFG */
299typedef struct
300{
301  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
302  UINT8 SpurShiftingClkAdjValue;      /* IN, Spur shifting clock adjust value, range [205, 227] */ 
303} MXL_SPUR_SHIFT_ADJ_CFG_T, *PMXL_SPUR_SHIFT_ADJ_CFG_T;
304
305/* MXL_TUNER_HLFRF_OPTIMIZATION_CFG  */
306typedef struct
307{
308  UINT8 I2cSlaveAddr;           /* IN, I2C Address of MxL Device */
309  MXL_BOOL Enable;              /* IN, Enable or Disable the control */
310} MXL_HLFRF_CFG_T, *PMXL_HLFRF_CFG_T;
311
312/* MXL_TUNER_FINE_TUNE_CFG */
313typedef struct
314{
315  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
316  MXL_BOOL ScaleUp;                   /* IN, 0 means decrease one step, 1 means increase one step */
317} MXL_FINE_TUNE_CFG_T, *PMXL_FINE_TUNE_CFG_T;
318
319/* MXL_TUNER_ENABLE_FINE_TUNE_CFG */
320typedef struct
321{
322  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
323  MXL_BOOL EnableFineTune;            /* IN, enable/disable fine tune */
324} MXL_ENABLE_FINE_TUNE_CFG_T, *PMXL_ENABLE_FINE_TUNE_CFG_T;
325
326/* MXL_TUNER_SIGNAL_TYPE_REQ */
327typedef enum
328{
329  SIGNAL_TYPE_DIGITAL = 0,
330  SIGNAL_TYPE_ANALOG
331} MXL_SIGNAL_TYPE_E;
332
333typedef struct
334{
335  UINT8 I2cSlaveAddr;     
336  MXL_SIGNAL_TYPE_E SignalMode; 
337} MXL_SIGNAL_TYPE_T, *PMXL_SIGNAL_TYPE_T;
338
339/* MXL_TUNER_LOCK_STATUS_REQ */
340typedef struct
341{
342  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
343  MXL_BOOL RfSynLock;                 /* OUT, Tuner RF synthesis lock Status */
344  MXL_BOOL RefSynLock;                /* OUT, Tuner Ref synthesis lock Status */
345} MXL_TUNER_LOCK_STATUS_T, *PMXL_TUNER_LOCK_STATUS_T;
346
347/* MXL_TUNER_AGC_LOCK_REQ */
348typedef struct
349{
350  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
351  MXL_BOOL AgcLock;                   /* OUT, Tuner AGC lock Status */
352} MXL_TUNER_AGC_LOCK_T, *PMXL_TUNER_AGC_LOCK_T;
353
354/* MXL_TUNER_RX_PWR_REQ */
355typedef struct
356{
357  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
358  REAL32 RxPwr;                       /* OUT, Tuner RF Input Power in dBm */
359} MXL_TUNER_RX_PWR_T, *PMXL_TUNER_RX_PWR_T;
360
361/* MXL_TUNER_AFC_CORRECTION_REQ */
362typedef struct
363{
364  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
365  REAL64 AfcOffsetKHz;                /* OUT, Tuner AFC correction offset in kHz */
366} MXL_TUNER_AFC_CORRECTION_T, *PMXL_TUNER_AFC_CORRECTION_T;
367
368/* MXL_TUNER_TELETEXT_SPUR_CFG */
369typedef struct
370{
371  UINT8 I2cSlaveAddr;                 /* IN, I2C Address of MxL Device */
372  UINT32 numofDCCalSamples;
373  UINT32 dcCalSamplesInterval;
374  UINT32 initialTimeDelay;
375  REAL64 dcCalThreshold;
376} MXL_TELETEXT_SPUR_CFG_T, *PMXL_TELETEXT_SPUR_CFG_T;
377
378/* API COMMAND interface structure */
379typedef struct
380{
381  MXL_CMD_TYPE_E commandId;  /* Command Identifier */
382
383  union
384  {
385    MXL_RESET_CFG_T cmdResetCfg;
386    MXL_OVERWRITE_DEFAULT_CFG_T cmdOverwriteDefault;
387    MXL_XTAL_SET_CFG_T cmdXtalCfg;
388    MXL_PWR_MODE_CFG_T cmdPwrModeCfg;
389    MXL_IF_OUT_CFG_T cmdIfOutCfg;   
390    MXL_GPO_CFG_T cmdGpoCfg;
391
392    MXL_DEV_INFO_T cmdDevInfoReq;
393    MXL_GPO_INFO_T cmdGpoReq;
394
395    MXL_TUNER_MODE_CFG_T cmdModeCfg;
396    MXL_POWER_UP_CFG_T cmdTunerPoweUpCfg;
397    MXL_START_TUNE_CFG_T cmdStartTuneCfg;
398    MXL_AGC_SET_CFG_T cmdAgcSetCfg; 
399    MXL_TUNER_TUNE_CFG_T cmdChanTuneCfg;
400    MXL_SPUR_SHIFT_ADJ_CFG_T cmdSuprShiftAdjCfg;
401    MXL_FINE_TUNE_CFG_T cmdFineTuneCfg;
402    MXL_ENABLE_FINE_TUNE_CFG_T cmdEnableFineTuneCfg;
403    MXL_HLFRF_CFG_T cmdHlfrfCfg;
404    MXL_TELETEXT_SPUR_CFG_T cmdTeletextSpurCfg;
405
406    MXL_SIGNAL_TYPE_T cmdTunerSignalTypeReq;
407    MXL_TUNER_LOCK_STATUS_T cmdTunerLockReq;
408    MXL_TUNER_RX_PWR_T cmdTunerPwrReq;
409    MXL_TUNER_AGC_LOCK_T cmdTunerAgcLockReq;
410    MXL_TUNER_AFC_CORRECTION_T cmdTunerAfcCorectionReq;
411  } MxLIf;
412} MXL_COMMAND_T;
413
414/******************************************************************************
415    Global Variable Declarations
416******************************************************************************/
417
418extern const UINT8 MxLWareDrvVersion[];
419extern const UINT8 BuildNumber;
420
421/******************************************************************************
422    Prototypes
423******************************************************************************/
424
425#ifndef __MXL_GUI__
426MXL_STATUS MxLWare601_API_ConfigDevice(MXL_COMMAND_T *ParamPtr);
427MXL_STATUS MxLWare601_API_GetDeviceStatus(MXL_COMMAND_T *ParamPtr);
428MXL_STATUS MxLWare601_API_ConfigTuner(MXL_COMMAND_T *ParamPtr);
429MXL_STATUS MxLWare601_API_GetTunerStatus(MXL_COMMAND_T *ParamPtr);
430#endif
431
432#endif /* __MXL601_TUNER_API_H__*/
433
434
435
436
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