| 1 | /******************************************************************************* |
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| 2 | * |
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| 3 | * FILE NAME : MxL601_TunerCfg.h |
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| 4 | * |
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| 5 | * AUTHOR : Dong Liu |
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| 6 | * |
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| 7 | * DATE CREATED : 11/16/2011 |
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| 8 | * |
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| 9 | * DESCRIPTION : This file contains MxL601 common control register |
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| 10 | * definitions |
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| 11 | * |
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| 12 | ******************************************************************************* |
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| 13 | * Copyright (c) 2011, MaxLinear, Inc. |
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| 14 | ******************************************************************************/ |
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| 15 | |
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| 16 | #ifndef __MXL601_TUNER_CFG_H__ |
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| 17 | #define __MXL601_TUNER_CFG_H__ |
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| 18 | |
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| 19 | /****************************************************************************** |
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| 20 | Include Header Files |
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| 21 | (No absolute paths - paths handled by make file) |
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| 22 | ******************************************************************************/ |
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| 23 | |
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| 24 | #include "MxL601_OEM_Drv.h" |
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| 25 | #include "MxL601_TunerSpurTable.h" |
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| 26 | |
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| 27 | /****************************************************************************** |
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| 28 | Macros |
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| 29 | ******************************************************************************/ |
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| 30 | |
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| 31 | //#define CUSTOMER_SPECIFIC_SETTING_1 |
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| 32 | |
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| 33 | #define AIC_RESET_REG 0xFF // For MxL601 Tuner |
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| 34 | |
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| 35 | #define PAGE_CHANGE_REG 0x00 // Page change, can configured as page 0 or page 1 |
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| 36 | #define XTAL_CAP_CTRL_REG 0x01 // Xtal frequency and CAP register |
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| 37 | #define XTAL_ENABLE_DIV_REG 0x02 // Xtal enable and frequency div 4 register |
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| 38 | #define XTAL_CALI_SET_REG 0x03 // Xtal calibration enable register enable register |
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| 39 | #define IF_FREQ_SEL_REG 0x04 // IF frequency selection and manual set bypass register |
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| 40 | #define IF_PATH_GAIN_REG 0x05 // IF gain level and path selection register |
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| 41 | #define IF_FCW_LOW_REG 0x06 // Low register of IF FCW set when manual program IF frequency |
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| 42 | #define IF_FCW_HIGH_REG 0x07 // High register of IF FCW set when manual program IF frequency |
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| 43 | #define AGC_CONFIG_REG 0x08 // AGC configuration, include AGC select and AGC type |
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| 44 | #define AGC_SET_POINT_REG 0x09 |
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| 45 | #define AGC_FLIP_REG 0x5E |
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| 46 | #define AGC_SLOPE_REG 0xB5 |
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| 47 | #define AGC_OFFSET_REG 0xB4 |
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| 48 | #define GPO_SETTING_REG 0x0A // GPO set and inquiring register |
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| 49 | #define TUNER_ENABLE_REG 0x0B // Power up register, bit<0> |
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| 50 | #define TUNE_MODE_REG 0x0D |
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| 51 | #define MAIN_REG_AMP 0x0E |
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| 52 | #define CHAN_TUNE_BW_REG 0x0F // Band width register |
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| 53 | #define CHAN_TUNE_LOW_REG 0x10 // Tune frequency set low byte |
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| 54 | #define CHAN_TUNE_HI_REG 0x11 // Tune frequency set high byte |
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| 55 | #define START_TUNE_REG 0x12 // sequencer setting register |
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| 56 | #define FINE_TUNE_SET_REG 0x13 // Fine tune operation register |
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| 57 | #define FINE_TUNE_CTRL_REG_0 0x13 // Fine tune operation register |
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| 58 | #define FINE_TUNE_CTRL_REG_1 0x14 // Fine tune operation register |
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| 59 | |
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| 60 | #define FINE_TUNE_OFFSET_LOW_REG 0x14 // Fine tune frequency offset low byte |
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| 61 | #define FINE_TUNE_OFFSET_HIGH_REG 0x15 // Fine tune frequency offset high byte |
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| 62 | #define CHIP_ID_REQ_REG 0x18 // Tuner Chip ID register |
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| 63 | #define CHIP_VERSION_REQ_REG 0x1A // Tuner Chip Revision register |
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| 64 | |
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| 65 | #define RFPIN_RB_LOW_REG 0x1D // RF power low 8 bit register |
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| 66 | #define RFPIN_RB_HIGH_REG 0x1E // RF power high 8 bit register |
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| 67 | #define SIGNAL_TYPE_REG 0x1E // Signal type |
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| 68 | |
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| 69 | #define DFE_CTRL_ACCUM_LOW_REG 0x24 // Bit<7:0> |
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| 70 | #define DFE_CTRL_ACCUM_MID_REG 0x25 // Bit<7:0> |
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| 71 | #define DFE_CTRL_ACCUM_HI_REG 0x26 // Bit<1:0> |
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| 72 | |
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| 73 | #define DFE_CTRL_TRIG_REG 0xA0 // Bit<3> |
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| 74 | #define DFE_CTRL_RB_HI_REG 0x7B // Bit<7:0> |
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| 75 | #define DFE_CTRL_RB_LOW_REG 0x7A // Bit<1:0> |
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| 76 | |
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| 77 | #define RF_REF_STATUS_REG 0x2B // RF/REF lock status register |
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| 78 | |
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| 79 | #define AGC_SAGCLOCK_STATUS_REG 0x2C |
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| 80 | |
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| 81 | #define DFE_DACIF_BYP_GAIN_REG 0x43 |
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| 82 | #define DIG_ANA_RFRSSI_REG 0x57 |
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| 83 | |
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| 84 | #define RSSI_RESET_REG 0x78 |
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| 85 | |
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| 86 | #define FINE_TUNE_INIT1_REG 0xA9 |
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| 87 | #define FINE_TUNE_INIT2_REG 0xAA |
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| 88 | |
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| 89 | #define DFE_AGC_CEIL1_REG 0xB0 |
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| 90 | |
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| 91 | #define DFE_RFLUT_BYP_REG 0xDB // Dec: 220, bit<7> |
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| 92 | //#define DFE_RFLUT_DIV_IN_BYP_REG 0xDB // Dec: 220, bit<6> |
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| 93 | #define DFE_RFLUT_DIV_MOD_REG 0xDB // Dec: 221 |
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| 94 | //#define DFE_RFSX_INT_MOD_REG 0xDB // Dec: 222 |
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| 95 | |
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| 96 | #define DFE_RFLUT_SWP1_REG 0x49 |
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| 97 | |
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| 98 | #define DFE_RFSX_FRAC_MOD1_REG 0xDF |
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| 99 | #define DFE_RFSX_FRAC_MOD2_REG 0xE0 |
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| 100 | #define DFE_RFSX_FRAC_MOD3_REG 0xE1 |
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| 101 | #define DFE_RFSX_FRAC_MOD4_REG 0xE2 |
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| 102 | |
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| 103 | #define DFE_REFLUT_BYP_REG 0xEA // Dec: 240, bit<6> |
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| 104 | #define DFE_REFSX_INT_MOD_REG 0xEB // Dec: 241 |
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| 105 | |
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| 106 | #define APP_MODE_FREQ_HZ_THRESHOLD_1 358000000 |
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| 107 | #define APP_MODE_FREQ_HZ_THRESHOLD_2 625000000 |
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| 108 | |
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| 109 | #define SPUR_SHIFT_FREQ_WINDOW 500000 // +- 0.5MHz |
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| 110 | |
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| 111 | #define IF_GAIN_SET_POINT1 10 |
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| 112 | #define IF_GAIN_SET_POINT2 11 |
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| 113 | #define IF_GAIN_SET_POINT3 12 |
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| 114 | |
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| 115 | #define SPUR_SHIFT_CLOCK_ADJUST_MIN 205 |
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| 116 | #define SPUR_SHIFT_CLOCK_ADJUST_MAX 227 |
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| 117 | |
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| 118 | #define DIG_ANA_IF_CFG_0 0x5A |
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| 119 | #define DIG_ANA_IF_CFG_1 0x5B |
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| 120 | #define DIG_ANA_IF_PWR 0x5C |
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| 121 | |
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| 122 | #define DFE_CSF_SS_SEL 0xEA |
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| 123 | #define DFE_DACIF_GAIN 0xDC |
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| 124 | |
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| 125 | #define FINE_TUNE_FREQ_DECREASE 0x01 |
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| 126 | #define FINE_TUNE_FREQ_INCREASE 0x02 |
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| 127 | |
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| 128 | #define RF_SX_FRAC_N_RANGE 0xDD |
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| 129 | |
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| 130 | #define HIGH_IF_35250_KHZ 35250 |
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| 131 | |
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| 132 | #define DFE_FDC_OFFSET_I_LSB 0xAF // Page 1 |
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| 133 | #define DFE_FDC_OFFSET_I_MSB 0xB0 // Page 1 |
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| 134 | |
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| 135 | #define DFE_FDC_OFFSET_Q_LSB 0xB1 // Page 1 |
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| 136 | #define DFE_FDC_OFFSET_Q_MSB 0xB2 // Page 1 |
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| 137 | |
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| 138 | #define DFE_REFINTMOD_RB 0x3B // <8 bits> |
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| 139 | #define DFE_RFLUT_DIV_IN_RB 0xB8 // Page 1 <5 bits> |
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| 140 | #define DFE_RFINITMOD_RB 0xB9 // Page 1 <7 bits> |
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| 141 | #define DFE_RFFRACMOD_RB 0xBA // Page 1 <26 bits> |
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| 142 | #define DFE_RFLUT_BYP 0x32 // Page 1 <1 bit> |
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| 143 | #define DFE_RFINITMOD_W 0x33 // Page 1 <7 bits> |
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| 144 | #define DFE_RFFRACMOD_W 0x34 // Page 1 <26 bits> |
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| 145 | |
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| 146 | #define DFE_SEQ_RFSX_MOD_VALID_BYP 0x58 // Page 1 <bit 1> dfe_seq_digana_rfsx_mod_valid_byp |
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| 147 | #define DFE_SEQ_RFSX_MOD_VALID 0x58 // Page 1 <bit 0> dfe_seq_digana_rfsx_mod_valid |
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| 148 | |
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| 149 | #define MAX_LUT_SIZE 8 |
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| 150 | #define MAX_DC_CAL_SAMPLES 50 |
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| 151 | |
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| 152 | #define DFE_FDC_IIR0_1 0x87 |
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| 153 | #define DFE_FDC_IIR2_3 0x88 |
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| 154 | |
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| 155 | /****************************************************************************** |
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| 156 | User-Defined Types (Typedefs) |
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| 157 | ******************************************************************************/ |
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| 158 | |
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| 159 | typedef struct |
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| 160 | { |
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| 161 | UINT8 regAddr; |
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| 162 | UINT8 mask; |
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| 163 | UINT8 data; |
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| 164 | } REG_CTRL_INFO_T, *PREG_CTRL_INFO_T; |
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| 165 | |
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| 166 | typedef struct |
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| 167 | { |
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| 168 | UINT8 i2cAddr; |
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| 169 | UINT8 xtalAmp_Rb; |
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| 170 | UINT8 xtalAmp_LinRb; |
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| 171 | UINT8 appMode; |
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| 172 | } XTAL_SPUR_CFG_T; |
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| 173 | |
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| 174 | typedef struct |
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| 175 | { |
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| 176 | UINT16 if_fcw_invert; |
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| 177 | UINT16 if_fcw_noninvert; |
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| 178 | } IF_FCW_LUT_T; |
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| 179 | |
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| 180 | typedef struct |
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| 181 | { |
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| 182 | UINT8 i2cAddr; |
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| 183 | UINT8 if_sel; |
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| 184 | UINT8 if_fcw_byp; |
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| 185 | UINT8 if_invert; |
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| 186 | UINT32 manualIFOutFreqInKHz; |
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| 187 | } IF_FCW_CFG_T; |
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| 188 | |
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| 189 | /****************************************************************************** |
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| 190 | Global Variable Declarations |
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| 191 | ******************************************************************************/ |
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| 192 | |
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| 193 | extern REG_CTRL_INFO_T MxL_OverwriteDefaults[]; |
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| 194 | extern REG_CTRL_INFO_T AnalogNtsc[]; |
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| 195 | extern REG_CTRL_INFO_T AnalogPal[]; |
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| 196 | extern REG_CTRL_INFO_T AnalogSecam[]; |
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| 197 | extern REG_CTRL_INFO_T DigitalDvbc[]; |
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| 198 | extern REG_CTRL_INFO_T DigitalIsdbtAtsc[]; |
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| 199 | extern REG_CTRL_INFO_T DigitalDvbt[]; |
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| 200 | |
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| 201 | extern REG_CTRL_INFO_T Ntsc_RfLutSwpHIF[]; |
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| 202 | extern REG_CTRL_INFO_T Ntsc_16MHzRfLutSwpLIF[]; |
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| 203 | extern REG_CTRL_INFO_T Ntsc_24MHzRfLutSwpLIF[]; |
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| 204 | |
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| 205 | extern REG_CTRL_INFO_T Pal_RfLutSwpLIF[]; |
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| 206 | extern REG_CTRL_INFO_T PalD_RfLutSwpHIF[]; |
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| 207 | extern REG_CTRL_INFO_T PalI_RfLutSwpHIF[]; |
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| 208 | extern REG_CTRL_INFO_T PalBG_8MHzBW_RfLutSwpHIF[]; |
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| 209 | extern REG_CTRL_INFO_T PalBG_7MHzBW_RfLutSwpHIF[]; |
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| 210 | extern REG_CTRL_INFO_T Ntsc_HRCRfLutSwpLIF[]; |
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| 211 | |
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| 212 | /****************************************************************************** |
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| 213 | Prototypes |
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| 214 | ******************************************************************************/ |
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| 215 | |
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| 216 | // Functions for register write operation |
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| 217 | MXL_STATUS Ctrl_ProgramRegisters(UINT8 I2cAddr, PREG_CTRL_INFO_T ctrlRegInfoPtr); |
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| 218 | MXL_STATUS Ctrl_WriteRegField(UINT8 I2cAddr, PREG_CTRL_INFO_T ctrlRegInfoPtr); |
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| 219 | |
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| 220 | // Functions called by MxLWare API |
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| 221 | MXL_STATUS Ctrl_SetRfFreqLutReg(UINT8 i2cAddress, UINT32 FreqInHz, PCHAN_DEPENDENT_FREQ_TABLE_T freqLutPtr); |
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| 222 | |
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| 223 | REAL32 MxL_GetTunerSignedBits(UINT32 bits, UINT8 signedUnsigned, UINT8 numBits, UINT8 fractionBit); |
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| 224 | REAL64 MxL_CalculateVariance(REAL32 *dataPtr, UINT8 numOfItems); |
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| 225 | #endif /* __MXL601_TUNER_CFG_H__*/ |
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| 226 | |
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| 227 | |
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| 228 | |
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| 229 | |
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