/******************************************************************* * DMW_ChannelDB.c * * Interface code to middle ware for DST Module/STB channel DB management * especially about NVRAM. * * some of DMW_CDB_XXX APIs are implemented in this module. * * Copyright 2003 Digital STREAM Technology, Inc. * All Rights Reserved * * $Id: DMW_ChannelDB.c,v 1.31 2004 cafrii Exp $ * ********************************************************************/ #include "DMW_Platform.h" #include "DHL_OSAL.h" #include "DHL_DBG.h" #include "DMW_Config.h" #include "DMW_ChannelAPI.h" #include "DMW_DebugUtil.h" #include "dmw_ucm_priv.h" #include "dmw_nvram_priv.h" #if !USE_INCLUDED_CRC_CODE #include "DHL_UTL.h" #endif //#include //#include DHL_MODULE("$cdb", 0); //--------------------------------------------------------- // Configurations.. #undef STATIC #if 1 #define STATIC // for test debugging.. #else #define STATIC static // for release code.. #endif //--------------------------------------------------------- #if COMMENT _______Util______(){} #endif STATIC UINT32 _m2d(UINT8 *p, int bytesize) // memory to digit { UINT32 result = 0; int i; if (bytesize > 4) bytesize = 4; for (i=0; i 4) bytesize = 4; // 'data' is only 4 byte-sized variable at maximum. for (i=0; i>= 8; } return statusOK; } #if COMMENT _______CRC______(){} #endif #if USE_INCLUDED_CRC_CODE static UINT32 crc_table[256]; #define DEMUX_CRC_ADDER_MASK 0x04C11DB7 void nvr_init_crc_table() { int i, j; UINT32 crc; // Initialize CRC table for (i=0; i<256; i++) { crc = 0; for (j=7; j>=0; j--) { if (((i >> j) ^ (crc >> 31)) & 1) { crc=(crc<<1)^DEMUX_CRC_ADDER_MASK; } else { crc<<=1; } } crc_table[i] = crc; } } // cafrii 041109 add // crc32 ¸¦ °è»êÇÑ´Ù. // UINT32 nvr_calc_crc32(UINT32 crc_start, const UINT8 *data, UINT32 len) { UINT32 crc = crc_start; // 0xFFFFFFFF; UINT32 i; if (crc_table[1] == 0) { // ¾ÆÁ÷ ÃʱâÈ­°¡ ¾ÈµÈ ¸ð¾çÀÌ´Ù. dprint(2, "..initializing crc table..\n"); nvr_init_crc_table(); } for (i = 0; i < len; ++i) { crc = (crc << 8) ^ crc_table[(crc >> 24) ^ (*data++)]; } return(crc); } #else UINT32 nvr_calc_crc32(UINT32 crc_start, const UINT8 *data, UINT32 len) { return DHL_UTL_CalcCRC32(crc_start, data, len); } #endif #if COMMENT _______Level_1_______(){} #endif STATIC BOOL nvr_is_safe_area(UINT32 offset, UINT32 size) { // NvRAM¿¡ Á¢±ÙÇϱâ Àü¿¡ ÀÌ ¿µ¿ª (offset, size)ÀÌ »ç¿ë°¡´ÉÇÑ ¿µ¿ªÀÎÁö üũ. if (offset & 0x80000000) // device 1. Flash { #if SUPPORT_DMW_FLASH_DB // cafrii, 031201 add more check code offset &= 0x7fffffff; if (offset + size > (UINT32)NvRamGetAvailableSize(1)) return FALSE; // over the maximum. return TRUE; // cafrii 031112 #else return FALSE; #endif } else // device 0. EEPROM. { #if SUPPORT_DMW_EEPROM if (offset + size > (UINT32)NvRamGetAvailableSize(0)) return FALSE; else return TRUE; // safe!! this range is allowed to use. #else return FALSE; #endif } } // Level 1 public API. // NvRam I/O. // UINT32 DMW_CDB_GetNvRamAvailableSize(int device) { // ÇØ´ç NvRAM deviceÀÇ »ç¿ë°¡´ÉÇÑ ¿µ¿ª Å©±â¸¦ ¸®ÅÏ. // if (device == 0) // EEPROM return NvRamGetAvailableSize(0); else return NvRamGetAvailableSize(1); } // cafrii 031201, add one more arguments, // and save directory number information in NVPARAM area. // STATUS DMW_CDB_LowLevelFormatNvRam(void) { int err = statusOK; // CAUTION! // ÀÌ ÇÔ¼ö´Â ÀÏ¹Ý application ÇÁ·Î±×·¥À» À§ÇÑ °ÍÀÌ ¾Æ´Ï°í, // ¾ç»ê¿ë ÇÁ·Î±×·¥ ¶Ç´Â °Ë»ç/¼ö¸®¿ë Å×½ºÆ® ÇÁ·Î±×·¥À» À§ÇÑ °ÍÀÓ. // Á¦Ç° »ý»ê½Ã ÃÖÃÊ Blank EEPROM »óÅ¿¡¼­´Â 1ȸ ½Ç½Ã ÇÊ¿äÇÔ. // // cafrii 070424 add comment // ºÎÆÃ Áß¿¡ NvRam ¿µ¿ª¿¡ ¹®Á¦°¡ ÀÖ´Ù°í ÆÇ´ÜµÇ¸é // application Äڵ忡¼­ formatÀ» ÇÒ ¼ö ÀÖÀ½. #if SUPPORT_DMW_FLASH_DB err = NvRamFormat(); // cafrii 031112 if (err) return (STATUS)err; #endif return statusOK; } /* DMW_CDB_CheckNvRam: NvRamÀÌ Á¦´ë·Î formatÀÌ µÇ¾ú´ÂÁö, »ç¿ë °¡´ÉÇÑÁö üũÇÑ´Ù. */ STATUS DMW_CDB_CheckNvRam(void) { return NvRamCheckValid(); } /* DMW_CDB_ReadNvRam: NvRam ¿µ¿ªÀ» Àд´Ù. */ STATUS DMW_CDB_ReadNvRam(UINT32 address, UINT32 size, UINT8 *buf) { if (!nvr_is_safe_area(address, size)) return statusNvRamBadAddress; return NvRamRead(address, size, buf); } /* DMW_CDB_WriteNvRam: NvRam ¿µ¿ª¿¡ µ¥ÀÌÅ͸¦ ±â·ÏÇÑ´Ù. */ STATUS DMW_CDB_WriteNvRam(UINT32 address, UINT32 size, UINT8 *buf) { if (!nvr_is_safe_area(address, size)) return statusNvRamBadAddress; return NvRamWrite(address, size, buf); } //---------------------------------------------------------- // EEPROM test ÇÔ¼öµé.. // STATUS DMW_CDB_DumpNvRam(UINT32 start, int size, char *name) { int err; UINT8 *buf; if (size <= 0 || size > 16384) { return statusOutOfRange; } buf = DHL_OS_Malloc(size); if (buf == NULL) { return statusOutOfResource; } DHL_OS_Printf(" NvRam (%x~%x): '%s'\n", start, start+size, name ? name : ""); err = DMW_CDB_ReadNvRam(start, size, (UINT8 *)buf); if (!err) { memdump2(buf, size, "NvRam", (UINT32)start-(UINT32)buf); } DHL_OS_Free((void**)&buf); return statusOK; } STATUS DMW_CDB_InitNvRam(void) { NvRamInit(); dprint(0, "Config:EEPROM size %d\n", NvRamGetAvailableSize(0)); return statusOK; } //****************************************************************** // // Read/Write Channel DB // // NVRAM access API. #if COMMENT _______Level_3_______(){} #endif STATIC UINT16 g_epgIndex; UINT16 nvr_generate_epg_index(UINT32 arg) { return ++g_epgIndex; } void nvr_reset_epg_index() { g_epgIndex = 0; } /* Unicode (16bit) stringÀÇ ±æÀ̸¦ °è»ê. StringÀº Null ¹®ÀÚ·Î Á¾·áµÇ°Å³ª ¶Ç´Â maxlen ¿¡ ÀÇÇØ¼­ Á¾·áµÊ. maxlenÀÌ -1ÀÏ °æ¿ì ÃÖ´ë ±æÀÌ Á¦ÇÑ ¾øÀ½. ¿ÀÁ÷ Null Á¾·á¸¸ µÊ. µÞ ºÎºÐÀÇ °ø¹é¹®ÀÚ´Â ±æÀÌ¿¡ Æ÷ÇÔÇÏÁö ¾Êµµ·Ï ÇÑ´Ù. (todo) */ int nvr_uc16len(UINT16 *str, int maxlen) { UINT16 *p = str; if (!p) return 0; while (*p && p