| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2003-2009, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: bchp_3520.h $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/3 $ |
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| 12 | * $brcm_Date: 5/29/09 11:33p $ |
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| 13 | * |
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| 14 | * [File Description:] |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /magnum/basemodules/chp/3520/bchp_3520.h $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/3 5/29/09 11:33p dliu |
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| 21 | * PR55183: Add end of acquisition interrupt |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/2 5/26/09 1:46p dliu |
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| 24 | * PR55183: Add OOB lock interrupt defintion |
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| 25 | * |
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| 26 | * Hydra_Software_Devel/1 9/10/04 1:32p enavarro |
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| 27 | * PR 12617: initial version |
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| 28 | * |
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| 29 | ***************************************************************************/ |
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| 30 | |
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| 31 | #ifndef BCHP_3520_H__ |
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| 32 | #define BCHP_3520_H__ |
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| 33 | |
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| 34 | /* BCM3520 host registers */ |
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| 35 | #define BCM3520_SH_SFR_H_ADR_16_15 0x0084 |
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| 36 | #define BCM3520_SH_SFR_H_ADR_14_7 0x0085 |
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| 37 | #define BCM3520_SH_SFR_IO_MBOX_STATUS 0x0086 |
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| 38 | #define BCM3520_SH_SFR_IO_MBOX_A_15_8 0x0087 |
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| 39 | #define BCM3520_SH_SFR_IO_MBOX_D_31_24 0x0088 |
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| 40 | #define BCM3520_SH_SFR_IO_MBOX_D_23_16 0x0089 |
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| 41 | #define BCM3520_SH_SFR_IO_MBOX_D_15_8 0x008a |
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| 42 | #define BCM3520_SH_SFR_IO_MBOX_D_7_0 0x008b |
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| 43 | #define BCM3520_SH_SFR_IO_MBOX_CMD 0x008c |
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| 44 | #define BCM3520_SH_AP_SFR_H_MSG1 0x0093 |
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| 45 | #define BCM3520_SH_AP_SFR_H_MSG2 0x0094 |
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| 46 | #define BCM3520_SH_AP_SFR_JDEC 0x0095 |
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| 47 | #define BCM3520_SH_AP_SFR_H_CTL1 0x009a |
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| 48 | #define BCM3520_SH_AP_SFR_H_STAT1 0x009b |
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| 49 | #define BCM3520_SH_AP_SFR_H_STAT2 0x009c |
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| 50 | #define BCM3520_SH_AP_SFR_H_STAT3 0x009d |
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| 51 | #define BCM3520_SH_AP_SFR_H_STAT4 0x009e |
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| 52 | #define BCM3520_SH_AP_SFR_H_IE1 0x009f |
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| 53 | #define BCM3520_SH_AP_SFR_H_IE2 0x00a0 |
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| 54 | #define BCM3520_SH_AP_SFR_H_IE3 0x00a1 |
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| 55 | #define BCM3520_SH_AP_SFR_H_IE4 0x00a2 |
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| 56 | #define BCM3520_SH_AP_SFR_H_FSTAT1 0x00a3 |
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| 57 | #define BCM3520_SH_AP_SFR_H_FSTAT2 0x00a4 |
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| 58 | #define BCM3520_SH_AP_SFR_H_FSTAT3 0x00a5 |
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| 59 | #define BCM3520_SH_AP_SFR_H_FSTAT4 0x00a6 |
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| 60 | #define BCM3520_SH_AP_SFR_GPIN_1 0x00a9 |
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| 61 | #define BCM3520_SH_AP_SFR_GPIN_0 0x00aa |
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| 62 | #define BCM3520_SH_AP_SFR_GPOUT_1 0x00ab |
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| 63 | #define BCM3520_SH_AP_SFR_GPOUT_0 0x00ac |
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| 64 | #define BCM3520_SH_AP_SFR_GPIOENB_1 0x00ad |
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| 65 | #define BCM3520_SH_AP_SFR_GPIOENB_0 0x00ae |
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| 66 | #define BCM3520_SH_AP_SFR_GPIO_OW_1 0x00bc |
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| 67 | #define BCM3520_SH_AP_SFR_GPIO_OW_0 0x00bd |
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| 68 | #define BCM3520_SH_AP_SFR_HCTL_DBG 0x00be |
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| 69 | #define BCM3520_SH_AP_SFR_TMUX 0x00c9 |
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| 70 | #define BCM3520_SH_AP_SFR_AP_CMD 0x00e4 |
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| 71 | #define BCM3520_SH_AP_SFR_CP_CFG 0x00ef |
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| 72 | |
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| 73 | /* BSC IO_MBOX registers */ |
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| 74 | #define BCM3520_BSC_CHIP_ADDRESS 0x0800 |
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| 75 | #define BCM3520_BSC_DATA_IN0_3 0x0804 |
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| 76 | #define BCM3520_BSC_DATA_IN4_7 0x0808 |
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| 77 | #define BCM3520_BSC_CNT_REG 0x080C |
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| 78 | #define BCM3520_BSC_CTL_REG 0x0810 |
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| 79 | #define BCM3520_BSC_IIC_ENABLE 0x0814 |
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| 80 | #define BCM3520_BSC_DATA_OUT0_3 0x0818 |
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| 81 | #define BCM3520_BSC_DATA_OUT4_7 0x081C |
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| 82 | #define BCM3520_BSC_IRQEN 0x0820 |
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| 83 | #define BCM3520_BSC_IRQSTS 0x0824 |
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| 84 | |
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| 85 | /* Antenna IO_MBOX registers */ |
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| 86 | #define BCM3520_ANT_CNTL 0x0900 |
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| 87 | #define BCM3520_ANT_TX_CNTL 0x0904 |
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| 88 | #define BCM3520_ANT_TX_LOGIC 0x0908 |
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| 89 | #define BCM3520_ANT_TX_DATA 0x090C |
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| 90 | #define BCM3520_ANT_TX_2_TX_WAIT 0x0910 |
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| 91 | #define BCM3520_ANT_RX_LOGIC1 0x0914 |
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| 92 | #define BCM3520_ANT_RX_LOGIC0 0x0918 |
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| 93 | #define BCM3520_ANT_RX_PERIOD 0x091C |
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| 94 | #define BCM3520_ANT_RX_STATUS 0x0920 |
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| 95 | #define BCM3520_ANT_RX_ST_COND 0x0924 |
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| 96 | #define BCM3520_ANT_IRQSTS 0x0928 |
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| 97 | #define BCM3520_ANT_IRQEN 0x092C |
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| 98 | |
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| 99 | /* TM registers */ |
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| 100 | #define BCM3520_TM_CLK_SEL 0x0000 |
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| 101 | #define BCM3520_TM_SFT_RST 0x0004 |
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| 102 | #define BCM3520_TM_OUTPUT_PAD_CTRL 0x0008 |
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| 103 | #define BCM3520_TM_DS_OB_XPT_PAD_CTRL 0x000C |
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| 104 | #define BCM3520_TM_GPO_AUDIO_PAD_CTRL 0x0010 |
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| 105 | #define BCM3520_TM_DIAG_CTRL 0x0014 |
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| 106 | #define BCM3520_TM_MBIST_CTRL 0x0018 |
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| 107 | #define BCM3520_TM_PWRDN_CTRL 0x001C |
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| 108 | #define BCM3520_TM_PIN_STRAP 0x0020 |
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| 109 | #define BCM3520_TM_PIN_STRAP_OVRD 0x0024 |
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| 110 | #define BCM3520_TM_SCAN_TRI_ISB 0x0028 |
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| 111 | #define BCM3520_TM_SCAN_TRI_RBUS 0x002C |
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| 112 | #define BCM3520_TM_TMODE_CTRL 0x0030 |
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| 113 | #define BCM3520_TM_OSC_CTRL_REG0 0x0034 |
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| 114 | #define BCM3520_TM_OSC_CTRL_REG1 0x0038 |
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| 115 | #define BCM3520_TM_DDAC_CTRL_REG 0x003C |
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| 116 | #define BCM3520_TM_GENPLL_CTRL_REG 0x0040 |
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| 117 | #define BCM3520_TM_CHIP_ID 0x0044 |
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| 118 | #define BCM3520_TM_CHIP_ID_INT 0x0048 |
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| 119 | #define BCM3520_TM_TP_IN_CTRL 0x004C |
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| 120 | #define BCM3520_TM_TP_OUT_REG 0x0050 |
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| 121 | #define BCM3520_TM_DAC_TEST_CTRL 0x0054 |
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| 122 | #define BCM3520_TM_SS_AGC_HSYNC_REG 0x0058 |
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| 123 | #define BCM3520_TM_SPARE_REGISTER_0 0x005C |
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| 124 | #define BCM3520_TM_SPARE_REGISTER_1 0x0060 |
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| 125 | |
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| 126 | /* H_CTL1 register bits */ |
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| 127 | #define BCM3520_AP_RUN 0x00 |
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| 128 | #define BCM3520_AP_RESET 0x01 |
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| 129 | #define BCM3520_AP_IDLE 0x02 |
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| 130 | #define BCM3520_AP_MASK 0x03 |
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| 131 | #define BCM3520_AP_HABR 0x04 |
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| 132 | #define BCM3520_AP_HAB_MASK 0x07 |
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| 133 | #define BCM3520_AP_HAB_AVAILABLE 0x00 |
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| 134 | |
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| 135 | /* JDEC register bits */ |
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| 136 | #define BCM3520_JDEC_EEPROM 0x00 |
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| 137 | #define BCM3520_JDEC_ROM 0x01 |
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| 138 | #define BCM3520_JDEC_RAM 0x02 |
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| 139 | #define BCM3520_JDEC_EXTRAM 0x03 |
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| 140 | |
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| 141 | /* H_STAT1 register bits */ |
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| 142 | #define BCM3520_STAT1_H_ER 0x80 |
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| 143 | #define BCM3520_STAT1_IOMB_ER 0x40 |
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| 144 | #define BCM3520_STAT1_MEM_ER 0x20 |
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| 145 | #define BCM3520_STAT1_H_HAB_ER 0x10 |
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| 146 | #define BCM3520_STAT1_HAB_DONE 0x04 |
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| 147 | #define BCM3520_STAT1_IOMB_DONE 0x02 |
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| 148 | #define BCM3520_STAT1_AP_OP_CHG 0x01 |
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| 149 | #define BCM3520_STAT1_ERROR_MASK 0xF0 |
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| 150 | |
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| 151 | /* H_STAT2 register bits */ |
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| 152 | #define BCM3520_STAT2_INIT_DONE 0x80 |
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| 153 | #define BCM3520_STAT2_RT_LOCK 0x40 |
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| 154 | #define BCM3520_STAT2_IN_LOCK 0x20 |
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| 155 | #define BCM3520_STAT2_OUT_OF_LOCK 0x10 |
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| 156 | #define BCM3520_STAT2_LOCK_MASK 0x30 |
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| 157 | #define BCM3520_STAT2_HAB_ERROR 0x08 |
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| 158 | #define BCM3520_STAT2_CRIT_ERROR 0x04 |
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| 159 | #define BCM3520_STAT2_ANT 0x02 |
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| 160 | #define BCM3520_STAT2_BSC 0x01 |
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| 161 | #define BCM3520_STAT2_ERROR_MASK 0x0C |
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| 162 | |
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| 163 | #define BCM3520_STAT3_ACQ_FINISHED 0x01 |
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| 164 | #define BCM3520_STAT3_ACQ_OOB_FINISHED 0x02 |
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| 165 | #define BCM3520_STAT3_OOB_LOCKED 0x08 |
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| 166 | #define BCM3520_STAT3_OOB_NOT_LOCKED 0x10 |
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| 167 | #define BCM3520_STAT3_OOB_LOCK_MASK 0x18 |
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| 168 | #define BCM3520_STAT3_OOB_RT_LOCK_STATUS 0x20 |
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| 169 | |
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| 170 | |
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| 171 | #endif /* BCHP_3520_H__ */ |
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