source: svn/newcon3bcm2_21bu/magnum/basemodules/chp/7552/bchp_7552.c @ 76

Last change on this file since 76 was 76, checked in by megakiss, 10 years ago

1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
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1/***************************************************************************
2 *     Copyright (c) 2006-2012, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bchp_7552.c $
11 * $brcm_Revision: Hydra_Software_Devel/18 $
12 * $brcm_Date: 3/30/12 6:31p $
13 *
14 * Module Description:
15 *   See Module Overview below.
16 *
17 * Revision History:
18 *
19 * $brcm_Log: /magnum/basemodules/chp/7552/bchp_7552.c $
20 *
21 * Hydra_Software_Devel/18   3/30/12 6:31p xhuang
22 * SW7552-95: support 1GB DDR
23 *
24 * Hydra_Software_Devel/17   1/13/12 1:24p xhuang
25 * SW7552-191: incorrect use of atom setting
26 *
27 * Hydra_Software_Devel/16   12/23/11 5:51p xhuang
28 * SW7552-141: merge to main
29 *
30 * Hydra_Software_Devel/SW7552-141/2   12/6/11 1:35p jianweiz
31 * SW7552-141: workaround chip id for blank chip
32 *
33 * Hydra_Software_Devel/SW7552-141/1   12/6/11 3:45p jianweiz
34 * SW7552-141: Read Family_ID and remove UFE powerup
35 *
36 * Hydra_Software_Devel/15   11/10/11 6:57p xhuang
37 * SW7552-9: Refactored the Magnum core reset logic to address some power
38 * management related issues
39 *
40 * Hydra_Software_Devel/14   11/10/11 5:53p xhuang
41 * SW7552-9: Add AVS support
42 *
43 * Hydra_Software_Devel/13   11/3/11 2:47p xhuang
44 * SW7552-9: fix GISB timeout in PM2.0
45 *
46 * Hydra_Software_Devel/12   10/31/11 11:52a farshidf
47 * CDFEDEMOD-25: merge to main
48 *
49 * Hydra_Software_Devel/SW7552_134/5   10/31/11 11:39a bsandeep
50 * CDFEDEMOD-25: To fix the DVB-C flakiness. Added UFE resets. Without
51 * these resets 1st DS acquire takes 384 ms intsead of 50 ms.
52 *
53 * Hydra_Software_Devel/SW7552_134/4   10/27/11 2:06p xhuang
54 * SW7552-9: Add 7552 power management support
55 *
56 * Hydra_Software_Devel/SW7552_134/3   10/26/11 3:32p farshidf
57 * SW7552-134: remove the UFE settings
58 *
59 * Hydra_Software_Devel/SW7552_134/2   10/24/11 3:29p farshidf
60 * SW7552-134: add the new bchp file for UFE
61 *
62 * Hydra_Software_Devel/SW7552_134/1   10/19/11 4:18p farshidf
63 * SW7552-134: update the UFE power up settings
64 *
65 * Hydra_Software_Devel/10   9/1/11 5:48p jtna
66 * SW7552-115: change name to BCHP_Feature_eRfmCapable
67 *
68 * Hydra_Software_Devel/9   9/1/11 6:18p xhuang
69 * SW7552-115: Add BCHP features for RFM
70 *
71 * Hydra_Software_Devel/8   8/17/11 6:35p xhuang
72 * SW7552-104: fix GISB timeout when set to OTP disabled modules
73 *
74 * Hydra_Software_Devel/7   8/12/11 1:09p xhuang
75 * SW7552-101: Add B0 support
76 *
77 * Hydra_Software_Devel/6   8/1/11 7:29p xhuang
78 * SW7552-75: return success if get feature value
79 *
80 * Hydra_Software_Devel/5   7/27/11 11:55a xhuang
81 * SW7552-75: Merge to mainline
82 *
83 * Hydra_Software_Devel/4   7/18/11 7:31p xhuang
84 * SW7552-59: support runtime set for different 7552 bond out
85 *
86 * Hydra_Software_Devel/3   6/3/11 3:14p xhuang
87 * SW7552-34: enable 324M clk for M2MC
88 *
89 * Hydra_Software_Devel/2   5/31/11 5:19p xhuang
90 * SW7552-34: power up AVD and frontend before interrupt open to avoid
91 * GISB timeout
92 *
93 * Hydra_Software_Devel/1   10/14/10 3:50p xhuang
94 * SW7552-4: Add support for 7552
95 *
96 ***************************************************************************/
97#include "bstd.h"
98#include "bdbg.h"
99#include "bkni.h"
100#include "breg_mem.h"
101#include "bchp.h"
102#include "bchp_priv.h"
103#include "bchp_7552.h"
104#include "bchp_sun_top_ctrl.h"
105#include "bchp_decode_sd_0.h"
106#include "bchp_decode_ip_shim_0.h"
107#include "bchp_sun_gisb_arb.h"
108#include "bchp_memc_ddr23_shim_addr_cntl_0.h"
109#include "bchp_memc_ddr_0.h"
110#include "bchp_ufe_afe.h"
111#include "bchp_sdadc.h"
112#include "bchp_ufe_misc2.h"
113#include "bchp_clkgen.h"
114#include "bchp_ufe.h"
115#include "bchp_pwr.h"
116#include "bchp_avs_ro_registers_0.h"
117#include "bchp_avs.h"
118BDBG_MODULE(BCHP);
119
120/* Miscellaneous macros. */
121#define BCHP_P_MAJOR_REV_SHIFT          (4)
122
123/* Chip info and features */
124typedef struct BCHP_P_7552_Info
125{
126    uint32_t      ulChipIdReg; /* index into the table. */
127
128    /* Chip Id */
129    uint16_t      usChipId;
130
131    /* Major revision */
132    uint16_t      usMajor;
133
134    /* Minor revision */
135    uint16_t      usMinor;
136
137    /* TODO: Other features or infos if needed */
138} BCHP_P_7552_Info;
139
140
141/* Lookup table for chip features and etc.
142 * The are many times when the chip device id register
143 * not conforming to the standard numbering convention. We do
144 * it this way to work-around those problems.
145 *
146 * TODO: Update this table to support new revisions.
147 */
148static const BCHP_P_7552_Info s_aChipInfoTable[] =
149{
150#if BCHP_VER == BCHP_VER_A0
151    /* A0 code will run on A0 */
152   {0x75310000, BCHP_BCM7531, BCHP_MAJOR_A, BCHP_MINOR_0},
153   {0x75320000, BCHP_BCM7532, BCHP_MAJOR_A, BCHP_MINOR_0},
154   {0x75410000, BCHP_BCM7541, BCHP_MAJOR_A, BCHP_MINOR_0},
155   {0x75420000, BCHP_BCM7542, BCHP_MAJOR_A, BCHP_MINOR_0},
156   {0x75510000, BCHP_BCM7551, BCHP_MAJOR_A, BCHP_MINOR_0},
157   {0x75520000, BCHP_BCM7552, BCHP_MAJOR_A, BCHP_MINOR_0},
158   {0x75610000, BCHP_BCM7561, BCHP_MAJOR_A, BCHP_MINOR_0},
159   {0x75620000, BCHP_BCM7562, BCHP_MAJOR_A, BCHP_MINOR_0},
160   {0x75740000, BCHP_BCM7574, BCHP_MAJOR_A, BCHP_MINOR_0},   
161   {0x75810000, BCHP_BCM7581, BCHP_MAJOR_A, BCHP_MINOR_0},
162   {0x75820000, BCHP_BCM7582, BCHP_MAJOR_A, BCHP_MINOR_0},
163   {0x75910000, BCHP_BCM7591, BCHP_MAJOR_A, BCHP_MINOR_0},   
164   {0x75920000, BCHP_BCM7592, BCHP_MAJOR_A, BCHP_MINOR_0},
165#elif BCHP_VER == BCHP_VER_B0   
166   {0x75310010, BCHP_BCM7531, BCHP_MAJOR_B, BCHP_MINOR_0},
167   {0x75320010, BCHP_BCM7532, BCHP_MAJOR_B, BCHP_MINOR_0},
168   {0x75410010, BCHP_BCM7541, BCHP_MAJOR_B, BCHP_MINOR_0},
169   {0x75420010, BCHP_BCM7542, BCHP_MAJOR_B, BCHP_MINOR_0},
170   {0x75510010, BCHP_BCM7551, BCHP_MAJOR_B, BCHP_MINOR_0},
171   {0x75520010, BCHP_BCM7552, BCHP_MAJOR_B, BCHP_MINOR_0},
172   {0x75610010, BCHP_BCM7561, BCHP_MAJOR_B, BCHP_MINOR_0},
173   {0x75620010, BCHP_BCM7562, BCHP_MAJOR_B, BCHP_MINOR_0},
174   {0x75740010, BCHP_BCM7574, BCHP_MAJOR_B, BCHP_MINOR_0},   
175   {0x75810010, BCHP_BCM7581, BCHP_MAJOR_B, BCHP_MINOR_0},
176   {0x75820010, BCHP_BCM7582, BCHP_MAJOR_B, BCHP_MINOR_0},
177   {0x75910010, BCHP_BCM7591, BCHP_MAJOR_B, BCHP_MINOR_0},   
178   {0x75920010, BCHP_BCM7592, BCHP_MAJOR_B, BCHP_MINOR_0},
179#else
180    #error "Port required"
181#endif
182};
183
184static uint16_t s_ulChipID = 0x0;
185
186/* Chip context */
187typedef struct BCHP_P_7552_Context
188{
189    uint32_t                           ulBlackMagic;
190    BREG_Handle                        hRegister;
191    const BCHP_P_7552_Info            *pChipInfo;
192    BCHP_P_AvsHandle                  hAvsHandle;
193} BCHP_P_7552_Context;
194
195/* Max entry of lookup table */
196#define BCHP_P_CHIP_INFO_MAX_ENTRY \
197    (sizeof(s_aChipInfoTable) / sizeof(BCHP_P_7552_Info))
198
199/* This macro checks for a validity of a handle, and
200 * cast to context pointer. */
201#define BCHP_P_GET_CONTEXT(handle, context) \
202{ \
203    if(!(handle) || \
204       !((handle)->chipHandle) || \
205       (((BCHP_P_7552_Context*)((handle)->chipHandle))->ulBlackMagic != \
206       sizeof(BCHP_P_7552_Context))) \
207    { \
208        BDBG_ERR(("Corrupted context handle\n")); \
209        (context) = NULL; \
210    } \
211    else \
212    { \
213        (context) = (BCHP_P_7552_Context*)((handle)->chipHandle); \
214    } \
215    BDBG_ASSERT(context); \
216}
217
218/* Static function prototypes */
219static BERR_Code BCHP_P_Close7552
220    ( BCHP_Handle                      hChip );
221
222static BERR_Code BCHP_P_GetChipInfoComformWithBaseClass
223    ( const BCHP_Handle                hChip,
224      uint16_t                        *pusChipId,
225      uint16_t                        *pusChipRev );
226
227static BERR_Code BCHP_P_GetChipInfo
228    ( const BCHP_Handle                hChip,
229      uint16_t                        *pusChipId,
230      uint16_t                        *pusChipMajorRev,
231      uint16_t                        *pusChipMinorRev );
232
233static BERR_Code BCHP_P_GetFeature
234    ( const BCHP_Handle                hChip,
235      const BCHP_Feature               eFeature,
236      void                            *pFeatureValue );
237
238static BERR_Code BCHP_P_ResetMagnumCores
239    ( const BCHP_Handle                hChip );
240
241static void BCHP_P_MonitorPvt
242    ( BCHP_Handle                      hChip,
243      BCHP_AvsSettings                *pSettings );
244
245static BERR_Code BCHP_P_GetAvsData
246    ( BCHP_Handle                      hChip,
247      BCHP_AvsData                    *pData );
248
249static BERR_Code BCHP_P_StandbyMode
250    ( BCHP_Handle                      hChip,
251      bool                             activate );
252
253/***************************************************************************
254 * Open BCM7552 Chip.
255 *
256 */
257BERR_Code BCHP_Open7552
258    ( BCHP_Handle                     *phChip,
259      BREG_Handle                      hRegister )
260{
261    BCHP_P_Context *pChip;
262    BCHP_P_7552_Context *p7552Chip;
263    uint32_t ulChipIdReg;
264    uint32_t ulIdx;
265    uint32_t ulVal;
266        BERR_Code rc;
267   
268    BDBG_ENTER(BCHP_Open7552);
269
270    if((!phChip) ||
271       (!hRegister))
272    {
273        BDBG_ERR(("Invalid parameter\n"));
274        return BERR_TRACE(BERR_INVALID_PARAMETER);
275    }
276
277    /* If error ocurr user get a NULL *phChip */
278    *phChip = NULL;
279
280    /* Alloc the base chip context. */
281    pChip = (BCHP_P_Context*)(BKNI_Malloc(sizeof(BCHP_P_Context)));
282    if(!pChip)
283    {
284        return BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
285    }
286
287    /* Clear out the context and set defaults. */
288    BKNI_Memset((void*)pChip, 0x0, sizeof(BCHP_P_Context));
289
290    p7552Chip = (BCHP_P_7552_Context*)
291        (BKNI_Malloc(sizeof(BCHP_P_7552_Context)));
292    if(!p7552Chip)
293    {
294        BKNI_Free(pChip);
295        return BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
296    }
297
298    /* Clear out the context and set defaults. */
299    BKNI_Memset((void*)p7552Chip, 0x0, sizeof(BCHP_P_7552_Context));
300
301    /* Fill up the base chip context. */
302    pChip->chipHandle       = (void*)p7552Chip;
303        pChip->regHandle        = hRegister;
304    pChip->pCloseFunc       = BCHP_P_Close7552;
305    pChip->pGetChipInfoFunc = BCHP_P_GetChipInfoComformWithBaseClass;
306    pChip->pGetFeatureFunc  = BCHP_P_GetFeature;
307    pChip->pMonitorPvtFunc  = BCHP_P_MonitorPvt;
308    pChip->pGetAvsDataFunc  = BCHP_P_GetAvsData;
309        pChip->pStandbyModeFunc = BCHP_P_StandbyMode;
310
311    /* Fill up the chip context. */
312    p7552Chip->ulBlackMagic = sizeof(BCHP_P_7552_Context);
313    p7552Chip->hRegister    = hRegister;
314
315    BCHP_P_ResetMagnumCores( pChip );
316        /* Open BCHP_PWR */
317    rc = BCHP_PWR_Open(&pChip->pwrManager, pChip); 
318    if (rc) {
319        BKNI_Free(pChip);
320        BKNI_Free(p7552Chip);
321        return BERR_TRACE(rc);
322    }
323       
324
325    /* Open AVS module */
326    BCHP_P_AvsOpen(&p7552Chip->hAvsHandle, pChip);
327    if(!p7552Chip->hAvsHandle)
328    {
329                /*BCHP_PWR_Close(pChip->pwrManager); <--- Add this when adding PWR_Open */
330        BKNI_Free(pChip);
331        BKNI_Free(p7552Chip);
332        return BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
333    }
334
335    /* Chip Family Register id is use for indexing into the table. */
336    ulChipIdReg = BREG_Read32(hRegister, BCHP_SUN_TOP_CTRL_PRODUCT_ID);
337
338/* decompose 32 bit chip id for use with printf format string %x%c%d
339Example: 0x75520000 becomes "7552A0" */
340#define PRINT_CHIP(CHIPID) \
341    ((CHIPID)>>16), ((((CHIPID)&0xF0)>>4)+'A'), ((CHIPID)&0x0F)
342
343    for(ulIdx = 0; ulIdx < BCHP_P_CHIP_INFO_MAX_ENTRY; ulIdx++)
344    {
345        BDBG_MSG(("Supported Chip Family and revision: %x%c%d", PRINT_CHIP(s_aChipInfoTable[ulIdx].ulChipIdReg)));
346        BDBG_MSG(("Supported Chip ID: %x", s_aChipInfoTable[ulIdx].usChipId));
347        BDBG_MSG(("\n"));
348    }
349
350    /* Lookup corresponding chip id. */
351    for(ulIdx = 0; ulIdx < BCHP_P_CHIP_INFO_MAX_ENTRY; ulIdx++)
352    {
353        const BCHP_P_7552_Info *compareChipInfo = &s_aChipInfoTable[ulIdx];
354
355        if(compareChipInfo->ulChipIdReg == ulChipIdReg)
356        {
357            /* Chip Information. */
358            p7552Chip->pChipInfo = compareChipInfo;
359            break;
360        }
361        else if (ulIdx == BCHP_P_CHIP_INFO_MAX_ENTRY - 1 && compareChipInfo->usMajor == (ulChipIdReg&0xF0)>>4)
362        {
363            /* This is a future minor revision. We will allow it with a WRN. */
364            BDBG_WRN(("An unknown minor revision %x%c%d has been detected. Certain operations may result in erratic behavior. Please confirm this chip revision is supported with this software.",
365                PRINT_CHIP(ulChipIdReg)));
366            p7552Chip->pChipInfo = compareChipInfo;
367            break;
368        }
369    }
370
371    if(!p7552Chip->pChipInfo)
372    {
373        BKNI_Free(p7552Chip);
374        BKNI_Free(pChip);
375        BDBG_ERR(("*****************************************************************\n"));
376        BDBG_ERR(("ERROR ERROR ERROR ERROR \n"));
377        BDBG_ERR(("Unsupported Revision: %x%c%d", PRINT_CHIP(ulChipIdReg)));
378        BDBG_ERR(("*****************************************************************\n"));
379        phChip = NULL;
380        BDBG_ASSERT(phChip);
381        return BERR_TRACE(BERR_INVALID_PARAMETER);
382    }
383    s_ulChipID = p7552Chip->pChipInfo->usChipId;
384    BDBG_MSG(("found %x%c%d", PRINT_CHIP(p7552Chip->pChipInfo->ulChipIdReg)));
385
386    /* All done. now return the new fresh context to user. */
387    *phChip = (BCHP_Handle)pChip;
388
389#if BCHP_PWR_RESOURCE_AVD0
390        BCHP_PWR_AcquireResource(pChip, BCHP_PWR_RESOURCE_AVD0);       
391#endif
392
393#if BCHP_PWR_SUPPORT
394        BCHP_P_ResetMagnumCores( pChip );
395#endif
396
397    /* Clear AVD/SVD shutdown enable bit */
398        BREG_Write32(hRegister, BCHP_DECODE_IP_SHIM_0_SOFTSHUTDOWN_CTRL_REG, 0x0);
399
400    /* TODO: Bring up the clocks */
401    BDBG_MSG(("Hack Hack,programming BCHP_SUN_GISB_ARB_REQ_MASK, this should be done in CFE"));
402    /* This mask controls which clients can be GISB master. */
403
404    ulVal = BREG_Read32(hRegister, BCHP_SUN_GISB_ARB_REQ_MASK);
405    ulVal &= ~( BCHP_MASK(SUN_GISB_ARB_REQ_MASK, avd_0) |
406        BCHP_MASK( SUN_GISB_ARB_REQ_MASK, raaga)|
407            BCHP_MASK(SUN_GISB_ARB_REQ_MASK, rdc) );
408    BREG_Write32(hRegister, BCHP_SUN_GISB_ARB_REQ_MASK, ulVal);
409   
410#if (BCHP_VER == BCHP_VER_A0)
411    /* Power up UFE */
412        ulVal = BREG_Read32 (hRegister, BCHP_UFE_AFE_TNR0_PWRUP_01);
413    ulVal |=  (BCHP_FIELD_DATA(UFE_AFE_TNR0_PWRUP_01, i_pwrup_BIAS, 0x1));
414    BREG_Write32(hRegister, BCHP_UFE_AFE_TNR0_PWRUP_01, ulVal);
415
416    ulVal = BREG_Read32 (hRegister, BCHP_UFE_AFE_TNR0_PWRUP_01);
417    ulVal |=  (BCHP_FIELD_DATA(UFE_AFE_TNR0_PWRUP_01, i_pwrup_SDADC_REG1p0, 0x1));
418    BREG_Write32(hRegister, BCHP_UFE_AFE_TNR0_PWRUP_01, ulVal);
419
420        ulVal = BREG_Read32 (hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02);
421    ulVal |=  (BCHP_FIELD_DATA(UFE_AFE_TNR0_PWRUP_02, PHY_PLL_master_PWRUP, 0x1));
422    BREG_Write32(hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, ulVal);
423
424        ulVal = BREG_Read32 (hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02);
425    ulVal |=  (BCHP_FIELD_DATA(UFE_AFE_TNR0_PWRUP_02, i_pwrup_PHYPLL_ch, 0x20));
426    BREG_Write32(hRegister, BCHP_UFE_AFE_TNR0_PWRUP_02, ulVal);
427
428    BREG_Write32(hRegister, BCHP_UFE_AFE_TNR0_RESET_01, 0xFFFFDFFF);
429
430    BREG_Write32(hRegister, BCHP_UFE_MISC2_CLK_RESET, 0x0);
431
432    BREG_Write32(hRegister, BCHP_SDADC_CTRL_PWRUP, 0x3);
433    BREG_Write32(hRegister, BCHP_SDADC_CTRL_RESET, 0x0);
434       
435
436       
437        BREG_Write32(hRegister, BCHP_UFE_RST, (BREG_Read32(hRegister, BCHP_UFE_RST) | 0xC0000000));
438    BREG_Write32(hRegister, BCHP_UFE_RST, (BREG_Read32(hRegister, BCHP_UFE_RST) & 0x3FFFFFFF));
439#endif
440       
441#if BCHP_PWR_RESOURCE_AVD0     
442        BCHP_PWR_ReleaseResource(pChip, BCHP_PWR_RESOURCE_AVD0);
443#endif
444
445    /* Set M2MC clk to 324M */
446    ulVal = BREG_Read32 (hRegister, BCHP_CLKGEN_INTERNAL_MUX_SELECT);
447    ulVal |=  (BCHP_FIELD_DATA(CLKGEN_INTERNAL_MUX_SELECT, GFX_M2MC_CORE_CLOCK, 0x1));
448    BREG_Write32(hRegister, BCHP_CLKGEN_INTERNAL_MUX_SELECT, ulVal);
449
450    BDBG_LEAVE(BCHP_Open7552);
451    return BERR_SUCCESS;
452}
453
454
455/***************************************************************************
456 * {private}
457 *
458 */
459static BERR_Code BCHP_P_Close7552
460    ( BCHP_Handle                      hChip )
461{
462    BCHP_P_7552_Context *p7552Chip;
463
464    BDBG_ENTER(BCHP_P_Close7552);
465
466    BCHP_P_GET_CONTEXT(hChip, p7552Chip);
467
468    if(!p7552Chip)
469    {
470        return BERR_TRACE(BERR_INVALID_PARAMETER);
471    }
472
473    if (p7552Chip->hAvsHandle) {
474                BCHP_P_AvsClose(p7552Chip->hAvsHandle);
475        p7552Chip->hAvsHandle = NULL;
476        }
477
478        /* Note: PWR_Close goes here (after AvsClose) */
479    BCHP_PWR_Close(hChip->pwrManager);
480
481    /* Invalidate the magic number. */
482    p7552Chip->ulBlackMagic = 0;
483
484    BKNI_Free((void*)p7552Chip);
485    BKNI_Free((void*)hChip);
486
487    BDBG_LEAVE(BCHP_P_Close7552);
488    return BERR_SUCCESS;
489}
490
491
492/***************************************************************************
493 * {private}
494 *
495 */
496static BERR_Code BCHP_P_GetChipInfoComformWithBaseClass
497    ( const BCHP_Handle                hChip,
498      uint16_t                        *pusChipId,
499      uint16_t                        *pusChipRev )
500
501{
502    BERR_Code eStatus;
503    uint16_t usMajor=0;
504    uint16_t usMinor=0;
505
506    eStatus = BERR_TRACE(BCHP_P_GetChipInfo(hChip, pusChipId,
507        &usMajor, &usMinor));
508    if(BERR_SUCCESS != eStatus)
509    {
510        return eStatus;
511    }
512
513    if(pusChipRev)
514    {
515        *pusChipRev = ((usMajor << BCHP_P_MAJOR_REV_SHIFT) + usMinor);
516    }
517
518    return BERR_SUCCESS;
519}
520
521
522/***************************************************************************
523 * {private}
524 *
525 */
526static BERR_Code BCHP_P_GetChipInfo
527    ( const BCHP_Handle                hChip,
528      uint16_t                        *pusChipId,
529      uint16_t                        *pusChipMajorRev,
530      uint16_t                        *pusChipMinorRev )
531{
532    const BCHP_P_7552_Context *p7552Chip;
533
534    BDBG_ENTER(BCHP_P_GetChipInfo);
535
536    BCHP_P_GET_CONTEXT(hChip, p7552Chip);
537
538    if(!p7552Chip)
539    {
540        return BERR_TRACE(BERR_INVALID_PARAMETER);
541    }
542
543    if(pusChipId)
544    {
545        *pusChipId = p7552Chip->pChipInfo->usChipId;
546    }
547
548    if(pusChipMajorRev)
549    {
550        *pusChipMajorRev = p7552Chip->pChipInfo->usMajor;
551    }
552
553    if(pusChipMinorRev)
554    {
555        *pusChipMinorRev = p7552Chip->pChipInfo->usMinor;
556    }
557
558    BDBG_LEAVE(BCHP_P_GetChipInfo);
559    return BERR_SUCCESS;
560}
561
562/***************************************************************************
563 * {private}
564 *
565 */
566static BERR_Code BCHP_P_GetFeature
567    ( const BCHP_Handle                hChip,
568      const BCHP_Feature               eFeature,
569      void                            *pFeatureValue )
570{
571    BERR_Code            rc = BERR_UNKNOWN;
572    BCHP_P_7552_Context *p7552Chip;
573    uint32_t             ulBondStatus;
574    uint32_t             uiReg;
575    uint32_t             ddr_type, ddrDevice;
576    uint32_t             memc_config;
577    uint32_t             avd_freq;
578   
579    BDBG_ENTER(BCHP_P_GetFeature);
580
581    /* get base context */
582    BCHP_P_GET_CONTEXT(hChip, p7552Chip);
583
584    /* read bond-out status common for many features */
585    ulBondStatus = BREG_Read32(p7552Chip->hRegister,
586        BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0);
587
588    /* which feature? */
589    switch (eFeature)
590    {
591    case BCHP_Feature_e3DGraphicsCapable:
592        /* 3D capable? (bool) */
593        *(bool *)pFeatureValue = false;
594        rc = BERR_SUCCESS;
595        break;
596
597    case BCHP_Feature_eDvoPortCapable:
598        /* dvo port capable? (bool) */
599        *(bool *)pFeatureValue = false;
600        rc = BERR_SUCCESS;
601        break;
602
603    case BCHP_Feature_eMacrovisionCapable:
604        /* macrovision capable? (bool) */
605                *(bool *)pFeatureValue = BCHP_GET_FIELD_DATA(ulBondStatus,
606                        SUN_TOP_CTRL_OTP_OPTION_STATUS_0, otp_option_macrovision_disable) ? false : true;
607        rc = BERR_SUCCESS;
608        break;
609
610    case BCHP_Feature_eMpegDecoderCount:
611        /* number of MPEG decoders (int) */
612        *(int *)pFeatureValue = 1;
613        rc = BERR_SUCCESS;
614        break;
615
616    case BCHP_Feature_eHdcpCapable:
617        /* HDCP capable? (bool) */
618        *(bool *)pFeatureValue = BCHP_GET_FIELD_DATA(ulBondStatus,
619            SUN_TOP_CTRL_OTP_OPTION_STATUS_0, otp_option_hdcp_disable ) ? false : true;
620        rc = BERR_SUCCESS;
621        break;
622
623    case BCHP_Feature_e3desCapable:
624        /* 3DES capable? (bool) */
625        *(bool *)pFeatureValue = true;
626        rc = BERR_SUCCESS;
627        break;
628
629    case BCHP_Feature_e1080pCapable:
630        /* 1080p Capable? (bool) */
631        *(bool *)pFeatureValue = true;
632        rc = BERR_SUCCESS;
633        break;
634
635    case BCHP_Feature_eMemCtrl1Capable:
636    {
637        /* 2nd Memory Ctrl present? (bool) */
638        *(bool *)pFeatureValue = false;
639        rc = BERR_SUCCESS;
640        break ;
641    }
642
643    case BCHP_Feature_eMemCtrl0DDR3ModeCapable:
644       /* DDR Mode: 0 (DDR3 parts), 1 (DDR2 parts) */
645       /* This should be DDR3 for 7552 */
646
647       uiReg = BREG_Read32(p7552Chip->hRegister, BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG);
648       ddr_type = BCHP_GET_FIELD_DATA(uiReg, MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG, DDR_MODE);
649
650       if (ddr_type)
651       {
652          *(bool *)pFeatureValue = false;
653       }
654       else
655       {
656          *(bool *)pFeatureValue = true;
657       }
658
659       rc = BERR_SUCCESS;
660       break;
661
662    case BCHP_Feature_eMemCtrl0DDRDeviceTechCount:
663
664       /* Size of memory part in MBits ie: 256, 512, 1024 */
665       /* Device Tech: 0 (256Mbits), 1 (512MBbits), 2 (1Gbit), 3 (2Gbit), 4 (4Gbit), 5 (8Gbit) */
666       uiReg = BREG_Read32(p7552Chip->hRegister, BCHP_MEMC_DDR_0_CNTRLR_CONFIG);
667       ddrDevice = BCHP_GET_FIELD_DATA(uiReg, MEMC_DDR_0_CNTRLR_CONFIG, DEVICE_TECH);
668
669       switch(ddrDevice)
670       {
671          case 0:
672
673             *(int *)pFeatureValue = 256;
674             rc = BERR_SUCCESS;
675             break;
676
677          case 1:
678
679             *(int *)pFeatureValue = 512;
680             rc = BERR_SUCCESS;
681             break;
682
683          case 2:
684
685             *(int *)pFeatureValue = 1024;
686             rc = BERR_SUCCESS;
687             break;
688
689          case 3:
690
691             *(int *)pFeatureValue = 2048;
692             rc = BERR_SUCCESS;
693             break;
694
695          case 4:
696
697             *(int *)pFeatureValue = 4096;
698             rc = BERR_SUCCESS;
699             break;
700          case 5:
701
702             *(int *)pFeatureValue = 8192;
703             rc = BERR_SUCCESS;
704             break;             
705       }
706
707       break;
708
709    case BCHP_Feature_eMemCtrl0DramWidthCount:
710
711       /* DRAM Width: 0 (32 bit), 1 (16 bit) */
712       uiReg = BREG_Read32(p7552Chip->hRegister, BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG);
713       memc_config = BCHP_GET_FIELD_DATA(uiReg, MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG, DRAM_WIDTH);
714
715       if (memc_config == 0)
716       {
717          *(int *)pFeatureValue = 32;
718       }
719       else
720       {
721          *(int *)pFeatureValue = 16;
722       }
723
724       rc = BERR_SUCCESS;
725       break;
726
727    case BCHP_Feature_eMemCtrl1DDR3ModeCapable:    /* True = DDR3 */
728
729       /* Second DDR Mode: Not support in 7552 */
730
731       rc = BERR_TRACE(BERR_NOT_SUPPORTED);
732       break;
733
734    case BCHP_Feature_eMemCtrl1DDRDeviceTechCount:
735
736       /* Device Tech: 0 (256Mbits), 1 (512MBbits), 2 (1Gbit), 3 (2Gbit), 4 (4Gbit) */
737       rc = BERR_TRACE(BERR_NOT_SUPPORTED);
738       break;
739
740    case BCHP_Feature_eMemCtrl1DramWidthCount:
741
742       /* DRAM Width: 0 (32 bit), 1 (16 bit) */
743       rc = BERR_TRACE(BERR_NOT_SUPPORTED);
744       break;
745    case BCHP_Feature_eAVDCoreFreq:
746
747       uiReg = BREG_Read32(p7552Chip->hRegister, BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2);
748       avd_freq = BCHP_GET_FIELD_DATA(uiReg, CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2, MDIV_CH2);
749       if(avd_freq == 0)
750           *(int *)pFeatureValue = 0;
751       else
752           *(int *)pFeatureValue = 3006/avd_freq;
753
754       rc = BERR_SUCCESS;
755       break;
756
757    case BCHP_Feature_eRfmCapable:
758        /* RFM capable? (bool) */
759        if((s_ulChipID == 0x7532) || (s_ulChipID == 0x7542) ||
760            (s_ulChipID == 0x7552) || (s_ulChipID == 0x7562) ||
761            (s_ulChipID == 0x7574) || (s_ulChipID == 0x7582) ||
762            (s_ulChipID == 0x7592))       
763        {
764            *(bool *)pFeatureValue = true;
765        }
766        else
767        {
768            *(bool *)pFeatureValue = false;
769        }
770        rc = BERR_SUCCESS;
771        break;
772       
773    default:
774        rc = BERR_TRACE(BERR_UNKNOWN);
775    }
776
777    /* return result */
778    BDBG_LEAVE(BCHP_P_GetFeature);
779    return rc;
780}
781
782/***************************************************************************
783 * Public function:
784 *  Be called in bint_7552.c since bchp handle can not pass to bint module
785 */
786uint16_t BCHP_GetChipID (void)
787{
788    BDBG_MSG(("BCHP_GetChipID %x", s_ulChipID));
789    BDBG_ASSERT(s_ulChipID);
790    return s_ulChipID;
791}
792
793static BERR_Code BCHP_P_ResetMagnumCores
794    ( const BCHP_Handle                hChip )
795
796{
797        /* Reset some cores. This is needed to avoid L1 interrupts before BXXX_Open can be called per core. */
798    /* Note, SW_INIT set/clear registers don't need read-modify-write. */
799    BREG_Write32(hChip->regHandle, BCHP_SUN_TOP_CTRL_SW_INIT_0_SET,
800           BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_SET, xpt_sw_init, 1 )
801        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_SET, avd0_sw_init, 1 )    /* avd0_sw_init */
802        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_SET, vec_sw_init, 1 )
803        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_SET, aio_sw_init, 1 )
804        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_SET, bvn_sw_init, 1 )
805        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_SET, raaga_sw_init, 1 ));
806
807    /* Now clear the reset. */
808    BREG_Write32(hChip->regHandle, BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR,
809           BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_CLEAR, xpt_sw_init, 1 )
810        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_CLEAR, avd0_sw_init, 1 )    /* avd0_sw_init */
811        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_CLEAR, vec_sw_init, 1 )
812        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_CLEAR, aio_sw_init, 1 )
813        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_CLEAR, bvn_sw_init, 1 )
814        | BCHP_FIELD_DATA( SUN_TOP_CTRL_SW_INIT_0_CLEAR, raaga_sw_init, 1 ));
815       
816    return BERR_SUCCESS;
817}
818
819/* This gets called regularly to handle the AVS processing */
820static void BCHP_P_MonitorPvt( BCHP_Handle hChip, BCHP_AvsSettings *pSettings )
821{
822    BCHP_P_7552_Context *p7552Chip;
823
824    BDBG_ENTER(BCHP_P_MonitorPvt);
825    BSTD_UNUSED(pSettings);
826
827    /* get base context */
828    BCHP_P_GET_CONTEXT(hChip, p7552Chip);
829
830    if (p7552Chip->hAvsHandle)
831        BCHP_P_AvsMonitorPvt(p7552Chip->hAvsHandle);
832
833    BDBG_LEAVE(BCHP_P_MonitorPvt);
834}
835
836/* This provides the current AVS data */
837static BERR_Code BCHP_P_GetAvsData( BCHP_Handle hChip, BCHP_AvsData *pData )
838{
839    BCHP_P_7552_Context *p7552Chip;
840    uint32_t voltage, temperature;
841
842    BDBG_ASSERT(pData);
843
844    BDBG_ENTER(BCHP_GetAVdata);
845
846    /* get base context */
847    BCHP_P_GET_CONTEXT(hChip, p7552Chip);
848
849    voltage = BREG_Read32(p7552Chip->hRegister, BCHP_AVS_RO_REGISTERS_0_PVT_1P10V_0_MNTR_STATUS);
850    voltage = BCHP_GET_FIELD_DATA(voltage, AVS_RO_REGISTERS_0_PVT_1P10V_0_MNTR_STATUS, data);
851    pData->voltage = (990 * voltage * 8) / (7*1024);
852
853    temperature = BREG_Read32(p7552Chip->hRegister, BCHP_AVS_RO_REGISTERS_0_PVT_TEMPERATURE_MNTR_STATUS);
854    temperature = BCHP_GET_FIELD_DATA(temperature, AVS_RO_REGISTERS_0_PVT_TEMPERATURE_MNTR_STATUS, data);
855    pData->temperature = 418000 - (556 * temperature);
856
857    BDBG_LEAVE(BCHP_GetAVdata);
858    return BERR_SUCCESS;
859}
860
861static BERR_Code BCHP_P_StandbyMode( BCHP_Handle hChip, bool activate )
862{
863    BCHP_P_7552_Context *p7552Chip;
864
865    BDBG_ENTER(BCHP_P_StandbyMode);
866
867    /* get base context */
868    BCHP_P_GET_CONTEXT(hChip, p7552Chip);
869
870        /* Do anything required for CHP Standby changes */
871
872    if (p7552Chip->hAvsHandle)
873        BCHP_P_AvsStandbyMode(p7552Chip->hAvsHandle, activate);
874
875    BDBG_LEAVE(BCHP_P_StandbyMode);
876    return BERR_SUCCESS;
877}
878
879/* End of File */
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