| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2011, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_bscd.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/2 $ |
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| 13 | * $brcm_Date: 5/17/11 11:27p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Mon May 16 20:56:33 2011 |
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| 23 | * MD5 Checksum f5f09b2bf7ad40890d2e5dc57d4789b6 |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/a0/bchp_bscd.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/2 5/17/11 11:27p xhuang |
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| 36 | * SW7552-2: update with central RDB |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_BSCD_H__ |
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| 41 | #define BCHP_BSCD_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *BSCD - Broadcom Serial Control Master D |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_BSCD_CHIP_ADDRESS 0x00408980 /* BSC Chip Address And Read/Write Control */ |
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| 47 | #define BCHP_BSCD_DATA_IN0 0x00408984 /* BSC Write Data Register 0 */ |
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| 48 | #define BCHP_BSCD_DATA_IN1 0x00408988 /* BSC Write Data Register 1 */ |
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| 49 | #define BCHP_BSCD_DATA_IN2 0x0040898c /* BSC Write Data Register 2 */ |
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| 50 | #define BCHP_BSCD_DATA_IN3 0x00408990 /* BSC Write Data Register 3 */ |
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| 51 | #define BCHP_BSCD_DATA_IN4 0x00408994 /* BSC Write Data Register 4 */ |
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| 52 | #define BCHP_BSCD_DATA_IN5 0x00408998 /* BSC Write Data Register 5 */ |
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| 53 | #define BCHP_BSCD_DATA_IN6 0x0040899c /* BSC Write Data Register 6 */ |
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| 54 | #define BCHP_BSCD_DATA_IN7 0x004089a0 /* BSC Write Data Register 7 */ |
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| 55 | #define BCHP_BSCD_CNT_REG 0x004089a4 /* BSC Transfer Count Register */ |
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| 56 | #define BCHP_BSCD_CTL_REG 0x004089a8 /* BSC Control Register */ |
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| 57 | #define BCHP_BSCD_IIC_ENABLE 0x004089ac /* BSC Read/Write Enable And Interrupt */ |
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| 58 | #define BCHP_BSCD_DATA_OUT0 0x004089b0 /* BSC Read Data Register 0 */ |
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| 59 | #define BCHP_BSCD_DATA_OUT1 0x004089b4 /* BSC Read Data Register 1 */ |
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| 60 | #define BCHP_BSCD_DATA_OUT2 0x004089b8 /* BSC Read Data Register 2 */ |
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| 61 | #define BCHP_BSCD_DATA_OUT3 0x004089bc /* BSC Read Data Register 3 */ |
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| 62 | #define BCHP_BSCD_DATA_OUT4 0x004089c0 /* BSC Read Data Register 4 */ |
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| 63 | #define BCHP_BSCD_DATA_OUT5 0x004089c4 /* BSC Read Data Register 5 */ |
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| 64 | #define BCHP_BSCD_DATA_OUT6 0x004089c8 /* BSC Read Data Register 6 */ |
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| 65 | #define BCHP_BSCD_DATA_OUT7 0x004089cc /* BSC Read Data Register 7 */ |
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| 66 | #define BCHP_BSCD_CTLHI_REG 0x004089d0 /* BSC Control Register */ |
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| 67 | #define BCHP_BSCD_SCL_PARAM 0x004089d4 /* BSC SCL Parameter Register */ |
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| 68 | |
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| 69 | /*************************************************************************** |
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| 70 | *CHIP_ADDRESS - BSC Chip Address And Read/Write Control |
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| 71 | ***************************************************************************/ |
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| 72 | /* BSCD :: CHIP_ADDRESS :: reserved0 [31:08] */ |
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| 73 | #define BCHP_BSCD_CHIP_ADDRESS_reserved0_MASK 0xffffff00 |
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| 74 | #define BCHP_BSCD_CHIP_ADDRESS_reserved0_SHIFT 8 |
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| 75 | |
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| 76 | /* BSCD :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ |
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| 77 | #define BCHP_BSCD_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe |
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| 78 | #define BCHP_BSCD_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 |
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| 79 | #define BCHP_BSCD_CHIP_ADDRESS_CHIP_ADDRESS_DEFAULT 0 |
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| 80 | |
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| 81 | /* BSCD :: CHIP_ADDRESS :: SPARE [00:00] */ |
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| 82 | #define BCHP_BSCD_CHIP_ADDRESS_SPARE_MASK 0x00000001 |
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| 83 | #define BCHP_BSCD_CHIP_ADDRESS_SPARE_SHIFT 0 |
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| 84 | #define BCHP_BSCD_CHIP_ADDRESS_SPARE_DEFAULT 0 |
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| 85 | |
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| 86 | /*************************************************************************** |
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| 87 | *DATA_IN0 - BSC Write Data Register 0 |
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| 88 | ***************************************************************************/ |
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| 89 | /* BSCD :: DATA_IN0 :: DATA_IN0 [31:00] */ |
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| 90 | #define BCHP_BSCD_DATA_IN0_DATA_IN0_MASK 0xffffffff |
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| 91 | #define BCHP_BSCD_DATA_IN0_DATA_IN0_SHIFT 0 |
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| 92 | |
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| 93 | /*************************************************************************** |
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| 94 | *DATA_IN1 - BSC Write Data Register 1 |
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| 95 | ***************************************************************************/ |
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| 96 | /* BSCD :: DATA_IN1 :: DATA_IN1 [31:00] */ |
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| 97 | #define BCHP_BSCD_DATA_IN1_DATA_IN1_MASK 0xffffffff |
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| 98 | #define BCHP_BSCD_DATA_IN1_DATA_IN1_SHIFT 0 |
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| 99 | |
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| 100 | /*************************************************************************** |
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| 101 | *DATA_IN2 - BSC Write Data Register 2 |
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| 102 | ***************************************************************************/ |
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| 103 | /* BSCD :: DATA_IN2 :: DATA_IN2 [31:00] */ |
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| 104 | #define BCHP_BSCD_DATA_IN2_DATA_IN2_MASK 0xffffffff |
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| 105 | #define BCHP_BSCD_DATA_IN2_DATA_IN2_SHIFT 0 |
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| 106 | |
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| 107 | /*************************************************************************** |
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| 108 | *DATA_IN3 - BSC Write Data Register 3 |
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| 109 | ***************************************************************************/ |
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| 110 | /* BSCD :: DATA_IN3 :: DATA_IN3 [31:00] */ |
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| 111 | #define BCHP_BSCD_DATA_IN3_DATA_IN3_MASK 0xffffffff |
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| 112 | #define BCHP_BSCD_DATA_IN3_DATA_IN3_SHIFT 0 |
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| 113 | |
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| 114 | /*************************************************************************** |
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| 115 | *DATA_IN4 - BSC Write Data Register 4 |
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| 116 | ***************************************************************************/ |
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| 117 | /* BSCD :: DATA_IN4 :: DATA_IN4 [31:00] */ |
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| 118 | #define BCHP_BSCD_DATA_IN4_DATA_IN4_MASK 0xffffffff |
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| 119 | #define BCHP_BSCD_DATA_IN4_DATA_IN4_SHIFT 0 |
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| 120 | |
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| 121 | /*************************************************************************** |
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| 122 | *DATA_IN5 - BSC Write Data Register 5 |
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| 123 | ***************************************************************************/ |
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| 124 | /* BSCD :: DATA_IN5 :: DATA_IN5 [31:00] */ |
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| 125 | #define BCHP_BSCD_DATA_IN5_DATA_IN5_MASK 0xffffffff |
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| 126 | #define BCHP_BSCD_DATA_IN5_DATA_IN5_SHIFT 0 |
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| 127 | |
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| 128 | /*************************************************************************** |
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| 129 | *DATA_IN6 - BSC Write Data Register 6 |
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| 130 | ***************************************************************************/ |
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| 131 | /* BSCD :: DATA_IN6 :: DATA_IN6 [31:00] */ |
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| 132 | #define BCHP_BSCD_DATA_IN6_DATA_IN6_MASK 0xffffffff |
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| 133 | #define BCHP_BSCD_DATA_IN6_DATA_IN6_SHIFT 0 |
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| 134 | |
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| 135 | /*************************************************************************** |
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| 136 | *DATA_IN7 - BSC Write Data Register 7 |
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| 137 | ***************************************************************************/ |
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| 138 | /* BSCD :: DATA_IN7 :: DATA_IN7 [31:00] */ |
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| 139 | #define BCHP_BSCD_DATA_IN7_DATA_IN7_MASK 0xffffffff |
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| 140 | #define BCHP_BSCD_DATA_IN7_DATA_IN7_SHIFT 0 |
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| 141 | |
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| 142 | /*************************************************************************** |
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| 143 | *CNT_REG - BSC Transfer Count Register |
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| 144 | ***************************************************************************/ |
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| 145 | /* BSCD :: CNT_REG :: reserved0 [31:12] */ |
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| 146 | #define BCHP_BSCD_CNT_REG_reserved0_MASK 0xfffff000 |
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| 147 | #define BCHP_BSCD_CNT_REG_reserved0_SHIFT 12 |
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| 148 | |
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| 149 | /* BSCD :: CNT_REG :: CNT_REG2 [11:06] */ |
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| 150 | #define BCHP_BSCD_CNT_REG_CNT_REG2_MASK 0x00000fc0 |
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| 151 | #define BCHP_BSCD_CNT_REG_CNT_REG2_SHIFT 6 |
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| 152 | #define BCHP_BSCD_CNT_REG_CNT_REG2_DEFAULT 0 |
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| 153 | |
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| 154 | /* BSCD :: CNT_REG :: CNT_REG1 [05:00] */ |
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| 155 | #define BCHP_BSCD_CNT_REG_CNT_REG1_MASK 0x0000003f |
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| 156 | #define BCHP_BSCD_CNT_REG_CNT_REG1_SHIFT 0 |
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| 157 | #define BCHP_BSCD_CNT_REG_CNT_REG1_DEFAULT 0 |
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| 158 | |
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| 159 | /*************************************************************************** |
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| 160 | *CTL_REG - BSC Control Register |
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| 161 | ***************************************************************************/ |
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| 162 | /* BSCD :: CTL_REG :: reserved0 [31:11] */ |
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| 163 | #define BCHP_BSCD_CTL_REG_reserved0_MASK 0xfffff800 |
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| 164 | #define BCHP_BSCD_CTL_REG_reserved0_SHIFT 11 |
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| 165 | |
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| 166 | /* BSCD :: CTL_REG :: SDA_DELAY_SEL [10:08] */ |
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| 167 | #define BCHP_BSCD_CTL_REG_SDA_DELAY_SEL_MASK 0x00000700 |
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| 168 | #define BCHP_BSCD_CTL_REG_SDA_DELAY_SEL_SHIFT 8 |
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| 169 | #define BCHP_BSCD_CTL_REG_SDA_DELAY_SEL_DEFAULT 0 |
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| 170 | |
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| 171 | /* BSCD :: CTL_REG :: DIV_CLK [07:07] */ |
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| 172 | #define BCHP_BSCD_CTL_REG_DIV_CLK_MASK 0x00000080 |
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| 173 | #define BCHP_BSCD_CTL_REG_DIV_CLK_SHIFT 7 |
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| 174 | #define BCHP_BSCD_CTL_REG_DIV_CLK_DEFAULT 0 |
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| 175 | |
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| 176 | /* BSCD :: CTL_REG :: INT_EN [06:06] */ |
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| 177 | #define BCHP_BSCD_CTL_REG_INT_EN_MASK 0x00000040 |
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| 178 | #define BCHP_BSCD_CTL_REG_INT_EN_SHIFT 6 |
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| 179 | #define BCHP_BSCD_CTL_REG_INT_EN_DEFAULT 0 |
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| 180 | |
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| 181 | /* BSCD :: CTL_REG :: SCL_SEL [05:04] */ |
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| 182 | #define BCHP_BSCD_CTL_REG_SCL_SEL_MASK 0x00000030 |
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| 183 | #define BCHP_BSCD_CTL_REG_SCL_SEL_SHIFT 4 |
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| 184 | #define BCHP_BSCD_CTL_REG_SCL_SEL_DEFAULT 0 |
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| 185 | |
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| 186 | /* BSCD :: CTL_REG :: DELAY_DIS [03:03] */ |
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| 187 | #define BCHP_BSCD_CTL_REG_DELAY_DIS_MASK 0x00000008 |
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| 188 | #define BCHP_BSCD_CTL_REG_DELAY_DIS_SHIFT 3 |
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| 189 | #define BCHP_BSCD_CTL_REG_DELAY_DIS_DEFAULT 0 |
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| 190 | |
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| 191 | /* BSCD :: CTL_REG :: DEGLITCH_DIS [02:02] */ |
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| 192 | #define BCHP_BSCD_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 |
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| 193 | #define BCHP_BSCD_CTL_REG_DEGLITCH_DIS_SHIFT 2 |
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| 194 | #define BCHP_BSCD_CTL_REG_DEGLITCH_DIS_DEFAULT 0 |
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| 195 | |
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| 196 | /* BSCD :: CTL_REG :: DTF [01:00] */ |
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| 197 | #define BCHP_BSCD_CTL_REG_DTF_MASK 0x00000003 |
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| 198 | #define BCHP_BSCD_CTL_REG_DTF_SHIFT 0 |
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| 199 | #define BCHP_BSCD_CTL_REG_DTF_DEFAULT 0 |
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| 200 | |
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| 201 | /*************************************************************************** |
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| 202 | *IIC_ENABLE - BSC Read/Write Enable And Interrupt |
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| 203 | ***************************************************************************/ |
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| 204 | /* BSCD :: IIC_ENABLE :: reserved0 [31:07] */ |
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| 205 | #define BCHP_BSCD_IIC_ENABLE_reserved0_MASK 0xffffff80 |
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| 206 | #define BCHP_BSCD_IIC_ENABLE_reserved0_SHIFT 7 |
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| 207 | |
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| 208 | /* BSCD :: IIC_ENABLE :: RESTART [06:06] */ |
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| 209 | #define BCHP_BSCD_IIC_ENABLE_RESTART_MASK 0x00000040 |
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| 210 | #define BCHP_BSCD_IIC_ENABLE_RESTART_SHIFT 6 |
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| 211 | #define BCHP_BSCD_IIC_ENABLE_RESTART_DEFAULT 0 |
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| 212 | |
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| 213 | /* BSCD :: IIC_ENABLE :: NO_START [05:05] */ |
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| 214 | #define BCHP_BSCD_IIC_ENABLE_NO_START_MASK 0x00000020 |
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| 215 | #define BCHP_BSCD_IIC_ENABLE_NO_START_SHIFT 5 |
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| 216 | #define BCHP_BSCD_IIC_ENABLE_NO_START_DEFAULT 0 |
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| 217 | |
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| 218 | /* BSCD :: IIC_ENABLE :: NO_STOP [04:04] */ |
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| 219 | #define BCHP_BSCD_IIC_ENABLE_NO_STOP_MASK 0x00000010 |
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| 220 | #define BCHP_BSCD_IIC_ENABLE_NO_STOP_SHIFT 4 |
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| 221 | #define BCHP_BSCD_IIC_ENABLE_NO_STOP_DEFAULT 0 |
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| 222 | |
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| 223 | /* BSCD :: IIC_ENABLE :: reserved1 [03:03] */ |
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| 224 | #define BCHP_BSCD_IIC_ENABLE_reserved1_MASK 0x00000008 |
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| 225 | #define BCHP_BSCD_IIC_ENABLE_reserved1_SHIFT 3 |
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| 226 | |
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| 227 | /* BSCD :: IIC_ENABLE :: NO_ACK [02:02] */ |
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| 228 | #define BCHP_BSCD_IIC_ENABLE_NO_ACK_MASK 0x00000004 |
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| 229 | #define BCHP_BSCD_IIC_ENABLE_NO_ACK_SHIFT 2 |
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| 230 | #define BCHP_BSCD_IIC_ENABLE_NO_ACK_DEFAULT 0 |
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| 231 | |
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| 232 | /* BSCD :: IIC_ENABLE :: INTRP [01:01] */ |
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| 233 | #define BCHP_BSCD_IIC_ENABLE_INTRP_MASK 0x00000002 |
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| 234 | #define BCHP_BSCD_IIC_ENABLE_INTRP_SHIFT 1 |
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| 235 | #define BCHP_BSCD_IIC_ENABLE_INTRP_DEFAULT 0 |
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| 236 | |
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| 237 | /* BSCD :: IIC_ENABLE :: ENABLE [00:00] */ |
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| 238 | #define BCHP_BSCD_IIC_ENABLE_ENABLE_MASK 0x00000001 |
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| 239 | #define BCHP_BSCD_IIC_ENABLE_ENABLE_SHIFT 0 |
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| 240 | #define BCHP_BSCD_IIC_ENABLE_ENABLE_DEFAULT 0 |
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| 241 | |
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| 242 | /*************************************************************************** |
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| 243 | *DATA_OUT0 - BSC Read Data Register 0 |
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| 244 | ***************************************************************************/ |
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| 245 | /* BSCD :: DATA_OUT0 :: DATA_OUT0 [31:00] */ |
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| 246 | #define BCHP_BSCD_DATA_OUT0_DATA_OUT0_MASK 0xffffffff |
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| 247 | #define BCHP_BSCD_DATA_OUT0_DATA_OUT0_SHIFT 0 |
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| 248 | |
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| 249 | /*************************************************************************** |
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| 250 | *DATA_OUT1 - BSC Read Data Register 1 |
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| 251 | ***************************************************************************/ |
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| 252 | /* BSCD :: DATA_OUT1 :: DATA_OUT1 [31:00] */ |
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| 253 | #define BCHP_BSCD_DATA_OUT1_DATA_OUT1_MASK 0xffffffff |
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| 254 | #define BCHP_BSCD_DATA_OUT1_DATA_OUT1_SHIFT 0 |
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| 255 | |
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| 256 | /*************************************************************************** |
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| 257 | *DATA_OUT2 - BSC Read Data Register 2 |
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| 258 | ***************************************************************************/ |
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| 259 | /* BSCD :: DATA_OUT2 :: DATA_OUT2 [31:00] */ |
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| 260 | #define BCHP_BSCD_DATA_OUT2_DATA_OUT2_MASK 0xffffffff |
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| 261 | #define BCHP_BSCD_DATA_OUT2_DATA_OUT2_SHIFT 0 |
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| 262 | |
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| 263 | /*************************************************************************** |
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| 264 | *DATA_OUT3 - BSC Read Data Register 3 |
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| 265 | ***************************************************************************/ |
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| 266 | /* BSCD :: DATA_OUT3 :: DATA_OUT3 [31:00] */ |
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| 267 | #define BCHP_BSCD_DATA_OUT3_DATA_OUT3_MASK 0xffffffff |
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| 268 | #define BCHP_BSCD_DATA_OUT3_DATA_OUT3_SHIFT 0 |
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| 269 | |
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| 270 | /*************************************************************************** |
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| 271 | *DATA_OUT4 - BSC Read Data Register 4 |
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| 272 | ***************************************************************************/ |
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| 273 | /* BSCD :: DATA_OUT4 :: DATA_OUT4 [31:00] */ |
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| 274 | #define BCHP_BSCD_DATA_OUT4_DATA_OUT4_MASK 0xffffffff |
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| 275 | #define BCHP_BSCD_DATA_OUT4_DATA_OUT4_SHIFT 0 |
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| 276 | |
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| 277 | /*************************************************************************** |
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| 278 | *DATA_OUT5 - BSC Read Data Register 5 |
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| 279 | ***************************************************************************/ |
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| 280 | /* BSCD :: DATA_OUT5 :: DATA_OUT5 [31:00] */ |
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| 281 | #define BCHP_BSCD_DATA_OUT5_DATA_OUT5_MASK 0xffffffff |
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| 282 | #define BCHP_BSCD_DATA_OUT5_DATA_OUT5_SHIFT 0 |
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| 283 | |
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| 284 | /*************************************************************************** |
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| 285 | *DATA_OUT6 - BSC Read Data Register 6 |
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| 286 | ***************************************************************************/ |
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| 287 | /* BSCD :: DATA_OUT6 :: DATA_OUT6 [31:00] */ |
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| 288 | #define BCHP_BSCD_DATA_OUT6_DATA_OUT6_MASK 0xffffffff |
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| 289 | #define BCHP_BSCD_DATA_OUT6_DATA_OUT6_SHIFT 0 |
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| 290 | |
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| 291 | /*************************************************************************** |
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| 292 | *DATA_OUT7 - BSC Read Data Register 7 |
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| 293 | ***************************************************************************/ |
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| 294 | /* BSCD :: DATA_OUT7 :: DATA_OUT7 [31:00] */ |
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| 295 | #define BCHP_BSCD_DATA_OUT7_DATA_OUT7_MASK 0xffffffff |
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| 296 | #define BCHP_BSCD_DATA_OUT7_DATA_OUT7_SHIFT 0 |
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| 297 | |
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| 298 | /*************************************************************************** |
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| 299 | *CTLHI_REG - BSC Control Register |
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| 300 | ***************************************************************************/ |
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| 301 | /* BSCD :: CTLHI_REG :: reserved0 [31:08] */ |
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| 302 | #define BCHP_BSCD_CTLHI_REG_reserved0_MASK 0xffffff00 |
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| 303 | #define BCHP_BSCD_CTLHI_REG_reserved0_SHIFT 8 |
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| 304 | |
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| 305 | /* BSCD :: CTLHI_REG :: INPUT_SWITCHING_LEVEL [07:07] */ |
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| 306 | #define BCHP_BSCD_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080 |
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| 307 | #define BCHP_BSCD_CTLHI_REG_INPUT_SWITCHING_LEVEL_SHIFT 7 |
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| 308 | #define BCHP_BSCD_CTLHI_REG_INPUT_SWITCHING_LEVEL_DEFAULT 0 |
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| 309 | |
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| 310 | /* BSCD :: CTLHI_REG :: DATA_REG_SIZE [06:06] */ |
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| 311 | #define BCHP_BSCD_CTLHI_REG_DATA_REG_SIZE_MASK 0x00000040 |
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| 312 | #define BCHP_BSCD_CTLHI_REG_DATA_REG_SIZE_SHIFT 6 |
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| 313 | #define BCHP_BSCD_CTLHI_REG_DATA_REG_SIZE_DEFAULT 0 |
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| 314 | |
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| 315 | /* BSCD :: CTLHI_REG :: reserved1 [05:02] */ |
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| 316 | #define BCHP_BSCD_CTLHI_REG_reserved1_MASK 0x0000003c |
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| 317 | #define BCHP_BSCD_CTLHI_REG_reserved1_SHIFT 2 |
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| 318 | |
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| 319 | /* BSCD :: CTLHI_REG :: IGNORE_ACK [01:01] */ |
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| 320 | #define BCHP_BSCD_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 |
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| 321 | #define BCHP_BSCD_CTLHI_REG_IGNORE_ACK_SHIFT 1 |
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| 322 | #define BCHP_BSCD_CTLHI_REG_IGNORE_ACK_DEFAULT 0 |
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| 323 | |
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| 324 | /* BSCD :: CTLHI_REG :: WAIT_DIS [00:00] */ |
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| 325 | #define BCHP_BSCD_CTLHI_REG_WAIT_DIS_MASK 0x00000001 |
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| 326 | #define BCHP_BSCD_CTLHI_REG_WAIT_DIS_SHIFT 0 |
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| 327 | #define BCHP_BSCD_CTLHI_REG_WAIT_DIS_DEFAULT 0 |
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| 328 | |
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| 329 | /*************************************************************************** |
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| 330 | *SCL_PARAM - BSC SCL Parameter Register |
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| 331 | ***************************************************************************/ |
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| 332 | /* BSCD :: SCL_PARAM :: reserved_for_eco0 [31:00] */ |
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| 333 | #define BCHP_BSCD_SCL_PARAM_reserved_for_eco0_MASK 0xffffffff |
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| 334 | #define BCHP_BSCD_SCL_PARAM_reserved_for_eco0_SHIFT 0 |
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| 335 | #define BCHP_BSCD_SCL_PARAM_reserved_for_eco0_DEFAULT 0 |
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| 336 | |
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| 337 | #endif /* #ifndef BCHP_BSCD_H__ */ |
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| 338 | |
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| 339 | /* End of File */ |
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