| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_bmisc.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/2 $ |
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| 13 | * $brcm_Date: 2/7/12 1:19p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Tue Feb 7 10:59:54 2012 |
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| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_bmisc.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/2 2/7/12 1:19p pntruong |
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| 36 | * SW7552-89: Synced up with central rdb. |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_BMISC_H__ |
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| 41 | #define BCHP_BMISC_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *BMISC - BVN Back Control Registers |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_BMISC_SW_INIT 0x00646400 /* BVN Back Soft Init */ |
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| 47 | #define BCHP_BMISC_TEST_PORT_SEL 0x00646404 /* BVN Back Test Port Select */ |
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| 48 | #define BCHP_BMISC_TEST_PORT_DATA 0x00646408 /* BVN Back Test Port Status */ |
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| 49 | #define BCHP_BMISC_BVNB_CLOCK_CTRL 0x00646418 /* BVN Back clock control register */ |
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| 50 | #define BCHP_BMISC_SCRATCH_0 0x0064641c /* Scratch Register */ |
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| 51 | |
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| 52 | /*************************************************************************** |
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| 53 | *SW_INIT - BVN Back Soft Init |
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| 54 | ***************************************************************************/ |
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| 55 | /* BMISC :: SW_INIT :: reserved0 [31:18] */ |
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| 56 | #define BCHP_BMISC_SW_INIT_reserved0_MASK 0xfffc0000 |
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| 57 | #define BCHP_BMISC_SW_INIT_reserved0_SHIFT 18 |
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| 58 | |
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| 59 | /* BMISC :: SW_INIT :: GFD_1 [17:17] */ |
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| 60 | #define BCHP_BMISC_SW_INIT_GFD_1_MASK 0x00020000 |
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| 61 | #define BCHP_BMISC_SW_INIT_GFD_1_SHIFT 17 |
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| 62 | #define BCHP_BMISC_SW_INIT_GFD_1_DEFAULT 0x00000000 |
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| 63 | |
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| 64 | /* BMISC :: SW_INIT :: GFD_0 [16:16] */ |
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| 65 | #define BCHP_BMISC_SW_INIT_GFD_0_MASK 0x00010000 |
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| 66 | #define BCHP_BMISC_SW_INIT_GFD_0_SHIFT 16 |
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| 67 | #define BCHP_BMISC_SW_INIT_GFD_0_DEFAULT 0x00000000 |
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| 68 | |
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| 69 | /* BMISC :: SW_INIT :: reserved1 [15:10] */ |
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| 70 | #define BCHP_BMISC_SW_INIT_reserved1_MASK 0x0000fc00 |
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| 71 | #define BCHP_BMISC_SW_INIT_reserved1_SHIFT 10 |
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| 72 | |
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| 73 | /* BMISC :: SW_INIT :: CMP_1 [09:09] */ |
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| 74 | #define BCHP_BMISC_SW_INIT_CMP_1_MASK 0x00000200 |
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| 75 | #define BCHP_BMISC_SW_INIT_CMP_1_SHIFT 9 |
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| 76 | #define BCHP_BMISC_SW_INIT_CMP_1_DEFAULT 0x00000000 |
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| 77 | |
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| 78 | /* BMISC :: SW_INIT :: CMP_0 [08:08] */ |
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| 79 | #define BCHP_BMISC_SW_INIT_CMP_0_MASK 0x00000100 |
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| 80 | #define BCHP_BMISC_SW_INIT_CMP_0_SHIFT 8 |
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| 81 | #define BCHP_BMISC_SW_INIT_CMP_0_DEFAULT 0x00000000 |
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| 82 | |
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| 83 | /* BMISC :: SW_INIT :: reserved2 [07:05] */ |
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| 84 | #define BCHP_BMISC_SW_INIT_reserved2_MASK 0x000000e0 |
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| 85 | #define BCHP_BMISC_SW_INIT_reserved2_SHIFT 5 |
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| 86 | |
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| 87 | /* BMISC :: SW_INIT :: CAP_SCB0_BUF [04:04] */ |
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| 88 | #define BCHP_BMISC_SW_INIT_CAP_SCB0_BUF_MASK 0x00000010 |
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| 89 | #define BCHP_BMISC_SW_INIT_CAP_SCB0_BUF_SHIFT 4 |
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| 90 | #define BCHP_BMISC_SW_INIT_CAP_SCB0_BUF_DEFAULT 0x00000000 |
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| 91 | |
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| 92 | /* BMISC :: SW_INIT :: reserved3 [03:02] */ |
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| 93 | #define BCHP_BMISC_SW_INIT_reserved3_MASK 0x0000000c |
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| 94 | #define BCHP_BMISC_SW_INIT_reserved3_SHIFT 2 |
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| 95 | |
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| 96 | /* BMISC :: SW_INIT :: CAP_1 [01:01] */ |
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| 97 | #define BCHP_BMISC_SW_INIT_CAP_1_MASK 0x00000002 |
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| 98 | #define BCHP_BMISC_SW_INIT_CAP_1_SHIFT 1 |
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| 99 | #define BCHP_BMISC_SW_INIT_CAP_1_DEFAULT 0x00000000 |
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| 100 | |
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| 101 | /* BMISC :: SW_INIT :: CAP_0 [00:00] */ |
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| 102 | #define BCHP_BMISC_SW_INIT_CAP_0_MASK 0x00000001 |
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| 103 | #define BCHP_BMISC_SW_INIT_CAP_0_SHIFT 0 |
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| 104 | #define BCHP_BMISC_SW_INIT_CAP_0_DEFAULT 0x00000000 |
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| 105 | |
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| 106 | /*************************************************************************** |
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| 107 | *TEST_PORT_SEL - BVN Back Test Port Select |
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| 108 | ***************************************************************************/ |
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| 109 | /* BMISC :: TEST_PORT_SEL :: reserved0 [31:03] */ |
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| 110 | #define BCHP_BMISC_TEST_PORT_SEL_reserved0_MASK 0xfffffff8 |
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| 111 | #define BCHP_BMISC_TEST_PORT_SEL_reserved0_SHIFT 3 |
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| 112 | |
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| 113 | /* BMISC :: TEST_PORT_SEL :: BVNE_TP_OUT_SEL [02:02] */ |
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| 114 | #define BCHP_BMISC_TEST_PORT_SEL_BVNE_TP_OUT_SEL_MASK 0x00000004 |
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| 115 | #define BCHP_BMISC_TEST_PORT_SEL_BVNE_TP_OUT_SEL_SHIFT 2 |
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| 116 | #define BCHP_BMISC_TEST_PORT_SEL_BVNE_TP_OUT_SEL_DEFAULT 0x00000000 |
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| 117 | |
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| 118 | /* BMISC :: TEST_PORT_SEL :: TEST_PORT_SEL [01:00] */ |
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| 119 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_MASK 0x00000003 |
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| 120 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_SHIFT 0 |
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| 121 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_DEFAULT 0x00000000 |
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| 122 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_TP_OUT_3 3 |
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| 123 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_TP_OUT_2 2 |
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| 124 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_TP_OUT_1 1 |
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| 125 | #define BCHP_BMISC_TEST_PORT_SEL_TEST_PORT_SEL_TP_OUT_0 0 |
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| 126 | |
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| 127 | /*************************************************************************** |
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| 128 | *TEST_PORT_DATA - BVN Back Test Port Status |
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| 129 | ***************************************************************************/ |
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| 130 | /* BMISC :: TEST_PORT_DATA :: TEST_PORT_DATA [31:00] */ |
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| 131 | #define BCHP_BMISC_TEST_PORT_DATA_TEST_PORT_DATA_MASK 0xffffffff |
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| 132 | #define BCHP_BMISC_TEST_PORT_DATA_TEST_PORT_DATA_SHIFT 0 |
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| 133 | #define BCHP_BMISC_TEST_PORT_DATA_TEST_PORT_DATA_DEFAULT 0x00000000 |
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| 134 | |
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| 135 | /*************************************************************************** |
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| 136 | *BVNB_CLOCK_CTRL - BVN Back clock control register |
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| 137 | ***************************************************************************/ |
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| 138 | /* BMISC :: BVNB_CLOCK_CTRL :: reserved0 [31:01] */ |
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| 139 | #define BCHP_BMISC_BVNB_CLOCK_CTRL_reserved0_MASK 0xfffffffe |
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| 140 | #define BCHP_BMISC_BVNB_CLOCK_CTRL_reserved0_SHIFT 1 |
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| 141 | |
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| 142 | /* BMISC :: BVNB_CLOCK_CTRL :: CLK_FREE_RUN_MODE [00:00] */ |
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| 143 | #define BCHP_BMISC_BVNB_CLOCK_CTRL_CLK_FREE_RUN_MODE_MASK 0x00000001 |
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| 144 | #define BCHP_BMISC_BVNB_CLOCK_CTRL_CLK_FREE_RUN_MODE_SHIFT 0 |
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| 145 | #define BCHP_BMISC_BVNB_CLOCK_CTRL_CLK_FREE_RUN_MODE_DEFAULT 0x00000000 |
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| 146 | |
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| 147 | /*************************************************************************** |
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| 148 | *SCRATCH_0 - Scratch Register |
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| 149 | ***************************************************************************/ |
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| 150 | /* BMISC :: SCRATCH_0 :: VALUE [31:00] */ |
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| 151 | #define BCHP_BMISC_SCRATCH_0_VALUE_MASK 0xffffffff |
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| 152 | #define BCHP_BMISC_SCRATCH_0_VALUE_SHIFT 0 |
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| 153 | #define BCHP_BMISC_SCRATCH_0_VALUE_DEFAULT 0x00000000 |
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| 154 | |
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| 155 | #endif /* #ifndef BCHP_BMISC_H__ */ |
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| 156 | |
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| 157 | /* End of File */ |
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