| 1 | /*************************************************************************** |
|---|
| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
|---|
| 3 | * All Rights Reserved |
|---|
| 4 | * Confidential Property of Broadcom Corporation |
|---|
| 5 | * |
|---|
| 6 | * |
|---|
| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
|---|
| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
|---|
| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
|---|
| 10 | * |
|---|
| 11 | * $brcm_Workfile: bchp_bspi.h $ |
|---|
| 12 | * $brcm_Revision: Hydra_Software_Devel/2 $ |
|---|
| 13 | * $brcm_Date: 2/7/12 1:20p $ |
|---|
| 14 | * |
|---|
| 15 | * Module Description: |
|---|
| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
|---|
| 17 | * |
|---|
| 18 | * This module was generated magically with RDB from a source description |
|---|
| 19 | * file. You must edit the source file for changes to be made to this file. |
|---|
| 20 | * |
|---|
| 21 | * |
|---|
| 22 | * Date: Generated on Tue Feb 7 10:59:53 2012 |
|---|
| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
|---|
| 24 | * |
|---|
| 25 | * Compiled with: RDB Utility combo_header.pl |
|---|
| 26 | * RDB Parser 3.0 |
|---|
| 27 | * unknown unknown |
|---|
| 28 | * Perl Interpreter 5.008008 |
|---|
| 29 | * Operating System linux |
|---|
| 30 | * |
|---|
| 31 | * Revision History: |
|---|
| 32 | * |
|---|
| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_bspi.h $ |
|---|
| 34 | * |
|---|
| 35 | * Hydra_Software_Devel/2 2/7/12 1:20p pntruong |
|---|
| 36 | * SW7552-89: Synced up with central rdb. |
|---|
| 37 | * |
|---|
| 38 | ***************************************************************************/ |
|---|
| 39 | |
|---|
| 40 | #ifndef BCHP_BSPI_H__ |
|---|
| 41 | #define BCHP_BSPI_H__ |
|---|
| 42 | |
|---|
| 43 | /*************************************************************************** |
|---|
| 44 | *BSPI - Public BSPI Control Registers |
|---|
| 45 | ***************************************************************************/ |
|---|
| 46 | #define BCHP_BSPI_REVISION_ID 0x00413000 /* Revision ID */ |
|---|
| 47 | #define BCHP_BSPI_SCRATCH 0x00413004 /* Revision ID */ |
|---|
| 48 | #define BCHP_BSPI_MAST_N_BOOT_CTRL 0x00413008 /* Master/Boot SPI Control Register */ |
|---|
| 49 | #define BCHP_BSPI_BUSY_STATUS 0x0041300c /* BSPI Busy Status Register */ |
|---|
| 50 | #define BCHP_BSPI_INTR_STATUS 0x00413010 /* Interrupt Status Register */ |
|---|
| 51 | #define BCHP_BSPI_B0_STATUS 0x00413014 /* Prefetch Buffer 0 Status Register */ |
|---|
| 52 | #define BCHP_BSPI_B0_CTRL 0x00413018 /* Prefetch Buffer 0 Control Register */ |
|---|
| 53 | #define BCHP_BSPI_B1_STATUS 0x0041301c /* Prefetch Buffer 1 Status Register */ |
|---|
| 54 | #define BCHP_BSPI_B1_CTRL 0x00413020 /* Prefetch Buffer 1 Control Register */ |
|---|
| 55 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL 0x00413024 /* Dual/Single Receive Mode Control Register */ |
|---|
| 56 | #define BCHP_BSPI_FLEX_MODE_ENABLE 0x00413028 /* Flexible Control Mode Enable Register */ |
|---|
| 57 | #define BCHP_BSPI_BITS_PER_CYCLE 0x0041302c /* Bits per cycle "b-p-c" Control Register */ |
|---|
| 58 | #define BCHP_BSPI_BITS_PER_PHASE 0x00413030 /* Bits per Phase "b-p-p" Control Register */ |
|---|
| 59 | #define BCHP_BSPI_CMD_AND_MODE_BYTE 0x00413034 /* Command and Mode Data Register */ |
|---|
| 60 | #define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x00413038 /* Bspi FLash upper address byte register */ |
|---|
| 61 | #define BCHP_BSPI_BSPI_XOR_VALUE 0x0041303c /* BSPI FLASH XOR Value Register */ |
|---|
| 62 | #define BCHP_BSPI_BSPI_XOR_ENABLE 0x00413040 /* BSPI FLASH XOR Enable Register */ |
|---|
| 63 | #define BCHP_BSPI_BSPI_PIO_MODE_ENABLE 0x00413044 /* BSPI Pin Programmed IO Mode Enable Register */ |
|---|
| 64 | #define BCHP_BSPI_BSPI_PIO_IODIR 0x00413048 /* BSPI Pin Programmed IO Mode Direction Register */ |
|---|
| 65 | #define BCHP_BSPI_BSPI_PIO_DATA 0x0041304c /* BSPI Pin Programmed IO Mode Data Register */ |
|---|
| 66 | |
|---|
| 67 | /*************************************************************************** |
|---|
| 68 | *REVISION_ID - Revision ID |
|---|
| 69 | ***************************************************************************/ |
|---|
| 70 | /* BSPI :: REVISION_ID :: reserved0 [31:16] */ |
|---|
| 71 | #define BCHP_BSPI_REVISION_ID_reserved0_MASK 0xffff0000 |
|---|
| 72 | #define BCHP_BSPI_REVISION_ID_reserved0_SHIFT 16 |
|---|
| 73 | |
|---|
| 74 | /* BSPI :: REVISION_ID :: MAJOR [15:08] */ |
|---|
| 75 | #define BCHP_BSPI_REVISION_ID_MAJOR_MASK 0x0000ff00 |
|---|
| 76 | #define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT 8 |
|---|
| 77 | #define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT 0x00000004 |
|---|
| 78 | |
|---|
| 79 | /* BSPI :: REVISION_ID :: MINOR [07:00] */ |
|---|
| 80 | #define BCHP_BSPI_REVISION_ID_MINOR_MASK 0x000000ff |
|---|
| 81 | #define BCHP_BSPI_REVISION_ID_MINOR_SHIFT 0 |
|---|
| 82 | #define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT 0x00000000 |
|---|
| 83 | |
|---|
| 84 | /*************************************************************************** |
|---|
| 85 | *SCRATCH - Revision ID |
|---|
| 86 | ***************************************************************************/ |
|---|
| 87 | /* BSPI :: SCRATCH :: SCRATCH [31:00] */ |
|---|
| 88 | #define BCHP_BSPI_SCRATCH_SCRATCH_MASK 0xffffffff |
|---|
| 89 | #define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT 0 |
|---|
| 90 | #define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT 0x00000000 |
|---|
| 91 | |
|---|
| 92 | /*************************************************************************** |
|---|
| 93 | *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register |
|---|
| 94 | ***************************************************************************/ |
|---|
| 95 | /* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */ |
|---|
| 96 | #define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK 0xfffffffe |
|---|
| 97 | #define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT 1 |
|---|
| 98 | |
|---|
| 99 | /* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */ |
|---|
| 100 | #define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK 0x00000001 |
|---|
| 101 | #define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT 0 |
|---|
| 102 | #define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT 0x00000000 |
|---|
| 103 | |
|---|
| 104 | /*************************************************************************** |
|---|
| 105 | *BUSY_STATUS - BSPI Busy Status Register |
|---|
| 106 | ***************************************************************************/ |
|---|
| 107 | /* BSPI :: BUSY_STATUS :: reserved0 [31:01] */ |
|---|
| 108 | #define BCHP_BSPI_BUSY_STATUS_reserved0_MASK 0xfffffffe |
|---|
| 109 | #define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT 1 |
|---|
| 110 | |
|---|
| 111 | /* BSPI :: BUSY_STATUS :: busy [00:00] */ |
|---|
| 112 | #define BCHP_BSPI_BUSY_STATUS_busy_MASK 0x00000001 |
|---|
| 113 | #define BCHP_BSPI_BUSY_STATUS_busy_SHIFT 0 |
|---|
| 114 | #define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT 0x00000000 |
|---|
| 115 | |
|---|
| 116 | /*************************************************************************** |
|---|
| 117 | *INTR_STATUS - Interrupt Status Register |
|---|
| 118 | ***************************************************************************/ |
|---|
| 119 | /* BSPI :: INTR_STATUS :: reserved0 [31:02] */ |
|---|
| 120 | #define BCHP_BSPI_INTR_STATUS_reserved0_MASK 0xfffffffc |
|---|
| 121 | #define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT 2 |
|---|
| 122 | |
|---|
| 123 | /* BSPI :: INTR_STATUS :: intr_1 [01:01] */ |
|---|
| 124 | #define BCHP_BSPI_INTR_STATUS_intr_1_MASK 0x00000002 |
|---|
| 125 | #define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT 1 |
|---|
| 126 | #define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT 0x00000000 |
|---|
| 127 | |
|---|
| 128 | /* BSPI :: INTR_STATUS :: intr_0 [00:00] */ |
|---|
| 129 | #define BCHP_BSPI_INTR_STATUS_intr_0_MASK 0x00000001 |
|---|
| 130 | #define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT 0 |
|---|
| 131 | #define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT 0x00000000 |
|---|
| 132 | |
|---|
| 133 | /*************************************************************************** |
|---|
| 134 | *B0_STATUS - Prefetch Buffer 0 Status Register |
|---|
| 135 | ***************************************************************************/ |
|---|
| 136 | /* BSPI :: B0_STATUS :: reserved0 [31:31] */ |
|---|
| 137 | #define BCHP_BSPI_B0_STATUS_reserved0_MASK 0x80000000 |
|---|
| 138 | #define BCHP_BSPI_B0_STATUS_reserved0_SHIFT 31 |
|---|
| 139 | |
|---|
| 140 | /* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */ |
|---|
| 141 | #define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK 0x40000000 |
|---|
| 142 | #define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT 30 |
|---|
| 143 | #define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT 0x00000000 |
|---|
| 144 | |
|---|
| 145 | /* BSPI :: B0_STATUS :: b0_full [29:29] */ |
|---|
| 146 | #define BCHP_BSPI_B0_STATUS_b0_full_MASK 0x20000000 |
|---|
| 147 | #define BCHP_BSPI_B0_STATUS_b0_full_SHIFT 29 |
|---|
| 148 | #define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT 0x00000000 |
|---|
| 149 | |
|---|
| 150 | /* BSPI :: B0_STATUS :: b0_empty [28:28] */ |
|---|
| 151 | #define BCHP_BSPI_B0_STATUS_b0_empty_MASK 0x10000000 |
|---|
| 152 | #define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT 28 |
|---|
| 153 | #define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT 0x00000001 |
|---|
| 154 | |
|---|
| 155 | /* BSPI :: B0_STATUS :: b0_miss [27:27] */ |
|---|
| 156 | #define BCHP_BSPI_B0_STATUS_b0_miss_MASK 0x08000000 |
|---|
| 157 | #define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT 27 |
|---|
| 158 | #define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT 0x00000000 |
|---|
| 159 | |
|---|
| 160 | /* BSPI :: B0_STATUS :: b0_hit [26:26] */ |
|---|
| 161 | #define BCHP_BSPI_B0_STATUS_b0_hit_MASK 0x04000000 |
|---|
| 162 | #define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT 26 |
|---|
| 163 | #define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT 0x00000000 |
|---|
| 164 | |
|---|
| 165 | /* BSPI :: B0_STATUS :: b0_address [25:00] */ |
|---|
| 166 | #define BCHP_BSPI_B0_STATUS_b0_address_MASK 0x03ffffff |
|---|
| 167 | #define BCHP_BSPI_B0_STATUS_b0_address_SHIFT 0 |
|---|
| 168 | #define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT 0x00000000 |
|---|
| 169 | |
|---|
| 170 | /*************************************************************************** |
|---|
| 171 | *B0_CTRL - Prefetch Buffer 0 Control Register |
|---|
| 172 | ***************************************************************************/ |
|---|
| 173 | /* BSPI :: B0_CTRL :: reserved0 [31:01] */ |
|---|
| 174 | #define BCHP_BSPI_B0_CTRL_reserved0_MASK 0xfffffffe |
|---|
| 175 | #define BCHP_BSPI_B0_CTRL_reserved0_SHIFT 1 |
|---|
| 176 | |
|---|
| 177 | /* BSPI :: B0_CTRL :: b0_flush [00:00] */ |
|---|
| 178 | #define BCHP_BSPI_B0_CTRL_b0_flush_MASK 0x00000001 |
|---|
| 179 | #define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT 0 |
|---|
| 180 | #define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT 0x00000000 |
|---|
| 181 | |
|---|
| 182 | /*************************************************************************** |
|---|
| 183 | *B1_STATUS - Prefetch Buffer 1 Status Register |
|---|
| 184 | ***************************************************************************/ |
|---|
| 185 | /* BSPI :: B1_STATUS :: reserved0 [31:31] */ |
|---|
| 186 | #define BCHP_BSPI_B1_STATUS_reserved0_MASK 0x80000000 |
|---|
| 187 | #define BCHP_BSPI_B1_STATUS_reserved0_SHIFT 31 |
|---|
| 188 | |
|---|
| 189 | /* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */ |
|---|
| 190 | #define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK 0x40000000 |
|---|
| 191 | #define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT 30 |
|---|
| 192 | #define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT 0x00000000 |
|---|
| 193 | |
|---|
| 194 | /* BSPI :: B1_STATUS :: b1_full [29:29] */ |
|---|
| 195 | #define BCHP_BSPI_B1_STATUS_b1_full_MASK 0x20000000 |
|---|
| 196 | #define BCHP_BSPI_B1_STATUS_b1_full_SHIFT 29 |
|---|
| 197 | #define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT 0x00000000 |
|---|
| 198 | |
|---|
| 199 | /* BSPI :: B1_STATUS :: b1_empty [28:28] */ |
|---|
| 200 | #define BCHP_BSPI_B1_STATUS_b1_empty_MASK 0x10000000 |
|---|
| 201 | #define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT 28 |
|---|
| 202 | #define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT 0x00000001 |
|---|
| 203 | |
|---|
| 204 | /* BSPI :: B1_STATUS :: b1_miss [27:27] */ |
|---|
| 205 | #define BCHP_BSPI_B1_STATUS_b1_miss_MASK 0x08000000 |
|---|
| 206 | #define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT 27 |
|---|
| 207 | #define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT 0x00000000 |
|---|
| 208 | |
|---|
| 209 | /* BSPI :: B1_STATUS :: b1_hit [26:26] */ |
|---|
| 210 | #define BCHP_BSPI_B1_STATUS_b1_hit_MASK 0x04000000 |
|---|
| 211 | #define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT 26 |
|---|
| 212 | #define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT 0x00000000 |
|---|
| 213 | |
|---|
| 214 | /* BSPI :: B1_STATUS :: b1_address [25:00] */ |
|---|
| 215 | #define BCHP_BSPI_B1_STATUS_b1_address_MASK 0x03ffffff |
|---|
| 216 | #define BCHP_BSPI_B1_STATUS_b1_address_SHIFT 0 |
|---|
| 217 | #define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT 0x00000000 |
|---|
| 218 | |
|---|
| 219 | /*************************************************************************** |
|---|
| 220 | *B1_CTRL - Prefetch Buffer 1 Control Register |
|---|
| 221 | ***************************************************************************/ |
|---|
| 222 | /* BSPI :: B1_CTRL :: reserved0 [31:01] */ |
|---|
| 223 | #define BCHP_BSPI_B1_CTRL_reserved0_MASK 0xfffffffe |
|---|
| 224 | #define BCHP_BSPI_B1_CTRL_reserved0_SHIFT 1 |
|---|
| 225 | |
|---|
| 226 | /* BSPI :: B1_CTRL :: b1_flush [00:00] */ |
|---|
| 227 | #define BCHP_BSPI_B1_CTRL_b1_flush_MASK 0x00000001 |
|---|
| 228 | #define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT 0 |
|---|
| 229 | #define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT 0x00000000 |
|---|
| 230 | |
|---|
| 231 | /*************************************************************************** |
|---|
| 232 | *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register |
|---|
| 233 | ***************************************************************************/ |
|---|
| 234 | /* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */ |
|---|
| 235 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK 0xffffffe0 |
|---|
| 236 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT 5 |
|---|
| 237 | |
|---|
| 238 | /* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */ |
|---|
| 239 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK 0x00000010 |
|---|
| 240 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT 4 |
|---|
| 241 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT 0x00000000 |
|---|
| 242 | |
|---|
| 243 | /* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */ |
|---|
| 244 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK 0x00000008 |
|---|
| 245 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT 3 |
|---|
| 246 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT 0x00000000 |
|---|
| 247 | |
|---|
| 248 | /* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */ |
|---|
| 249 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK 0x00000004 |
|---|
| 250 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT 2 |
|---|
| 251 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT 0x00000000 |
|---|
| 252 | |
|---|
| 253 | /* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */ |
|---|
| 254 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK 0x00000002 |
|---|
| 255 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT 1 |
|---|
| 256 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT 0x00000000 |
|---|
| 257 | |
|---|
| 258 | /* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */ |
|---|
| 259 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK 0x00000001 |
|---|
| 260 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT 0 |
|---|
| 261 | #define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT 0x00000000 |
|---|
| 262 | |
|---|
| 263 | /*************************************************************************** |
|---|
| 264 | *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register |
|---|
| 265 | ***************************************************************************/ |
|---|
| 266 | /* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */ |
|---|
| 267 | #define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK 0xfffffffe |
|---|
| 268 | #define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT 1 |
|---|
| 269 | |
|---|
| 270 | /* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */ |
|---|
| 271 | #define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK 0x00000001 |
|---|
| 272 | #define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT 0 |
|---|
| 273 | #define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT 0x00000000 |
|---|
| 274 | |
|---|
| 275 | /*************************************************************************** |
|---|
| 276 | *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register |
|---|
| 277 | ***************************************************************************/ |
|---|
| 278 | /* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */ |
|---|
| 279 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK 0xfc000000 |
|---|
| 280 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT 26 |
|---|
| 281 | |
|---|
| 282 | /* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */ |
|---|
| 283 | #define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK 0x03000000 |
|---|
| 284 | #define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT 24 |
|---|
| 285 | #define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT 0x00000000 |
|---|
| 286 | |
|---|
| 287 | /* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */ |
|---|
| 288 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK 0x00fc0000 |
|---|
| 289 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT 18 |
|---|
| 290 | |
|---|
| 291 | /* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */ |
|---|
| 292 | #define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK 0x00030000 |
|---|
| 293 | #define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT 16 |
|---|
| 294 | #define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT 0x00000000 |
|---|
| 295 | |
|---|
| 296 | /* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */ |
|---|
| 297 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK 0x0000fc00 |
|---|
| 298 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT 10 |
|---|
| 299 | |
|---|
| 300 | /* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */ |
|---|
| 301 | #define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK 0x00000300 |
|---|
| 302 | #define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT 8 |
|---|
| 303 | #define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT 0x00000000 |
|---|
| 304 | |
|---|
| 305 | /* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */ |
|---|
| 306 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK 0x000000fc |
|---|
| 307 | #define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT 2 |
|---|
| 308 | |
|---|
| 309 | /* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */ |
|---|
| 310 | #define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK 0x00000003 |
|---|
| 311 | #define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT 0 |
|---|
| 312 | #define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT 0x00000000 |
|---|
| 313 | |
|---|
| 314 | /*************************************************************************** |
|---|
| 315 | *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register |
|---|
| 316 | ***************************************************************************/ |
|---|
| 317 | /* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */ |
|---|
| 318 | #define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK 0xfe000000 |
|---|
| 319 | #define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT 25 |
|---|
| 320 | |
|---|
| 321 | /* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */ |
|---|
| 322 | #define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK 0x01000000 |
|---|
| 323 | #define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT 24 |
|---|
| 324 | #define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT 0x00000000 |
|---|
| 325 | |
|---|
| 326 | /* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */ |
|---|
| 327 | #define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK 0x00fe0000 |
|---|
| 328 | #define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT 17 |
|---|
| 329 | |
|---|
| 330 | /* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */ |
|---|
| 331 | #define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK 0x00010000 |
|---|
| 332 | #define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT 16 |
|---|
| 333 | #define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT 0x00000000 |
|---|
| 334 | |
|---|
| 335 | /* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */ |
|---|
| 336 | #define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK 0x0000fe00 |
|---|
| 337 | #define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT 9 |
|---|
| 338 | |
|---|
| 339 | /* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */ |
|---|
| 340 | #define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK 0x00000100 |
|---|
| 341 | #define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT 8 |
|---|
| 342 | #define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT 0x00000000 |
|---|
| 343 | |
|---|
| 344 | /* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */ |
|---|
| 345 | #define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK 0x000000ff |
|---|
| 346 | #define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT 0 |
|---|
| 347 | #define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT 0x00000008 |
|---|
| 348 | |
|---|
| 349 | /*************************************************************************** |
|---|
| 350 | *CMD_AND_MODE_BYTE - Command and Mode Data Register |
|---|
| 351 | ***************************************************************************/ |
|---|
| 352 | /* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */ |
|---|
| 353 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK 0xff000000 |
|---|
| 354 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT 24 |
|---|
| 355 | |
|---|
| 356 | /* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */ |
|---|
| 357 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK 0x00ff0000 |
|---|
| 358 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT 16 |
|---|
| 359 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT 0x00000000 |
|---|
| 360 | |
|---|
| 361 | /* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */ |
|---|
| 362 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK 0x0000ff00 |
|---|
| 363 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT 8 |
|---|
| 364 | |
|---|
| 365 | /* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */ |
|---|
| 366 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK 0x000000ff |
|---|
| 367 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT 0 |
|---|
| 368 | #define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT 0x0000000b |
|---|
| 369 | |
|---|
| 370 | /*************************************************************************** |
|---|
| 371 | *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register |
|---|
| 372 | ***************************************************************************/ |
|---|
| 373 | /* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */ |
|---|
| 374 | #define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000 |
|---|
| 375 | #define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24 |
|---|
| 376 | #define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000 |
|---|
| 377 | |
|---|
| 378 | /* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */ |
|---|
| 379 | #define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK 0x00ffffff |
|---|
| 380 | #define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT 0 |
|---|
| 381 | |
|---|
| 382 | /*************************************************************************** |
|---|
| 383 | *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register |
|---|
| 384 | ***************************************************************************/ |
|---|
| 385 | /* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */ |
|---|
| 386 | #define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK 0xfff00000 |
|---|
| 387 | #define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT 20 |
|---|
| 388 | #define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT 0x00000000 |
|---|
| 389 | |
|---|
| 390 | /* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */ |
|---|
| 391 | #define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK 0x000fffff |
|---|
| 392 | #define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT 0 |
|---|
| 393 | |
|---|
| 394 | /*************************************************************************** |
|---|
| 395 | *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register |
|---|
| 396 | ***************************************************************************/ |
|---|
| 397 | /* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */ |
|---|
| 398 | #define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK 0xfffffffe |
|---|
| 399 | #define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT 1 |
|---|
| 400 | |
|---|
| 401 | /* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */ |
|---|
| 402 | #define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK 0x00000001 |
|---|
| 403 | #define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT 0 |
|---|
| 404 | #define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT 0x00000000 |
|---|
| 405 | |
|---|
| 406 | /*************************************************************************** |
|---|
| 407 | *BSPI_PIO_MODE_ENABLE - BSPI Pin Programmed IO Mode Enable Register |
|---|
| 408 | ***************************************************************************/ |
|---|
| 409 | /* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */ |
|---|
| 410 | #define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK 0xfffffffe |
|---|
| 411 | #define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT 1 |
|---|
| 412 | |
|---|
| 413 | /* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */ |
|---|
| 414 | #define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK 0x00000001 |
|---|
| 415 | #define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT 0 |
|---|
| 416 | #define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT 0x00000000 |
|---|
| 417 | |
|---|
| 418 | /*************************************************************************** |
|---|
| 419 | *BSPI_PIO_IODIR - BSPI Pin Programmed IO Mode Direction Register |
|---|
| 420 | ***************************************************************************/ |
|---|
| 421 | /* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */ |
|---|
| 422 | #define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK 0xfffffff8 |
|---|
| 423 | #define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT 3 |
|---|
| 424 | |
|---|
| 425 | /* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */ |
|---|
| 426 | #define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK 0x00000007 |
|---|
| 427 | #define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT 0 |
|---|
| 428 | #define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT 0x00000003 |
|---|
| 429 | |
|---|
| 430 | /*************************************************************************** |
|---|
| 431 | *BSPI_PIO_DATA - BSPI Pin Programmed IO Mode Data Register |
|---|
| 432 | ***************************************************************************/ |
|---|
| 433 | /* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */ |
|---|
| 434 | #define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK 0xfffffff8 |
|---|
| 435 | #define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT 3 |
|---|
| 436 | |
|---|
| 437 | /* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */ |
|---|
| 438 | #define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK 0x00000007 |
|---|
| 439 | #define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT 0 |
|---|
| 440 | #define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT 0x00000000 |
|---|
| 441 | |
|---|
| 442 | #endif /* #ifndef BCHP_BSPI_H__ */ |
|---|
| 443 | |
|---|
| 444 | /* End of File */ |
|---|
