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bchp_nand.h

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1	/***************************************************************************
2	* Copyright (c) 1999-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	*
7	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
8	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
9	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
10	*
11	* $brcm_Workfile: bchp_nand.h $
12	* $brcm_Revision: Hydra_Software_Devel/2 $
13	* $brcm_Date: 2/7/12 1:35p $
14	*
15	* Module Description:
16	* DO NOT EDIT THIS FILE DIRECTLY
17	*
18	* This module was generated magically with RDB from a source description
19	* file. You must edit the source file for changes to be made to this file.
20	*
21	*
22	* Date: Generated on Tue Feb 7 10:59:54 2012
23	* MD5 Checksum d41d8cd98f00b204e9800998ecf8427e
24	*
25	* Compiled with: RDB Utility combo_header.pl
26	* RDB Parser 3.0
27	* unknown unknown
28	* Perl Interpreter 5.008008
29	* Operating System linux
30	*
31	* Revision History:
32	*
33	* $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_nand.h $
34	*
35	* Hydra_Software_Devel/2 2/7/12 1:35p pntruong
36	* SW7552-89: Synced up with central rdb.
37	*
38	***************************************************************************/
39
40	#ifndef BCHP_NAND_H__
41	#define BCHP_NAND_H__
42
43	/***************************************************************************
44	*NAND - Nand Flash Control Registers
45	***************************************************************************/
46	#define BCHP_NAND_REVISION 0x00412800 /* NAND Revision */
47	#define BCHP_NAND_CMD_START 0x00412804 /* Nand Flash Command Start */
48	#define BCHP_NAND_CMD_EXT_ADDRESS 0x00412808 /* Nand Flash Command Extended Address */
49	#define BCHP_NAND_CMD_ADDRESS 0x0041280c /* Nand Flash Command Address */
50	#define BCHP_NAND_CMD_END_ADDRESS 0x00412810 /* Nand Flash Command End Address */
51	#define BCHP_NAND_CS_NAND_SELECT 0x00412814 /* Nand Flash EBI CS Select */
52	#define BCHP_NAND_CS_NAND_XOR 0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
53	#define BCHP_NAND_SPARE_AREA_READ_OFS_0 0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
54	#define BCHP_NAND_SPARE_AREA_READ_OFS_4 0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
55	#define BCHP_NAND_SPARE_AREA_READ_OFS_8 0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
56	#define BCHP_NAND_SPARE_AREA_READ_OFS_C 0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
57	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0 0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
58	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4 0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
59	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8 0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
60	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C 0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
61	#define BCHP_NAND_ACC_CONTROL 0x00412840 /* Nand Flash Access Control */
62	#define BCHP_NAND_CONFIG 0x00412848 /* Nand Flash Config */
63	#define BCHP_NAND_TIMING_1 0x00412850 /* Nand Flash Timing Parameters 1 */
64	#define BCHP_NAND_TIMING_2 0x00412854 /* Nand Flash Timing Parameters 2 */
65	#define BCHP_NAND_SEMAPHORE 0x00412858 /* Semaphore */
66	#define BCHP_NAND_FLASH_DEVICE_ID 0x00412860 /* Nand Flash Device ID */
67	#define BCHP_NAND_FLASH_DEVICE_ID_EXT 0x00412864 /* Nand Flash Extended Device ID */
68	#define BCHP_NAND_BLOCK_LOCK_STATUS 0x00412868 /* Nand Flash Block Lock Status */
69	#define BCHP_NAND_INTFC_STATUS 0x0041286c /* Nand Flash Interface Status */
70	#define BCHP_NAND_ECC_CORR_EXT_ADDR 0x00412870 /* ECC Correctable Error Extended Address */
71	#define BCHP_NAND_ECC_CORR_ADDR 0x00412874 /* ECC Correctable Error Address */
72	#define BCHP_NAND_ECC_UNC_EXT_ADDR 0x00412878 /* ECC Uncorrectable Error Extended Address */
73	#define BCHP_NAND_ECC_UNC_ADDR 0x0041287c /* ECC Uncorrectable Error Address */
74	#define BCHP_NAND_READ_ERROR_COUNT 0x00412880 /* Read Error Count */
75	#define BCHP_NAND_CORR_STAT_THRESHOLD 0x00412884 /* Correctable Error Reporting Threshold */
76	#define BCHP_NAND_ONFI_STATUS 0x00412888 /* ONFI Status */
77	#define BCHP_NAND_ONFI_DEBUG_DATA 0x0041288c /* ONFI Debug Data */
78	#define BCHP_NAND_FLASH_READ_EXT_ADDR 0x00412890 /* Flash Read Data Extended Address */
79	#define BCHP_NAND_FLASH_READ_ADDR 0x00412894 /* Flash Read Data Address */
80	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR 0x00412898 /* Page Program Extended Address */
81	#define BCHP_NAND_PROGRAM_PAGE_ADDR 0x0041289c /* Page Program Address */
82	#define BCHP_NAND_COPY_BACK_EXT_ADDR 0x004128a0 /* Copy Back Extended Address */
83	#define BCHP_NAND_COPY_BACK_ADDR 0x004128a4 /* Copy Back Address */
84	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR 0x004128a8 /* Block Erase Extended Address */
85	#define BCHP_NAND_BLOCK_ERASE_ADDR 0x004128ac /* Block Erase Address */
86	#define BCHP_NAND_INV_READ_EXT_ADDR 0x004128b0 /* Flash Invalid Data Extended Address */
87	#define BCHP_NAND_INV_READ_ADDR 0x004128b4 /* Flash Invalid Data Address */
88	#define BCHP_NAND_BLK_WR_PROTECT 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
89	#define BCHP_NAND_ACC_CONTROL_CS1 0x004128d0 /* Nand Flash Access Control */
90	#define BCHP_NAND_CONFIG_CS1 0x004128d4 /* Nand Flash Config */
91	#define BCHP_NAND_TIMING_1_CS1 0x004128d8 /* Nand Flash Timing Parameters 1 */
92	#define BCHP_NAND_TIMING_2_CS1 0x004128dc /* Nand Flash Timing Parameters 2 */
93	#define BCHP_NAND_ACC_CONTROL_CS2 0x004128e0 /* Nand Flash Access Control */
94	#define BCHP_NAND_CONFIG_CS2 0x004128e4 /* Nand Flash Config */
95	#define BCHP_NAND_TIMING_1_CS2 0x004128e8 /* Nand Flash Timing Parameters 1 */
96	#define BCHP_NAND_TIMING_2_CS2 0x004128ec /* Nand Flash Timing Parameters 2 */
97	#define BCHP_NAND_ACC_CONTROL_CS3 0x004128f0 /* Nand Flash Access Control */
98	#define BCHP_NAND_CONFIG_CS3 0x004128f4 /* Nand Flash Config */
99	#define BCHP_NAND_TIMING_1_CS3 0x004128f8 /* Nand Flash Timing Parameters 1 */
100	#define BCHP_NAND_TIMING_2_CS3 0x004128fc /* Nand Flash Timing Parameters 2 */
101	#define BCHP_NAND_ACC_CONTROL_CS4 0x00412900 /* Nand Flash Access Control */
102	#define BCHP_NAND_CONFIG_CS4 0x00412904 /* Nand Flash Config */
103	#define BCHP_NAND_TIMING_1_CS4 0x00412908 /* Nand Flash Timing Parameters 1 */
104	#define BCHP_NAND_TIMING_2_CS4 0x0041290c /* Nand Flash Timing Parameters 2 */
105	#define BCHP_NAND_SPARE_AREA_READ_OFS_10 0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
106	#define BCHP_NAND_SPARE_AREA_READ_OFS_14 0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
107	#define BCHP_NAND_SPARE_AREA_READ_OFS_18 0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
108	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C 0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
109	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10 0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
110	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14 0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
111	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18 0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
112	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C 0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
113	#define BCHP_NAND_LL_OP 0x00412978 /* Nand Flash Low Level Operation */
114	#define BCHP_NAND_LL_RDDATA 0x0041297c /* Nand Flash Low Level Read Data */
115
116	/***************************************************************************
117	*REVISION - NAND Revision
118	***************************************************************************/
119	/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
120	#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK 0x80000000
121	#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT 31
122	#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT 0x00000001
123
124	/* NAND :: REVISION :: reserved0 [30:16] */
125	#define BCHP_NAND_REVISION_reserved0_MASK 0x7fff0000
126	#define BCHP_NAND_REVISION_reserved0_SHIFT 16
127
128	/* NAND :: REVISION :: MAJOR [15:08] */
129	#define BCHP_NAND_REVISION_MAJOR_MASK 0x0000ff00
130	#define BCHP_NAND_REVISION_MAJOR_SHIFT 8
131	#define BCHP_NAND_REVISION_MAJOR_DEFAULT 0x00000005
132
133	/* NAND :: REVISION :: MINOR [07:00] */
134	#define BCHP_NAND_REVISION_MINOR_MASK 0x000000ff
135	#define BCHP_NAND_REVISION_MINOR_SHIFT 0
136	#define BCHP_NAND_REVISION_MINOR_DEFAULT 0x00000000
137
138	/***************************************************************************
139	*CMD_START - Nand Flash Command Start
140	***************************************************************************/
141	/* NAND :: CMD_START :: reserved0 [31:29] */
142	#define BCHP_NAND_CMD_START_reserved0_MASK 0xe0000000
143	#define BCHP_NAND_CMD_START_reserved0_SHIFT 29
144
145	/* NAND :: CMD_START :: OPCODE [28:24] */
146	#define BCHP_NAND_CMD_START_OPCODE_MASK 0x1f000000
147	#define BCHP_NAND_CMD_START_OPCODE_SHIFT 24
148	#define BCHP_NAND_CMD_START_OPCODE_DEFAULT 0x00000000
149	#define BCHP_NAND_CMD_START_OPCODE_NULL 0
150	#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ 1
151	#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ 2
152	#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ 3
153	#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE 4
154	#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5
155	#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK 6
156	#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ 7
157	#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE 8
158	#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET 9
159	#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK 10
160	#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11
161	#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12
162	#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13
163	#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ 14
164	#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15
165	#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16
166
167	/* NAND :: CMD_START :: reserved1 [23:00] */
168	#define BCHP_NAND_CMD_START_reserved1_MASK 0x00ffffff
169	#define BCHP_NAND_CMD_START_reserved1_SHIFT 0
170
171	/***************************************************************************
172	*CMD_EXT_ADDRESS - Nand Flash Command Extended Address
173	***************************************************************************/
174	/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
175	#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK 0xfff80000
176	#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT 19
177
178	/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
179	#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK 0x00070000
180	#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT 16
181	#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT 0x00000000
182
183	/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
184	#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK 0x0000ffff
185	#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT 0
186	#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT 0x00000000
187
188	/***************************************************************************
189	*CMD_ADDRESS - Nand Flash Command Address
190	***************************************************************************/
191	/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
192	#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK 0xffffffff
193	#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT 0
194	#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT 0x00000000
195
196	/***************************************************************************
197	*CMD_END_ADDRESS - Nand Flash Command End Address
198	***************************************************************************/
199	/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
200	#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK 0xffffffff
201	#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT 0
202	#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT 0x00000000
203
204	/***************************************************************************
205	*CS_NAND_SELECT - Nand Flash EBI CS Select
206	***************************************************************************/
207	/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
208	#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK 0x80000000
209	#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT 31
210	#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT 0x00000000
211
212	/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
213	#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK 0x40000000
214	#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT 30
215
216	/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
217	#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK 0x20000000
218	#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT 29
219
220	/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
221	#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK 0x10000000
222	#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT 28
223	#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT 0x00000000
224
225	/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
226	#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK 0x0fff0000
227	#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT 16
228
229	/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
230	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK 0x00008000
231	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT 15
232	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT 0x00000000
233
234	/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
235	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK 0x00004000
236	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT 14
237	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT 0x00000000
238
239	/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
240	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK 0x00002000
241	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT 13
242	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT 0x00000000
243
244	/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
245	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK 0x00001000
246	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT 12
247	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT 0x00000000
248
249	/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
250	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK 0x00000800
251	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT 11
252	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT 0x00000000
253
254	/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
255	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK 0x00000400
256	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT 10
257	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT 0x00000000
258
259	/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
260	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK 0x00000200
261	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT 9
262	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT 0x00000000
263
264	/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
265	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK 0x00000100
266	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT 8
267
268	/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
269	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK 0x00000080
270	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT 7
271	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT 0x00000000
272
273	/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
274	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK 0x00000040
275	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT 6
276	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT 0x00000000
277
278	/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
279	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK 0x00000020
280	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT 5
281	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT 0x00000000
282
283	/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
284	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK 0x00000010
285	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT 4
286	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT 0x00000000
287
288	/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
289	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK 0x00000008
290	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT 3
291	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT 0x00000000
292
293	/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
294	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK 0x00000004
295	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT 2
296	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT 0x00000000
297
298	/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
299	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK 0x00000002
300	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT 1
301	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT 0x00000000
302
303	/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
304	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK 0x00000001
305	#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT 0
306
307	/***************************************************************************
308	*CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
309	***************************************************************************/
310	/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
311	#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK 0x80000000
312	#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT 31
313	#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT 0x00000000
314
315	/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
316	#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK 0x7fffff00
317	#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT 8
318
319	/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
320	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK 0x00000080
321	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT 7
322	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT 0x00000000
323
324	/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
325	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK 0x00000040
326	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT 6
327	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT 0x00000000
328
329	/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
330	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK 0x00000020
331	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT 5
332	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT 0x00000000
333
334	/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
335	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK 0x00000010
336	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT 4
337	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT 0x00000000
338
339	/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
340	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK 0x00000008
341	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT 3
342	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT 0x00000000
343
344	/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
345	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK 0x00000004
346	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT 2
347	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT 0x00000000
348
349	/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
350	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK 0x00000002
351	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT 1
352	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT 0x00000000
353
354	/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
355	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK 0x00000001
356	#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT 0
357
358	/***************************************************************************
359	*SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
360	***************************************************************************/
361	/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
362	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK 0xff000000
363	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT 24
364	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
365
366	/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
367	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
368	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT 16
369	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
370
371	/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
372	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
373	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT 8
374	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
375
376	/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
377	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK 0x000000ff
378	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT 0
379	#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
380
381	/***************************************************************************
382	*SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
383	***************************************************************************/
384	/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
385	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK 0xff000000
386	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT 24
387	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
388
389	/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
390	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
391	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT 16
392	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
393
394	/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
395	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
396	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT 8
397	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
398
399	/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
400	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK 0x000000ff
401	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT 0
402	#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
403
404	/***************************************************************************
405	*SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
406	***************************************************************************/
407	/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
408	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK 0xff000000
409	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT 24
410	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
411
412	/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
413	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
414	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT 16
415	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
416
417	/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
418	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
419	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT 8
420	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
421
422	/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
423	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK 0x000000ff
424	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT 0
425	#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
426
427	/***************************************************************************
428	*SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
429	***************************************************************************/
430	/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
431	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK 0xff000000
432	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT 24
433	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
434
435	/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
436	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
437	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT 16
438	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
439
440	/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
441	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
442	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT 8
443	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
444
445	/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
446	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK 0x000000ff
447	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT 0
448	#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
449
450	/***************************************************************************
451	*SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
452	***************************************************************************/
453	/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
454	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK 0xff000000
455	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT 24
456	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT 0x000000ff
457
458	/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
459	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK 0x00ff0000
460	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT 16
461	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT 0x000000ff
462
463	/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
464	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK 0x0000ff00
465	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT 8
466	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT 0x000000ff
467
468	/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
469	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK 0x000000ff
470	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT 0
471	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT 0x000000ff
472
473	/***************************************************************************
474	*SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
475	***************************************************************************/
476	/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
477	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK 0xff000000
478	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT 24
479	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT 0x000000ff
480
481	/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
482	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK 0x00ff0000
483	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT 16
484	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT 0x000000ff
485
486	/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
487	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK 0x0000ff00
488	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT 8
489	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT 0x000000ff
490
491	/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
492	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK 0x000000ff
493	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT 0
494	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT 0x000000ff
495
496	/***************************************************************************
497	*SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
498	***************************************************************************/
499	/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
500	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK 0xff000000
501	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT 24
502	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT 0x000000ff
503
504	/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
505	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK 0x00ff0000
506	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT 16
507	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT 0x000000ff
508
509	/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
510	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK 0x0000ff00
511	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT 8
512	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT 0x000000ff
513
514	/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
515	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK 0x000000ff
516	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT 0
517	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT 0x000000ff
518
519	/***************************************************************************
520	*SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
521	***************************************************************************/
522	/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
523	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK 0xff000000
524	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT 24
525	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT 0x000000ff
526
527	/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
528	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK 0x00ff0000
529	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT 16
530	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT 0x000000ff
531
532	/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
533	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK 0x0000ff00
534	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT 8
535	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT 0x000000ff
536
537	/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
538	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK 0x000000ff
539	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT 0
540	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT 0x000000ff
541
542	/***************************************************************************
543	*ACC_CONTROL - Nand Flash Access Control
544	***************************************************************************/
545	/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
546	#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK 0x80000000
547	#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT 31
548	#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT 0x00000001
549
550	/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
551	#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK 0x40000000
552	#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT 30
553	#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT 0x00000001
554
555	/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
556	#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK 0x20000000
557	#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT 29
558
559	/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
560	#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK 0x10000000
561	#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT 28
562	#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT 0x00000001
563
564	/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
565	#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK 0x08000000
566	#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT 27
567	#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT 0x00000000
568
569	/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
570	#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK 0x04000000
571	#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT 26
572	#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT 0x00000001
573
574	/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
575	#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK 0x02000000
576	#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT 25
577	#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT 0x00000001
578
579	/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
580	#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK 0x01000000
581	#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT 24
582	#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT 0x00000001
583
584	/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
585	#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK 0x00f00000
586	#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT 20
587	#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT 0x0000000f
588
589	/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
590	#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK 0x000f0000
591	#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT 16
592	#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT 0x0000000f
593
594	/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
595	#define BCHP_NAND_ACC_CONTROL_reserved0_MASK 0x00008000
596	#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT 15
597
598	/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
599	#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK 0x00004000
600	#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT 14
601	#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT 0x00000000
602
603	/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
604	#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK 0x00003f00
605	#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT 8
606	#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT 0x00000010
607
608	/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
609	#define BCHP_NAND_ACC_CONTROL_reserved1_MASK 0x00000080
610	#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT 7
611
612	/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
613	#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK 0x00000040
614	#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT 6
615	#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT 0x00000000
616
617	/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
618	#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK 0x0000003f
619	#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT 0
620	#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT 0x00000010
621
622	/***************************************************************************
623	*CONFIG - Nand Flash Config
624	***************************************************************************/
625	/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
626	#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK 0x80000000
627	#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT 31
628	#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT 0x00000000
629
630	/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
631	#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK 0x70000000
632	#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT 28
633	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB 6
634	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB 5
635	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB 3
636	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB 1
637	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB 0
638	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB 2
639	#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB 4
640
641	/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
642	#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK 0x0f000000
643	#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT 24
644	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB 0
645	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB 1
646	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB 2
647	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB 3
648	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB 4
649	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB 5
650	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB 6
651	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB 7
652	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB 8
653	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB 9
654	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB 10
655	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB 11
656	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB 12
657	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB 13
658	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB 14
659	#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB 15
660
661	/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
662	#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK 0x00800000
663	#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT 23
664	#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8 0
665	#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16 1
666
667	/* NAND :: CONFIG :: reserved0 [22:22] */
668	#define BCHP_NAND_CONFIG_reserved0_MASK 0x00400000
669	#define BCHP_NAND_CONFIG_reserved0_SHIFT 22
670
671	/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
672	#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK 0x00300000
673	#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT 20
674	#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512 0
675	#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB 1
676	#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB 2
677	#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB 3
678
679	/* NAND :: CONFIG :: reserved1 [19:19] */
680	#define BCHP_NAND_CONFIG_reserved1_MASK 0x00080000
681	#define BCHP_NAND_CONFIG_reserved1_SHIFT 19
682
683	/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
684	#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK 0x00070000
685	#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT 16
686
687	/* NAND :: CONFIG :: reserved2 [15:15] */
688	#define BCHP_NAND_CONFIG_reserved2_MASK 0x00008000
689	#define BCHP_NAND_CONFIG_reserved2_SHIFT 15
690
691	/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
692	#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK 0x00007000
693	#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT 12
694
695	/* NAND :: CONFIG :: reserved3 [11:11] */
696	#define BCHP_NAND_CONFIG_reserved3_MASK 0x00000800
697	#define BCHP_NAND_CONFIG_reserved3_SHIFT 11
698
699	/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
700	#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK 0x00000700
701	#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT 8
702
703	/* NAND :: CONFIG :: reserved4 [07:00] */
704	#define BCHP_NAND_CONFIG_reserved4_MASK 0x000000ff
705	#define BCHP_NAND_CONFIG_reserved4_SHIFT 0
706
707	/***************************************************************************
708	*TIMING_1 - Nand Flash Timing Parameters 1
709	***************************************************************************/
710	/* NAND :: TIMING_1 :: tWP [31:28] */
711	#define BCHP_NAND_TIMING_1_tWP_MASK 0xf0000000
712	#define BCHP_NAND_TIMING_1_tWP_SHIFT 28
713	#define BCHP_NAND_TIMING_1_tWP_DEFAULT 0x00000006
714
715	/* NAND :: TIMING_1 :: tWH [27:24] */
716	#define BCHP_NAND_TIMING_1_tWH_MASK 0x0f000000
717	#define BCHP_NAND_TIMING_1_tWH_SHIFT 24
718	#define BCHP_NAND_TIMING_1_tWH_DEFAULT 0x00000005
719
720	/* NAND :: TIMING_1 :: tRP [23:20] */
721	#define BCHP_NAND_TIMING_1_tRP_MASK 0x00f00000
722	#define BCHP_NAND_TIMING_1_tRP_SHIFT 20
723	#define BCHP_NAND_TIMING_1_tRP_DEFAULT 0x00000007
724
725	/* NAND :: TIMING_1 :: tREH [19:16] */
726	#define BCHP_NAND_TIMING_1_tREH_MASK 0x000f0000
727	#define BCHP_NAND_TIMING_1_tREH_SHIFT 16
728	#define BCHP_NAND_TIMING_1_tREH_DEFAULT 0x00000004
729
730	/* NAND :: TIMING_1 :: tCS [15:12] */
731	#define BCHP_NAND_TIMING_1_tCS_MASK 0x0000f000
732	#define BCHP_NAND_TIMING_1_tCS_SHIFT 12
733	#define BCHP_NAND_TIMING_1_tCS_DEFAULT 0x00000008
734
735	/* NAND :: TIMING_1 :: tCLH [11:08] */
736	#define BCHP_NAND_TIMING_1_tCLH_MASK 0x00000f00
737	#define BCHP_NAND_TIMING_1_tCLH_SHIFT 8
738	#define BCHP_NAND_TIMING_1_tCLH_DEFAULT 0x00000004
739
740	/* NAND :: TIMING_1 :: tALH [07:04] */
741	#define BCHP_NAND_TIMING_1_tALH_MASK 0x000000f0
742	#define BCHP_NAND_TIMING_1_tALH_SHIFT 4
743	#define BCHP_NAND_TIMING_1_tALH_DEFAULT 0x00000005
744
745	/* NAND :: TIMING_1 :: tADL [03:00] */
746	#define BCHP_NAND_TIMING_1_tADL_MASK 0x0000000f
747	#define BCHP_NAND_TIMING_1_tADL_SHIFT 0
748	#define BCHP_NAND_TIMING_1_tADL_DEFAULT 0x0000000b
749
750	/***************************************************************************
751	*TIMING_2 - Nand Flash Timing Parameters 2
752	***************************************************************************/
753	/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
754	#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK 0x80000000
755	#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT 31
756	#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT 0x00000000
757	#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108 0
758	#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216 1
759
760	/* NAND :: TIMING_2 :: reserved0 [30:13] */
761	#define BCHP_NAND_TIMING_2_reserved0_MASK 0x7fffe000
762	#define BCHP_NAND_TIMING_2_reserved0_SHIFT 13
763
764	/* NAND :: TIMING_2 :: tWB [12:09] */
765	#define BCHP_NAND_TIMING_2_tWB_MASK 0x00001e00
766	#define BCHP_NAND_TIMING_2_tWB_SHIFT 9
767	#define BCHP_NAND_TIMING_2_tWB_DEFAULT 0x0000000f
768
769	/* NAND :: TIMING_2 :: tWHR [08:04] */
770	#define BCHP_NAND_TIMING_2_tWHR_MASK 0x000001f0
771	#define BCHP_NAND_TIMING_2_tWHR_SHIFT 4
772	#define BCHP_NAND_TIMING_2_tWHR_DEFAULT 0x00000009
773
774	/* NAND :: TIMING_2 :: tREAD [03:00] */
775	#define BCHP_NAND_TIMING_2_tREAD_MASK 0x0000000f
776	#define BCHP_NAND_TIMING_2_tREAD_SHIFT 0
777	#define BCHP_NAND_TIMING_2_tREAD_DEFAULT 0x00000006
778
779	/***************************************************************************
780	*SEMAPHORE - Semaphore
781	***************************************************************************/
782	/* NAND :: SEMAPHORE :: reserved0 [31:08] */
783	#define BCHP_NAND_SEMAPHORE_reserved0_MASK 0xffffff00
784	#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT 8
785
786	/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
787	#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK 0x000000ff
788	#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT 0
789	#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT 0x00000000
790
791	/***************************************************************************
792	*FLASH_DEVICE_ID - Nand Flash Device ID
793	***************************************************************************/
794	/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
795	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK 0xff000000
796	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT 24
797
798	/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
799	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK 0x00ff0000
800	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT 16
801
802	/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
803	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK 0x0000ff00
804	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT 8
805
806	/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
807	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK 0x000000ff
808	#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT 0
809
810	/***************************************************************************
811	*FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
812	***************************************************************************/
813	/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
814	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK 0xff000000
815	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT 24
816
817	/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
818	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK 0x00ff0000
819	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT 16
820
821	/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
822	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK 0x0000ff00
823	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT 8
824
825	/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
826	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK 0x000000ff
827	#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT 0
828
829	/***************************************************************************
830	*BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
831	***************************************************************************/
832	/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
833	#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK 0xffffff00
834	#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT 8
835
836	/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
837	#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK 0x000000ff
838	#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT 0
839	#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT 0x00000000
840
841	/***************************************************************************
842	*INTFC_STATUS - Nand Flash Interface Status
843	***************************************************************************/
844	/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
845	#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK 0x80000000
846	#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT 31
847
848	/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
849	#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK 0x40000000
850	#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT 30
851
852	/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
853	#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK 0x20000000
854	#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT 29
855
856	/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
857	#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK 0x10000000
858	#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT 28
859
860	/* NAND :: INTFC_STATUS :: ERASED [27:27] */
861	#define BCHP_NAND_INTFC_STATUS_ERASED_MASK 0x08000000
862	#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT 27
863
864	/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
865	#define BCHP_NAND_INTFC_STATUS_reserved0_MASK 0x07ffff00
866	#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT 8
867
868	/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
869	#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK 0x000000ff
870	#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT 0
871	#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT 0x00000000
872
873	/***************************************************************************
874	*ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
875	***************************************************************************/
876	/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
877	#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK 0xfff80000
878	#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT 19
879
880	/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
881	#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK 0x00070000
882	#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT 16
883	#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
884
885	/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
886	#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
887	#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT 0
888	#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
889
890	/***************************************************************************
891	*ECC_CORR_ADDR - ECC Correctable Error Address
892	***************************************************************************/
893	/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
894	#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK 0xffffffff
895	#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT 0
896	#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT 0x00000000
897
898	/***************************************************************************
899	*ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
900	***************************************************************************/
901	/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
902	#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK 0xfff80000
903	#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT 19
904
905	/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
906	#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK 0x00070000
907	#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT 16
908	#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
909
910	/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
911	#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
912	#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT 0
913	#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
914
915	/***************************************************************************
916	*ECC_UNC_ADDR - ECC Uncorrectable Error Address
917	***************************************************************************/
918	/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
919	#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK 0xffffffff
920	#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT 0
921	#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT 0x00000000
922
923	/***************************************************************************
924	*READ_ERROR_COUNT - Read Error Count
925	***************************************************************************/
926	/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
927	#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK 0xffffffff
928	#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT 0
929	#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT 0x00000000
930
931	/***************************************************************************
932	*CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
933	***************************************************************************/
934	/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
935	#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK 0xffffffe0
936	#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT 5
937
938	/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
939	#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK 0x0000001f
940	#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT 0
941	#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT 0x00000001
942
943	/***************************************************************************
944	*ONFI_STATUS - ONFI Status
945	***************************************************************************/
946	/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
947	#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK 0xf0000000
948	#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT 28
949	#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT 0x00000000
950
951	/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
952	#define BCHP_NAND_ONFI_STATUS_reserved0_MASK 0x0fffffc0
953	#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT 6
954
955	/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
956	#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK 0x00000020
957	#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT 5
958
959	/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
960	#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK 0x00000010
961	#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT 4
962
963	/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
964	#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK 0x00000008
965	#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT 3
966
967	/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
968	#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK 0x00000004
969	#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT 2
970
971	/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
972	#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK 0x00000002
973	#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT 1
974
975	/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
976	#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK 0x00000001
977	#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT 0
978
979	/***************************************************************************
980	*ONFI_DEBUG_DATA - ONFI Debug Data
981	***************************************************************************/
982	/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
983	#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK 0xffffffff
984	#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT 0
985
986	/***************************************************************************
987	*FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
988	***************************************************************************/
989	/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
990	#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK 0xfff80000
991	#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT 19
992
993	/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
994	#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
995	#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT 16
996	#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
997
998	/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
999	#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
1000	#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
1001	#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
1002
1003	/***************************************************************************
1004	*FLASH_READ_ADDR - Flash Read Data Address
1005	***************************************************************************/
1006	/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
1007	#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK 0xffffffff
1008	#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT 0
1009	#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT 0x00000000
1010
1011	/***************************************************************************
1012	*PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
1013	***************************************************************************/
1014	/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
1015	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK 0xfff80000
1016	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT 19
1017
1018	/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
1019	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK 0x00070000
1020	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT 16
1021	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
1022
1023	/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
1024	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
1025	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
1026	#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
1027
1028	/***************************************************************************
1029	*PROGRAM_PAGE_ADDR - Page Program Address
1030	***************************************************************************/
1031	/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
1032	#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK 0xffffffff
1033	#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT 0
1034	#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT 0x00000000
1035
1036	/***************************************************************************
1037	*COPY_BACK_EXT_ADDR - Copy Back Extended Address
1038	***************************************************************************/
1039	/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
1040	#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK 0xfff80000
1041	#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT 19
1042
1043	/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
1044	#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK 0x00070000
1045	#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT 16
1046	#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
1047
1048	/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
1049	#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
1050	#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT 0
1051	#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
1052
1053	/***************************************************************************
1054	*COPY_BACK_ADDR - Copy Back Address
1055	***************************************************************************/
1056	/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
1057	#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK 0xffffffff
1058	#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT 0
1059	#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT 0x00000000
1060
1061	/***************************************************************************
1062	*BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
1063	***************************************************************************/
1064	/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
1065	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK 0xfff80000
1066	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT 19
1067
1068	/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
1069	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK 0x00070000
1070	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT 16
1071	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
1072
1073	/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
1074	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
1075	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT 0
1076	#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
1077
1078	/***************************************************************************
1079	*BLOCK_ERASE_ADDR - Block Erase Address
1080	***************************************************************************/
1081	/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
1082	#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK 0xffffffff
1083	#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT 0
1084	#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT 0x00000000
1085
1086	/***************************************************************************
1087	*INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
1088	***************************************************************************/
1089	/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
1090	#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK 0xfff80000
1091	#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT 19
1092
1093	/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
1094	#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK 0x00070000
1095	#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT 16
1096	#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT 0x00000000
1097
1098	/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
1099	#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK 0x0000ffff
1100	#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT 0
1101	#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT 0x00000000
1102
1103	/***************************************************************************
1104	*INV_READ_ADDR - Flash Invalid Data Address
1105	***************************************************************************/
1106	/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
1107	#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK 0xffffffff
1108	#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT 0
1109	#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT 0x00000000
1110
1111	/***************************************************************************
1112	*BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
1113	***************************************************************************/
1114	/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
1115	#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK 0xffffffff
1116	#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT 0
1117	#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT 0x00000000
1118
1119	/***************************************************************************
1120	*ACC_CONTROL_CS1 - Nand Flash Access Control
1121	***************************************************************************/
1122	/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
1123	#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK 0x80000000
1124	#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT 31
1125	#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT 0x00000001
1126
1127	/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
1128	#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK 0x40000000
1129	#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT 30
1130	#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT 0x00000001
1131
1132	/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
1133	#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK 0x20000000
1134	#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT 29
1135
1136	/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
1137	#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK 0x10000000
1138	#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT 28
1139	#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT 0x00000001
1140
1141	/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
1142	#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK 0x08000000
1143	#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT 27
1144	#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT 0x00000000
1145
1146	/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
1147	#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK 0x04000000
1148	#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT 26
1149	#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT 0x00000001
1150
1151	/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
1152	#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK 0x02000000
1153	#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT 25
1154	#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT 0x00000001
1155
1156	/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
1157	#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK 0x01000000
1158	#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT 24
1159	#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT 0x00000001
1160
1161	/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
1162	#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK 0x00f00000
1163	#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT 20
1164
1165	/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
1166	#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK 0x000f0000
1167	#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT 16
1168	#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT 0x0000000f
1169
1170	/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
1171	#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK 0x0000ff80
1172	#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT 7
1173
1174	/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
1175	#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK 0x00000040
1176	#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT 6
1177	#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT 0x00000000
1178
1179	/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
1180	#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK 0x0000003f
1181	#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT 0
1182	#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT 0x00000010
1183
1184	/***************************************************************************
1185	*CONFIG_CS1 - Nand Flash Config
1186	***************************************************************************/
1187	/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
1188	#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK 0x80000000
1189	#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT 31
1190	#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT 0x00000000
1191
1192	/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
1193	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK 0x70000000
1194	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT 28
1195	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB 6
1196	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB 5
1197	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB 3
1198	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB 1
1199	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB 0
1200	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB 2
1201	#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB 4
1202
1203	/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
1204	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK 0x0f000000
1205	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT 24
1206	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB 0
1207	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB 1
1208	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB 2
1209	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB 3
1210	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB 4
1211	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB 5
1212	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB 6
1213	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB 7
1214	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB 8
1215	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB 9
1216	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB 10
1217	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB 11
1218	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB 12
1219	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB 13
1220	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB 14
1221	#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB 15
1222
1223	/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
1224	#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK 0x00800000
1225	#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT 23
1226	#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8 0
1227	#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16 1
1228
1229	/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
1230	#define BCHP_NAND_CONFIG_CS1_reserved0_MASK 0x00400000
1231	#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT 22
1232
1233	/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
1234	#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK 0x00300000
1235	#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT 20
1236	#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512 0
1237	#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB 1
1238	#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB 2
1239	#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB 3
1240
1241	/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
1242	#define BCHP_NAND_CONFIG_CS1_reserved1_MASK 0x00080000
1243	#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT 19
1244
1245	/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
1246	#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK 0x00070000
1247	#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT 16
1248
1249	/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
1250	#define BCHP_NAND_CONFIG_CS1_reserved2_MASK 0x00008000
1251	#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT 15
1252
1253	/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
1254	#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK 0x00007000
1255	#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT 12
1256
1257	/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
1258	#define BCHP_NAND_CONFIG_CS1_reserved3_MASK 0x00000800
1259	#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT 11
1260
1261	/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
1262	#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK 0x00000700
1263	#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT 8
1264
1265	/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
1266	#define BCHP_NAND_CONFIG_CS1_reserved4_MASK 0x000000ff
1267	#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT 0
1268
1269	/***************************************************************************
1270	*TIMING_1_CS1 - Nand Flash Timing Parameters 1
1271	***************************************************************************/
1272	/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
1273	#define BCHP_NAND_TIMING_1_CS1_tWP_MASK 0xf0000000
1274	#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT 28
1275	#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT 0x00000006
1276
1277	/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
1278	#define BCHP_NAND_TIMING_1_CS1_tWH_MASK 0x0f000000
1279	#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT 24
1280	#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT 0x00000005
1281
1282	/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
1283	#define BCHP_NAND_TIMING_1_CS1_tRP_MASK 0x00f00000
1284	#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT 20
1285	#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT 0x00000007
1286
1287	/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
1288	#define BCHP_NAND_TIMING_1_CS1_tREH_MASK 0x000f0000
1289	#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT 16
1290	#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT 0x00000004
1291
1292	/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
1293	#define BCHP_NAND_TIMING_1_CS1_tCS_MASK 0x0000f000
1294	#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT 12
1295	#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT 0x00000008
1296
1297	/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
1298	#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK 0x00000f00
1299	#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT 8
1300	#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT 0x00000004
1301
1302	/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
1303	#define BCHP_NAND_TIMING_1_CS1_tALH_MASK 0x000000f0
1304	#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT 4
1305	#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT 0x00000005
1306
1307	/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
1308	#define BCHP_NAND_TIMING_1_CS1_tADL_MASK 0x0000000f
1309	#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT 0
1310	#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT 0x0000000b
1311
1312	/***************************************************************************
1313	*TIMING_2_CS1 - Nand Flash Timing Parameters 2
1314	***************************************************************************/
1315	/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
1316	#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK 0x80000000
1317	#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT 31
1318	#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT 0x00000000
1319	#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108 0
1320	#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216 1
1321
1322	/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
1323	#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK 0x7fffe000
1324	#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT 13
1325
1326	/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
1327	#define BCHP_NAND_TIMING_2_CS1_tWB_MASK 0x00001e00
1328	#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT 9
1329	#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT 0x0000000f
1330
1331	/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
1332	#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK 0x000001f0
1333	#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT 4
1334	#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT 0x00000009
1335
1336	/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
1337	#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK 0x0000000f
1338	#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT 0
1339	#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT 0x00000006
1340
1341	/***************************************************************************
1342	*ACC_CONTROL_CS2 - Nand Flash Access Control
1343	***************************************************************************/
1344	/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
1345	#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK 0x80000000
1346	#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT 31
1347	#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT 0x00000001
1348
1349	/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
1350	#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK 0x40000000
1351	#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT 30
1352	#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT 0x00000001
1353
1354	/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
1355	#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK 0x20000000
1356	#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT 29
1357
1358	/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
1359	#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK 0x10000000
1360	#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT 28
1361	#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT 0x00000001
1362
1363	/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
1364	#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK 0x08000000
1365	#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT 27
1366	#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT 0x00000000
1367
1368	/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
1369	#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK 0x04000000
1370	#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT 26
1371	#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT 0x00000001
1372
1373	/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
1374	#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK 0x02000000
1375	#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT 25
1376	#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT 0x00000001
1377
1378	/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
1379	#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK 0x01000000
1380	#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT 24
1381	#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT 0x00000001
1382
1383	/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
1384	#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK 0x00f00000
1385	#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT 20
1386
1387	/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
1388	#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK 0x000f0000
1389	#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT 16
1390	#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT 0x0000000f
1391
1392	/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
1393	#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK 0x0000ff80
1394	#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT 7
1395
1396	/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
1397	#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK 0x00000040
1398	#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT 6
1399	#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT 0x00000000
1400
1401	/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
1402	#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK 0x0000003f
1403	#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT 0
1404	#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT 0x00000010
1405
1406	/***************************************************************************
1407	*CONFIG_CS2 - Nand Flash Config
1408	***************************************************************************/
1409	/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
1410	#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK 0x80000000
1411	#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT 31
1412	#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT 0x00000000
1413
1414	/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
1415	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK 0x70000000
1416	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT 28
1417	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB 6
1418	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB 5
1419	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB 3
1420	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB 1
1421	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB 0
1422	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB 2
1423	#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB 4
1424
1425	/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
1426	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK 0x0f000000
1427	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT 24
1428	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB 0
1429	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB 1
1430	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB 2
1431	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB 3
1432	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB 4
1433	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB 5
1434	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB 6
1435	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB 7
1436	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB 8
1437	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB 9
1438	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB 10
1439	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB 11
1440	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB 12
1441	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB 13
1442	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB 14
1443	#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB 15
1444
1445	/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
1446	#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK 0x00800000
1447	#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT 23
1448	#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8 0
1449	#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16 1
1450
1451	/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
1452	#define BCHP_NAND_CONFIG_CS2_reserved0_MASK 0x00400000
1453	#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT 22
1454
1455	/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
1456	#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK 0x00300000
1457	#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT 20
1458	#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512 0
1459	#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB 1
1460	#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB 2
1461	#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB 3
1462
1463	/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
1464	#define BCHP_NAND_CONFIG_CS2_reserved1_MASK 0x00080000
1465	#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT 19
1466
1467	/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
1468	#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK 0x00070000
1469	#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT 16
1470
1471	/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
1472	#define BCHP_NAND_CONFIG_CS2_reserved2_MASK 0x00008000
1473	#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT 15
1474
1475	/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
1476	#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK 0x00007000
1477	#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT 12
1478
1479	/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
1480	#define BCHP_NAND_CONFIG_CS2_reserved3_MASK 0x00000800
1481	#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT 11
1482
1483	/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
1484	#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK 0x00000700
1485	#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT 8
1486
1487	/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
1488	#define BCHP_NAND_CONFIG_CS2_reserved4_MASK 0x000000ff
1489	#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT 0
1490
1491	/***************************************************************************
1492	*TIMING_1_CS2 - Nand Flash Timing Parameters 1
1493	***************************************************************************/
1494	/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
1495	#define BCHP_NAND_TIMING_1_CS2_tWP_MASK 0xf0000000
1496	#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT 28
1497	#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT 0x00000006
1498
1499	/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
1500	#define BCHP_NAND_TIMING_1_CS2_tWH_MASK 0x0f000000
1501	#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT 24
1502	#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT 0x00000005
1503
1504	/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
1505	#define BCHP_NAND_TIMING_1_CS2_tRP_MASK 0x00f00000
1506	#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT 20
1507	#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT 0x00000007
1508
1509	/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
1510	#define BCHP_NAND_TIMING_1_CS2_tREH_MASK 0x000f0000
1511	#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT 16
1512	#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT 0x00000004
1513
1514	/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
1515	#define BCHP_NAND_TIMING_1_CS2_tCS_MASK 0x0000f000
1516	#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT 12
1517	#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT 0x00000008
1518
1519	/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
1520	#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK 0x00000f00
1521	#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT 8
1522	#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT 0x00000004
1523
1524	/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
1525	#define BCHP_NAND_TIMING_1_CS2_tALH_MASK 0x000000f0
1526	#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT 4
1527	#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT 0x00000005
1528
1529	/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
1530	#define BCHP_NAND_TIMING_1_CS2_tADL_MASK 0x0000000f
1531	#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT 0
1532	#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT 0x0000000b
1533
1534	/***************************************************************************
1535	*TIMING_2_CS2 - Nand Flash Timing Parameters 2
1536	***************************************************************************/
1537	/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
1538	#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK 0x80000000
1539	#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT 31
1540	#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT 0x00000000
1541	#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108 0
1542	#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216 1
1543
1544	/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
1545	#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK 0x7fffe000
1546	#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT 13
1547
1548	/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
1549	#define BCHP_NAND_TIMING_2_CS2_tWB_MASK 0x00001e00
1550	#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT 9
1551	#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT 0x0000000f
1552
1553	/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
1554	#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK 0x000001f0
1555	#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT 4
1556	#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT 0x00000009
1557
1558	/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
1559	#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK 0x0000000f
1560	#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT 0
1561	#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT 0x00000006
1562
1563	/***************************************************************************
1564	*ACC_CONTROL_CS3 - Nand Flash Access Control
1565	***************************************************************************/
1566	/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
1567	#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK 0x80000000
1568	#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT 31
1569	#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT 0x00000001
1570
1571	/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
1572	#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK 0x40000000
1573	#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT 30
1574	#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT 0x00000001
1575
1576	/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
1577	#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK 0x20000000
1578	#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT 29
1579
1580	/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
1581	#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK 0x10000000
1582	#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT 28
1583	#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT 0x00000001
1584
1585	/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
1586	#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK 0x08000000
1587	#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT 27
1588	#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT 0x00000000
1589
1590	/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
1591	#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK 0x04000000
1592	#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT 26
1593	#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT 0x00000001
1594
1595	/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
1596	#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK 0x02000000
1597	#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT 25
1598	#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT 0x00000001
1599
1600	/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
1601	#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK 0x01000000
1602	#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT 24
1603	#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT 0x00000001
1604
1605	/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
1606	#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK 0x00f00000
1607	#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT 20
1608
1609	/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
1610	#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK 0x000f0000
1611	#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT 16
1612	#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT 0x0000000f
1613
1614	/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
1615	#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK 0x0000ff80
1616	#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT 7
1617
1618	/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
1619	#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK 0x00000040
1620	#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT 6
1621	#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT 0x00000000
1622
1623	/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
1624	#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK 0x0000003f
1625	#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT 0
1626	#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT 0x00000010
1627
1628	/***************************************************************************
1629	*CONFIG_CS3 - Nand Flash Config
1630	***************************************************************************/
1631	/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
1632	#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK 0x80000000
1633	#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT 31
1634	#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT 0x00000000
1635
1636	/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
1637	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK 0x70000000
1638	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT 28
1639	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB 6
1640	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB 5
1641	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB 3
1642	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB 1
1643	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB 0
1644	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB 2
1645	#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB 4
1646
1647	/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
1648	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK 0x0f000000
1649	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT 24
1650	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB 0
1651	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB 1
1652	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB 2
1653	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB 3
1654	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB 4
1655	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB 5
1656	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB 6
1657	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB 7
1658	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB 8
1659	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB 9
1660	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB 10
1661	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB 11
1662	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB 12
1663	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB 13
1664	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB 14
1665	#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB 15
1666
1667	/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
1668	#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK 0x00800000
1669	#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT 23
1670	#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8 0
1671	#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16 1
1672
1673	/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
1674	#define BCHP_NAND_CONFIG_CS3_reserved0_MASK 0x00400000
1675	#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT 22
1676
1677	/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
1678	#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK 0x00300000
1679	#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT 20
1680	#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512 0
1681	#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB 1
1682	#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB 2
1683	#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB 3
1684
1685	/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
1686	#define BCHP_NAND_CONFIG_CS3_reserved1_MASK 0x00080000
1687	#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT 19
1688
1689	/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
1690	#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK 0x00070000
1691	#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT 16
1692
1693	/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
1694	#define BCHP_NAND_CONFIG_CS3_reserved2_MASK 0x00008000
1695	#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT 15
1696
1697	/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
1698	#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK 0x00007000
1699	#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT 12
1700
1701	/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
1702	#define BCHP_NAND_CONFIG_CS3_reserved3_MASK 0x00000800
1703	#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT 11
1704
1705	/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
1706	#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK 0x00000700
1707	#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT 8
1708
1709	/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
1710	#define BCHP_NAND_CONFIG_CS3_reserved4_MASK 0x000000ff
1711	#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT 0
1712
1713	/***************************************************************************
1714	*TIMING_1_CS3 - Nand Flash Timing Parameters 1
1715	***************************************************************************/
1716	/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
1717	#define BCHP_NAND_TIMING_1_CS3_tWP_MASK 0xf0000000
1718	#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT 28
1719	#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT 0x00000006
1720
1721	/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
1722	#define BCHP_NAND_TIMING_1_CS3_tWH_MASK 0x0f000000
1723	#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT 24
1724	#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT 0x00000005
1725
1726	/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
1727	#define BCHP_NAND_TIMING_1_CS3_tRP_MASK 0x00f00000
1728	#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT 20
1729	#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT 0x00000007
1730
1731	/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
1732	#define BCHP_NAND_TIMING_1_CS3_tREH_MASK 0x000f0000
1733	#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT 16
1734	#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT 0x00000004
1735
1736	/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
1737	#define BCHP_NAND_TIMING_1_CS3_tCS_MASK 0x0000f000
1738	#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT 12
1739	#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT 0x00000008
1740
1741	/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
1742	#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK 0x00000f00
1743	#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT 8
1744	#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT 0x00000004
1745
1746	/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
1747	#define BCHP_NAND_TIMING_1_CS3_tALH_MASK 0x000000f0
1748	#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT 4
1749	#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT 0x00000005
1750
1751	/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
1752	#define BCHP_NAND_TIMING_1_CS3_tADL_MASK 0x0000000f
1753	#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT 0
1754	#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT 0x0000000b
1755
1756	/***************************************************************************
1757	*TIMING_2_CS3 - Nand Flash Timing Parameters 2
1758	***************************************************************************/
1759	/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
1760	#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK 0x80000000
1761	#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT 31
1762	#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT 0x00000000
1763	#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108 0
1764	#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216 1
1765
1766	/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
1767	#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK 0x7fffe000
1768	#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT 13
1769
1770	/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
1771	#define BCHP_NAND_TIMING_2_CS3_tWB_MASK 0x00001e00
1772	#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT 9
1773	#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT 0x0000000f
1774
1775	/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
1776	#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK 0x000001f0
1777	#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT 4
1778	#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT 0x00000009
1779
1780	/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
1781	#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK 0x0000000f
1782	#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT 0
1783	#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT 0x00000006
1784
1785	/***************************************************************************
1786	*ACC_CONTROL_CS4 - Nand Flash Access Control
1787	***************************************************************************/
1788	/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
1789	#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK 0x80000000
1790	#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT 31
1791	#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT 0x00000001
1792
1793	/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
1794	#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK 0x40000000
1795	#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT 30
1796	#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT 0x00000001
1797
1798	/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
1799	#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK 0x20000000
1800	#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT 29
1801
1802	/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
1803	#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK 0x10000000
1804	#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT 28
1805	#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT 0x00000001
1806
1807	/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
1808	#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK 0x08000000
1809	#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT 27
1810	#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT 0x00000000
1811
1812	/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
1813	#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK 0x04000000
1814	#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT 26
1815	#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT 0x00000001
1816
1817	/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
1818	#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK 0x02000000
1819	#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT 25
1820	#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT 0x00000001
1821
1822	/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
1823	#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK 0x01000000
1824	#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT 24
1825	#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT 0x00000001
1826
1827	/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
1828	#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK 0x00f00000
1829	#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT 20
1830
1831	/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
1832	#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK 0x000f0000
1833	#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT 16
1834	#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT 0x0000000f
1835
1836	/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
1837	#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK 0x0000ff80
1838	#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT 7
1839
1840	/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
1841	#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK 0x00000040
1842	#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT 6
1843	#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT 0x00000000
1844
1845	/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
1846	#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK 0x0000003f
1847	#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT 0
1848	#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT 0x00000010
1849
1850	/***************************************************************************
1851	*CONFIG_CS4 - Nand Flash Config
1852	***************************************************************************/
1853	/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
1854	#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK 0x80000000
1855	#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT 31
1856	#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT 0x00000000
1857
1858	/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
1859	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK 0x70000000
1860	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT 28
1861	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB 6
1862	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB 5
1863	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB 3
1864	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB 1
1865	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB 0
1866	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB 2
1867	#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB 4
1868
1869	/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
1870	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK 0x0f000000
1871	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT 24
1872	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB 0
1873	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB 1
1874	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB 2
1875	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB 3
1876	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB 4
1877	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB 5
1878	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB 6
1879	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB 7
1880	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB 8
1881	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB 9
1882	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB 10
1883	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB 11
1884	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB 12
1885	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB 13
1886	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB 14
1887	#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB 15
1888
1889	/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
1890	#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK 0x00800000
1891	#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT 23
1892	#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8 0
1893	#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16 1
1894
1895	/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
1896	#define BCHP_NAND_CONFIG_CS4_reserved0_MASK 0x00400000
1897	#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT 22
1898
1899	/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
1900	#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK 0x00300000
1901	#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT 20
1902	#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512 0
1903	#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB 1
1904	#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB 2
1905	#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB 3
1906
1907	/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
1908	#define BCHP_NAND_CONFIG_CS4_reserved1_MASK 0x00080000
1909	#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT 19
1910
1911	/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
1912	#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK 0x00070000
1913	#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT 16
1914
1915	/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
1916	#define BCHP_NAND_CONFIG_CS4_reserved2_MASK 0x00008000
1917	#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT 15
1918
1919	/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
1920	#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK 0x00007000
1921	#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT 12
1922
1923	/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
1924	#define BCHP_NAND_CONFIG_CS4_reserved3_MASK 0x00000800
1925	#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT 11
1926
1927	/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
1928	#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK 0x00000700
1929	#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT 8
1930
1931	/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
1932	#define BCHP_NAND_CONFIG_CS4_reserved4_MASK 0x000000ff
1933	#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT 0
1934
1935	/***************************************************************************
1936	*TIMING_1_CS4 - Nand Flash Timing Parameters 1
1937	***************************************************************************/
1938	/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
1939	#define BCHP_NAND_TIMING_1_CS4_tWP_MASK 0xf0000000
1940	#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT 28
1941	#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT 0x00000006
1942
1943	/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
1944	#define BCHP_NAND_TIMING_1_CS4_tWH_MASK 0x0f000000
1945	#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT 24
1946	#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT 0x00000005
1947
1948	/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
1949	#define BCHP_NAND_TIMING_1_CS4_tRP_MASK 0x00f00000
1950	#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT 20
1951	#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT 0x00000007
1952
1953	/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
1954	#define BCHP_NAND_TIMING_1_CS4_tREH_MASK 0x000f0000
1955	#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT 16
1956	#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT 0x00000004
1957
1958	/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
1959	#define BCHP_NAND_TIMING_1_CS4_tCS_MASK 0x0000f000
1960	#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT 12
1961	#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT 0x00000008
1962
1963	/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
1964	#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK 0x00000f00
1965	#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT 8
1966	#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT 0x00000004
1967
1968	/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
1969	#define BCHP_NAND_TIMING_1_CS4_tALH_MASK 0x000000f0
1970	#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT 4
1971	#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT 0x00000005
1972
1973	/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
1974	#define BCHP_NAND_TIMING_1_CS4_tADL_MASK 0x0000000f
1975	#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT 0
1976	#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT 0x0000000b
1977
1978	/***************************************************************************
1979	*TIMING_2_CS4 - Nand Flash Timing Parameters 2
1980	***************************************************************************/
1981	/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
1982	#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK 0x80000000
1983	#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT 31
1984	#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT 0x00000000
1985	#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108 0
1986	#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216 1
1987
1988	/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
1989	#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK 0x7fffe000
1990	#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT 13
1991
1992	/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
1993	#define BCHP_NAND_TIMING_2_CS4_tWB_MASK 0x00001e00
1994	#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT 9
1995	#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT 0x0000000f
1996
1997	/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
1998	#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK 0x000001f0
1999	#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT 4
2000	#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT 0x00000009
2001
2002	/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
2003	#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK 0x0000000f
2004	#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT 0
2005	#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT 0x00000006
2006
2007	/***************************************************************************
2008	*SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
2009	***************************************************************************/
2010	/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
2011	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK 0xff000000
2012	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT 24
2013	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
2014
2015	/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
2016	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
2017	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT 16
2018	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
2019
2020	/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
2021	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
2022	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT 8
2023	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
2024
2025	/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
2026	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK 0x000000ff
2027	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT 0
2028	#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
2029
2030	/***************************************************************************
2031	*SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
2032	***************************************************************************/
2033	/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
2034	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK 0xff000000
2035	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT 24
2036	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
2037
2038	/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
2039	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
2040	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT 16
2041	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
2042
2043	/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
2044	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
2045	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT 8
2046	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
2047
2048	/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
2049	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK 0x000000ff
2050	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT 0
2051	#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
2052
2053	/***************************************************************************
2054	*SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
2055	***************************************************************************/
2056	/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
2057	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK 0xff000000
2058	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT 24
2059	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
2060
2061	/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
2062	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
2063	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT 16
2064	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
2065
2066	/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
2067	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
2068	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT 8
2069	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
2070
2071	/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
2072	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK 0x000000ff
2073	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT 0
2074	#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
2075
2076	/***************************************************************************
2077	*SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
2078	***************************************************************************/
2079	/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
2080	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK 0xff000000
2081	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT 24
2082	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
2083
2084	/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
2085	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
2086	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT 16
2087	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
2088
2089	/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
2090	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
2091	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT 8
2092	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
2093
2094	/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
2095	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
2096	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT 0
2097	#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
2098
2099	/***************************************************************************
2100	*SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
2101	***************************************************************************/
2102	/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
2103	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK 0xff000000
2104	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT 24
2105	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT 0x000000ff
2106
2107	/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
2108	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK 0x00ff0000
2109	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT 16
2110	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT 0x000000ff
2111
2112	/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
2113	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK 0x0000ff00
2114	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT 8
2115	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT 0x000000ff
2116
2117	/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
2118	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK 0x000000ff
2119	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT 0
2120	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT 0x000000ff
2121
2122	/***************************************************************************
2123	*SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
2124	***************************************************************************/
2125	/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
2126	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK 0xff000000
2127	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT 24
2128	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT 0x000000ff
2129
2130	/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
2131	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK 0x00ff0000
2132	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT 16
2133	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT 0x000000ff
2134
2135	/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
2136	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK 0x0000ff00
2137	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT 8
2138	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT 0x000000ff
2139
2140	/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
2141	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK 0x000000ff
2142	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT 0
2143	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT 0x000000ff
2144
2145	/***************************************************************************
2146	*SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
2147	***************************************************************************/
2148	/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
2149	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK 0xff000000
2150	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT 24
2151	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT 0x000000ff
2152
2153	/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
2154	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK 0x00ff0000
2155	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT 16
2156	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT 0x000000ff
2157
2158	/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
2159	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK 0x0000ff00
2160	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT 8
2161	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT 0x000000ff
2162
2163	/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
2164	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK 0x000000ff
2165	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT 0
2166	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT 0x000000ff
2167
2168	/***************************************************************************
2169	*SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
2170	***************************************************************************/
2171	/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
2172	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK 0xff000000
2173	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT 24
2174	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT 0x000000ff
2175
2176	/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
2177	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK 0x00ff0000
2178	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT 16
2179	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT 0x000000ff
2180
2181	/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
2182	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK 0x0000ff00
2183	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT 8
2184	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT 0x000000ff
2185
2186	/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
2187	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK 0x000000ff
2188	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT 0
2189	#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT 0x000000ff
2190
2191	/***************************************************************************
2192	*LL_OP - Nand Flash Low Level Operation
2193	***************************************************************************/
2194	/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
2195	#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK 0x80000000
2196	#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT 31
2197	#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT 0x00000000
2198
2199	/* NAND :: LL_OP :: reserved0 [30:20] */
2200	#define BCHP_NAND_LL_OP_reserved0_MASK 0x7ff00000
2201	#define BCHP_NAND_LL_OP_reserved0_SHIFT 20
2202
2203	/* NAND :: LL_OP :: CLE [19:19] */
2204	#define BCHP_NAND_LL_OP_CLE_MASK 0x00080000
2205	#define BCHP_NAND_LL_OP_CLE_SHIFT 19
2206	#define BCHP_NAND_LL_OP_CLE_DEFAULT 0x00000000
2207
2208	/* NAND :: LL_OP :: ALE [18:18] */
2209	#define BCHP_NAND_LL_OP_ALE_MASK 0x00040000
2210	#define BCHP_NAND_LL_OP_ALE_SHIFT 18
2211	#define BCHP_NAND_LL_OP_ALE_DEFAULT 0x00000000
2212
2213	/* NAND :: LL_OP :: WE [17:17] */
2214	#define BCHP_NAND_LL_OP_WE_MASK 0x00020000
2215	#define BCHP_NAND_LL_OP_WE_SHIFT 17
2216	#define BCHP_NAND_LL_OP_WE_DEFAULT 0x00000000
2217
2218	/* NAND :: LL_OP :: RE [16:16] */
2219	#define BCHP_NAND_LL_OP_RE_MASK 0x00010000
2220	#define BCHP_NAND_LL_OP_RE_SHIFT 16
2221	#define BCHP_NAND_LL_OP_RE_DEFAULT 0x00000000
2222
2223	/* NAND :: LL_OP :: DATA [15:00] */
2224	#define BCHP_NAND_LL_OP_DATA_MASK 0x0000ffff
2225	#define BCHP_NAND_LL_OP_DATA_SHIFT 0
2226	#define BCHP_NAND_LL_OP_DATA_DEFAULT 0x00000000
2227
2228	/***************************************************************************
2229	*LL_RDDATA - Nand Flash Low Level Read Data
2230	***************************************************************************/
2231	/* NAND :: LL_RDDATA :: reserved0 [31:16] */
2232	#define BCHP_NAND_LL_RDDATA_reserved0_MASK 0xffff0000
2233	#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT 16
2234
2235	/* NAND :: LL_RDDATA :: DATA [15:00] */
2236	#define BCHP_NAND_LL_RDDATA_DATA_MASK 0x0000ffff
2237	#define BCHP_NAND_LL_RDDATA_DATA_SHIFT 0
2238	#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT 0x00000000
2239
2240	/***************************************************************************
2241	*FLASH_CACHE%i - Flash Cache Buffer Read Access
2242	***************************************************************************/
2243	#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE 0x00412a00
2244	#define BCHP_NAND_FLASH_CACHEi_ARRAY_START 0
2245	#define BCHP_NAND_FLASH_CACHEi_ARRAY_END 127
2246	#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE 32
2247
2248	/***************************************************************************
2249	*FLASH_CACHE%i - Flash Cache Buffer Read Access
2250	***************************************************************************/
2251	/* NAND :: FLASH_CACHEi :: WORD [31:00] */
2252	#define BCHP_NAND_FLASH_CACHEi_WORD_MASK 0xffffffff
2253	#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT 0
2254
2255
2256	#endif /* #ifndef BCHP_NAND_H__ */
2257
2258	/* End of File */

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source: svn/newcon3bcm2_21bu/magnum/basemodules/chp/7552/rdb/b0/bchp_nand.h

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