| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_pm.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/3 $ |
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| 13 | * $brcm_Date: 2/7/12 1:36p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Tue Feb 7 10:59:54 2012 |
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| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_pm.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/3 2/7/12 1:36p pntruong |
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| 36 | * SW7552-89: Synced up with central rdb. |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_PM_H__ |
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| 41 | #define BCHP_PM_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *PM - Peripheral Module Configuration |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_PM_CONFIG 0x00406180 /* PERIPHERAL MODULE CONFIGURATION REGISTER */ |
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| 47 | #define BCHP_PM_CLK_CTRL 0x00406184 /* UPG Clock control register */ |
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| 48 | #define BCHP_PM_RST_CTRL 0x00406188 /* UPG reset control register */ |
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| 49 | |
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| 50 | /*************************************************************************** |
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| 51 | *CONFIG - PERIPHERAL MODULE CONFIGURATION REGISTER |
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| 52 | ***************************************************************************/ |
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| 53 | /* PM :: CONFIG :: reserved_for_eco0 [31:23] */ |
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| 54 | #define BCHP_PM_CONFIG_reserved_for_eco0_MASK 0xff800000 |
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| 55 | #define BCHP_PM_CONFIG_reserved_for_eco0_SHIFT 23 |
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| 56 | #define BCHP_PM_CONFIG_reserved_for_eco0_DEFAULT 0x00000000 |
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| 57 | |
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| 58 | /* PM :: CONFIG :: uart_enable_busy_detect [22:22] */ |
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| 59 | #define BCHP_PM_CONFIG_uart_enable_busy_detect_MASK 0x00400000 |
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| 60 | #define BCHP_PM_CONFIG_uart_enable_busy_detect_SHIFT 22 |
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| 61 | #define BCHP_PM_CONFIG_uart_enable_busy_detect_DEFAULT 0x00000000 |
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| 62 | |
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| 63 | /* PM :: CONFIG :: uart_disable_busy_wr [21:21] */ |
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| 64 | #define BCHP_PM_CONFIG_uart_disable_busy_wr_MASK 0x00200000 |
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| 65 | #define BCHP_PM_CONFIG_uart_disable_busy_wr_SHIFT 21 |
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| 66 | #define BCHP_PM_CONFIG_uart_disable_busy_wr_DEFAULT 0x00000000 |
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| 67 | |
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| 68 | /* PM :: CONFIG :: reserved1 [20:16] */ |
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| 69 | #define BCHP_PM_CONFIG_reserved1_MASK 0x001f0000 |
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| 70 | #define BCHP_PM_CONFIG_reserved1_SHIFT 16 |
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| 71 | |
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| 72 | /* PM :: CONFIG :: uart_clk_sel [15:15] */ |
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| 73 | #define BCHP_PM_CONFIG_uart_clk_sel_MASK 0x00008000 |
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| 74 | #define BCHP_PM_CONFIG_uart_clk_sel_SHIFT 15 |
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| 75 | #define BCHP_PM_CONFIG_uart_clk_sel_DEFAULT 0x00000000 |
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| 76 | |
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| 77 | /* PM :: CONFIG :: uart_sw_reset [14:14] */ |
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| 78 | #define BCHP_PM_CONFIG_uart_sw_reset_MASK 0x00004000 |
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| 79 | #define BCHP_PM_CONFIG_uart_sw_reset_SHIFT 14 |
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| 80 | #define BCHP_PM_CONFIG_uart_sw_reset_DEFAULT 0x00000000 |
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| 81 | |
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| 82 | /* PM :: CONFIG :: reserved_for_eco2 [13:11] */ |
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| 83 | #define BCHP_PM_CONFIG_reserved_for_eco2_MASK 0x00003800 |
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| 84 | #define BCHP_PM_CONFIG_reserved_for_eco2_SHIFT 11 |
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| 85 | #define BCHP_PM_CONFIG_reserved_for_eco2_DEFAULT 0x00000000 |
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| 86 | |
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| 87 | /* PM :: CONFIG :: mcif_sw_init [10:10] */ |
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| 88 | #define BCHP_PM_CONFIG_mcif_sw_init_MASK 0x00000400 |
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| 89 | #define BCHP_PM_CONFIG_mcif_sw_init_SHIFT 10 |
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| 90 | #define BCHP_PM_CONFIG_mcif_sw_init_DEFAULT 0x00000000 |
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| 91 | |
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| 92 | /* PM :: CONFIG :: mcif_sw_reset [09:09] */ |
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| 93 | #define BCHP_PM_CONFIG_mcif_sw_reset_MASK 0x00000200 |
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| 94 | #define BCHP_PM_CONFIG_mcif_sw_reset_SHIFT 9 |
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| 95 | #define BCHP_PM_CONFIG_mcif_sw_reset_DEFAULT 0x00000000 |
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| 96 | |
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| 97 | /* PM :: CONFIG :: sc_late_sw_reset [08:08] */ |
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| 98 | #define BCHP_PM_CONFIG_sc_late_sw_reset_MASK 0x00000100 |
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| 99 | #define BCHP_PM_CONFIG_sc_late_sw_reset_SHIFT 8 |
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| 100 | #define BCHP_PM_CONFIG_sc_late_sw_reset_DEFAULT 0x00000000 |
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| 101 | |
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| 102 | /* PM :: CONFIG :: sc_sw_reset [07:07] */ |
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| 103 | #define BCHP_PM_CONFIG_sc_sw_reset_MASK 0x00000080 |
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| 104 | #define BCHP_PM_CONFIG_sc_sw_reset_SHIFT 7 |
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| 105 | #define BCHP_PM_CONFIG_sc_sw_reset_DEFAULT 0x00000000 |
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| 106 | |
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| 107 | /* PM :: CONFIG :: reserved_for_eco3 [06:00] */ |
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| 108 | #define BCHP_PM_CONFIG_reserved_for_eco3_MASK 0x0000007f |
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| 109 | #define BCHP_PM_CONFIG_reserved_for_eco3_SHIFT 0 |
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| 110 | #define BCHP_PM_CONFIG_reserved_for_eco3_DEFAULT 0x00000000 |
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| 111 | |
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| 112 | /*************************************************************************** |
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| 113 | *CLK_CTRL - UPG Clock control register |
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| 114 | ***************************************************************************/ |
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| 115 | /* PM :: CLK_CTRL :: reserved0 [31:18] */ |
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| 116 | #define BCHP_PM_CLK_CTRL_reserved0_MASK 0xfffc0000 |
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| 117 | #define BCHP_PM_CLK_CTRL_reserved0_SHIFT 18 |
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| 118 | |
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| 119 | /* PM :: CLK_CTRL :: tmon [17:17] */ |
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| 120 | #define BCHP_PM_CLK_CTRL_tmon_MASK 0x00020000 |
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| 121 | #define BCHP_PM_CLK_CTRL_tmon_SHIFT 17 |
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| 122 | #define BCHP_PM_CLK_CTRL_tmon_DEFAULT 0x00000001 |
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| 123 | |
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| 124 | /* PM :: CLK_CTRL :: timer [16:16] */ |
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| 125 | #define BCHP_PM_CLK_CTRL_timer_MASK 0x00010000 |
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| 126 | #define BCHP_PM_CLK_CTRL_timer_SHIFT 16 |
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| 127 | #define BCHP_PM_CLK_CTRL_timer_DEFAULT 0x00000001 |
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| 128 | |
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| 129 | /* PM :: CLK_CTRL :: gpio [15:15] */ |
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| 130 | #define BCHP_PM_CLK_CTRL_gpio_MASK 0x00008000 |
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| 131 | #define BCHP_PM_CLK_CTRL_gpio_SHIFT 15 |
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| 132 | #define BCHP_PM_CLK_CTRL_gpio_DEFAULT 0x00000001 |
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| 133 | |
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| 134 | /* PM :: CLK_CTRL :: reserved_for_eco1 [14:10] */ |
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| 135 | #define BCHP_PM_CLK_CTRL_reserved_for_eco1_MASK 0x00007c00 |
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| 136 | #define BCHP_PM_CLK_CTRL_reserved_for_eco1_SHIFT 10 |
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| 137 | #define BCHP_PM_CLK_CTRL_reserved_for_eco1_DEFAULT 0x00000000 |
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| 138 | |
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| 139 | /* PM :: CLK_CTRL :: pwmb [09:09] */ |
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| 140 | #define BCHP_PM_CLK_CTRL_pwmb_MASK 0x00000200 |
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| 141 | #define BCHP_PM_CLK_CTRL_pwmb_SHIFT 9 |
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| 142 | #define BCHP_PM_CLK_CTRL_pwmb_DEFAULT 0x00000001 |
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| 143 | |
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| 144 | /* PM :: CLK_CTRL :: pwma [08:08] */ |
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| 145 | #define BCHP_PM_CLK_CTRL_pwma_MASK 0x00000100 |
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| 146 | #define BCHP_PM_CLK_CTRL_pwma_SHIFT 8 |
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| 147 | #define BCHP_PM_CLK_CTRL_pwma_DEFAULT 0x00000001 |
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| 148 | |
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| 149 | /* PM :: CLK_CTRL :: reserved_for_eco2 [07:05] */ |
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| 150 | #define BCHP_PM_CLK_CTRL_reserved_for_eco2_MASK 0x000000e0 |
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| 151 | #define BCHP_PM_CLK_CTRL_reserved_for_eco2_SHIFT 5 |
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| 152 | #define BCHP_PM_CLK_CTRL_reserved_for_eco2_DEFAULT 0x00000000 |
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| 153 | |
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| 154 | /* PM :: CLK_CTRL :: bscc [04:04] */ |
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| 155 | #define BCHP_PM_CLK_CTRL_bscc_MASK 0x00000010 |
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| 156 | #define BCHP_PM_CLK_CTRL_bscc_SHIFT 4 |
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| 157 | #define BCHP_PM_CLK_CTRL_bscc_DEFAULT 0x00000001 |
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| 158 | |
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| 159 | /* PM :: CLK_CTRL :: bscb [03:03] */ |
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| 160 | #define BCHP_PM_CLK_CTRL_bscb_MASK 0x00000008 |
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| 161 | #define BCHP_PM_CLK_CTRL_bscb_SHIFT 3 |
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| 162 | #define BCHP_PM_CLK_CTRL_bscb_DEFAULT 0x00000001 |
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| 163 | |
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| 164 | /* PM :: CLK_CTRL :: bsca [02:02] */ |
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| 165 | #define BCHP_PM_CLK_CTRL_bsca_MASK 0x00000004 |
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| 166 | #define BCHP_PM_CLK_CTRL_bsca_SHIFT 2 |
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| 167 | #define BCHP_PM_CLK_CTRL_bsca_DEFAULT 0x00000001 |
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| 168 | |
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| 169 | /* PM :: CLK_CTRL :: reserved_for_eco3 [01:01] */ |
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| 170 | #define BCHP_PM_CLK_CTRL_reserved_for_eco3_MASK 0x00000002 |
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| 171 | #define BCHP_PM_CLK_CTRL_reserved_for_eco3_SHIFT 1 |
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| 172 | #define BCHP_PM_CLK_CTRL_reserved_for_eco3_DEFAULT 0x00000000 |
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| 173 | |
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| 174 | /* PM :: CLK_CTRL :: irb [00:00] */ |
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| 175 | #define BCHP_PM_CLK_CTRL_irb_MASK 0x00000001 |
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| 176 | #define BCHP_PM_CLK_CTRL_irb_SHIFT 0 |
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| 177 | #define BCHP_PM_CLK_CTRL_irb_DEFAULT 0x00000001 |
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| 178 | |
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| 179 | /*************************************************************************** |
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| 180 | *RST_CTRL - UPG reset control register |
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| 181 | ***************************************************************************/ |
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| 182 | /* PM :: RST_CTRL :: reserved0 [31:18] */ |
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| 183 | #define BCHP_PM_RST_CTRL_reserved0_MASK 0xfffc0000 |
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| 184 | #define BCHP_PM_RST_CTRL_reserved0_SHIFT 18 |
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| 185 | |
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| 186 | /* PM :: RST_CTRL :: tmon [17:17] */ |
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| 187 | #define BCHP_PM_RST_CTRL_tmon_MASK 0x00020000 |
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| 188 | #define BCHP_PM_RST_CTRL_tmon_SHIFT 17 |
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| 189 | #define BCHP_PM_RST_CTRL_tmon_DEFAULT 0x00000000 |
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| 190 | |
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| 191 | /* PM :: RST_CTRL :: timer [16:16] */ |
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| 192 | #define BCHP_PM_RST_CTRL_timer_MASK 0x00010000 |
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| 193 | #define BCHP_PM_RST_CTRL_timer_SHIFT 16 |
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| 194 | #define BCHP_PM_RST_CTRL_timer_DEFAULT 0x00000000 |
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| 195 | |
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| 196 | /* PM :: RST_CTRL :: gpio [15:15] */ |
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| 197 | #define BCHP_PM_RST_CTRL_gpio_MASK 0x00008000 |
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| 198 | #define BCHP_PM_RST_CTRL_gpio_SHIFT 15 |
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| 199 | #define BCHP_PM_RST_CTRL_gpio_DEFAULT 0x00000000 |
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| 200 | |
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| 201 | /* PM :: RST_CTRL :: reserved_for_eco1 [14:10] */ |
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| 202 | #define BCHP_PM_RST_CTRL_reserved_for_eco1_MASK 0x00007c00 |
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| 203 | #define BCHP_PM_RST_CTRL_reserved_for_eco1_SHIFT 10 |
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| 204 | #define BCHP_PM_RST_CTRL_reserved_for_eco1_DEFAULT 0x00000000 |
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| 205 | |
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| 206 | /* PM :: RST_CTRL :: pwmb [09:09] */ |
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| 207 | #define BCHP_PM_RST_CTRL_pwmb_MASK 0x00000200 |
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| 208 | #define BCHP_PM_RST_CTRL_pwmb_SHIFT 9 |
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| 209 | #define BCHP_PM_RST_CTRL_pwmb_DEFAULT 0x00000000 |
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| 210 | |
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| 211 | /* PM :: RST_CTRL :: pwma [08:08] */ |
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| 212 | #define BCHP_PM_RST_CTRL_pwma_MASK 0x00000100 |
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| 213 | #define BCHP_PM_RST_CTRL_pwma_SHIFT 8 |
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| 214 | #define BCHP_PM_RST_CTRL_pwma_DEFAULT 0x00000000 |
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| 215 | |
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| 216 | /* PM :: RST_CTRL :: reserved_for_eco2 [07:05] */ |
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| 217 | #define BCHP_PM_RST_CTRL_reserved_for_eco2_MASK 0x000000e0 |
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| 218 | #define BCHP_PM_RST_CTRL_reserved_for_eco2_SHIFT 5 |
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| 219 | #define BCHP_PM_RST_CTRL_reserved_for_eco2_DEFAULT 0x00000000 |
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| 220 | |
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| 221 | /* PM :: RST_CTRL :: bscc [04:04] */ |
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| 222 | #define BCHP_PM_RST_CTRL_bscc_MASK 0x00000010 |
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| 223 | #define BCHP_PM_RST_CTRL_bscc_SHIFT 4 |
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| 224 | #define BCHP_PM_RST_CTRL_bscc_DEFAULT 0x00000000 |
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| 225 | |
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| 226 | /* PM :: RST_CTRL :: bscb [03:03] */ |
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| 227 | #define BCHP_PM_RST_CTRL_bscb_MASK 0x00000008 |
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| 228 | #define BCHP_PM_RST_CTRL_bscb_SHIFT 3 |
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| 229 | #define BCHP_PM_RST_CTRL_bscb_DEFAULT 0x00000000 |
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| 230 | |
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| 231 | /* PM :: RST_CTRL :: bsca [02:02] */ |
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| 232 | #define BCHP_PM_RST_CTRL_bsca_MASK 0x00000004 |
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| 233 | #define BCHP_PM_RST_CTRL_bsca_SHIFT 2 |
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| 234 | #define BCHP_PM_RST_CTRL_bsca_DEFAULT 0x00000000 |
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| 235 | |
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| 236 | /* PM :: RST_CTRL :: reserved_for_eco3 [01:01] */ |
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| 237 | #define BCHP_PM_RST_CTRL_reserved_for_eco3_MASK 0x00000002 |
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| 238 | #define BCHP_PM_RST_CTRL_reserved_for_eco3_SHIFT 1 |
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| 239 | #define BCHP_PM_RST_CTRL_reserved_for_eco3_DEFAULT 0x00000000 |
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| 240 | |
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| 241 | /* PM :: RST_CTRL :: irb [00:00] */ |
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| 242 | #define BCHP_PM_RST_CTRL_irb_MASK 0x00000001 |
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| 243 | #define BCHP_PM_RST_CTRL_irb_SHIFT 0 |
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| 244 | #define BCHP_PM_RST_CTRL_irb_DEFAULT 0x00000000 |
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| 245 | |
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| 246 | #endif /* #ifndef BCHP_PM_H__ */ |
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| 247 | |
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| 248 | /* End of File */ |
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