| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_sdadc.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/3 $ |
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| 13 | * $brcm_Date: 2/7/12 1:39p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Tue Feb 7 10:59:54 2012 |
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| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_sdadc.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/3 2/7/12 1:39p pntruong |
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| 36 | * SW7552-89: Synced up with central rdb. |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_SDADC_H__ |
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| 41 | #define BCHP_SDADC_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *SDADC - UFE SDADC Register Set |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_SDADC_CTRL_SYS0 0x00c00200 /* Misc. top level controls */ |
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| 47 | #define BCHP_SDADC_CTRL_SYS1 0x00c00204 /* Misc. top level controls */ |
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| 48 | #define BCHP_SDADC_CTRL_PWRUP 0x00c00208 /* Power up controls */ |
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| 49 | #define BCHP_SDADC_CTRL_RESET 0x00c0020c /* Reset controls */ |
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| 50 | #define BCHP_SDADC_CTRL_ICH 0x00c00210 /* I-channel ADC controls */ |
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| 51 | #define BCHP_SDADC_CTRL_QCH 0x00c00214 /* Q-channel ADC controls */ |
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| 52 | #define BCHP_SDADC_STATUS_ICH 0x00c00218 /* I-channel ADC status */ |
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| 53 | #define BCHP_SDADC_STATUS_QCH 0x00c0021c /* Q-channel ADC status */ |
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| 54 | |
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| 55 | /*************************************************************************** |
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| 56 | *CTRL_SYS0 - Misc. top level controls |
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| 57 | ***************************************************************************/ |
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| 58 | /* SDADC :: CTRL_SYS0 :: i_adcclk_reset [31:31] */ |
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| 59 | #define BCHP_SDADC_CTRL_SYS0_i_adcclk_reset_MASK 0x80000000 |
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| 60 | #define BCHP_SDADC_CTRL_SYS0_i_adcclk_reset_SHIFT 31 |
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| 61 | #define BCHP_SDADC_CTRL_SYS0_i_adcclk_reset_DEFAULT 0x00000000 |
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| 62 | |
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| 63 | /* SDADC :: CTRL_SYS0 :: i_adcclk_inv [30:30] */ |
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| 64 | #define BCHP_SDADC_CTRL_SYS0_i_adcclk_inv_MASK 0x40000000 |
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| 65 | #define BCHP_SDADC_CTRL_SYS0_i_adcclk_inv_SHIFT 30 |
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| 66 | #define BCHP_SDADC_CTRL_SYS0_i_adcclk_inv_DEFAULT 0x00000000 |
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| 67 | |
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| 68 | /* SDADC :: CTRL_SYS0 :: i_ctl_adc_bias [29:10] */ |
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| 69 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_adc_bias_MASK 0x3ffffc00 |
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| 70 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_adc_bias_SHIFT 10 |
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| 71 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_adc_bias_DEFAULT 0x00000000 |
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| 72 | |
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| 73 | /* SDADC :: CTRL_SYS0 :: i_ctl_vcm [09:08] */ |
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| 74 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_vcm_MASK 0x00000300 |
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| 75 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_vcm_SHIFT 8 |
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| 76 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_vcm_DEFAULT 0x00000000 |
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| 77 | |
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| 78 | /* SDADC :: CTRL_SYS0 :: i_ctl_rc [07:05] */ |
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| 79 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_rc_MASK 0x000000e0 |
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| 80 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_rc_SHIFT 5 |
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| 81 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_rc_DEFAULT 0x00000000 |
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| 82 | |
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| 83 | /* SDADC :: CTRL_SYS0 :: i_ctl_flash_fullscale [04:03] */ |
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| 84 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_flash_fullscale_MASK 0x00000018 |
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| 85 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_flash_fullscale_SHIFT 3 |
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| 86 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_flash_fullscale_DEFAULT 0x00000000 |
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| 87 | |
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| 88 | /* SDADC :: CTRL_SYS0 :: i_ctl_adc_gain [02:00] */ |
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| 89 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_adc_gain_MASK 0x00000007 |
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| 90 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_adc_gain_SHIFT 0 |
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| 91 | #define BCHP_SDADC_CTRL_SYS0_i_ctl_adc_gain_DEFAULT 0x00000000 |
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| 92 | |
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| 93 | /*************************************************************************** |
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| 94 | *CTRL_SYS1 - Misc. top level controls |
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| 95 | ***************************************************************************/ |
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| 96 | /* SDADC :: CTRL_SYS1 :: i_ctl_adc_dly [31:26] */ |
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| 97 | #define BCHP_SDADC_CTRL_SYS1_i_ctl_adc_dly_MASK 0xfc000000 |
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| 98 | #define BCHP_SDADC_CTRL_SYS1_i_ctl_adc_dly_SHIFT 26 |
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| 99 | #define BCHP_SDADC_CTRL_SYS1_i_ctl_adc_dly_DEFAULT 0x00000000 |
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| 100 | |
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| 101 | /* SDADC :: CTRL_SYS1 :: i_ctl_adc_spare [25:16] */ |
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| 102 | #define BCHP_SDADC_CTRL_SYS1_i_ctl_adc_spare_MASK 0x03ff0000 |
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| 103 | #define BCHP_SDADC_CTRL_SYS1_i_ctl_adc_spare_SHIFT 16 |
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| 104 | #define BCHP_SDADC_CTRL_SYS1_i_ctl_adc_spare_DEFAULT 0x00000000 |
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| 105 | |
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| 106 | /* SDADC :: CTRL_SYS1 :: i_clk_sel [15:15] */ |
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| 107 | #define BCHP_SDADC_CTRL_SYS1_i_clk_sel_MASK 0x00008000 |
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| 108 | #define BCHP_SDADC_CTRL_SYS1_i_clk_sel_SHIFT 15 |
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| 109 | #define BCHP_SDADC_CTRL_SYS1_i_clk_sel_DEFAULT 0x00000000 |
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| 110 | |
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| 111 | /* SDADC :: CTRL_SYS1 :: i_rst_n [14:14] */ |
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| 112 | #define BCHP_SDADC_CTRL_SYS1_i_rst_n_MASK 0x00004000 |
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| 113 | #define BCHP_SDADC_CTRL_SYS1_i_rst_n_SHIFT 14 |
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| 114 | #define BCHP_SDADC_CTRL_SYS1_i_rst_n_DEFAULT 0x00000001 |
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| 115 | |
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| 116 | /* SDADC :: CTRL_SYS1 :: i_cntr_enable [13:13] */ |
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| 117 | #define BCHP_SDADC_CTRL_SYS1_i_cntr_enable_MASK 0x00002000 |
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| 118 | #define BCHP_SDADC_CTRL_SYS1_i_cntr_enable_SHIFT 13 |
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| 119 | #define BCHP_SDADC_CTRL_SYS1_i_cntr_enable_DEFAULT 0x00000000 |
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| 120 | |
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| 121 | /* SDADC :: CTRL_SYS1 :: i_cntr_select [12:12] */ |
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| 122 | #define BCHP_SDADC_CTRL_SYS1_i_cntr_select_MASK 0x00001000 |
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| 123 | #define BCHP_SDADC_CTRL_SYS1_i_cntr_select_SHIFT 12 |
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| 124 | #define BCHP_SDADC_CTRL_SYS1_i_cntr_select_DEFAULT 0x00000000 |
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| 125 | |
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| 126 | /* SDADC :: CTRL_SYS1 :: reserved0 [11:00] */ |
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| 127 | #define BCHP_SDADC_CTRL_SYS1_reserved0_MASK 0x00000fff |
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| 128 | #define BCHP_SDADC_CTRL_SYS1_reserved0_SHIFT 0 |
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| 129 | |
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| 130 | /*************************************************************************** |
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| 131 | *CTRL_PWRUP - Power up controls |
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| 132 | ***************************************************************************/ |
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| 133 | /* SDADC :: CTRL_PWRUP :: reserved0 [31:02] */ |
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| 134 | #define BCHP_SDADC_CTRL_PWRUP_reserved0_MASK 0xfffffffc |
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| 135 | #define BCHP_SDADC_CTRL_PWRUP_reserved0_SHIFT 2 |
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| 136 | |
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| 137 | /* SDADC :: CTRL_PWRUP :: i_Ich_pwrup [01:01] */ |
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| 138 | #define BCHP_SDADC_CTRL_PWRUP_i_Ich_pwrup_MASK 0x00000002 |
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| 139 | #define BCHP_SDADC_CTRL_PWRUP_i_Ich_pwrup_SHIFT 1 |
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| 140 | #define BCHP_SDADC_CTRL_PWRUP_i_Ich_pwrup_DEFAULT 0x00000000 |
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| 141 | |
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| 142 | /* SDADC :: CTRL_PWRUP :: i_Qch_pwrup [00:00] */ |
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| 143 | #define BCHP_SDADC_CTRL_PWRUP_i_Qch_pwrup_MASK 0x00000001 |
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| 144 | #define BCHP_SDADC_CTRL_PWRUP_i_Qch_pwrup_SHIFT 0 |
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| 145 | #define BCHP_SDADC_CTRL_PWRUP_i_Qch_pwrup_DEFAULT 0x00000000 |
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| 146 | |
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| 147 | /*************************************************************************** |
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| 148 | *CTRL_RESET - Reset controls |
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| 149 | ***************************************************************************/ |
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| 150 | /* SDADC :: CTRL_RESET :: reserved0 [31:02] */ |
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| 151 | #define BCHP_SDADC_CTRL_RESET_reserved0_MASK 0xfffffffc |
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| 152 | #define BCHP_SDADC_CTRL_RESET_reserved0_SHIFT 2 |
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| 153 | |
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| 154 | /* SDADC :: CTRL_RESET :: i_Ich_reset [01:01] */ |
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| 155 | #define BCHP_SDADC_CTRL_RESET_i_Ich_reset_MASK 0x00000002 |
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| 156 | #define BCHP_SDADC_CTRL_RESET_i_Ich_reset_SHIFT 1 |
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| 157 | #define BCHP_SDADC_CTRL_RESET_i_Ich_reset_DEFAULT 0x00000001 |
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| 158 | |
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| 159 | /* SDADC :: CTRL_RESET :: i_Qch_reset [00:00] */ |
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| 160 | #define BCHP_SDADC_CTRL_RESET_i_Qch_reset_MASK 0x00000001 |
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| 161 | #define BCHP_SDADC_CTRL_RESET_i_Qch_reset_SHIFT 0 |
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| 162 | #define BCHP_SDADC_CTRL_RESET_i_Qch_reset_DEFAULT 0x00000001 |
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| 163 | |
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| 164 | /*************************************************************************** |
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| 165 | *CTRL_ICH - I-channel ADC controls |
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| 166 | ***************************************************************************/ |
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| 167 | /* SDADC :: CTRL_ICH :: i_ctl_Ich_flash_offset [31:08] */ |
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| 168 | #define BCHP_SDADC_CTRL_ICH_i_ctl_Ich_flash_offset_MASK 0xffffff00 |
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| 169 | #define BCHP_SDADC_CTRL_ICH_i_ctl_Ich_flash_offset_SHIFT 8 |
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| 170 | #define BCHP_SDADC_CTRL_ICH_i_ctl_Ich_flash_offset_DEFAULT 0x00492492 |
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| 171 | |
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| 172 | /* SDADC :: CTRL_ICH :: reserved0 [07:06] */ |
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| 173 | #define BCHP_SDADC_CTRL_ICH_reserved0_MASK 0x000000c0 |
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| 174 | #define BCHP_SDADC_CTRL_ICH_reserved0_SHIFT 6 |
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| 175 | |
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| 176 | /* SDADC :: CTRL_ICH :: i_Ich_scram_off [05:05] */ |
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| 177 | #define BCHP_SDADC_CTRL_ICH_i_Ich_scram_off_MASK 0x00000020 |
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| 178 | #define BCHP_SDADC_CTRL_ICH_i_Ich_scram_off_SHIFT 5 |
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| 179 | #define BCHP_SDADC_CTRL_ICH_i_Ich_scram_off_DEFAULT 0x00000000 |
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| 180 | |
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| 181 | /* SDADC :: CTRL_ICH :: i_Ich_flash_calsel [04:04] */ |
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| 182 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_calsel_MASK 0x00000010 |
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| 183 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_calsel_SHIFT 4 |
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| 184 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_calsel_DEFAULT 0x00000000 |
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| 185 | |
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| 186 | /* SDADC :: CTRL_ICH :: i_Ich_flash_resetCal [03:03] */ |
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| 187 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_resetCal_MASK 0x00000008 |
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| 188 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_resetCal_SHIFT 3 |
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| 189 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_resetCal_DEFAULT 0x00000000 |
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| 190 | |
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| 191 | /* SDADC :: CTRL_ICH :: i_Ich_flash_cal_on [02:02] */ |
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| 192 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_cal_on_MASK 0x00000004 |
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| 193 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_cal_on_SHIFT 2 |
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| 194 | #define BCHP_SDADC_CTRL_ICH_i_Ich_flash_cal_on_DEFAULT 0x00000000 |
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| 195 | |
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| 196 | /* SDADC :: CTRL_ICH :: reserved1 [01:00] */ |
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| 197 | #define BCHP_SDADC_CTRL_ICH_reserved1_MASK 0x00000003 |
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| 198 | #define BCHP_SDADC_CTRL_ICH_reserved1_SHIFT 0 |
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| 199 | |
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| 200 | /*************************************************************************** |
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| 201 | *CTRL_QCH - Q-channel ADC controls |
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| 202 | ***************************************************************************/ |
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| 203 | /* SDADC :: CTRL_QCH :: i_ctl_Qch_flash_offset [31:08] */ |
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| 204 | #define BCHP_SDADC_CTRL_QCH_i_ctl_Qch_flash_offset_MASK 0xffffff00 |
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| 205 | #define BCHP_SDADC_CTRL_QCH_i_ctl_Qch_flash_offset_SHIFT 8 |
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| 206 | #define BCHP_SDADC_CTRL_QCH_i_ctl_Qch_flash_offset_DEFAULT 0x00492492 |
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| 207 | |
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| 208 | /* SDADC :: CTRL_QCH :: reserved0 [07:06] */ |
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| 209 | #define BCHP_SDADC_CTRL_QCH_reserved0_MASK 0x000000c0 |
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| 210 | #define BCHP_SDADC_CTRL_QCH_reserved0_SHIFT 6 |
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| 211 | |
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| 212 | /* SDADC :: CTRL_QCH :: i_Qch_scram_off [05:05] */ |
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| 213 | #define BCHP_SDADC_CTRL_QCH_i_Qch_scram_off_MASK 0x00000020 |
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| 214 | #define BCHP_SDADC_CTRL_QCH_i_Qch_scram_off_SHIFT 5 |
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| 215 | #define BCHP_SDADC_CTRL_QCH_i_Qch_scram_off_DEFAULT 0x00000000 |
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| 216 | |
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| 217 | /* SDADC :: CTRL_QCH :: i_Qch_flash_calsel [04:04] */ |
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| 218 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_calsel_MASK 0x00000010 |
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| 219 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_calsel_SHIFT 4 |
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| 220 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_calsel_DEFAULT 0x00000000 |
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| 221 | |
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| 222 | /* SDADC :: CTRL_QCH :: i_Qch_flash_resetCal [03:03] */ |
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| 223 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_resetCal_MASK 0x00000008 |
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| 224 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_resetCal_SHIFT 3 |
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| 225 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_resetCal_DEFAULT 0x00000000 |
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| 226 | |
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| 227 | /* SDADC :: CTRL_QCH :: i_Qch_flash_cal_on [02:02] */ |
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| 228 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_cal_on_MASK 0x00000004 |
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| 229 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_cal_on_SHIFT 2 |
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| 230 | #define BCHP_SDADC_CTRL_QCH_i_Qch_flash_cal_on_DEFAULT 0x00000000 |
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| 231 | |
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| 232 | /* SDADC :: CTRL_QCH :: reserved1 [01:00] */ |
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| 233 | #define BCHP_SDADC_CTRL_QCH_reserved1_MASK 0x00000003 |
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| 234 | #define BCHP_SDADC_CTRL_QCH_reserved1_SHIFT 0 |
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| 235 | |
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| 236 | /*************************************************************************** |
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| 237 | *STATUS_ICH - I-channel ADC status |
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| 238 | ***************************************************************************/ |
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| 239 | /* SDADC :: STATUS_ICH :: o_Ich_flash_cal_done [31:31] */ |
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| 240 | #define BCHP_SDADC_STATUS_ICH_o_Ich_flash_cal_done_MASK 0x80000000 |
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| 241 | #define BCHP_SDADC_STATUS_ICH_o_Ich_flash_cal_done_SHIFT 31 |
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| 242 | |
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| 243 | /* SDADC :: STATUS_ICH :: o_Ich_flash_caldata [30:07] */ |
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| 244 | #define BCHP_SDADC_STATUS_ICH_o_Ich_flash_caldata_MASK 0x7fffff80 |
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| 245 | #define BCHP_SDADC_STATUS_ICH_o_Ich_flash_caldata_SHIFT 7 |
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| 246 | #define BCHP_SDADC_STATUS_ICH_o_Ich_flash_caldata_DEFAULT 0x00000000 |
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| 247 | |
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| 248 | /* SDADC :: STATUS_ICH :: reserved0 [06:00] */ |
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| 249 | #define BCHP_SDADC_STATUS_ICH_reserved0_MASK 0x0000007f |
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| 250 | #define BCHP_SDADC_STATUS_ICH_reserved0_SHIFT 0 |
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| 251 | |
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| 252 | /*************************************************************************** |
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| 253 | *STATUS_QCH - Q-channel ADC status |
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| 254 | ***************************************************************************/ |
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| 255 | /* SDADC :: STATUS_QCH :: o_Qch_flash_cal_done [31:31] */ |
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| 256 | #define BCHP_SDADC_STATUS_QCH_o_Qch_flash_cal_done_MASK 0x80000000 |
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| 257 | #define BCHP_SDADC_STATUS_QCH_o_Qch_flash_cal_done_SHIFT 31 |
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| 258 | |
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| 259 | /* SDADC :: STATUS_QCH :: o_Qch_flash_caldata [30:07] */ |
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| 260 | #define BCHP_SDADC_STATUS_QCH_o_Qch_flash_caldata_MASK 0x7fffff80 |
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| 261 | #define BCHP_SDADC_STATUS_QCH_o_Qch_flash_caldata_SHIFT 7 |
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| 262 | #define BCHP_SDADC_STATUS_QCH_o_Qch_flash_caldata_DEFAULT 0x00000000 |
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| 263 | |
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| 264 | /* SDADC :: STATUS_QCH :: reserved0 [06:00] */ |
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| 265 | #define BCHP_SDADC_STATUS_QCH_reserved0_MASK 0x0000007f |
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| 266 | #define BCHP_SDADC_STATUS_QCH_reserved0_SHIFT 0 |
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| 267 | |
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| 268 | #endif /* #ifndef BCHP_SDADC_H__ */ |
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| 269 | |
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| 270 | /* End of File */ |
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