| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_sm.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/2 $ |
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| 13 | * $brcm_Date: 2/7/12 1:40p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Tue Feb 7 10:59:54 2012 |
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| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_sm.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/2 2/7/12 1:40p pntruong |
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| 36 | * SW7552-89: Synced up with central rdb. |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_SM_H__ |
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| 41 | #define BCHP_SM_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *SM - Soft Modem Registers |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_SM_DEVICE_CTL 0x00403800 /* Device Control Register */ |
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| 47 | #define BCHP_SM_IRQ_CSR 0x00403804 /* Interrupt Service Register */ |
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| 48 | #define BCHP_SM_EXT_DAA_CMD 0x00403808 /* External DAA Command Register */ |
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| 49 | #define BCHP_SM_EXT_DAA_STAT 0x0040380c /* External DAA Status Register */ |
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| 50 | #define BCHP_SM_GP_TIMER_CFG 0x00403810 /* General Purpose Timer Configuration Register */ |
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| 51 | #define BCHP_SM_GP_TIMER_STAT 0x00403814 /* General Purpose Timer Down Counter Status Register */ |
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| 52 | #define BCHP_SM_OH_TIMER_DIAG 0x00403818 /* Off Hook Timer Diagnostic Register */ |
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| 53 | #define BCHP_SM_DIAG_CFG 0x0040381c /* Diagnostic Configuration Register */ |
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| 54 | #define BCHP_SM_REV 0x00403820 /* Soft Modem Interface Revision Register */ |
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| 55 | #define BCHP_SM_DAA_FIELD_SEL 0x00403824 /* DAA Polling Field Selection Register */ |
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| 56 | |
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| 57 | /*************************************************************************** |
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| 58 | *DEVICE_CTL - Device Control Register |
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| 59 | ***************************************************************************/ |
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| 60 | /* SM :: DEVICE_CTL :: MAX_FS_TIME [31:16] */ |
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| 61 | #define BCHP_SM_DEVICE_CTL_MAX_FS_TIME_MASK 0xffff0000 |
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| 62 | #define BCHP_SM_DEVICE_CTL_MAX_FS_TIME_SHIFT 16 |
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| 63 | #define BCHP_SM_DEVICE_CTL_MAX_FS_TIME_DEFAULT 0x00000000 |
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| 64 | |
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| 65 | /* SM :: DEVICE_CTL :: L_END [15:15] */ |
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| 66 | #define BCHP_SM_DEVICE_CTL_L_END_MASK 0x00008000 |
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| 67 | #define BCHP_SM_DEVICE_CTL_L_END_SHIFT 15 |
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| 68 | #define BCHP_SM_DEVICE_CTL_L_END_DEFAULT 0x00000000 |
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| 69 | |
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| 70 | /* SM :: DEVICE_CTL :: reserved0 [14:14] */ |
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| 71 | #define BCHP_SM_DEVICE_CTL_reserved0_MASK 0x00004000 |
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| 72 | #define BCHP_SM_DEVICE_CTL_reserved0_SHIFT 14 |
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| 73 | |
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| 74 | /* union - case Si3021_mode [13:13] */ |
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| 75 | /* SM :: DEVICE_CTL :: Si3021_mode :: POLL_LINK [13:13] */ |
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| 76 | #define BCHP_SM_DEVICE_CTL_Si3021_mode_POLL_LINK_MASK 0x00002000 |
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| 77 | #define BCHP_SM_DEVICE_CTL_Si3021_mode_POLL_LINK_SHIFT 13 |
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| 78 | #define BCHP_SM_DEVICE_CTL_Si3021_mode_POLL_LINK_DEFAULT 0x00000000 |
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| 79 | |
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| 80 | /* union - case GP_DAA_mode [13:13] */ |
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| 81 | /* SM :: DEVICE_CTL :: GP_DAA_mode :: reserved0 [13:13] */ |
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| 82 | #define BCHP_SM_DEVICE_CTL_GP_DAA_mode_reserved0_MASK 0x00002000 |
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| 83 | #define BCHP_SM_DEVICE_CTL_GP_DAA_mode_reserved0_SHIFT 13 |
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| 84 | |
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| 85 | /* SM :: DEVICE_CTL :: CNT_PCK [12:12] */ |
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| 86 | #define BCHP_SM_DEVICE_CTL_CNT_PCK_MASK 0x00001000 |
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| 87 | #define BCHP_SM_DEVICE_CTL_CNT_PCK_SHIFT 12 |
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| 88 | #define BCHP_SM_DEVICE_CTL_CNT_PCK_DEFAULT 0x00000000 |
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| 89 | |
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| 90 | /* SM :: DEVICE_CTL :: LOOP [11:11] */ |
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| 91 | #define BCHP_SM_DEVICE_CTL_LOOP_MASK 0x00000800 |
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| 92 | #define BCHP_SM_DEVICE_CTL_LOOP_SHIFT 11 |
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| 93 | #define BCHP_SM_DEVICE_CTL_LOOP_DEFAULT 0x00000000 |
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| 94 | |
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| 95 | /* SM :: DEVICE_CTL :: TIME_SF [10:09] */ |
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| 96 | #define BCHP_SM_DEVICE_CTL_TIME_SF_MASK 0x00000600 |
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| 97 | #define BCHP_SM_DEVICE_CTL_TIME_SF_SHIFT 9 |
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| 98 | #define BCHP_SM_DEVICE_CTL_TIME_SF_DEFAULT 0x00000000 |
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| 99 | |
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| 100 | /* SM :: DEVICE_CTL :: reserved1 [08:03] */ |
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| 101 | #define BCHP_SM_DEVICE_CTL_reserved1_MASK 0x000001f8 |
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| 102 | #define BCHP_SM_DEVICE_CTL_reserved1_SHIFT 3 |
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| 103 | |
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| 104 | /* SM :: DEVICE_CTL :: TX_FLUSH [02:02] */ |
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| 105 | #define BCHP_SM_DEVICE_CTL_TX_FLUSH_MASK 0x00000004 |
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| 106 | #define BCHP_SM_DEVICE_CTL_TX_FLUSH_SHIFT 2 |
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| 107 | #define BCHP_SM_DEVICE_CTL_TX_FLUSH_DEFAULT 0x00000000 |
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| 108 | |
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| 109 | /* SM :: DEVICE_CTL :: RX_FLUSH [01:01] */ |
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| 110 | #define BCHP_SM_DEVICE_CTL_RX_FLUSH_MASK 0x00000002 |
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| 111 | #define BCHP_SM_DEVICE_CTL_RX_FLUSH_SHIFT 1 |
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| 112 | #define BCHP_SM_DEVICE_CTL_RX_FLUSH_DEFAULT 0x00000000 |
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| 113 | |
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| 114 | /* SM :: DEVICE_CTL :: S_RST [00:00] */ |
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| 115 | #define BCHP_SM_DEVICE_CTL_S_RST_MASK 0x00000001 |
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| 116 | #define BCHP_SM_DEVICE_CTL_S_RST_SHIFT 0 |
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| 117 | #define BCHP_SM_DEVICE_CTL_S_RST_DEFAULT 0x00000001 |
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| 118 | |
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| 119 | /*************************************************************************** |
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| 120 | *IRQ_CSR - Interrupt Service Register |
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| 121 | ***************************************************************************/ |
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| 122 | /* SM :: IRQ_CSR :: TIME [31:31] */ |
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| 123 | #define BCHP_SM_IRQ_CSR_TIME_MASK 0x80000000 |
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| 124 | #define BCHP_SM_IRQ_CSR_TIME_SHIFT 31 |
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| 125 | #define BCHP_SM_IRQ_CSR_TIME_DEFAULT 0x00000000 |
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| 126 | |
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| 127 | /* SM :: IRQ_CSR :: IO_DONE [30:30] */ |
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| 128 | #define BCHP_SM_IRQ_CSR_IO_DONE_MASK 0x40000000 |
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| 129 | #define BCHP_SM_IRQ_CSR_IO_DONE_SHIFT 30 |
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| 130 | #define BCHP_SM_IRQ_CSR_IO_DONE_DEFAULT 0x00000000 |
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| 131 | |
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| 132 | /* SM :: IRQ_CSR :: OH_TIMEOUT [29:29] */ |
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| 133 | #define BCHP_SM_IRQ_CSR_OH_TIMEOUT_MASK 0x20000000 |
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| 134 | #define BCHP_SM_IRQ_CSR_OH_TIMEOUT_SHIFT 29 |
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| 135 | #define BCHP_SM_IRQ_CSR_OH_TIMEOUT_DEFAULT 0x00000000 |
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| 136 | |
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| 137 | /* SM :: IRQ_CSR :: RNG_HK_VALID [28:28] */ |
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| 138 | #define BCHP_SM_IRQ_CSR_RNG_HK_VALID_MASK 0x10000000 |
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| 139 | #define BCHP_SM_IRQ_CSR_RNG_HK_VALID_SHIFT 28 |
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| 140 | #define BCHP_SM_IRQ_CSR_RNG_HK_VALID_DEFAULT 0x00000000 |
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| 141 | |
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| 142 | /* SM :: IRQ_CSR :: OFF_Hook [27:27] */ |
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| 143 | #define BCHP_SM_IRQ_CSR_OFF_Hook_MASK 0x08000000 |
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| 144 | #define BCHP_SM_IRQ_CSR_OFF_Hook_SHIFT 27 |
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| 145 | #define BCHP_SM_IRQ_CSR_OFF_Hook_DEFAULT 0x00000000 |
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| 146 | |
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| 147 | /* SM :: IRQ_CSR :: Ring_Detect [26:26] */ |
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| 148 | #define BCHP_SM_IRQ_CSR_Ring_Detect_MASK 0x04000000 |
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| 149 | #define BCHP_SM_IRQ_CSR_Ring_Detect_SHIFT 26 |
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| 150 | #define BCHP_SM_IRQ_CSR_Ring_Detect_DEFAULT 0x00000000 |
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| 151 | |
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| 152 | /* SM :: IRQ_CSR :: LINK_ERR [25:25] */ |
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| 153 | #define BCHP_SM_IRQ_CSR_LINK_ERR_MASK 0x02000000 |
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| 154 | #define BCHP_SM_IRQ_CSR_LINK_ERR_SHIFT 25 |
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| 155 | #define BCHP_SM_IRQ_CSR_LINK_ERR_DEFAULT 0x00000000 |
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| 156 | |
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| 157 | /* SM :: IRQ_CSR :: reserved0 [24:24] */ |
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| 158 | #define BCHP_SM_IRQ_CSR_reserved0_MASK 0x01000000 |
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| 159 | #define BCHP_SM_IRQ_CSR_reserved0_SHIFT 24 |
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| 160 | |
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| 161 | /* SM :: IRQ_CSR :: TX_OE [23:23] */ |
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| 162 | #define BCHP_SM_IRQ_CSR_TX_OE_MASK 0x00800000 |
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| 163 | #define BCHP_SM_IRQ_CSR_TX_OE_SHIFT 23 |
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| 164 | #define BCHP_SM_IRQ_CSR_TX_OE_DEFAULT 0x00000000 |
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| 165 | |
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| 166 | /* SM :: IRQ_CSR :: TX_UE [22:22] */ |
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| 167 | #define BCHP_SM_IRQ_CSR_TX_UE_MASK 0x00400000 |
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| 168 | #define BCHP_SM_IRQ_CSR_TX_UE_SHIFT 22 |
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| 169 | #define BCHP_SM_IRQ_CSR_TX_UE_DEFAULT 0x00000000 |
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| 170 | |
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| 171 | /* SM :: IRQ_CSR :: reserved1 [21:20] */ |
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| 172 | #define BCHP_SM_IRQ_CSR_reserved1_MASK 0x00300000 |
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| 173 | #define BCHP_SM_IRQ_CSR_reserved1_SHIFT 20 |
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| 174 | |
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| 175 | /* SM :: IRQ_CSR :: RX_OE [19:19] */ |
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| 176 | #define BCHP_SM_IRQ_CSR_RX_OE_MASK 0x00080000 |
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| 177 | #define BCHP_SM_IRQ_CSR_RX_OE_SHIFT 19 |
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| 178 | #define BCHP_SM_IRQ_CSR_RX_OE_DEFAULT 0x00000000 |
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| 179 | |
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| 180 | /* SM :: IRQ_CSR :: RX_UE [18:18] */ |
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| 181 | #define BCHP_SM_IRQ_CSR_RX_UE_MASK 0x00040000 |
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| 182 | #define BCHP_SM_IRQ_CSR_RX_UE_SHIFT 18 |
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| 183 | #define BCHP_SM_IRQ_CSR_RX_UE_DEFAULT 0x00000000 |
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| 184 | |
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| 185 | /* SM :: IRQ_CSR :: reserved2 [17:16] */ |
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| 186 | #define BCHP_SM_IRQ_CSR_reserved2_MASK 0x00030000 |
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| 187 | #define BCHP_SM_IRQ_CSR_reserved2_SHIFT 16 |
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| 188 | |
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| 189 | /* SM :: IRQ_CSR :: TIME_EN [15:15] */ |
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| 190 | #define BCHP_SM_IRQ_CSR_TIME_EN_MASK 0x00008000 |
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| 191 | #define BCHP_SM_IRQ_CSR_TIME_EN_SHIFT 15 |
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| 192 | #define BCHP_SM_IRQ_CSR_TIME_EN_DEFAULT 0x00000000 |
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| 193 | |
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| 194 | /* SM :: IRQ_CSR :: IO_DONE_EN [14:14] */ |
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| 195 | #define BCHP_SM_IRQ_CSR_IO_DONE_EN_MASK 0x00004000 |
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| 196 | #define BCHP_SM_IRQ_CSR_IO_DONE_EN_SHIFT 14 |
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| 197 | #define BCHP_SM_IRQ_CSR_IO_DONE_EN_DEFAULT 0x00000000 |
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| 198 | |
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| 199 | /* SM :: IRQ_CSR :: OH_TO_EN [13:13] */ |
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| 200 | #define BCHP_SM_IRQ_CSR_OH_TO_EN_MASK 0x00002000 |
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| 201 | #define BCHP_SM_IRQ_CSR_OH_TO_EN_SHIFT 13 |
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| 202 | #define BCHP_SM_IRQ_CSR_OH_TO_EN_DEFAULT 0x00000000 |
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| 203 | |
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| 204 | /* SM :: IRQ_CSR :: HANG_UP_EN [12:12] */ |
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| 205 | #define BCHP_SM_IRQ_CSR_HANG_UP_EN_MASK 0x00001000 |
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| 206 | #define BCHP_SM_IRQ_CSR_HANG_UP_EN_SHIFT 12 |
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| 207 | #define BCHP_SM_IRQ_CSR_HANG_UP_EN_DEFAULT 0x00000000 |
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| 208 | |
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| 209 | /* SM :: IRQ_CSR :: RING_1_EN [11:11] */ |
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| 210 | #define BCHP_SM_IRQ_CSR_RING_1_EN_MASK 0x00000800 |
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| 211 | #define BCHP_SM_IRQ_CSR_RING_1_EN_SHIFT 11 |
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| 212 | #define BCHP_SM_IRQ_CSR_RING_1_EN_DEFAULT 0x00000000 |
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| 213 | |
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| 214 | /* SM :: IRQ_CSR :: RING_0_EN [10:10] */ |
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| 215 | #define BCHP_SM_IRQ_CSR_RING_0_EN_MASK 0x00000400 |
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| 216 | #define BCHP_SM_IRQ_CSR_RING_0_EN_SHIFT 10 |
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| 217 | #define BCHP_SM_IRQ_CSR_RING_0_EN_DEFAULT 0x00000000 |
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| 218 | |
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| 219 | /* SM :: IRQ_CSR :: LINK_ERR_EN [09:09] */ |
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| 220 | #define BCHP_SM_IRQ_CSR_LINK_ERR_EN_MASK 0x00000200 |
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| 221 | #define BCHP_SM_IRQ_CSR_LINK_ERR_EN_SHIFT 9 |
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| 222 | #define BCHP_SM_IRQ_CSR_LINK_ERR_EN_DEFAULT 0x00000000 |
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| 223 | |
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| 224 | /* SM :: IRQ_CSR :: reserved3 [08:08] */ |
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| 225 | #define BCHP_SM_IRQ_CSR_reserved3_MASK 0x00000100 |
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| 226 | #define BCHP_SM_IRQ_CSR_reserved3_SHIFT 8 |
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| 227 | |
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| 228 | /* SM :: IRQ_CSR :: TOE_EN [07:07] */ |
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| 229 | #define BCHP_SM_IRQ_CSR_TOE_EN_MASK 0x00000080 |
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| 230 | #define BCHP_SM_IRQ_CSR_TOE_EN_SHIFT 7 |
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| 231 | #define BCHP_SM_IRQ_CSR_TOE_EN_DEFAULT 0x00000000 |
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| 232 | |
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| 233 | /* SM :: IRQ_CSR :: TUE_EN [06:06] */ |
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| 234 | #define BCHP_SM_IRQ_CSR_TUE_EN_MASK 0x00000040 |
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| 235 | #define BCHP_SM_IRQ_CSR_TUE_EN_SHIFT 6 |
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| 236 | #define BCHP_SM_IRQ_CSR_TUE_EN_DEFAULT 0x00000000 |
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| 237 | |
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| 238 | /* SM :: IRQ_CSR :: TAE_EN [05:05] */ |
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| 239 | #define BCHP_SM_IRQ_CSR_TAE_EN_MASK 0x00000020 |
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| 240 | #define BCHP_SM_IRQ_CSR_TAE_EN_SHIFT 5 |
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| 241 | #define BCHP_SM_IRQ_CSR_TAE_EN_DEFAULT 0x00000000 |
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| 242 | |
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| 243 | /* SM :: IRQ_CSR :: TDE_EN [04:04] */ |
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| 244 | #define BCHP_SM_IRQ_CSR_TDE_EN_MASK 0x00000010 |
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| 245 | #define BCHP_SM_IRQ_CSR_TDE_EN_SHIFT 4 |
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| 246 | #define BCHP_SM_IRQ_CSR_TDE_EN_DEFAULT 0x00000000 |
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| 247 | |
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| 248 | /* SM :: IRQ_CSR :: ROE_EN [03:03] */ |
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| 249 | #define BCHP_SM_IRQ_CSR_ROE_EN_MASK 0x00000008 |
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| 250 | #define BCHP_SM_IRQ_CSR_ROE_EN_SHIFT 3 |
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| 251 | #define BCHP_SM_IRQ_CSR_ROE_EN_DEFAULT 0x00000000 |
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| 252 | |
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| 253 | /* SM :: IRQ_CSR :: RUE_EN [02:02] */ |
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| 254 | #define BCHP_SM_IRQ_CSR_RUE_EN_MASK 0x00000004 |
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| 255 | #define BCHP_SM_IRQ_CSR_RUE_EN_SHIFT 2 |
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| 256 | #define BCHP_SM_IRQ_CSR_RUE_EN_DEFAULT 0x00000000 |
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| 257 | |
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| 258 | /* SM :: IRQ_CSR :: RAE_EN [01:01] */ |
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| 259 | #define BCHP_SM_IRQ_CSR_RAE_EN_MASK 0x00000002 |
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| 260 | #define BCHP_SM_IRQ_CSR_RAE_EN_SHIFT 1 |
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| 261 | #define BCHP_SM_IRQ_CSR_RAE_EN_DEFAULT 0x00000000 |
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| 262 | |
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| 263 | /* SM :: IRQ_CSR :: RDE_EN [00:00] */ |
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| 264 | #define BCHP_SM_IRQ_CSR_RDE_EN_MASK 0x00000001 |
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| 265 | #define BCHP_SM_IRQ_CSR_RDE_EN_SHIFT 0 |
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| 266 | #define BCHP_SM_IRQ_CSR_RDE_EN_DEFAULT 0x00000000 |
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| 267 | |
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| 268 | /*************************************************************************** |
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| 269 | *EXT_DAA_CMD - External DAA Command Register |
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| 270 | ***************************************************************************/ |
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| 271 | /* union - case Si3021_mode [31:00] */ |
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| 272 | /* SM :: EXT_DAA_CMD :: Si3021_mode :: reserved0 [31:14] */ |
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| 273 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_reserved0_MASK 0xffffc000 |
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| 274 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_reserved0_SHIFT 14 |
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| 275 | |
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| 276 | /* SM :: EXT_DAA_CMD :: Si3021_mode :: READ [13:13] */ |
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| 277 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_READ_MASK 0x00002000 |
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| 278 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_READ_SHIFT 13 |
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| 279 | |
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| 280 | /* SM :: EXT_DAA_CMD :: Si3021_mode :: ADDRESS [12:08] */ |
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| 281 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_ADDRESS_MASK 0x00001f00 |
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| 282 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_ADDRESS_SHIFT 8 |
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| 283 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_ADDRESS_DEFAULT 0x00000000 |
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| 284 | |
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| 285 | /* SM :: EXT_DAA_CMD :: Si3021_mode :: DATA [07:00] */ |
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| 286 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_DATA_MASK 0x000000ff |
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| 287 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_DATA_SHIFT 0 |
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| 288 | #define BCHP_SM_EXT_DAA_CMD_Si3021_mode_DATA_DEFAULT 0x00000000 |
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| 289 | |
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| 290 | /* union - case GP_DAA_mode [31:00] */ |
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| 291 | /* SM :: EXT_DAA_CMD :: GP_DAA_mode :: BUSY [31:31] */ |
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| 292 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_BUSY_MASK 0x80000000 |
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| 293 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_BUSY_SHIFT 31 |
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| 294 | |
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| 295 | /* SM :: EXT_DAA_CMD :: GP_DAA_mode :: reserved0 [30:19] */ |
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| 296 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_reserved0_MASK 0x7ff80000 |
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| 297 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_reserved0_SHIFT 19 |
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| 298 | |
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| 299 | /* SM :: EXT_DAA_CMD :: GP_DAA_mode :: IO_FN [18:17] */ |
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| 300 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_IO_FN_MASK 0x00060000 |
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| 301 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_IO_FN_SHIFT 17 |
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| 302 | |
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| 303 | /* SM :: EXT_DAA_CMD :: GP_DAA_mode :: DLY_BSY [16:16] */ |
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| 304 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_DLY_BSY_MASK 0x00010000 |
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| 305 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_DLY_BSY_SHIFT 16 |
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| 306 | |
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| 307 | /* SM :: EXT_DAA_CMD :: GP_DAA_mode :: DAA_CMD [15:00] */ |
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| 308 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_DAA_CMD_MASK 0x0000ffff |
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| 309 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_DAA_CMD_SHIFT 0 |
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| 310 | #define BCHP_SM_EXT_DAA_CMD_GP_DAA_mode_DAA_CMD_DEFAULT 0x00000000 |
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| 311 | |
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| 312 | /*************************************************************************** |
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| 313 | *EXT_DAA_STAT - External DAA Status Register |
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| 314 | ***************************************************************************/ |
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| 315 | /* union - case Si3021_mode [31:00] */ |
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| 316 | /* SM :: EXT_DAA_STAT :: Si3021_mode :: reserved0 [31:16] */ |
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| 317 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_reserved0_MASK 0xffff0000 |
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| 318 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_reserved0_SHIFT 16 |
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| 319 | |
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| 320 | /* SM :: EXT_DAA_STAT :: Si3021_mode :: BUSY [15:15] */ |
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| 321 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_BUSY_MASK 0x00008000 |
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| 322 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_BUSY_SHIFT 15 |
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| 323 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_BUSY_DEFAULT 0x00000000 |
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| 324 | |
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| 325 | /* SM :: EXT_DAA_STAT :: Si3021_mode :: reserved1 [14:08] */ |
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| 326 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_reserved1_MASK 0x00007f00 |
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| 327 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_reserved1_SHIFT 8 |
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| 328 | |
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| 329 | /* SM :: EXT_DAA_STAT :: Si3021_mode :: DAA_RSP [07:00] */ |
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| 330 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_DAA_RSP_MASK 0x000000ff |
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| 331 | #define BCHP_SM_EXT_DAA_STAT_Si3021_mode_DAA_RSP_SHIFT 0 |
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| 332 | |
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| 333 | /* union - case GP_DAA_mode [31:00] */ |
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| 334 | /* SM :: EXT_DAA_STAT :: GP_DAA_mode :: BUSY [31:31] */ |
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| 335 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_BUSY_MASK 0x80000000 |
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| 336 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_BUSY_SHIFT 31 |
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| 337 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_BUSY_DEFAULT 0x00000000 |
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| 338 | |
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| 339 | /* SM :: EXT_DAA_STAT :: GP_DAA_mode :: reserved0 [30:16] */ |
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| 340 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_reserved0_MASK 0x7fff0000 |
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| 341 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_reserved0_SHIFT 16 |
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| 342 | |
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| 343 | /* SM :: EXT_DAA_STAT :: GP_DAA_mode :: DAA_RSP [15:00] */ |
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| 344 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_DAA_RSP_MASK 0x0000ffff |
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| 345 | #define BCHP_SM_EXT_DAA_STAT_GP_DAA_mode_DAA_RSP_SHIFT 0 |
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| 346 | |
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| 347 | /*************************************************************************** |
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| 348 | *GP_TIMER_CFG - General Purpose Timer Configuration Register |
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| 349 | ***************************************************************************/ |
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| 350 | /* SM :: GP_TIMER_CFG :: GP_TIMER_RELOAD [31:00] */ |
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| 351 | #define BCHP_SM_GP_TIMER_CFG_GP_TIMER_RELOAD_MASK 0xffffffff |
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| 352 | #define BCHP_SM_GP_TIMER_CFG_GP_TIMER_RELOAD_SHIFT 0 |
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| 353 | #define BCHP_SM_GP_TIMER_CFG_GP_TIMER_RELOAD_DEFAULT 0x00000000 |
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| 354 | |
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| 355 | /*************************************************************************** |
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| 356 | *GP_TIMER_STAT - General Purpose Timer Down Counter Status Register |
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| 357 | ***************************************************************************/ |
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| 358 | /* SM :: GP_TIMER_STAT :: GP_TIME_COUNT [31:00] */ |
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| 359 | #define BCHP_SM_GP_TIMER_STAT_GP_TIME_COUNT_MASK 0xffffffff |
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| 360 | #define BCHP_SM_GP_TIMER_STAT_GP_TIME_COUNT_SHIFT 0 |
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| 361 | #define BCHP_SM_GP_TIMER_STAT_GP_TIME_COUNT_DEFAULT 0x00000000 |
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| 362 | |
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| 363 | /*************************************************************************** |
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| 364 | *OH_TIMER_DIAG - Off Hook Timer Diagnostic Register |
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| 365 | ***************************************************************************/ |
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| 366 | /* SM :: OH_TIMER_DIAG :: CNT_PB_CLK [31:31] */ |
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| 367 | #define BCHP_SM_OH_TIMER_DIAG_CNT_PB_CLK_MASK 0x80000000 |
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| 368 | #define BCHP_SM_OH_TIMER_DIAG_CNT_PB_CLK_SHIFT 31 |
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| 369 | #define BCHP_SM_OH_TIMER_DIAG_CNT_PB_CLK_DEFAULT 0x00000000 |
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| 370 | |
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| 371 | /* SM :: OH_TIMER_DIAG :: reserved0 [30:13] */ |
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| 372 | #define BCHP_SM_OH_TIMER_DIAG_reserved0_MASK 0x7fffe000 |
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| 373 | #define BCHP_SM_OH_TIMER_DIAG_reserved0_SHIFT 13 |
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| 374 | |
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| 375 | /* SM :: OH_TIMER_DIAG :: OH_TIMER [12:00] */ |
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| 376 | #define BCHP_SM_OH_TIMER_DIAG_OH_TIMER_MASK 0x00001fff |
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| 377 | #define BCHP_SM_OH_TIMER_DIAG_OH_TIMER_SHIFT 0 |
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| 378 | |
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| 379 | /*************************************************************************** |
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| 380 | *DIAG_CFG - Diagnostic Configuration Register |
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| 381 | ***************************************************************************/ |
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| 382 | /* SM :: DIAG_CFG :: reserved0 [31:05] */ |
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| 383 | #define BCHP_SM_DIAG_CFG_reserved0_MASK 0xffffffe0 |
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| 384 | #define BCHP_SM_DIAG_CFG_reserved0_SHIFT 5 |
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| 385 | |
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| 386 | /* SM :: DIAG_CFG :: TST_PT_SEL [04:00] */ |
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| 387 | #define BCHP_SM_DIAG_CFG_TST_PT_SEL_MASK 0x0000001f |
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| 388 | #define BCHP_SM_DIAG_CFG_TST_PT_SEL_SHIFT 0 |
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| 389 | #define BCHP_SM_DIAG_CFG_TST_PT_SEL_DEFAULT 0x00000000 |
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| 390 | |
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| 391 | /*************************************************************************** |
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| 392 | *REV - Soft Modem Interface Revision Register |
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| 393 | ***************************************************************************/ |
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| 394 | /* SM :: REV :: IF_MODE [31:31] */ |
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| 395 | #define BCHP_SM_REV_IF_MODE_MASK 0x80000000 |
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| 396 | #define BCHP_SM_REV_IF_MODE_SHIFT 31 |
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| 397 | #define BCHP_SM_REV_IF_MODE_DEFAULT 0x00000000 |
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| 398 | #define BCHP_SM_REV_IF_MODE_Si3021_mode 0 |
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| 399 | #define BCHP_SM_REV_IF_MODE_GP_DAA_mode 1 |
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| 400 | |
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| 401 | /* SM :: REV :: reserved0 [30:08] */ |
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| 402 | #define BCHP_SM_REV_reserved0_MASK 0x7fffff00 |
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| 403 | #define BCHP_SM_REV_reserved0_SHIFT 8 |
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| 404 | |
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| 405 | /* SM :: REV :: REVISION [07:00] */ |
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| 406 | #define BCHP_SM_REV_REVISION_MASK 0x000000ff |
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| 407 | #define BCHP_SM_REV_REVISION_SHIFT 0 |
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| 408 | |
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| 409 | /*************************************************************************** |
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| 410 | *DAA_FIELD_SEL - DAA Polling Field Selection Register |
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| 411 | ***************************************************************************/ |
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| 412 | /* union - case Si3021_mode [31:00] */ |
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| 413 | /* SM :: DAA_FIELD_SEL :: Si3021_mode :: reserved0 [31:00] */ |
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| 414 | #define BCHP_SM_DAA_FIELD_SEL_Si3021_mode_reserved0_MASK 0xffffffff |
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| 415 | #define BCHP_SM_DAA_FIELD_SEL_Si3021_mode_reserved0_SHIFT 0 |
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| 416 | |
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| 417 | /* union - case GP_DAA_mode [31:00] */ |
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| 418 | /* SM :: DAA_FIELD_SEL :: GP_DAA_mode :: SELECT_BITS [31:16] */ |
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| 419 | #define BCHP_SM_DAA_FIELD_SEL_GP_DAA_mode_SELECT_BITS_MASK 0xffff0000 |
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| 420 | #define BCHP_SM_DAA_FIELD_SEL_GP_DAA_mode_SELECT_BITS_SHIFT 16 |
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| 421 | #define BCHP_SM_DAA_FIELD_SEL_GP_DAA_mode_SELECT_BITS_DEFAULT 0x00000000 |
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| 422 | |
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| 423 | /* SM :: DAA_FIELD_SEL :: GP_DAA_mode :: INVERT_BITS [15:00] */ |
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| 424 | #define BCHP_SM_DAA_FIELD_SEL_GP_DAA_mode_INVERT_BITS_MASK 0x0000ffff |
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| 425 | #define BCHP_SM_DAA_FIELD_SEL_GP_DAA_mode_INVERT_BITS_SHIFT 0 |
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| 426 | #define BCHP_SM_DAA_FIELD_SEL_GP_DAA_mode_INVERT_BITS_DEFAULT 0x00000000 |
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| 427 | |
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| 428 | #endif /* #ifndef BCHP_SM_H__ */ |
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| 429 | |
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| 430 | /* End of File */ |
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