| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_timer.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/2 $ |
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| 13 | * $brcm_Date: 2/7/12 1:42p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Tue Feb 7 10:59:53 2012 |
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| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_timer.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/2 2/7/12 1:42p pntruong |
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| 36 | * SW7552-89: Synced up with central rdb. |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_TIMER_H__ |
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| 41 | #define BCHP_TIMER_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *TIMER - Watchdog & Programmable Timers |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_TIMER_TIMER_IS 0x00406680 /* TIMER INTERRUPT STATUS REGISTER */ |
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| 47 | #define BCHP_TIMER_TIMER_IE0 0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */ |
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| 48 | #define BCHP_TIMER_TIMER0_CTRL 0x00406688 /* TIMER0 CONTROL REGISTER */ |
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| 49 | #define BCHP_TIMER_TIMER1_CTRL 0x0040668c /* TIMER1 CONTROL REGISTER */ |
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| 50 | #define BCHP_TIMER_TIMER2_CTRL 0x00406690 /* TIMER2 CONTROL REGISTER */ |
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| 51 | #define BCHP_TIMER_TIMER3_CTRL 0x00406694 /* TIMER3 CONTROL REGISTER */ |
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| 52 | #define BCHP_TIMER_TIMER0_STAT 0x00406698 /* TIMER0 STATUS REGISTER */ |
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| 53 | #define BCHP_TIMER_TIMER1_STAT 0x0040669c /* TIMER1 STATUS REGISTER */ |
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| 54 | #define BCHP_TIMER_TIMER2_STAT 0x004066a0 /* TIMER2 STATUS REGISTER */ |
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| 55 | #define BCHP_TIMER_TIMER3_STAT 0x004066a4 /* TIMER3 STATUS REGISTER */ |
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| 56 | #define BCHP_TIMER_WDTIMEOUT 0x004066a8 /* WATCHDOG TIMEOUT REGISTER */ |
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| 57 | #define BCHP_TIMER_WDCMD 0x004066ac /* WATCHDOG COMMAND REGISTER */ |
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| 58 | #define BCHP_TIMER_WDCHIPRST_CNT 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */ |
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| 59 | #define BCHP_TIMER_WDCRS 0x004066b4 /* WATCHDOG CHIP RESET STATUS REGISTER */ |
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| 60 | #define BCHP_TIMER_TIMER_IE1 0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */ |
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| 61 | #define BCHP_TIMER_WDCTRL 0x004066bc /* WATCHDOG CONTROL REGISTER */ |
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| 62 | |
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| 63 | /*************************************************************************** |
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| 64 | *TIMER_IS - TIMER INTERRUPT STATUS REGISTER |
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| 65 | ***************************************************************************/ |
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| 66 | /* TIMER :: TIMER_IS :: reserved0 [31:05] */ |
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| 67 | #define BCHP_TIMER_TIMER_IS_reserved0_MASK 0xffffffe0 |
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| 68 | #define BCHP_TIMER_TIMER_IS_reserved0_SHIFT 5 |
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| 69 | |
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| 70 | /* TIMER :: TIMER_IS :: WDINT [04:04] */ |
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| 71 | #define BCHP_TIMER_TIMER_IS_WDINT_MASK 0x00000010 |
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| 72 | #define BCHP_TIMER_TIMER_IS_WDINT_SHIFT 4 |
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| 73 | #define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT 0x00000000 |
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| 74 | |
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| 75 | /* TIMER :: TIMER_IS :: TMR3TO [03:03] */ |
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| 76 | #define BCHP_TIMER_TIMER_IS_TMR3TO_MASK 0x00000008 |
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| 77 | #define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT 3 |
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| 78 | #define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT 0x00000000 |
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| 79 | |
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| 80 | /* TIMER :: TIMER_IS :: TMR2TO [02:02] */ |
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| 81 | #define BCHP_TIMER_TIMER_IS_TMR2TO_MASK 0x00000004 |
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| 82 | #define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT 2 |
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| 83 | #define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT 0x00000000 |
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| 84 | |
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| 85 | /* TIMER :: TIMER_IS :: TMR1TO [01:01] */ |
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| 86 | #define BCHP_TIMER_TIMER_IS_TMR1TO_MASK 0x00000002 |
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| 87 | #define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT 1 |
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| 88 | #define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT 0x00000000 |
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| 89 | |
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| 90 | /* TIMER :: TIMER_IS :: TMR0TO [00:00] */ |
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| 91 | #define BCHP_TIMER_TIMER_IS_TMR0TO_MASK 0x00000001 |
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| 92 | #define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT 0 |
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| 93 | #define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT 0x00000000 |
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| 94 | |
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| 95 | /*************************************************************************** |
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| 96 | *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER |
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| 97 | ***************************************************************************/ |
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| 98 | /* TIMER :: TIMER_IE0 :: reserved0 [31:05] */ |
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| 99 | #define BCHP_TIMER_TIMER_IE0_reserved0_MASK 0xffffffe0 |
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| 100 | #define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT 5 |
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| 101 | |
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| 102 | /* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */ |
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| 103 | #define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK 0x00000010 |
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| 104 | #define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT 4 |
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| 105 | #define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT 0x00000000 |
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| 106 | |
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| 107 | /* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */ |
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| 108 | #define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK 0x00000008 |
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| 109 | #define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT 3 |
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| 110 | #define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT 0x00000000 |
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| 111 | |
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| 112 | /* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */ |
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| 113 | #define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK 0x00000004 |
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| 114 | #define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT 2 |
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| 115 | #define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT 0x00000000 |
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| 116 | |
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| 117 | /* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */ |
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| 118 | #define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK 0x00000002 |
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| 119 | #define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT 1 |
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| 120 | #define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT 0x00000000 |
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| 121 | |
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| 122 | /* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */ |
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| 123 | #define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK 0x00000001 |
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| 124 | #define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT 0 |
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| 125 | #define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT 0x00000000 |
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| 126 | |
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| 127 | /*************************************************************************** |
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| 128 | *TIMER0_CTRL - TIMER0 CONTROL REGISTER |
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| 129 | ***************************************************************************/ |
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| 130 | /* TIMER :: TIMER0_CTRL :: ENA [31:31] */ |
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| 131 | #define BCHP_TIMER_TIMER0_CTRL_ENA_MASK 0x80000000 |
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| 132 | #define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT 31 |
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| 133 | #define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT 0x00000000 |
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| 134 | |
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| 135 | /* TIMER :: TIMER0_CTRL :: MODE [30:30] */ |
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| 136 | #define BCHP_TIMER_TIMER0_CTRL_MODE_MASK 0x40000000 |
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| 137 | #define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT 30 |
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| 138 | #define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT 0x00000000 |
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| 139 | |
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| 140 | /* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */ |
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| 141 | #define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK 0x3fffffff |
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| 142 | #define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT 0 |
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| 143 | #define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT 0x00000000 |
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| 144 | |
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| 145 | /*************************************************************************** |
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| 146 | *TIMER1_CTRL - TIMER1 CONTROL REGISTER |
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| 147 | ***************************************************************************/ |
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| 148 | /* TIMER :: TIMER1_CTRL :: ENA [31:31] */ |
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| 149 | #define BCHP_TIMER_TIMER1_CTRL_ENA_MASK 0x80000000 |
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| 150 | #define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT 31 |
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| 151 | #define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT 0x00000000 |
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| 152 | |
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| 153 | /* TIMER :: TIMER1_CTRL :: MODE [30:30] */ |
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| 154 | #define BCHP_TIMER_TIMER1_CTRL_MODE_MASK 0x40000000 |
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| 155 | #define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT 30 |
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| 156 | #define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT 0x00000000 |
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| 157 | |
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| 158 | /* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */ |
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| 159 | #define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK 0x3fffffff |
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| 160 | #define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT 0 |
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| 161 | #define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT 0x00000000 |
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| 162 | |
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| 163 | /*************************************************************************** |
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| 164 | *TIMER2_CTRL - TIMER2 CONTROL REGISTER |
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| 165 | ***************************************************************************/ |
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| 166 | /* TIMER :: TIMER2_CTRL :: ENA [31:31] */ |
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| 167 | #define BCHP_TIMER_TIMER2_CTRL_ENA_MASK 0x80000000 |
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| 168 | #define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT 31 |
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| 169 | #define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT 0x00000000 |
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| 170 | |
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| 171 | /* TIMER :: TIMER2_CTRL :: MODE [30:30] */ |
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| 172 | #define BCHP_TIMER_TIMER2_CTRL_MODE_MASK 0x40000000 |
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| 173 | #define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT 30 |
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| 174 | #define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT 0x00000000 |
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| 175 | |
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| 176 | /* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */ |
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| 177 | #define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK 0x3fffffff |
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| 178 | #define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT 0 |
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| 179 | #define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT 0x00000000 |
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| 180 | |
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| 181 | /*************************************************************************** |
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| 182 | *TIMER3_CTRL - TIMER3 CONTROL REGISTER |
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| 183 | ***************************************************************************/ |
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| 184 | /* TIMER :: TIMER3_CTRL :: ENA [31:31] */ |
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| 185 | #define BCHP_TIMER_TIMER3_CTRL_ENA_MASK 0x80000000 |
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| 186 | #define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT 31 |
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| 187 | #define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT 0x00000000 |
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| 188 | |
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| 189 | /* TIMER :: TIMER3_CTRL :: MODE [30:30] */ |
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| 190 | #define BCHP_TIMER_TIMER3_CTRL_MODE_MASK 0x40000000 |
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| 191 | #define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT 30 |
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| 192 | #define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT 0x00000000 |
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| 193 | |
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| 194 | /* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */ |
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| 195 | #define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK 0x3fffffff |
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| 196 | #define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT 0 |
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| 197 | #define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT 0x00000000 |
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| 198 | |
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| 199 | /*************************************************************************** |
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| 200 | *TIMER0_STAT - TIMER0 STATUS REGISTER |
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| 201 | ***************************************************************************/ |
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| 202 | /* TIMER :: TIMER0_STAT :: SPARE [31:30] */ |
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| 203 | #define BCHP_TIMER_TIMER0_STAT_SPARE_MASK 0xc0000000 |
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| 204 | #define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT 30 |
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| 205 | |
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| 206 | /* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */ |
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| 207 | #define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK 0x3fffffff |
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| 208 | #define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT 0 |
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| 209 | #define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT 0x00000000 |
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| 210 | |
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| 211 | /*************************************************************************** |
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| 212 | *TIMER1_STAT - TIMER1 STATUS REGISTER |
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| 213 | ***************************************************************************/ |
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| 214 | /* TIMER :: TIMER1_STAT :: SPARE [31:30] */ |
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| 215 | #define BCHP_TIMER_TIMER1_STAT_SPARE_MASK 0xc0000000 |
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| 216 | #define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT 30 |
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| 217 | |
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| 218 | /* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */ |
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| 219 | #define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK 0x3fffffff |
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| 220 | #define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT 0 |
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| 221 | #define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT 0x00000000 |
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| 222 | |
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| 223 | /*************************************************************************** |
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| 224 | *TIMER2_STAT - TIMER2 STATUS REGISTER |
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| 225 | ***************************************************************************/ |
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| 226 | /* TIMER :: TIMER2_STAT :: SPARE [31:30] */ |
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| 227 | #define BCHP_TIMER_TIMER2_STAT_SPARE_MASK 0xc0000000 |
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| 228 | #define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT 30 |
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| 229 | |
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| 230 | /* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */ |
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| 231 | #define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK 0x3fffffff |
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| 232 | #define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT 0 |
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| 233 | #define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT 0x00000000 |
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| 234 | |
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| 235 | /*************************************************************************** |
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| 236 | *TIMER3_STAT - TIMER3 STATUS REGISTER |
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| 237 | ***************************************************************************/ |
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| 238 | /* TIMER :: TIMER3_STAT :: SPARE [31:30] */ |
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| 239 | #define BCHP_TIMER_TIMER3_STAT_SPARE_MASK 0xc0000000 |
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| 240 | #define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT 30 |
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| 241 | |
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| 242 | /* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */ |
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| 243 | #define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK 0x3fffffff |
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| 244 | #define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT 0 |
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| 245 | #define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT 0x00000000 |
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| 246 | |
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| 247 | /*************************************************************************** |
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| 248 | *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER |
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| 249 | ***************************************************************************/ |
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| 250 | /* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */ |
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| 251 | #define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK 0xffffffff |
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| 252 | #define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT 0 |
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| 253 | #define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT 0x00000000 |
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| 254 | |
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| 255 | /*************************************************************************** |
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| 256 | *WDCMD - WATCHDOG COMMAND REGISTER |
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| 257 | ***************************************************************************/ |
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| 258 | /* TIMER :: WDCMD :: WDCMD [31:00] */ |
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| 259 | #define BCHP_TIMER_WDCMD_WDCMD_MASK 0xffffffff |
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| 260 | #define BCHP_TIMER_WDCMD_WDCMD_SHIFT 0 |
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| 261 | #define BCHP_TIMER_WDCMD_WDCMD_DEFAULT 0x00000000 |
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| 262 | |
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| 263 | /*************************************************************************** |
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| 264 | *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER |
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| 265 | ***************************************************************************/ |
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| 266 | /* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */ |
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| 267 | #define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK 0xfc000000 |
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| 268 | #define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT 26 |
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| 269 | |
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| 270 | /* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */ |
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| 271 | #define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK 0x03ffffff |
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| 272 | #define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT 0 |
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| 273 | #define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT 0x02ffffff |
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| 274 | |
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| 275 | /*************************************************************************** |
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| 276 | *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER |
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| 277 | ***************************************************************************/ |
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| 278 | /* TIMER :: WDCRS :: reserved0 [31:01] */ |
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| 279 | #define BCHP_TIMER_WDCRS_reserved0_MASK 0xfffffffe |
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| 280 | #define BCHP_TIMER_WDCRS_reserved0_SHIFT 1 |
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| 281 | |
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| 282 | /* TIMER :: WDCRS :: WDCR [00:00] */ |
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| 283 | #define BCHP_TIMER_WDCRS_WDCR_MASK 0x00000001 |
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| 284 | #define BCHP_TIMER_WDCRS_WDCR_SHIFT 0 |
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| 285 | #define BCHP_TIMER_WDCRS_WDCR_DEFAULT 0x00000000 |
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| 286 | |
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| 287 | /*************************************************************************** |
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| 288 | *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER |
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| 289 | ***************************************************************************/ |
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| 290 | /* TIMER :: TIMER_IE1 :: reserved0 [31:05] */ |
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| 291 | #define BCHP_TIMER_TIMER_IE1_reserved0_MASK 0xffffffe0 |
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| 292 | #define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT 5 |
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| 293 | |
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| 294 | /* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */ |
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| 295 | #define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK 0x00000010 |
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| 296 | #define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT 4 |
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| 297 | #define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT 0x00000000 |
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| 298 | |
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| 299 | /* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */ |
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| 300 | #define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK 0x00000008 |
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| 301 | #define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT 3 |
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| 302 | #define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT 0x00000000 |
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| 303 | |
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| 304 | /* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */ |
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| 305 | #define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK 0x00000004 |
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| 306 | #define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT 2 |
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| 307 | #define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT 0x00000000 |
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| 308 | |
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| 309 | /* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */ |
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| 310 | #define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK 0x00000002 |
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| 311 | #define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT 1 |
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| 312 | #define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT 0x00000000 |
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| 313 | |
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| 314 | /* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */ |
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| 315 | #define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK 0x00000001 |
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| 316 | #define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT 0 |
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| 317 | #define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT 0x00000000 |
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| 318 | |
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| 319 | /*************************************************************************** |
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| 320 | *WDCTRL - WATCHDOG CONTROL REGISTER |
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| 321 | ***************************************************************************/ |
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| 322 | /* TIMER :: WDCTRL :: reserved0 [31:03] */ |
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| 323 | #define BCHP_TIMER_WDCTRL_reserved0_MASK 0xfffffff8 |
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| 324 | #define BCHP_TIMER_WDCTRL_reserved0_SHIFT 3 |
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| 325 | |
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| 326 | /* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */ |
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| 327 | #define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK 0x00000004 |
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| 328 | #define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT 2 |
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| 329 | #define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT 0x00000000 |
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| 330 | |
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| 331 | /* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */ |
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| 332 | #define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK 0x00000003 |
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| 333 | #define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT 0 |
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| 334 | #define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT 0x00000000 |
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| 335 | |
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| 336 | #endif /* #ifndef BCHP_TIMER_H__ */ |
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| 337 | |
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| 338 | /* End of File */ |
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