| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 1999-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * |
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| 7 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 8 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 9 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 10 | * |
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| 11 | * $brcm_Workfile: bchp_uarta.h $ |
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| 12 | * $brcm_Revision: Hydra_Software_Devel/2 $ |
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| 13 | * $brcm_Date: 2/7/12 1:43p $ |
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| 14 | * |
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| 15 | * Module Description: |
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| 16 | * DO NOT EDIT THIS FILE DIRECTLY |
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| 17 | * |
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| 18 | * This module was generated magically with RDB from a source description |
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| 19 | * file. You must edit the source file for changes to be made to this file. |
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| 20 | * |
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| 21 | * |
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| 22 | * Date: Generated on Tue Feb 7 10:59:54 2012 |
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| 23 | * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
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| 24 | * |
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| 25 | * Compiled with: RDB Utility combo_header.pl |
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| 26 | * RDB Parser 3.0 |
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| 27 | * unknown unknown |
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| 28 | * Perl Interpreter 5.008008 |
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| 29 | * Operating System linux |
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| 30 | * |
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| 31 | * Revision History: |
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| 32 | * |
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| 33 | * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_uarta.h $ |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/2 2/7/12 1:43p pntruong |
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| 36 | * SW7552-89: Synced up with central rdb. |
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| 37 | * |
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| 38 | ***************************************************************************/ |
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| 39 | |
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| 40 | #ifndef BCHP_UARTA_H__ |
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| 41 | #define BCHP_UARTA_H__ |
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| 42 | |
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| 43 | /*************************************************************************** |
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| 44 | *UARTA - UART A |
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| 45 | ***************************************************************************/ |
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| 46 | #define BCHP_UARTA_RBR 0x00406800 /* Receive Buffer Register */ |
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| 47 | #define BCHP_UARTA_THR 0x00406800 /* Transmit Holding Register */ |
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| 48 | #define BCHP_UARTA_DLH 0x00406804 /* Divisor Latch High */ |
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| 49 | #define BCHP_UARTA_DLL 0x00406800 /* Divisor Latch Low */ |
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| 50 | #define BCHP_UARTA_IER 0x00406804 /* Interrupt Enable Register */ |
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| 51 | #define BCHP_UARTA_IIR 0x00406808 /* Interrupt Identity Register */ |
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| 52 | #define BCHP_UARTA_FCR 0x00406808 /* FIFO Control Register */ |
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| 53 | #define BCHP_UARTA_LCR 0x0040680c /* Line Control Register */ |
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| 54 | #define BCHP_UARTA_MCR 0x00406810 /* Modem Control Register */ |
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| 55 | #define BCHP_UARTA_LSR 0x00406814 /* Line Status Register */ |
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| 56 | #define BCHP_UARTA_MSR 0x00406818 /* Modem Status Register */ |
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| 57 | #define BCHP_UARTA_SCR 0x0040681c /* Scratchpad Register */ |
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| 58 | |
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| 59 | /*************************************************************************** |
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| 60 | *RBR - Receive Buffer Register |
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| 61 | ***************************************************************************/ |
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| 62 | /* UARTA :: RBR :: reserved0 [31:08] */ |
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| 63 | #define BCHP_UARTA_RBR_reserved0_MASK 0xffffff00 |
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| 64 | #define BCHP_UARTA_RBR_reserved0_SHIFT 8 |
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| 65 | |
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| 66 | /* UARTA :: RBR :: RBR [07:00] */ |
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| 67 | #define BCHP_UARTA_RBR_RBR_MASK 0x000000ff |
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| 68 | #define BCHP_UARTA_RBR_RBR_SHIFT 0 |
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| 69 | #define BCHP_UARTA_RBR_RBR_DEFAULT 0x00000000 |
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| 70 | |
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| 71 | /*************************************************************************** |
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| 72 | *THR - Transmit Holding Register |
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| 73 | ***************************************************************************/ |
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| 74 | /* UARTA :: THR :: reserved0 [31:08] */ |
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| 75 | #define BCHP_UARTA_THR_reserved0_MASK 0xffffff00 |
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| 76 | #define BCHP_UARTA_THR_reserved0_SHIFT 8 |
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| 77 | |
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| 78 | /* UARTA :: THR :: THR [07:00] */ |
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| 79 | #define BCHP_UARTA_THR_THR_MASK 0x000000ff |
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| 80 | #define BCHP_UARTA_THR_THR_SHIFT 0 |
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| 81 | #define BCHP_UARTA_THR_THR_DEFAULT 0x00000000 |
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| 82 | |
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| 83 | /*************************************************************************** |
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| 84 | *DLH - Divisor Latch High |
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| 85 | ***************************************************************************/ |
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| 86 | /* UARTA :: DLH :: reserved0 [31:08] */ |
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| 87 | #define BCHP_UARTA_DLH_reserved0_MASK 0xffffff00 |
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| 88 | #define BCHP_UARTA_DLH_reserved0_SHIFT 8 |
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| 89 | |
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| 90 | /* UARTA :: DLH :: DLH [07:00] */ |
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| 91 | #define BCHP_UARTA_DLH_DLH_MASK 0x000000ff |
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| 92 | #define BCHP_UARTA_DLH_DLH_SHIFT 0 |
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| 93 | #define BCHP_UARTA_DLH_DLH_DEFAULT 0x00000000 |
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| 94 | |
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| 95 | /*************************************************************************** |
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| 96 | *DLL - Divisor Latch Low |
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| 97 | ***************************************************************************/ |
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| 98 | /* UARTA :: DLL :: reserved0 [31:08] */ |
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| 99 | #define BCHP_UARTA_DLL_reserved0_MASK 0xffffff00 |
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| 100 | #define BCHP_UARTA_DLL_reserved0_SHIFT 8 |
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| 101 | |
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| 102 | /* UARTA :: DLL :: DLL [07:00] */ |
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| 103 | #define BCHP_UARTA_DLL_DLL_MASK 0x000000ff |
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| 104 | #define BCHP_UARTA_DLL_DLL_SHIFT 0 |
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| 105 | #define BCHP_UARTA_DLL_DLL_DEFAULT 0x00000000 |
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| 106 | |
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| 107 | /*************************************************************************** |
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| 108 | *IER - Interrupt Enable Register |
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| 109 | ***************************************************************************/ |
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| 110 | /* UARTA :: IER :: reserved0 [31:08] */ |
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| 111 | #define BCHP_UARTA_IER_reserved0_MASK 0xffffff00 |
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| 112 | #define BCHP_UARTA_IER_reserved0_SHIFT 8 |
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| 113 | |
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| 114 | /* UARTA :: IER :: PTIME [07:07] */ |
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| 115 | #define BCHP_UARTA_IER_PTIME_MASK 0x00000080 |
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| 116 | #define BCHP_UARTA_IER_PTIME_SHIFT 7 |
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| 117 | #define BCHP_UARTA_IER_PTIME_DEFAULT 0x00000000 |
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| 118 | |
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| 119 | /* UARTA :: IER :: reserved1 [06:04] */ |
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| 120 | #define BCHP_UARTA_IER_reserved1_MASK 0x00000070 |
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| 121 | #define BCHP_UARTA_IER_reserved1_SHIFT 4 |
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| 122 | |
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| 123 | /* UARTA :: IER :: EDSSI [03:03] */ |
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| 124 | #define BCHP_UARTA_IER_EDSSI_MASK 0x00000008 |
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| 125 | #define BCHP_UARTA_IER_EDSSI_SHIFT 3 |
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| 126 | #define BCHP_UARTA_IER_EDSSI_DEFAULT 0x00000000 |
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| 127 | |
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| 128 | /* UARTA :: IER :: ELSI [02:02] */ |
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| 129 | #define BCHP_UARTA_IER_ELSI_MASK 0x00000004 |
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| 130 | #define BCHP_UARTA_IER_ELSI_SHIFT 2 |
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| 131 | #define BCHP_UARTA_IER_ELSI_DEFAULT 0x00000000 |
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| 132 | |
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| 133 | /* UARTA :: IER :: ETBEI [01:01] */ |
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| 134 | #define BCHP_UARTA_IER_ETBEI_MASK 0x00000002 |
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| 135 | #define BCHP_UARTA_IER_ETBEI_SHIFT 1 |
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| 136 | #define BCHP_UARTA_IER_ETBEI_DEFAULT 0x00000000 |
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| 137 | |
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| 138 | /* UARTA :: IER :: ERBFI [00:00] */ |
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| 139 | #define BCHP_UARTA_IER_ERBFI_MASK 0x00000001 |
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| 140 | #define BCHP_UARTA_IER_ERBFI_SHIFT 0 |
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| 141 | #define BCHP_UARTA_IER_ERBFI_DEFAULT 0x00000000 |
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| 142 | |
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| 143 | /*************************************************************************** |
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| 144 | *IIR - Interrupt Identity Register |
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| 145 | ***************************************************************************/ |
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| 146 | /* UARTA :: IIR :: reserved0 [31:08] */ |
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| 147 | #define BCHP_UARTA_IIR_reserved0_MASK 0xffffff00 |
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| 148 | #define BCHP_UARTA_IIR_reserved0_SHIFT 8 |
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| 149 | |
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| 150 | /* UARTA :: IIR :: FIFOSE [07:06] */ |
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| 151 | #define BCHP_UARTA_IIR_FIFOSE_MASK 0x000000c0 |
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| 152 | #define BCHP_UARTA_IIR_FIFOSE_SHIFT 6 |
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| 153 | #define BCHP_UARTA_IIR_FIFOSE_DEFAULT 0x00000000 |
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| 154 | |
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| 155 | /* UARTA :: IIR :: reserved1 [05:04] */ |
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| 156 | #define BCHP_UARTA_IIR_reserved1_MASK 0x00000030 |
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| 157 | #define BCHP_UARTA_IIR_reserved1_SHIFT 4 |
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| 158 | |
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| 159 | /* UARTA :: IIR :: IID [03:00] */ |
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| 160 | #define BCHP_UARTA_IIR_IID_MASK 0x0000000f |
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| 161 | #define BCHP_UARTA_IIR_IID_SHIFT 0 |
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| 162 | #define BCHP_UARTA_IIR_IID_DEFAULT 0x00000001 |
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| 163 | |
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| 164 | /*************************************************************************** |
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| 165 | *FCR - FIFO Control Register |
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| 166 | ***************************************************************************/ |
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| 167 | /* UARTA :: FCR :: reserved0 [31:08] */ |
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| 168 | #define BCHP_UARTA_FCR_reserved0_MASK 0xffffff00 |
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| 169 | #define BCHP_UARTA_FCR_reserved0_SHIFT 8 |
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| 170 | |
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| 171 | /* UARTA :: FCR :: RT [07:06] */ |
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| 172 | #define BCHP_UARTA_FCR_RT_MASK 0x000000c0 |
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| 173 | #define BCHP_UARTA_FCR_RT_SHIFT 6 |
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| 174 | #define BCHP_UARTA_FCR_RT_DEFAULT 0x00000000 |
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| 175 | |
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| 176 | /* UARTA :: FCR :: TET [05:04] */ |
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| 177 | #define BCHP_UARTA_FCR_TET_MASK 0x00000030 |
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| 178 | #define BCHP_UARTA_FCR_TET_SHIFT 4 |
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| 179 | #define BCHP_UARTA_FCR_TET_DEFAULT 0x00000000 |
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| 180 | |
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| 181 | /* UARTA :: FCR :: DMAM [03:03] */ |
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| 182 | #define BCHP_UARTA_FCR_DMAM_MASK 0x00000008 |
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| 183 | #define BCHP_UARTA_FCR_DMAM_SHIFT 3 |
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| 184 | #define BCHP_UARTA_FCR_DMAM_DEFAULT 0x00000000 |
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| 185 | |
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| 186 | /* UARTA :: FCR :: XFIFOR [02:02] */ |
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| 187 | #define BCHP_UARTA_FCR_XFIFOR_MASK 0x00000004 |
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| 188 | #define BCHP_UARTA_FCR_XFIFOR_SHIFT 2 |
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| 189 | #define BCHP_UARTA_FCR_XFIFOR_DEFAULT 0x00000000 |
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| 190 | |
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| 191 | /* UARTA :: FCR :: RFIFOR [01:01] */ |
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| 192 | #define BCHP_UARTA_FCR_RFIFOR_MASK 0x00000002 |
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| 193 | #define BCHP_UARTA_FCR_RFIFOR_SHIFT 1 |
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| 194 | #define BCHP_UARTA_FCR_RFIFOR_DEFAULT 0x00000000 |
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| 195 | |
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| 196 | /* UARTA :: FCR :: FIFOE [00:00] */ |
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| 197 | #define BCHP_UARTA_FCR_FIFOE_MASK 0x00000001 |
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| 198 | #define BCHP_UARTA_FCR_FIFOE_SHIFT 0 |
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| 199 | #define BCHP_UARTA_FCR_FIFOE_DEFAULT 0x00000000 |
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| 200 | |
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| 201 | /*************************************************************************** |
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| 202 | *LCR - Line Control Register |
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| 203 | ***************************************************************************/ |
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| 204 | /* UARTA :: LCR :: reserved0 [31:08] */ |
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| 205 | #define BCHP_UARTA_LCR_reserved0_MASK 0xffffff00 |
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| 206 | #define BCHP_UARTA_LCR_reserved0_SHIFT 8 |
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| 207 | |
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| 208 | /* UARTA :: LCR :: DLAB [07:07] */ |
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| 209 | #define BCHP_UARTA_LCR_DLAB_MASK 0x00000080 |
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| 210 | #define BCHP_UARTA_LCR_DLAB_SHIFT 7 |
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| 211 | #define BCHP_UARTA_LCR_DLAB_DEFAULT 0x00000000 |
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| 212 | |
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| 213 | /* UARTA :: LCR :: BC [06:06] */ |
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| 214 | #define BCHP_UARTA_LCR_BC_MASK 0x00000040 |
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| 215 | #define BCHP_UARTA_LCR_BC_SHIFT 6 |
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| 216 | #define BCHP_UARTA_LCR_BC_DEFAULT 0x00000000 |
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| 217 | |
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| 218 | /* UARTA :: LCR :: reserved1 [05:05] */ |
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| 219 | #define BCHP_UARTA_LCR_reserved1_MASK 0x00000020 |
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| 220 | #define BCHP_UARTA_LCR_reserved1_SHIFT 5 |
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| 221 | |
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| 222 | /* UARTA :: LCR :: EPS [04:04] */ |
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| 223 | #define BCHP_UARTA_LCR_EPS_MASK 0x00000010 |
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| 224 | #define BCHP_UARTA_LCR_EPS_SHIFT 4 |
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| 225 | #define BCHP_UARTA_LCR_EPS_DEFAULT 0x00000000 |
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| 226 | |
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| 227 | /* UARTA :: LCR :: PEN [03:03] */ |
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| 228 | #define BCHP_UARTA_LCR_PEN_MASK 0x00000008 |
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| 229 | #define BCHP_UARTA_LCR_PEN_SHIFT 3 |
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| 230 | #define BCHP_UARTA_LCR_PEN_DEFAULT 0x00000000 |
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| 231 | |
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| 232 | /* UARTA :: LCR :: STOP [02:02] */ |
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| 233 | #define BCHP_UARTA_LCR_STOP_MASK 0x00000004 |
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| 234 | #define BCHP_UARTA_LCR_STOP_SHIFT 2 |
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| 235 | #define BCHP_UARTA_LCR_STOP_DEFAULT 0x00000000 |
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| 236 | |
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| 237 | /* UARTA :: LCR :: DLS [01:00] */ |
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| 238 | #define BCHP_UARTA_LCR_DLS_MASK 0x00000003 |
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| 239 | #define BCHP_UARTA_LCR_DLS_SHIFT 0 |
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| 240 | #define BCHP_UARTA_LCR_DLS_DEFAULT 0x00000000 |
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| 241 | |
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| 242 | /*************************************************************************** |
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| 243 | *MCR - Modem Control Register |
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| 244 | ***************************************************************************/ |
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| 245 | /* UARTA :: MCR :: reserved0 [31:07] */ |
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| 246 | #define BCHP_UARTA_MCR_reserved0_MASK 0xffffff80 |
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| 247 | #define BCHP_UARTA_MCR_reserved0_SHIFT 7 |
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| 248 | |
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| 249 | /* UARTA :: MCR :: SIRE [06:06] */ |
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| 250 | #define BCHP_UARTA_MCR_SIRE_MASK 0x00000040 |
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| 251 | #define BCHP_UARTA_MCR_SIRE_SHIFT 6 |
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| 252 | #define BCHP_UARTA_MCR_SIRE_DEFAULT 0x00000000 |
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| 253 | |
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| 254 | /* UARTA :: MCR :: AFCE [05:05] */ |
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| 255 | #define BCHP_UARTA_MCR_AFCE_MASK 0x00000020 |
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| 256 | #define BCHP_UARTA_MCR_AFCE_SHIFT 5 |
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| 257 | #define BCHP_UARTA_MCR_AFCE_DEFAULT 0x00000000 |
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| 258 | |
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| 259 | /* UARTA :: MCR :: LB [04:04] */ |
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| 260 | #define BCHP_UARTA_MCR_LB_MASK 0x00000010 |
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| 261 | #define BCHP_UARTA_MCR_LB_SHIFT 4 |
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| 262 | #define BCHP_UARTA_MCR_LB_DEFAULT 0x00000000 |
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| 263 | |
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| 264 | /* UARTA :: MCR :: OUT2 [03:03] */ |
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| 265 | #define BCHP_UARTA_MCR_OUT2_MASK 0x00000008 |
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| 266 | #define BCHP_UARTA_MCR_OUT2_SHIFT 3 |
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| 267 | #define BCHP_UARTA_MCR_OUT2_DEFAULT 0x00000000 |
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| 268 | |
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| 269 | /* UARTA :: MCR :: OUT1 [02:02] */ |
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| 270 | #define BCHP_UARTA_MCR_OUT1_MASK 0x00000004 |
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| 271 | #define BCHP_UARTA_MCR_OUT1_SHIFT 2 |
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| 272 | #define BCHP_UARTA_MCR_OUT1_DEFAULT 0x00000000 |
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| 273 | |
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| 274 | /* UARTA :: MCR :: RTS [01:01] */ |
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| 275 | #define BCHP_UARTA_MCR_RTS_MASK 0x00000002 |
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| 276 | #define BCHP_UARTA_MCR_RTS_SHIFT 1 |
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| 277 | #define BCHP_UARTA_MCR_RTS_DEFAULT 0x00000000 |
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| 278 | |
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| 279 | /* UARTA :: MCR :: DTR [00:00] */ |
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| 280 | #define BCHP_UARTA_MCR_DTR_MASK 0x00000001 |
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| 281 | #define BCHP_UARTA_MCR_DTR_SHIFT 0 |
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| 282 | #define BCHP_UARTA_MCR_DTR_DEFAULT 0x00000000 |
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| 283 | |
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| 284 | /*************************************************************************** |
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| 285 | *LSR - Line Status Register |
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| 286 | ***************************************************************************/ |
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| 287 | /* UARTA :: LSR :: reserved0 [31:08] */ |
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| 288 | #define BCHP_UARTA_LSR_reserved0_MASK 0xffffff00 |
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| 289 | #define BCHP_UARTA_LSR_reserved0_SHIFT 8 |
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| 290 | |
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| 291 | /* UARTA :: LSR :: RFE [07:07] */ |
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| 292 | #define BCHP_UARTA_LSR_RFE_MASK 0x00000080 |
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| 293 | #define BCHP_UARTA_LSR_RFE_SHIFT 7 |
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| 294 | #define BCHP_UARTA_LSR_RFE_DEFAULT 0x00000000 |
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| 295 | |
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| 296 | /* UARTA :: LSR :: TEMT [06:06] */ |
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| 297 | #define BCHP_UARTA_LSR_TEMT_MASK 0x00000040 |
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| 298 | #define BCHP_UARTA_LSR_TEMT_SHIFT 6 |
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| 299 | #define BCHP_UARTA_LSR_TEMT_DEFAULT 0x00000001 |
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| 300 | |
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| 301 | /* UARTA :: LSR :: THRE [05:05] */ |
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| 302 | #define BCHP_UARTA_LSR_THRE_MASK 0x00000020 |
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| 303 | #define BCHP_UARTA_LSR_THRE_SHIFT 5 |
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| 304 | #define BCHP_UARTA_LSR_THRE_DEFAULT 0x00000001 |
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| 305 | |
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| 306 | /* UARTA :: LSR :: BI [04:04] */ |
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| 307 | #define BCHP_UARTA_LSR_BI_MASK 0x00000010 |
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| 308 | #define BCHP_UARTA_LSR_BI_SHIFT 4 |
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| 309 | #define BCHP_UARTA_LSR_BI_DEFAULT 0x00000000 |
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| 310 | |
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| 311 | /* UARTA :: LSR :: FE [03:03] */ |
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| 312 | #define BCHP_UARTA_LSR_FE_MASK 0x00000008 |
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| 313 | #define BCHP_UARTA_LSR_FE_SHIFT 3 |
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| 314 | #define BCHP_UARTA_LSR_FE_DEFAULT 0x00000000 |
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| 315 | |
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| 316 | /* UARTA :: LSR :: PE [02:02] */ |
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| 317 | #define BCHP_UARTA_LSR_PE_MASK 0x00000004 |
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| 318 | #define BCHP_UARTA_LSR_PE_SHIFT 2 |
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| 319 | #define BCHP_UARTA_LSR_PE_DEFAULT 0x00000000 |
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| 320 | |
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| 321 | /* UARTA :: LSR :: OE [01:01] */ |
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| 322 | #define BCHP_UARTA_LSR_OE_MASK 0x00000002 |
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| 323 | #define BCHP_UARTA_LSR_OE_SHIFT 1 |
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| 324 | #define BCHP_UARTA_LSR_OE_DEFAULT 0x00000000 |
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| 325 | |
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| 326 | /* UARTA :: LSR :: DR [00:00] */ |
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| 327 | #define BCHP_UARTA_LSR_DR_MASK 0x00000001 |
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| 328 | #define BCHP_UARTA_LSR_DR_SHIFT 0 |
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| 329 | #define BCHP_UARTA_LSR_DR_DEFAULT 0x00000000 |
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| 330 | |
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| 331 | /*************************************************************************** |
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| 332 | *MSR - Modem Status Register |
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| 333 | ***************************************************************************/ |
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| 334 | /* UARTA :: MSR :: reserved0 [31:08] */ |
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| 335 | #define BCHP_UARTA_MSR_reserved0_MASK 0xffffff00 |
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| 336 | #define BCHP_UARTA_MSR_reserved0_SHIFT 8 |
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| 337 | |
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| 338 | /* UARTA :: MSR :: DCD [07:07] */ |
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| 339 | #define BCHP_UARTA_MSR_DCD_MASK 0x00000080 |
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| 340 | #define BCHP_UARTA_MSR_DCD_SHIFT 7 |
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| 341 | #define BCHP_UARTA_MSR_DCD_DEFAULT 0x00000000 |
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| 342 | |
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| 343 | /* UARTA :: MSR :: RI [06:06] */ |
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| 344 | #define BCHP_UARTA_MSR_RI_MASK 0x00000040 |
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| 345 | #define BCHP_UARTA_MSR_RI_SHIFT 6 |
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| 346 | #define BCHP_UARTA_MSR_RI_DEFAULT 0x00000000 |
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| 347 | |
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| 348 | /* UARTA :: MSR :: DSR [05:05] */ |
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| 349 | #define BCHP_UARTA_MSR_DSR_MASK 0x00000020 |
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| 350 | #define BCHP_UARTA_MSR_DSR_SHIFT 5 |
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| 351 | #define BCHP_UARTA_MSR_DSR_DEFAULT 0x00000000 |
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| 352 | |
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| 353 | /* UARTA :: MSR :: CTS [04:04] */ |
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| 354 | #define BCHP_UARTA_MSR_CTS_MASK 0x00000010 |
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| 355 | #define BCHP_UARTA_MSR_CTS_SHIFT 4 |
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| 356 | #define BCHP_UARTA_MSR_CTS_DEFAULT 0x00000000 |
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| 357 | |
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| 358 | /* UARTA :: MSR :: DDCD [03:03] */ |
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| 359 | #define BCHP_UARTA_MSR_DDCD_MASK 0x00000008 |
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| 360 | #define BCHP_UARTA_MSR_DDCD_SHIFT 3 |
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| 361 | #define BCHP_UARTA_MSR_DDCD_DEFAULT 0x00000000 |
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| 362 | |
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| 363 | /* UARTA :: MSR :: TERI [02:02] */ |
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| 364 | #define BCHP_UARTA_MSR_TERI_MASK 0x00000004 |
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| 365 | #define BCHP_UARTA_MSR_TERI_SHIFT 2 |
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| 366 | #define BCHP_UARTA_MSR_TERI_DEFAULT 0x00000000 |
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| 367 | |
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| 368 | /* UARTA :: MSR :: DDSR [01:01] */ |
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| 369 | #define BCHP_UARTA_MSR_DDSR_MASK 0x00000002 |
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| 370 | #define BCHP_UARTA_MSR_DDSR_SHIFT 1 |
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| 371 | #define BCHP_UARTA_MSR_DDSR_DEFAULT 0x00000000 |
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| 372 | |
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| 373 | /* UARTA :: MSR :: DCTS [00:00] */ |
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| 374 | #define BCHP_UARTA_MSR_DCTS_MASK 0x00000001 |
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| 375 | #define BCHP_UARTA_MSR_DCTS_SHIFT 0 |
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| 376 | #define BCHP_UARTA_MSR_DCTS_DEFAULT 0x00000000 |
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| 377 | |
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| 378 | /*************************************************************************** |
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| 379 | *SCR - Scratchpad Register |
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| 380 | ***************************************************************************/ |
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| 381 | /* UARTA :: SCR :: reserved0 [31:08] */ |
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| 382 | #define BCHP_UARTA_SCR_reserved0_MASK 0xffffff00 |
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| 383 | #define BCHP_UARTA_SCR_reserved0_SHIFT 8 |
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| 384 | |
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| 385 | /* UARTA :: SCR :: SCR [07:00] */ |
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| 386 | #define BCHP_UARTA_SCR_SCR_MASK 0x000000ff |
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| 387 | #define BCHP_UARTA_SCR_SCR_SHIFT 0 |
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| 388 | #define BCHP_UARTA_SCR_SCR_DEFAULT 0x00000000 |
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| 389 | |
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| 390 | #endif /* #ifndef BCHP_UARTA_H__ */ |
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| 391 | |
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| 392 | /* End of File */ |
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