source: svn/newcon3bcm2_21bu/magnum/basemodules/hab/3117/bhab_31xx_priv.c

Last change on this file was 76, checked in by megakiss, 10 years ago

1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
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File size: 61.0 KB
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1/***************************************************************************
2 *     Copyright (c) 2003-2011, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bhab_31xx_priv.c $
11 * $brcm_Revision: Hydra_Software_Devel/46 $
12 * $brcm_Date: 8/5/11 5:49p $
13 *
14 *
15 * Revision History:
16 *
17 * $brcm_Log: /magnum/basemodules/hab/3117/bhab_31xx_priv.c $
18 *
19 * Hydra_Software_Devel/46   8/5/11 5:49p mward
20 * SW7125-1057:  Eliminate dead code.  Disable host interrupt in
21 * BHAB_31xx_InitAp() whether or not loading AP code.
22 *
23 * Hydra_Software_Devel/45   3/10/11 5:18p mward
24 * SW7125-845:  Reconcile "deep power down" with BBS power-down script.
25 * If not loading AP, skip operations which can cause poor performance
26 * after power down without AP load.
27 *
28 * Hydra_Software_Devel/44   3/3/11 6:43p mward
29 * SW3128-2: Add Support for BCM3128.  Change n argument of _ReadMemory
30 * and _WriteMemory to uint32_t.
31 *
32 * Hydra_Software_Devel/43   2/1/11 5:35p VISHK
33 * SW7422-171: Nexus support for the 3128 (8 ADS core + tuner on daughter
34 * board) plug on 7422 board  Read and write memory modified to 32 bit
35 * addressing to support 3128 chipset as it has 32 bit memory addressing.
36 *
37 * Hydra_Software_Devel/42   12/16/10 1:41p mward
38 * SW7125-737:  Complete power down whether or not AP was loaded.
39 *
40 * Hydra_Software_Devel/41   12/16/10 1:38p mward
41 * SW7125-737:  BHAB_31xx_Close() free allocated resources in case of I2C
42 * error.
43 *
44 * Hydra_Software_Devel/SW7125-630/2   11/23/10 1:59p mward
45 * SW7125-737:  BHAB_31xx_Close() free allocated resources in case of I2C
46 * error.
47 *
48 * Hydra_Software_Devel/40   12/15/10 4:39p mward
49 * SW7125-737:  Reset AP and clear interrupts when NULL image indicates
50 * not to load it.
51 *
52 * Hydra_Software_Devel/39   12/8/10 2:55p mward
53 * SW7125-737:  Annotate SH_IND register accesses in BHAB_31xx_Close() and
54 * BHAB_31xx_P_ResetAp().
55 *
56 * Hydra_Software_Devel/38   12/2/10 8:38p VISHK
57 * SW7405-5037: To make the i2c address programmable for the slave
58 * device(LNA) of 31xx frontend chip.
59 *
60 * Hydra_Software_Devel/37   12/2/10 8:29p VISHK
61 * SW7420-1020: Request for non-blocking call support in Nexus frontend
62 *
63 * Hydra_Software_Devel/36   11/2/10 6:01p VISHK
64 * SW7420-1020: Request for non-blocking call support in Nexus frontend
65 *
66 * Hydra_Software_Devel/35   10/28/10 4:25p VISHK
67 * SW7420-1020: Request for non-blocking call support in Nexus frontend
68 *
69 * Hydra_Software_Devel/34   10/22/10 3:55p VISHK
70 * SW7420-1020: Request for non-blocking call support in Nexus frontend
71 *
72 * Hydra_Software_Devel/33   10/22/10 3:02p VISHK
73 * SW7125-630: Fixing deadlock with CTRL-C in kernel mode
74 *
75 * Hydra_Software_Devel/32   10/21/10 7:24p VISHK
76 * SW7420-1020: Request for non-blocking call support in Nexus frontend
77 *
78 * Hydra_Software_Devel/31   10/21/10 6:42p VISHK
79 * SW7420-1020: Request for non-blocking call support in Nexus frontend
80 *
81 * Hydra_Software_Devel/31   10/21/10 6:30p vishk
82 * SW7420-1020: Request for non-blocking call support in Nexus frontend
83 *
84 * Hydra_Software_Devel/31   10/21/10 6:29p vishk
85 * SW7420-1020: Request for non-blocking call support in Nexus frontend
86 *
87 * Hydra_Software_Devel/30   8/31/10 3:36p mward
88 * SW7125-35:  When closing, don't reset AP if it wasn't loaded by the
89 * host at start time.
90 *
91 * Hydra_Software_Devel/29   8/26/10 1:47p mward
92 * SW7125-597:  To avoid a resource leak, BHAB_31xx_Open() should return
93 * the allocated BHAB_Handle with the error code, for clean-up in
94 * BHAB_31xx_Close().  BHAB_31xx_Close() should check resources to clean
95 * up partial failures.
96 *
97 * Hydra_Software_Devel/28   7/2/10 4:22p vishk
98 * SW7420-873: Add support to inform application to update frontend tuner
99 * gain and to inform that there is no signal to tune upon multiple tries
100 * to acquire
101 *
102 * Hydra_Software_Devel/27   7/2/10 3:13p mward
103 * SW7420-839: In function BHAB_31xx_SetNmiConfig() array subscript was
104 * above array bounds.
105 *
106 * Hydra_Software_Devel/26   6/22/10 6:01p vishk
107 * SW7420-839: Add support to program AGC gain to 31xx TNR PI
108 *
109 * Hydra_Software_Devel/25   6/21/10 11:04a mward
110 * SW7125-35:  Add an option to init AP without re-loading AP image.
111 * Increase buf[] in BHAB_31xx_SetNmiConfig.  Free the pImpl when closing
112 * to avoid leak.
113 *
114 * Hydra_Software_Devel/24   3/4/10 3:24p VISHK
115 * SW7405-3978: bcm3117: BHAB_31xx_InitAp() has retry logic error
116 *
117 * Hydra_Software_Devel/23   1/21/10 12:31p VISHK
118 * SW7405-3820: BCM3109 reports poor BER at a specific range of signal
119 * power
120 *
121 * Hydra_Software_Devel/22   11/18/09 11:50a VISHK
122 * SW7405-3356: 3117 tuner wil get HAB timeout on Motorola DCX700 by plug
123 * and unplug RF feed back and force, it's been test against
124 * REFSW_MOT_31XX_20091105 label
125 *
126 * Hydra_Software_Devel/21   11/5/09 2:00p VISHK
127 * SW7405-3210: BADS_31xx_GetStatus not returning values for
128 * correctedCount, uncorrectedCount and berRawCount
129 *
130 * Hydra_Software_Devel/20   10/14/09 1:48p mward
131 * SW7405-2851: Compiler warning:  Added "const" to BHAB_NmiSettings and
132 * BHAB_WatchDogTimerSettings.
133 *
134 * Hydra_Software_Devel/19   10/5/09 10:46a vishk
135 * SW7405-2851: 31xx: Add support to configure the Watchdog feature of
136 * 31xx.
137 *
138 * Hydra_Software_Devel/18   8/27/09 12:45p vishk
139 * SW7405-2939: i2c communication issue (bhab error in
140 * BHAB_31xx_P_ResetAp)
141 *
142 * Hydra_Software_Devel/17   8/26/09 10:52a vishk
143 * SW7405-2700: 3117 does not report lock status to the app.
144 *
145 * Hydra_Software_Devel/16   7/13/09 2:26p vishk
146 * PR 56618: 3117 does not report lock status to the app.
147 *
148 * Hydra_Software_Devel/15   7/8/09 10:55a vishk
149 * PR 56618: 3117 does not report lock status to the app.
150 *
151 * Hydra_Software_Devel/14   7/7/09 1:44a vishk
152 * PR 56618: 3117 does not report lock status to the app.
153 *
154 * Hydra_Software_Devel/13   6/2/09 1:40p vishk
155 * PR 53208: 3117 AP does not initialize on firs attemp consistently
156 *
157 * Hydra_Software_Devel/12   6/1/09 3:30p vishk
158 * PR 53208: 3117 AP does not initialize on firs attemp consistently
159 *
160 * Hydra_Software_Devel/11   5/12/09 10:53a vishk
161 * PR 46431: Add support for BCM3117, BCM3114, and BCM3112
162 *
163 * Hydra_Software_Devel/10   4/16/09 11:28a vishk
164 * PR 46431: Add support for BCM3117, BCM3114, and BCM3112
165 *
166 * Hydra_Software_Devel/9   3/13/09 11:18a vishk
167 * PR 46431: Add support for BCM3117, BCM3114, and BCM3112
168 *
169 * Hydra_Software_Devel/8   3/12/09 4:36p vishk
170 * PR 46431: Add support for BCM3117, BCM3114, and BCM3112
171 *
172 * Hydra_Software_Devel/7   3/10/09 1:51p vishk
173 * PR 46431: Add support for BCM3117, BCM3114, and BCM3112
174 ***************************************************************************/
175#include "bhab_31xx_priv.h"
176
177BDBG_MODULE(bhab_31xx_priv);
178
179/******************************************************************************
180 BHAB_31xx_Open()
181******************************************************************************/
182BERR_Code BHAB_31xx_Open(
183    BHAB_Handle *handle,     /* [out] BHAB handle */
184    void        *pReg,       /* [in] pointer ot i2c or spi handle */
185    const BHAB_Settings *pDefSettings /* [in] Default Settings */
186)
187{
188    BERR_Code retCode;
189    BHAB_Handle hDev;
190    BHAB_31xx_P_Handle *h31xxDev;
191    unsigned i;
192
193    BDBG_ASSERT(pDefSettings->interruptEnableFunc);
194
195    hDev = (BHAB_Handle)BKNI_Malloc(sizeof(BHAB_P_Handle));
196    BDBG_ASSERT(hDev);
197    h31xxDev = (BHAB_31xx_P_Handle *)BKNI_Malloc(sizeof(BHAB_31xx_P_Handle));
198    BDBG_ASSERT(h31xxDev);
199    BKNI_Memset( h31xxDev, 0x00, sizeof(BHAB_31xx_P_Handle));
200    hDev->pImpl = (void*)h31xxDev;
201   
202    h31xxDev->hRegister = (BREG_I2C_Handle)pReg;
203    BKNI_Memcpy((void*)(&(hDev->settings)), (void*)pDefSettings, sizeof(BHAB_Settings));
204   
205
206    /* create events */
207    BHAB_CHK_RETCODE(BKNI_CreateEvent(&(h31xxDev->hInterruptEvent)));
208    BHAB_CHK_RETCODE(BKNI_CreateEvent(&(h31xxDev->hApiEvent)));
209    BHAB_CHK_RETCODE(BKNI_CreateEvent(&(h31xxDev->hInitDoneEvent)));
210    BHAB_CHK_RETCODE(BKNI_CreateEvent(&(h31xxDev->hHabDoneEvent)));
211    BHAB_CHK_RETCODE(BKNI_CreateMutex(&(h31xxDev->hMutex)));
212
213    h31xxDev->last_page_16_15 = 0xFF;
214    h31xxDev->last_page_14_7 = 0xFF;   
215
216    for(i=0; i<BHAB_DevId_eMax; i++){
217        h31xxDev->InterruptCallbackInfo[i].func = NULL;
218        h31xxDev->InterruptCallbackInfo[i].pParm1 = NULL;
219        h31xxDev->InterruptCallbackInfo[i].parm2 = (int)NULL;
220    }
221
222    BKNI_Memset( &h31xxDev->nmiSettings, 0x00, sizeof(BHAB_NmiSettings));
223    BKNI_Memset( &h31xxDev->wdtSettings, 0x00, sizeof(BHAB_WatchDogTimerSettings));
224
225    retCode = BHAB_31xx_P_DisableInterrupts(hDev);
226    h31xxDev->slaveChipAddr = pDefSettings->slaveChipAddr;
227
228done:
229    *handle = hDev;
230
231    return retCode;
232}
233
234
235/******************************************************************************
236 BHAB_31xx_Close()
237******************************************************************************/
238BERR_Code BHAB_31xx_Close(BHAB_Handle handle)
239{
240    BERR_Code retCode;
241    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
242    uint8_t buf[4], sb, i;
243   
244    BDBG_ASSERT(handle);
245
246#if (BCHP_CHIP != 7125) /* This reset prevents us from restarting without reloading AP */
247    buf[0]= 0x00;   /* SH_IND_GLOBAL_RESET1 */
248    buf[1]= 0x0f;   /* AP_WDT_RST=1 UPG_WDT_RST=1 UPG_RST=1 PERIPH_RST=1 */
249    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
250 
251    buf[0]= 0x01;   /* SH_IND_GLOBAL_RESET0 */
252    buf[1]= 0xff;   /* OTP_RST=1 TM_RST=1 reserved=1 DS_RST=1 AP_RST=1 reserved=1 reserved=1 CG_RST=1 */
253    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
254#endif
255
256    buf[0]= 0x02;   /* SH_IND_OSC_CTRL1 */
257    buf[1]= 0x00;   /* IAMP_ADJ=150uA ICBUF_ADG=150uA IBUFD_ADJ=200uA LIMIT_AMP=inactive XTAL_ADJ_CM 1.45V */
258    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
259
260    buf[0]= 0x03;   /* SH_IND_OSC_CTRL0 ' disable diffosc clocks */
261    buf[1]= 0x7d;   /* BYP_DBLR=0 DISABLE_CML6=1 DISABLE_CML5=1 DISABLE_CML4=1 DISABLE_CML3=1 DISABLE_CML2=1 ENABLE_FMON=0 PWRDN_DBLR=1 */
262    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
263
264    buf[0]= 0x05;   /* SH_IND_POWER_UP ' power down d2cdiff_54, d2cdiff_108 and tuner */
265    buf[1]= 0x00;   /* PWRUP_TUNER=0 PWRUP_108=0 PWRUP_54=0 */
266    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
267   
268    buf[0]= 0x07;   /* SH_IND_CLK_ENABLE1 ' disable internal register clocks */
269    buf[1]= 0x00;   /* EN_OTP_9=0 EN_UPG_27=0 */
270    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
271
272    buf[0]= 0x08;   /* SH_IND_CLK_ENABLE0 ' disable internal register clocks */
273    buf[1]= 0x00;   /* EN_UPG_54=0 EN_PLL_54=0 EN_DS_54=0 EN_AP_54=0 EN_AP_108=0 */
274    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
275
276    /* reset the AP */
277    sb = 0x1;
278    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb, 1));
279
280    /* reset all interrupt status */
281    for (i = 0; i < 4; i++)
282        buf[i] = 0xFF;
283    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), buf, 4));
284   
285    /* clear MSGx registers */
286    buf[0] = buf[1] = 0x00;
287    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_MSG1), buf, 2));
288
289    retCode = BHAB_31xx_P_DisableInterrupts(handle);
290done:
291    if (p31xx->hInterruptEvent) {BKNI_DestroyEvent(p31xx->hInterruptEvent);}
292    if (p31xx->hApiEvent){BKNI_DestroyEvent(p31xx->hApiEvent);}
293    if (p31xx->hInitDoneEvent){BKNI_DestroyEvent(p31xx->hInitDoneEvent);}
294    if (p31xx->hHabDoneEvent){BKNI_DestroyEvent(p31xx->hHabDoneEvent);}
295    if (p31xx->hMutex){BKNI_DestroyMutex(p31xx->hMutex);}
296
297    BKNI_Free((void*)p31xx);
298    BKNI_Free((void*)handle);
299
300    return retCode;
301}
302
303/******************************************************************************
304 BHAB_31xx_P_ClearAllInterrupts()
305******************************************************************************/ 
306BERR_Code BHAB_31xx_P_ClearAllInterrupts(
307    BHAB_Handle handle   /* [in] BHAB Handle */
308)
309{   
310    BERR_Code err;
311    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
312    const uint8_t val[4] = {0xFF, 0xFF, 0xFF, 0xFF};
313   
314     /* reset all interrupt status */
315    err = BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), val, 4);
316    return err;   
317}
318
319/******************************************************************************
320 BHAB_31xx_P_InitAp()
321******************************************************************************/
322BERR_Code BHAB_31xx_InitAp(
323    BHAB_Handle handle,       /* [in] BHAB handle */
324    const uint8_t *pHexImage  /* [in] pointer to BCM31xx microcode image */
325)
326{
327    BERR_Code retCode;
328    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
329    uint16_t n, addr;
330    const uint8_t *pImage;
331    uint8_t sb, retries, count=0;
332
333        /* Disable host interrupt */   
334        BHAB_CHK_RETCODE(BHAB_31xx_P_EnableHostInterrupt(handle, false));
335
336    /* We are loading AP code, it is appropriate to reset the AP when closing */
337    if (pHexImage)
338    {
339        p31xx->loadAP = true;
340   
341        /* reset the AP before downloading the microcode */
342        BHAB_CHK_RETCODE(BHAB_31xx_P_ResetAp(handle));
343   
344        /* download to RAM */
345        pImage = pHexImage;
346        while (1)
347        {
348            n = (*pImage++ << 8);
349            n |= *pImage++;
350           
351            if (n == 0)
352                break;
353           
354            addr = (*pImage++ << 8);
355            addr |= *pImage++;
356           
357            for (retries = 0; retries < 3; retries++)
358            {
359                BHAB_CHK_RETCODE(BHAB_31xx_WriteMemory(handle, addr, pImage, n));           
360               
361                /* check for host transfer error */
362                BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), &sb, 1));           
363                if ((sb & DEVICE(STAT1_H_ER)) == 0)
364                    break;
365               
366                BDBG_WRN(("host transfer error\n"));
367                BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), &sb, 1));           
368            }
369   
370            if (retries == 3)
371                return(BERR_OS_ERROR);
372   
373            pImage += n;
374        }
375   
376     start_over:               
377        /* enable init done interrupt */
378        BHAB_CHK_RETCODE(BHAB_31xx_P_EnableInitDoneInterrupt(handle));
379   
380        /* clear H_STAT1 */
381        sb = 0xFF;
382        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), &sb, 1));   
383   
384        /* start running the AP */
385        if ((retCode = BHAB_31xx_P_RunAp(handle)) != BERR_SUCCESS)
386            goto done;
387   
388        /* wait for init done interrupt */
389        if (BHAB_31xx_P_WaitForEvent(handle, p31xx->hInitDoneEvent, 150) != BERR_SUCCESS)
390        {
391            /* Disable host interrupt */   
392            BHAB_CHK_RETCODE(BHAB_31xx_P_EnableHostInterrupt(handle, false));
393       
394            /* reset the AP before downloading the microcode */
395            BHAB_CHK_RETCODE(BHAB_31xx_P_ResetAp(handle));
396            BKNI_Sleep(20);
397            BDBG_WRN(("AP initialization timeout. Starting over %d times", count)); 
398            if(count++ < BHAB_INIT_RETRIES)
399                goto start_over;       
400            BDBG_MSG(("AP initialization timeout.")); 
401            BERR_TRACE(retCode = BHAB_ERR_AP_NOT_INIT);           
402        }
403    }
404    else
405    {
406        BDBG_MSG(("BHAB_31xx_P_ClearAllInterrupts()"));
407        BHAB_CHK_RETCODE(BHAB_31xx_P_ClearAllInterrupts(handle));
408        BDBG_MSG(("BHAB_31xx_P_ResetAp()"));
409        BHAB_CHK_RETCODE(BHAB_31xx_P_ResetAp(handle));
410        BKNI_Sleep(20);
411    }
412 done:
413    return retCode;
414}
415
416
417/******************************************************************************
418 BHAB_31xx_GetApStatus()
419******************************************************************************/
420BERR_Code BHAB_31xx_GetApStatus(
421   BHAB_Handle handle,      /* [in] HAB device handle */
422   BHAB_ApStatus *pStatus   /* [out] AP status */
423)
424{
425    BERR_Code retCode;
426    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
427    uint8_t buf[4];
428
429    *pStatus = 0;
430    BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), buf, 4));
431    *pStatus = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
432   
433 done:
434    return retCode;
435}
436
437
438/******************************************************************************
439 BHAB_31xx_GetApVersion()
440******************************************************************************/
441BERR_Code BHAB_31xx_GetApVersion(
442    BHAB_Handle handle,     /* [in] BHAB handle */
443    uint16_t    *pChipId,   /* [out] BHAB chip ID */
444    uint16_t    *pChipVer,  /* [out] chip revision number */
445    uint8_t     *pApVer,    /* [out] AP microcode version */
446    uint8_t     *pScrVer,   /* [out] acquisition script version */
447    uint8_t     *pCfgVer    /* [out] host configuration version */
448)
449{
450    BERR_Code retCode;
451    uint8_t buf[8];
452
453    buf[0] = 0x09;
454    BHAB_CHK_RETCODE(BHAB_31xx_SendHabCommand(handle, buf, 1, buf, 8, true, true, 8));
455
456    *pChipId = ((buf[1] << 8) | buf[2]);
457    *pChipVer = ((buf[3] << 8) | buf[4]);
458    *pApVer = buf[5];
459    *pScrVer = buf[6];
460    *pCfgVer = buf[7];
461
462 done:
463    return retCode;
464}
465
466
467/******************************************************************************
468 BHAB_31xx_ReadRegister()
469******************************************************************************/
470BERR_Code BHAB_31xx_ReadRegister(
471    BHAB_Handle handle,     /* [in] BHAB handle */
472    uint32_t    reg,   /* [in] address of register to read */
473    uint32_t    *val   /* [in] contains data that was read */
474)
475{
476    BERR_Code retCode;
477    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
478    uint8_t sb;
479
480    if ((reg >= 0x80) && (reg <= 0xFF))
481    {
482        /* accessing host register space */
483        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, reg, &sb, 1));     
484        *val = (uint32_t)sb;
485    }
486    else
487    {
488        /* accessing internal registers through io_mbox */
489        BHAB_CHK_RETCODE(BHAB_31xx_ReadMbox(handle, (uint16_t)reg, val));
490    }
491
492 done:
493    return retCode;
494}
495
496
497/******************************************************************************
498 BHAB_31xx_WriteRegister()
499******************************************************************************/
500BERR_Code BHAB_31xx_WriteRegister(
501    BHAB_Handle handle,     /* [in] BHAB handle */
502    uint32_t    reg,   /* [in] address of register to read */
503    uint32_t    *val   /* [in] contains data that was read */
504)
505{
506    BERR_Code retCode;
507    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
508    uint8_t sb;
509
510    if ((reg >= 0x80) && (reg <= 0xFF))
511    {
512        /* accessing host register space */
513        sb = (uint8_t)(*val);
514        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, reg, &sb, 1));     
515    }
516    else
517    {
518        /* accessing internal registers through io_mbox */
519        BHAB_CHK_RETCODE(BHAB_31xx_WriteMbox(handle, (uint16_t)reg, val));
520    }
521
522 done:
523    return retCode;
524}
525
526
527/******************************************************************************
528 BHAB_31xx_ReadMemory()
529******************************************************************************/
530BERR_Code BHAB_31xx_ReadMemory(BHAB_Handle handle, uint32_t addr, uint8_t *buf, uint32_t n)
531{   
532    BERR_Code retCode;
533    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
534
535    if (((uint32_t)addr + (uint32_t)n) > BHAB_MEM_SIZE)
536        return BERR_TRACE(BERR_INVALID_PARAMETER);
537
538    BHAB_CHK_RETCODE(BHAB_31xx_P_SetApWindow(handle, BHAB_WINDOW_IRAM + addr));
539    BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, addr & 0x7F, buf, n));   
540
541 done:
542    return retCode;
543}
544
545
546/******************************************************************************
547 BHAB_31xx_WriteMemory()
548******************************************************************************/
549BERR_Code BHAB_31xx_WriteMemory(BHAB_Handle handle, uint32_t addr, const uint8_t *buf, uint32_t n)
550{   
551    BERR_Code retCode = BERR_SUCCESS;
552    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
553    uint32_t  curr_addr, nbytes, bytes_left;
554
555    if ((addr + n) > BHAB_IRAM_SIZE)
556        return BERR_TRACE(BERR_INVALID_PARAMETER);
557
558    curr_addr = addr;
559    bytes_left = n;
560    while (bytes_left > 0)
561    {
562        BHAB_CHK_RETCODE(BHAB_31xx_P_SetApWindow(handle, BHAB_WINDOW_IRAM + curr_addr));
563        nbytes = 128 - (curr_addr % 128);
564        if (nbytes > bytes_left)
565            nbytes = bytes_left;
566        bytes_left -= nbytes;
567        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, curr_addr & 0x7F, buf, nbytes));
568        curr_addr += nbytes;
569        buf += nbytes;
570    }
571
572 done:
573    return retCode;
574}
575
576/******************************************************************************
577 BHAB_31xx_ReadMbox()
578******************************************************************************/
579BERR_Code BHAB_31xx_ReadMbox(
580    BHAB_Handle handle,    /* [in] BHAB PI Handle */
581    uint32_t    reg,  /* [in] RBUS register address */
582    uint32_t    *val  /* [out] value read from register */
583)
584{   
585    BERR_Code retCode;
586    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
587    uint8_t sb, i, buf[4];
588
589    /* update bits 15:8 of mbox address if changed */
590    sb = reg >> 8;
591    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_A_15_8), &sb, 1));   
592    sb = reg >> 24;
593    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_A_31_24), &sb, 1));   
594    sb = reg >> 16;
595    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_A_23_16), &sb, 1));   
596   
597
598    /* read from mbox */
599    sb = reg & 0xFC;
600    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_CMD), &sb, 1));
601
602    /* check for mbox transfer complete */
603    for (i = 0; i < 3; i++)
604    {
605        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_STATUS), &sb, 1));       
606        if ((sb & 0x80) == 0)
607        {
608            if (sb & 0x40)
609            {
610                BERR_TRACE(retCode = BHAB_ERR_IOMB_XFER);
611                goto done;
612            }
613            else
614            {
615                /* transfer completed - now get the data */
616                BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_D_31_24), buf, 4));
617                *val = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
618            }
619            break;
620        }
621    }
622
623    if (i >= 3)
624    {
625        /* this should not happen */
626        BERR_TRACE(retCode = BHAB_ERR_IOMB_BUSY);
627        BDBG_ERR(("IO_MBOX busy\n"));
628    }
629
630 done:
631    return retCode;
632}
633
634
635/******************************************************************************
636 BHAB_31xx_WriteMbox()
637******************************************************************************/
638BERR_Code BHAB_31xx_WriteMbox(
639    BHAB_Handle handle,    /* [in] BHAB PI Handle */
640    uint32_t    reg,  /* [in] RBUS register address */
641    uint32_t    *val  /* [in] value to write */
642)
643{   
644    BERR_Code retCode;
645    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
646    uint8_t buf[8], sb, i;
647
648    /* write addr, data, and cmd in one i2c transaction */
649    buf[0] = reg >> 8;
650    buf[1] = *val >> 24;
651    buf[2] = *val >> 16;
652    buf[3] = *val >> 8;
653    buf[4] = *val & 0xFF; 
654    buf[5] = (reg & 0xFC) | 0x01;
655    buf[6] = reg >> 24;
656    buf[7] = reg >> 16; 
657
658    for (i = 0; i < 3; i++)
659    {
660        /* check for mbox transfer complete */
661        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_STATUS), &sb, 1));
662
663        if ((sb & 0x80) == 0) {
664            if (sb & 0x40) {
665                BDBG_ERR(("Before Transfer -  i = %d", i));
666                BERR_TRACE(retCode = BHAB_ERR_IOMB_XFER);
667                goto done;
668            }
669            break;         
670        }
671        else{
672            BDBG_ERR(("IO_MBOX operation in progress -  i = %d", i));
673        }
674    }
675
676    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_A_15_8), buf, 8));
677
678    for (i = 0; i < 3; i++)
679    {
680        /* check for mbox transfer complete */
681        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_IO_MBOX_STATUS), &sb, 1));
682
683        if ((sb & 0x80) == 0) {
684            if (sb & 0x40) {
685                BDBG_ERR(("After Transfer -  i = %d", i));
686                BERR_TRACE(retCode = BHAB_ERR_IOMB_XFER);
687                goto done;
688            }
689            break;         
690        }
691        else{
692            BDBG_ERR(("IO_MBOX operation in progress -  i = %d", i));
693        }
694    }
695
696    if (sb & 0x80)
697    {
698        /* this should not happen */
699        BERR_TRACE(retCode = BHAB_ERR_IOMB_BUSY);
700        BDBG_ERR(("IO_MBOX busy\n"));
701    }
702
703 done:
704    return retCode;
705}
706
707
708/******************************************************************************
709 BHAB_31xx_HandleInterrupt_isr()
710******************************************************************************/
711BERR_Code BHAB_31xx_HandleInterrupt_isr(
712    BHAB_Handle handle /* [in] BHAB handle */
713)
714{
715    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
716    BKNI_ASSERT_ISR_CONTEXT();
717
718    BDBG_ASSERT(handle);
719    handle->settings.interruptEnableFunc(false, handle->settings.interruptEnableFuncParam);
720   
721    BKNI_SetEvent(p31xx->hApiEvent);   
722    BKNI_SetEvent(p31xx->hInterruptEvent);
723    return BERR_SUCCESS;
724}
725
726
727/******************************************************************************
728 BHAB_31xx_ProcessInterruptEvent()
729******************************************************************************/
730BERR_Code BHAB_31xx_ProcessInterruptEvent(
731    BHAB_Handle handle  /* [in] BHAB handle */
732)
733{
734    BERR_Code retCode;
735    BDBG_ASSERT(handle);
736
737    BHAB_31xx_P_EnableHostInterrupt(handle, false);
738    BHAB_CHK_RETCODE(BHAB_31xx_P_DecodeInterrupt(handle));
739    BHAB_31xx_P_EnableHostInterrupt(handle, true);
740 done:
741    return retCode;
742}
743
744
745/******************************************************************************
746 BHAB_31xx_EnableLockInterrupt()
747******************************************************************************/ 
748BERR_Code BHAB_31xx_EnableLockInterrupt(
749    BHAB_Handle handle,  /* [in] BHAB handle */
750    BHAB_DevId eDevId,    /* [in] Device ID */
751    bool bEnable   /* [in] true = enable Lock  interrupt */
752)
753{
754    BERR_Code retCode = BERR_SUCCESS;
755    uint8_t sb[2], tb;
756    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
757   
758    if( eDevId == BHAB_DevId_eADS0) {
759        BHAB_31xx_P_EnableHostInterrupt(handle, false);
760            sb[0] = 0;
761            sb[1] = 0;
762        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE3), &sb[1], 1));
763
764        if(bEnable) {
765            sb[0] = DEVICE(STAT2_LOCK_MASK);
766            sb[1] |= (DEVICE(STAT3_GAIN_MASK) | DEVICE(STAT3_QAM_STATUS_READY));
767        }
768        else {
769            sb[0] = 0;
770            /*sb[1] &= ~DEVICE(STAT3_GAIN_MASK); ;*/
771           
772        }
773        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE2), sb, 2));         
774        BHAB_31xx_P_EnableHostInterrupt(handle, true);
775    }
776    else if ( eDevId == BHAB_DevId_eAOB0) {
777       
778        BHAB_31xx_P_EnableHostInterrupt(handle, false);
779        tb = 0;
780        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE3), &tb, 1));
781       
782        if(bEnable) {
783            tb |= (DEVICE(STAT3_LOCK_MASK) | DEVICE(STAT3_OOB_STATUS_READY));
784        }
785        else {
786            tb = 0;           
787        }
788
789        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE3), &tb, 1));         
790        BHAB_31xx_P_EnableHostInterrupt(handle, true);
791    }
792   
793 done:
794    return retCode;   
795}
796   
797
798/******************************************************************************
799 BHAB_31xx_InstallInterruptCallback()
800******************************************************************************/ 
801BERR_Code BHAB_31xx_InstallInterruptCallback(
802    BHAB_Handle handle,  /* [in] BHAB handle */
803    BHAB_DevId eDevId,    /* [in] Device ID */
804    BHAB_IntCallbackFunc fCallBack,
805    void * pParm1, 
806    int parm2
807)
808{
809    BHAB_P_CallbackInfo *callback;
810    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
811
812    BDBG_ASSERT(handle);
813   
814    /*TODO : setup bitmask to enable/disable interrupt callabcks*/
815
816    if (eDevId >= BHAB_DevId_eMax) {
817        return BERR_TRACE(BERR_INVALID_PARAMETER);
818    }
819
820    callback = &p31xx->InterruptCallbackInfo[eDevId];
821
822    callback->func = fCallBack;
823    callback->pParm1 = pParm1;
824    callback->parm2 = parm2;
825
826    return BERR_TRACE(BERR_SUCCESS);
827}
828
829
830/******************************************************************************
831 BHAB_31xx_UnInstallInterruptCallback()
832******************************************************************************/ 
833BERR_Code BHAB_31xx_UnInstallInterruptCallback(
834    BHAB_Handle handle,  /* [in] BHAB handle */
835    BHAB_DevId eDevId    /* [in] Device ID */
836)
837{
838    BHAB_P_CallbackInfo *callback;
839    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
840
841    BDBG_ASSERT(handle);
842   
843    if (eDevId >= BHAB_DevId_eMax) {
844        return BERR_TRACE(BERR_INVALID_PARAMETER);
845    }
846
847    callback = &p31xx->InterruptCallbackInfo[eDevId];
848
849    callback->func = NULL;
850    callback->pParm1 = NULL;
851    callback->parm2 = (int)NULL;
852
853    return BERR_TRACE(BERR_SUCCESS);
854}   
855   
856
857/******************************************************************************
858 BHAB_31xx_SendHabCommand()
859******************************************************************************/
860BERR_Code BHAB_31xx_SendHabCommand(
861    BHAB_Handle handle, /* [in] BHAB PI Handle */
862    uint8_t *write_buf, /* [in] specifies the HAB command to send */
863    uint8_t write_len,  /* [in] number of bytes in the HAB command */ 
864    uint8_t *read_buf,  /* [out] holds the data read from the HAB */ 
865    uint8_t read_len,   /* [in] number of bytes to read from the HAB */
866    bool bCheckForAck,  /* [in] true = determine if the AP has serviced the command */
867    bool bInsertTermination, /* [in] true = insert termination byte 0x00 in write buffer at read_len position */
868    uint8_t command_len
869)
870{
871    BERR_Code retCode;
872    uint8_t term_buf;
873
874    BHAB_P_ACQUIRE_MUTEX(handle);
875   
876    if ((write_len > 127) || (read_len > 127) || (write_len == 0))
877        return (BERR_TRACE(BERR_INVALID_PARAMETER));
878
879    BHAB_CHK_RETCODE(BHAB_31xx_P_CheckHab(handle));
880 
881    /* write the command to the HAB */
882    BHAB_CHK_RETCODE(BHAB_31xx_P_WriteHab(handle, 0, write_buf, write_len));
883
884    if(bInsertTermination){
885        term_buf = 0x00;
886        BHAB_CHK_RETCODE(BHAB_31xx_P_WriteHab(handle, command_len, &term_buf, 1));
887    }
888
889    /* wait for the AP to service the HAB, and then read any return data */
890    BHAB_CHK_RETCODE(BHAB_31xx_P_ServiceHab(handle, read_buf, read_len, bCheckForAck, write_buf[0] | 0x80));
891 
892 done:
893    BHAB_P_RELEASE_MUTEX(handle);
894
895    return retCode;
896}
897
898/******************************************************************************
899 BHAB_31xx_GetInterruptEventHandle()
900******************************************************************************/
901BERR_Code BHAB_31xx_GetInterruptEventHandle(
902    BHAB_Handle handle,            /* [in] BHAB handle */
903    BKNI_EventHandle *hEvent       /* [out] interrupt event handle */
904)
905{
906    *hEvent = ((BHAB_31xx_P_Handle *)(handle->pImpl))->hInterruptEvent;
907    return BERR_SUCCESS;
908}
909
910
911
912/****************************Private Functions*********************************/
913
914
915
916
917/******************************************************************************
918 BHAB_31xx_P_EnableHostInterrupt()
919******************************************************************************/
920BERR_Code BHAB_31xx_P_EnableHostInterrupt(
921    BHAB_Handle handle, /* [in] HAB handle */
922    bool bEnable        /* [in] true=enables the L1 interrupt on the host processor */
923)
924{
925    BKNI_EnterCriticalSection();
926    handle->settings.interruptEnableFunc(bEnable, handle->settings.interruptEnableFuncParam);
927    BKNI_LeaveCriticalSection();
928
929    return BERR_SUCCESS;
930}
931
932/******************************************************************************
933 BHAB_31xx_P_DisableInterrupts()
934******************************************************************************/ 
935BERR_Code BHAB_31xx_P_DisableInterrupts(
936    BHAB_Handle handle   /* [in] BHAB Handle */
937)
938{   
939    BERR_Code err;
940    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
941    const uint8_t val[4] = {0, 0, 0, 0};
942   
943    /* clear IEx registers */
944    err = BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE1), val, 4);
945    return err;   
946}
947
948
949/******************************************************************************
950 BHAB_31xx_P_EnableInitDoneInterrupt()
951******************************************************************************/ 
952BERR_Code BHAB_31xx_P_EnableHabDoneInterrupt(
953    BHAB_Handle handle /* [in] BHAB PI Handle */
954)
955{ 
956    BERR_Code retCode; 
957    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
958    uint8_t sb;
959   
960    sb = DEVICE(STAT1_HAB_DONE);
961    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), &sb, 1));
962    sb = DEVICE(STAT1_HAB_DONE);
963    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE1), &sb, 1));
964   
965 done:
966    return retCode;
967}
968
969
970/******************************************************************************
971 BHAB_31xx_P_EnableInitDoneInterrupt()
972******************************************************************************/ 
973BERR_Code BHAB_31xx_P_EnableInitDoneInterrupt(
974    BHAB_Handle handle /* [in] BHAB PI Handle */
975)
976{ 
977    BERR_Code retCode;
978    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
979    uint8_t sb;
980
981    sb = DEVICE(STAT2_INIT_DONE);
982    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT2), &sb, 1));   
983    sb = DEVICE(STAT2_INIT_DONE);
984    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE2), &sb, 1));
985   
986 done:
987    return retCode;
988}
989
990/******************************************************************************
991 BERR_31xx_Code BHAB_P_WaitForEvent()
992******************************************************************************/
993BERR_Code BHAB_31xx_P_WaitForEvent(
994    BHAB_Handle handle,             /* [in] BHAB PI Handle */
995    BKNI_EventHandle hEvent,   /* [in] event to wait on */
996    int timeoutMsec            /* [in] timeout in milliseconds */
997)
998{   
999    BERR_Code retCode = BERR_SUCCESS;
1000    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1001   
1002    while (1)
1003    {   
1004        BHAB_31xx_P_EnableHostInterrupt(handle, true);
1005
1006        retCode = BKNI_WaitForEvent(p31xx->hApiEvent, timeoutMsec);
1007        if ( retCode != BERR_SUCCESS ) { break; }
1008
1009        BHAB_31xx_P_EnableHostInterrupt(handle, false);
1010        BHAB_31xx_P_DecodeInterrupt(handle);
1011
1012        retCode = BKNI_WaitForEvent(hEvent, 0);
1013        if (retCode == BERR_SUCCESS || retCode == BERR_OS_ERROR) { break; }
1014    }
1015
1016    BHAB_31xx_P_EnableHostInterrupt(handle, true);
1017
1018    return retCode;
1019
1020}
1021
1022
1023/******************************************************************************
1024 BHAB_31xx_P_RunAp()
1025******************************************************************************/
1026BERR_Code BHAB_31xx_P_RunAp(BHAB_Handle handle)
1027{
1028    BERR_Code retCode;
1029    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1030    uint8_t   sb, sb2;
1031
1032    /* check if the AP is currently running */
1033    BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb, 1));
1034    if ((sb & DEVICE(AP_MASK)) != DEVICE(AP_RUN))
1035    {
1036        BHAB_31xx_P_EnableHostInterrupt(handle, true);
1037       
1038        /* start running the AP */
1039        sb2 = DEVICE(AP_RUN);
1040        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb2, 1));       
1041       
1042        /* verify that the AP is running */
1043        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb, 1));     
1044        if ((sb & DEVICE(AP_MASK)) != DEVICE(AP_RUN))
1045        {
1046            BDBG_ERR(("unable to run the AP\n"));
1047            BERR_TRACE(retCode = BHAB_ERR_AP_FAIL);
1048            goto done;
1049        }
1050       
1051        /* clear AP_change state bit */
1052        sb2 = DEVICE(STAT1_AP_OP_CHG);
1053        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), &sb2, 1));   
1054    }
1055    else
1056    {
1057        BDBG_WRN(("BHAB_P_RunAp(): AP already running\n"));
1058    }
1059
1060 done:
1061    return retCode;
1062}
1063
1064
1065/******************************************************************************
1066 BHAB_31xx_P_ResetAp()
1067******************************************************************************/
1068BERR_Code BHAB_31xx_P_ResetAp(BHAB_Handle handle)
1069{   
1070   
1071    uint8_t i, sb, buf[4];
1072    BERR_Code retCode = BERR_SUCCESS;
1073    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1074    uint32_t val=0;
1075    if (p31xx->loadAP)
1076    {
1077        buf[0]= 0x00;   /* SH_IND_GLOBAL_RESET1 */
1078        buf[1]= 0xff;   /* reserved=0xf AP_WDT_RST=1 UPG_WDT_RST=1 UPG_RST=1 PERIPH_RST=1 */
1079        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1080       
1081        buf[0]= 0x01;   /* SH_IND_GLOBAL_RESET0 */
1082        buf[1]= 0xff;   /* OTP_RST=1 TM_RST=1 reserved=1 DS_RST=1 AP_RST=1 reserved=1 reserved=1 CG_RST=1 */
1083        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1084    }
1085
1086    buf[0]= 0x02;   /* SH_IND_OSC_CTRL1 */
1087    buf[1]= 0xa0;   /* IAMP_ADJ=250uA ICBUF_ADG=250uA IBUFD_ADJ=200uA LIMIT_AMP=inactive XTAL_ADJ_CM 1.45V */
1088    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1089
1090    buf[0]= 0x03;   /* SH_IND_OSC_CTRL0 ' enable diffosc clocks */
1091    buf[1]= 0x40;   /* BYP_DBLR=0 DISABLE_CML6=1 DISABLE_CML5=0 DISABLE_CML4=0 DISABLE_CML3=0 DISABLE_CML2=0 ENABLE_FMON=0 PWRDN_DBLR=0 */
1092    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1093
1094    buf[0]= 0x06;   /* SH_IND_CLK_CNTRL */
1095    buf[1]= 0x00;   /* AP_CLK_SRC=DIFFOSC_108 */
1096    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1097   
1098    buf[0]= 0x05;   /* SH_IND_POWER_UP ' power up d2cdiff_54, d2cdiff_108 and tuner */
1099    buf[1]= 0x07;   /* PWRUP_TUNER=1 PWRUP_108=1 PWRUP_54=1 */
1100    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1101
1102    buf[0]= 0x09;   /* SH_IND_D2CDIFF_CNTRL NO_AC_108=0 NO_AC_54=0*/
1103    buf[1]= 0x00;   /* NO_AC_108=0 NO_AC_54=0 */
1104    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1105   
1106    buf[0]= 0x07;   /* SH_IND_CLK_ENABLE1 ' enable internal register clocks */
1107    buf[1]= 0xff;   /* reserved=0x3f EN_OTP_9=1 EN_UPG_27=1 */
1108    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1109
1110    buf[0]= 0x08;   /* SH_IND_CLK_ENABLE0 ' enable internal register clocks */
1111    buf[1]= 0xff;   /* EN_UPG_54=1 EN_PLL_54=1 reserved=0x3 EN_DS_54=1 reserved=0x1 EN_AP_54=1 EN_AP_108=1 */
1112    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1113
1114    buf[0]= 0x00;   /* SH_IND_GLOBAL_RESET1 */
1115    buf[1]= 0x00;   /* AP_WDT_RST=0 UPG_WDT_RST=0 UPG_RST=0 PERIPH_RST=0 */
1116    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1117
1118    buf[0]= 0x01;   /* SH_IND_GLOBAL_RESET0 */
1119    buf[1]= 0x00;   /* OTP_RST=0 TM_RST=0 DS_RST=0 AP_RST=0 CG_RST=0 */
1120    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_LOCAL_ADR), buf, 2)); 
1121   
1122    if (p31xx->loadAP)
1123    {
1124        /* initialize JDEC
1125           sb = DEVICE(JDEC_RAM); */
1126        sb = 0x6;
1127        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_JDEC), &sb, 1));   
1128       
1129        /* reset the AP
1130           sb = DEVICE(AP_RESET);*/
1131        sb = 0x1;
1132        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb, 1));
1133       
1134        /* Hab done command */
1135        sb = 0x0B;
1136        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_AP_CMD), &sb, 1));
1137   
1138        /* reset all interrupt status */
1139        for (i = 0; i < 4; i++)
1140            buf[i] = 0xFF;
1141        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT1), buf, 4));
1142   
1143        /* clear MSGx registers */
1144        buf[0] = buf[1] = 0x00;
1145        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_MSG1), buf, 2));
1146       
1147        /* verify that AP is reset */
1148        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb, 1));   
1149        if ((sb & DEVICE(AP_MASK)) != DEVICE(AP_RESET))
1150        {
1151            BDBG_ERR(("unable to reset the AP\n"));
1152            BERR_TRACE(retCode = BHAB_ERR_AP_FAIL);
1153        }
1154   
1155        val = 0x4e0102;
1156        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_DIV1), &val);
1157        val = 0x0;
1158        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_DIV2), &val);
1159        val = 0x1;
1160        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_CLK_US), &val);
1161        val = 0x2703;
1162        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_CLK_OB), &val);
1163        val = 0xc03;
1164        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_CLK_DS), &val);
1165        val = 0x1207;
1166        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_CLK_DS_AFE), &val);
1167        val = 0x0;
1168        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_BYP), &val);
1169        val = 0x0;
1170        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_RST), &val);
1171        val = 0x0;
1172        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_MISC), &val);
1173        val = 0x0;
1174        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_CTRL_1), &val);
1175        val = 0x57188058;
1176        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_CTRL_0), &val);
1177        val = 0x2e4;
1178        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_PHASE_1), &val);
1179        val = 0x0;
1180        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_PLL_PHASE_0), &val);
1181        val = 0x4000;
1182        BHAB_31xx_WriteMbox(handle, DEVICE(US_TOP_BIAS_CTRL), &val);
1183        val = 0x0;
1184        BHAB_31xx_WriteMbox(handle, DEVICE(US_ANALOG_CTRL_1), &val); 
1185        val = 0x131;
1186        BHAB_31xx_WriteMbox(handle, DEVICE(US_ANALOG_CTRL_0), &val);
1187   
1188        val = 0x40000001;
1189        BHAB_31xx_WriteMbox(handle, DEVICE(TM_TOP_GPIO_MUX_CTRL0), &val);
1190        val = 0x000;
1191        BHAB_31xx_WriteMbox(handle, DEVICE(TM_TOP_GPIO_MUX_CTRL1), &val);
1192        val = 0x5;
1193        BHAB_31xx_WriteMbox(handle, DEVICE(TIMER_WDCTRL), &val);
1194        val = 0x3ffffff;
1195        BHAB_31xx_WriteMbox(handle, DEVICE(TIMER_WDCHIPRST_CNT), &val);
1196        val = 0x10;
1197        BHAB_31xx_WriteMbox(handle, DEVICE(TIMER_TIMER_IE0), &val);
1198   
1199        val = 0x0;
1200        BHAB_31xx_ReadMbox(handle, DEVICE(DS_TUNER_ANACTL_WDATA_13_SPARE0), &val);
1201        val |= (p31xx->slaveChipAddr<< 21);
1202        val |= 0X20000000;
1203        BHAB_31xx_WriteMbox(handle, DEVICE(DS_TUNER_ANACTL_WDATA_13_SPARE0), &val);
1204       
1205        val = 0xfffffffe;
1206        BHAB_31xx_WriteMbox(handle, DEVICE(TIMER_WDTIMEOUT), &val);
1207        BHAB_31xx_ReadMbox(handle, DEVICE(TIMER_WDTIMEOUT), &val);
1208    }
1209
1210done:
1211    p31xx->last_page_16_15 = 0xFF;
1212    p31xx->last_page_14_7 = 0xFF;
1213
1214    return retCode;
1215}
1216
1217
1218/******************************************************************************
1219 BHAB_31xx_P_SetApWindow()
1220******************************************************************************/
1221BERR_Code BHAB_31xx_P_SetApWindow(
1222    BHAB_Handle handle,    /* [in] BHAB PI Handle */
1223    uint32_t window   /* [in] base address of the 128-byte window */
1224)
1225{   
1226    BERR_Code retCode = BERR_SUCCESS;
1227    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1228    uint8_t   haddr_16_15 = (window >> 15) & 0x03;
1229    uint8_t   haddr_14_7 = (window >> 7) & 0xFF;
1230    uint8_t   buf[2];
1231
1232    if (p31xx->last_page_16_15 != haddr_16_15)
1233    {
1234        buf[0] = haddr_16_15;
1235        buf[1] = haddr_14_7;
1236        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_ADR_16_15), buf, 2));
1237        p31xx->last_page_16_15 = haddr_16_15;
1238        p31xx->last_page_14_7 = haddr_14_7;
1239    }
1240    else if (p31xx->last_page_14_7 != haddr_14_7)
1241    {
1242        BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_SFR_H_ADR_14_7), &haddr_14_7, 1));     
1243        p31xx->last_page_14_7 = haddr_14_7;
1244    }
1245
1246 done:
1247    return retCode;
1248}
1249
1250
1251/******************************************************************************
1252 BHAB_31xx_P_ReadHab()
1253******************************************************************************/
1254BERR_Code BHAB_31xx_P_ReadHab(BHAB_Handle handle, uint8_t addr, uint8_t *buf, uint8_t n)
1255{
1256   
1257    BERR_Code retCode;
1258    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1259
1260    if ((addr & BHAB_HAB_SIZE) || (n & BHAB_HAB_SIZE))
1261        return BERR_TRACE(BERR_INVALID_PARAMETER);
1262
1263    if ((addr + n) > BHAB_HAB_SIZE)
1264        return BERR_TRACE(BERR_INVALID_PARAMETER);
1265
1266    BHAB_CHK_RETCODE(BHAB_31xx_P_SetApWindow(handle, BHAB_WINDOW_HAB));
1267    BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, addr, buf, n));
1268
1269 done:
1270    return retCode;
1271}
1272
1273
1274/******************************************************************************
1275 BHAB_31xx_P_WriteHab()
1276******************************************************************************/
1277BERR_Code BHAB_31xx_P_WriteHab(BHAB_Handle handle, uint8_t addr, uint8_t *buf, uint8_t n)
1278{
1279    BERR_Code retCode;
1280    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1281
1282    if ((addr & BHAB_HAB_SIZE) || (n & BHAB_HAB_SIZE))
1283        return BERR_TRACE(BERR_INVALID_PARAMETER);
1284
1285    if ((addr + n) > BHAB_HAB_SIZE)
1286        return BERR_TRACE(BERR_INVALID_PARAMETER);
1287
1288    BHAB_CHK_RETCODE(BHAB_31xx_P_SetApWindow(handle, BHAB_WINDOW_HAB));
1289    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, addr, buf, n));
1290
1291 done:
1292    return retCode;
1293}
1294
1295
1296/******************************************************************************
1297 BHAB_31xx_P_ServiceHab()
1298******************************************************************************/
1299BERR_Code BHAB_31xx_P_ServiceHab(
1300    BHAB_Handle handle,   /* [in] BHAB PI Handle */
1301    uint8_t *read_buf,  /* [out] holds the data read from the HAB */ 
1302    uint8_t read_len,   /* [in] number of bytes to read from the HAB */
1303    bool bCheckForAck,  /* [in] true = determine if the AP has serviced the command */
1304    uint8_t ack_byte    /* [in] value of the ack byte to expect */
1305)
1306{   
1307    BERR_Code retCode;
1308    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1309    uint8_t   sb, ie2, buf[2];
1310       
1311    BHAB_31xx_P_EnableHostInterrupt(handle, false);
1312   
1313    /* save ie2 */
1314    if((retCode = BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE2), &ie2, 1)) != BERR_SUCCESS )
1315        return retCode;
1316   
1317    /* clear ie2 */
1318    buf[0] = buf[1] = 0;
1319    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE1), buf, 2));
1320
1321    if (BERR_SUCCESS == BKNI_WaitForEvent(p31xx->hHabDoneEvent, 0))
1322    {
1323        BDBG_WRN(("Discarded a HabDoneEvent"));   
1324    }
1325   
1326    /* enable the hab done interrupt mask */   
1327    BHAB_CHK_RETCODE(BHAB_31xx_P_EnableHabDoneInterrupt(handle));
1328   
1329    /* send the command */
1330    sb = DEVICE(AP_HABR);
1331    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_CTL1), &sb, 1));
1332
1333    /* wait for HAB done interrupt */ 
1334    if (BHAB_31xx_P_WaitForEvent(handle, p31xx->hHabDoneEvent, 800) == BERR_TIMEOUT)
1335    {
1336        BDBG_ERR(("HAB timeout\n"));   
1337        sb = 0;
1338        /*BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE1), &sb, 1); */
1339        BERR_TRACE(retCode = BHAB_ERR_HAB_TIMEOUT);
1340        goto done;
1341    }
1342
1343    if (read_len > 0)
1344    {
1345        BHAB_CHK_RETCODE(BHAB_31xx_P_ReadHab(handle, 0, read_buf, read_len));
1346        if (bCheckForAck)
1347        {
1348            if (ack_byte != read_buf[0])
1349            {
1350                BDBG_ERR(("HAB command not serviced!\n"));
1351                BERR_TRACE(retCode = BHAB_ERR_HAB_NO_ACK);
1352            }
1353        }
1354    }
1355   
1356 done:
1357    BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE2), &ie2, 1);
1358
1359    return retCode;
1360}
1361
1362
1363/******************************************************************************
1364 BHAB_31xx_P_DecodeInterrupt()
1365******************************************************************************/
1366BERR_Code BHAB_31xx_P_DecodeInterrupt(BHAB_Handle handle)
1367{ 
1368    BERR_Code retCode;
1369    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1370    uint8_t   h_ie[3], h_fstat[3], new_stat2, new_stat3;
1371   
1372    BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_FSTAT1), h_fstat, 3));
1373    BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE1), h_ie, 3));
1374
1375
1376    new_stat2 = 0;
1377    new_stat3 = 0;
1378    if (!h_fstat[0] && !h_fstat[1] && !h_fstat[2])
1379    {
1380        return BERR_SUCCESS;
1381    }
1382   
1383    /*HAB DONE INTERRUPT*/
1384    if (h_fstat[0] & DEVICE(STAT1_HAB_DONE))
1385    {
1386        h_ie[0] = 0;
1387        BKNI_SetEvent(p31xx->hHabDoneEvent);           
1388    }
1389   
1390    /*INIT DONE INTERRUPT*/
1391    if (h_fstat[1] & DEVICE(STAT2_INIT_DONE))
1392    {
1393        h_ie[1] &= ~DEVICE(STAT2_INIT_DONE);
1394        new_stat2 |= DEVICE(STAT2_INIT_DONE);
1395        BKNI_SetEvent(p31xx->hInitDoneEvent);
1396    }
1397
1398   
1399    /* Down stream module interrupts */
1400    if ((h_fstat[1] & DEVICE(STAT2_LOCK_MASK)) ||(h_fstat[2] & ((DEVICE(STAT3_GAIN_MASK)) | (DEVICE(STAT3_QAM_STATUS_READY)))))
1401    {   
1402        BHAB_P_CallbackInfo *callback;
1403        callback = &p31xx->InterruptCallbackInfo[BHAB_DevId_eADS0];
1404       
1405        if (h_fstat[2] & DEVICE(STAT3_GET_GAIN))
1406        {
1407            new_stat3 |= DEVICE(STAT3_GET_GAIN);
1408            callback->parm2 = (int) BHAB_Interrupt_eUpdateGain;
1409            BDBG_MSG(("update gain"));
1410            BKNI_EnterCriticalSection();
1411            callback->func(callback->pParm1, callback->parm2);
1412            BKNI_LeaveCriticalSection();
1413        }
1414
1415        if (h_fstat[2] & DEVICE(STAT3_QAM_STATUS_READY))
1416        {
1417            new_stat3 |= DEVICE(STAT3_QAM_STATUS_READY);
1418            callback->parm2 = (int) BHAB_Interrupt_eQamAsyncStatusReady;
1419            BDBG_MSG(("Qam Async Status Ready."));
1420            BKNI_EnterCriticalSection();
1421            callback->func(callback->pParm1, callback->parm2);
1422            BKNI_LeaveCriticalSection();
1423        }
1424
1425        if (h_fstat[2] & DEVICE(STAT3_NO_SIGNAL))
1426        {
1427            new_stat3 |= DEVICE(STAT3_NO_SIGNAL);
1428            callback->parm2 = (int) BHAB_Interrupt_eNoSignal;
1429            BDBG_MSG(("no signal"));
1430            BKNI_EnterCriticalSection();
1431            callback->func(callback->pParm1, callback->parm2);
1432            BKNI_LeaveCriticalSection();
1433        }
1434       
1435        new_stat2 |= DEVICE(STAT2_LOCK_MASK);
1436
1437        if(h_fstat[1] & DEVICE(STAT2_LOCK_MASK)) {
1438            new_stat2 |= DEVICE(STAT2_LOCK_MASK);
1439            callback->parm2 = (int) BHAB_Interrupt_eLockChange;
1440            h_ie[1] &= ~DEVICE(STAT2_LOCK_MASK);
1441            BDBG_MSG(("Lock Change"));
1442            BKNI_EnterCriticalSection();
1443            callback->func(callback->pParm1, callback->parm2);
1444            BKNI_LeaveCriticalSection();
1445        }
1446       
1447        if (h_fstat[1] & DEVICE(STAT2_IN_LOCK))
1448        {
1449            BDBG_MSG(("locked"));
1450            new_stat2 &= ~DEVICE(STAT2_OUT_OF_LOCK);
1451            h_ie[1] |= DEVICE(STAT2_OUT_OF_LOCK);
1452
1453        }
1454        else if (h_fstat[1] & DEVICE(STAT2_OUT_OF_LOCK))
1455        {
1456
1457            BDBG_MSG(("not locked"));
1458            new_stat2 &= ~DEVICE(STAT2_IN_LOCK);
1459            h_ie[1] |= DEVICE(STAT2_IN_LOCK);
1460        } 
1461    }
1462
1463    /* Out of band module interrupts */
1464    if ((h_fstat[2] & DEVICE(STAT3_LOCK_MASK)) || (h_fstat[2] & DEVICE(STAT3_OOB_STATUS_READY)))
1465    {   
1466        BHAB_P_CallbackInfo *callback;
1467        callback = &p31xx->InterruptCallbackInfo[BHAB_DevId_eAOB0];
1468
1469        if (h_fstat[2] & DEVICE(STAT3_OOB_STATUS_READY))
1470        {
1471            new_stat3 |= DEVICE(STAT3_OOB_STATUS_READY);
1472            callback->parm2 = (int) BHAB_Interrupt_eOobAsyncStatusReady;
1473            BKNI_EnterCriticalSection();
1474            callback->func(callback->pParm1, callback->parm2);
1475            BKNI_LeaveCriticalSection();
1476        }
1477       
1478        if (h_fstat[2] & DEVICE(STAT3_LOCK_MASK))
1479        {
1480
1481            new_stat3 |= DEVICE(STAT3_LOCK_MASK);
1482            h_ie[2] &= ~DEVICE(STAT3_LOCK_MASK);
1483
1484            callback->parm2 = (int) BHAB_Interrupt_eLockChange; 
1485
1486            BKNI_EnterCriticalSection();
1487            callback->func(callback->pParm1, callback->parm2);
1488            BKNI_LeaveCriticalSection();
1489
1490            if (h_fstat[2] & DEVICE(STAT3_IN_LOCK))
1491            {
1492                BDBG_MSG(("locked"));
1493                new_stat3 &= ~DEVICE(STAT3_OUT_OF_LOCK);
1494                h_ie[2] |= DEVICE(STAT3_OUT_OF_LOCK);
1495
1496            }
1497            else
1498            {
1499                new_stat3 &= ~DEVICE(STAT3_IN_LOCK);
1500                h_ie[2] |= DEVICE(STAT3_IN_LOCK);
1501                BDBG_MSG(("not locked")); 
1502            }
1503        }
1504    }   
1505
1506    /* clear the interrupt status */
1507    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_IE1), h_ie, 3)); 
1508    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT2), &new_stat2, 1));
1509    BHAB_CHK_RETCODE(BREG_I2C_Write(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_STAT3), &new_stat3, 1));
1510   
1511 done:
1512    return retCode;
1513}
1514
1515
1516/******************************************************************************
1517 BHAB_31xx_P_DecodeError()
1518******************************************************************************/
1519BERR_Code BHAB_31xx_P_DecodeError(
1520    BHAB_Handle handle,           /* [in] BHAB PI Handle */
1521    BHAB_ApStatus *pApStatus /* [in] AP status returned by BHAB_GetApStatus */
1522)
1523{
1524    BERR_Code retCode = BERR_SUCCESS;
1525    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1526    uint8_t sb;
1527
1528    if (*pApStatus & BHAB_APSTATUS_HAB_ERR)
1529        retCode = BHAB_ERR_HABAV;
1530    else if (*pApStatus & BHAB_APSTATUS_MEM_ERR)
1531        retCode = BHAB_ERR_MEMAV;
1532    else if (*pApStatus & BHAB_APSTATUS_H_ERR)
1533        retCode = BHAB_ERR_HOST_XFER;
1534    else if (*pApStatus & BHAB_APSTATUS_IOMB_ERR)
1535        retCode = BHAB_ERR_IOMB_XFER;
1536    else if (*pApStatus & BHAB_APSTATUS_HABCMD_ERR)
1537        retCode = BHAB_ERR_HAB_ERR;
1538    else if (*pApStatus & BHAB_APSTATUS_AP_ERR)
1539    {
1540        BHAB_CHK_RETCODE(BREG_I2C_Read(p31xx->hRegister, handle->settings.chipAddr, DEVICE(SH_AP_SFR_H_MSG1), &sb, 1));     
1541        switch (sb)
1542        {
1543        case 1:
1544          retCode = BHAB_ERR_AP_BSC;
1545          break;
1546
1547        case 2:
1548          retCode = BHAB_ERR_AP_STACK;
1549          break;
1550
1551        case 3:
1552          retCode = BHAB_ERR_AP_WD;
1553          break;
1554
1555        case 4:
1556          retCode = BHAB_ERR_AP_ISB;
1557          break;
1558
1559        case 5:
1560          retCode = BHAB_ERR_AP_SCR;
1561          break;
1562
1563        case 6:
1564          retCode = BHAB_ERR_AP_IRQ;
1565          break;
1566
1567        case 7:
1568          retCode = BHAB_ERR_AP_COPY;
1569          break;
1570
1571        case 8:
1572          retCode = BHAB_ERR_AP_EEPROM;
1573          break;
1574
1575        case 9:
1576          retCode = BHAB_ERR_AP_HABAV;
1577          break;
1578
1579        default:
1580          BDBG_ERR(("unknown MSG1 (=0x%02X)\n", sb));
1581          retCode = BHAB_ERR_AP_UNKNOWN;
1582          break;
1583        }
1584    }
1585   
1586 done:
1587    return retCode;
1588}
1589
1590
1591/******************************************************************************
1592 BHAB_31xx_P_CheckHab()
1593******************************************************************************/
1594BERR_Code BHAB_31xx_P_CheckHab(
1595    BHAB_Handle handle    /* [in] BHAB Handle */
1596)
1597{
1598    BERR_Code retCode = BERR_SUCCESS;
1599    BHAB_ApStatus status = 0;
1600
1601    BHAB_CHK_RETCODE(BHAB_31xx_GetApStatus(handle, &status));
1602    if ((status & BHAB_APSTATUS_HAB_MASK) == BHAB_APSTATUS_HAB_READY) {
1603        retCode = BERR_SUCCESS;
1604    }
1605    else
1606    {
1607        BERR_TRACE(retCode = BHAB_31xx_P_DecodeError(handle, &status));
1608    }
1609   
1610 done:
1611    return retCode;
1612}
1613
1614/******************************************************************************
1615 BHAB_31xx_GetWatchDogTimer()
1616******************************************************************************/
1617BERR_Code BHAB_31xx_GetWatchDogTimer(
1618    BHAB_Handle handle,    /* [in] BHAB Handle */
1619    BHAB_WatchDogTimerSettings *wdtSettings
1620)
1621{
1622    BERR_Code retCode = BERR_SUCCESS;
1623    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1624   
1625    *wdtSettings = p31xx->wdtSettings;
1626   
1627     return retCode;
1628}
1629
1630/******************************************************************************
1631 BHAB_31xx_SetWatchDogTimer()
1632******************************************************************************/
1633BERR_Code BHAB_31xx_SetWatchDogTimer(
1634    BHAB_Handle handle,    /* [in] BHAB Handle */
1635    const BHAB_WatchDogTimerSettings *wdtSettings
1636)
1637{
1638    BERR_Code retCode = BERR_SUCCESS;
1639    uint8_t buf[11];
1640    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1641   
1642    BKNI_Memset(buf, 0x00, sizeof(buf));
1643   
1644    buf[0] = 0x1B;
1645
1646    if(wdtSettings->clearWatchDog.select < 0xf)
1647        buf[1] = wdtSettings->clearWatchDog.select;
1648    else
1649        BDBG_ERR(("unknown gpio selection.\n"));
1650   
1651    buf[1] |= (wdtSettings->clearWatchDog.enable << 4);
1652    buf[1] |= (wdtSettings->clearWatchDog.polarity << 5);
1653    buf[2] |= (wdtSettings->start << 2);
1654    buf[2] |= (wdtSettings->nmiMode << 1);
1655    buf[2] |= wdtSettings->oneShot;
1656    buf[3] = wdtSettings->timeout >> 24;
1657    buf[4] = wdtSettings->timeout >> 16;
1658    buf[5] = wdtSettings->timeout >> 8;
1659    buf[6] = wdtSettings->timeout;
1660
1661    /* NMI width is hardcoded. It can be made into a parameter if needed. */
1662    buf[7] = 0x0;
1663    buf[8] = 0x52;
1664    buf[9] = 0x65;
1665    buf[10] = 0xc0;
1666
1667    BHAB_CHK_RETCODE(BHAB_31xx_SendHabCommand(handle, buf, 11, buf, 1, true, true, 11));
1668   
1669    p31xx->wdtSettings = *wdtSettings;
1670   
1671 done:
1672    return retCode;
1673}
1674
1675/******************************************************************************
1676 BHAB_31xx_GetWatchDogTimer()
1677******************************************************************************/
1678BERR_Code BHAB_31xx_GetNmiConfig(
1679    BHAB_Handle handle,    /* [in] BHAB Handle */
1680    BHAB_NmiSettings *nmiSettings
1681)
1682{
1683    BERR_Code retCode = BERR_SUCCESS;
1684    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1685   
1686    *nmiSettings = p31xx->nmiSettings;
1687   
1688     return retCode;
1689}
1690
1691/******************************************************************************
1692 BHAB_31xx_SetWatchDogTimer()
1693******************************************************************************/
1694BERR_Code BHAB_31xx_SetNmiConfig(
1695    BHAB_Handle handle,    /* [in] BHAB Handle */
1696    const BHAB_NmiSettings *nmiSettings
1697)
1698{
1699    BERR_Code retCode = BERR_SUCCESS;
1700    uint8_t buf[6];
1701    BHAB_31xx_P_Handle *p31xx = (BHAB_31xx_P_Handle *)(handle->pImpl);
1702
1703    BKNI_Memset(buf, 0x00, sizeof(buf));
1704   
1705    buf[0] = 0x1a;
1706
1707    if(nmiSettings->nmi.select < 0xf)
1708        buf[1] = nmiSettings->nmi.select;
1709    else
1710        BDBG_ERR(("unknown gpio selection.\n"));
1711
1712    if(nmiSettings->powerDownDetect.select < 0xf)
1713        buf[2] = nmiSettings->powerDownDetect.select;
1714    else
1715        BDBG_ERR(("unknown gpio selection.\n"));
1716   
1717    if(nmiSettings->spare1.select < 0xf)
1718        buf[3] = nmiSettings->spare1.select;
1719    else
1720        BDBG_ERR(("unknown gpio selection.\n"));
1721   
1722    if(nmiSettings->spare2.select < 0xf)
1723        buf[4] = nmiSettings->spare2.select;
1724    else
1725        BDBG_ERR(("unknown gpio selection.\n"));
1726   
1727    buf[1] |= (nmiSettings->nmi.enable << 4);
1728    buf[2] |= (nmiSettings->powerDownDetect.enable << 4);
1729    buf[3] |= (nmiSettings->spare1.enable << 4);
1730    buf[4] |= (nmiSettings->spare2.enable << 4);
1731   
1732    buf[3] |= (nmiSettings->powerDownDetect.polarity << 5);
1733    buf[4] |= (nmiSettings->spare1.polarity << 5);
1734    buf[5] |= (nmiSettings->spare2.polarity << 5);
1735
1736    BHAB_CHK_RETCODE(BHAB_31xx_SendHabCommand(handle, buf, 5, buf, 1, true, true, 5));     
1737
1738    p31xx->nmiSettings = *nmiSettings;
1739   
1740 done:
1741    return retCode;
1742}
1743
1744
1745
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