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bint_7552.c @ 76

Last change on this file since 76 was 76, checked in by megakiss, 10 years ago
1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
Property svn:executable set to ``*
File size: 41.8 KB

Line
1	/***************************************************************************
2	* Copyright (c) 2003-2011, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bint_7552.c $
11	* $brcm_Revision: Hydra_Software_Devel/10 $
12	* $brcm_Date: 11/17/11 5:20p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/basemodules/int/7552/bint_7552.c $
19	*
20	* Hydra_Software_Devel/10 11/17/11 5:20p xhuang
21	* SW7552-9: merge to main.
22	*
23	* Hydra_Software_Devel/SW7552_134/2 11/17/11 5:18p xhuang
24	* SW7552-9: disable SYS_PM interrupt
25	*
26	* Hydra_Software_Devel/SW7552_134/1 10/26/11 3:31p farshidf
27	* SW7552-134: remove the UFE IRQ since it has not been used
28	*
29	* Hydra_Software_Devel/9 9/15/11 2:21p xhuang
30	* SW7552-108: fix warning
31	*
32	* Hydra_Software_Devel/8 8/17/11 6:35p xhuang
33	* SW7552-104: fix GISB timeout when set to OTP disabled modules
34	*
35	* Hydra_Software_Devel/7 5/25/11 6:13p xhuang
36	* SW7552-34: Add RFM interrupt handle
37	*
38	* Hydra_Software_Devel/6 4/28/11 6:44p xhuang
39	* SW7552-4: update interrupt table
40	*
41	* Hydra_Software_Devel/5 1/19/11 2:40p xhuang
42	* SW7552-4: update according to RDB change
43	*
44	* Hydra_Software_Devel/4 1/14/11 2:13p xhuang
45	* SW7552-4: sync interrupt table with CRDB
46	*
47	* Hydra_Software_Devel/3 11/23/10 3:12p xhuang
48	* SW7552-4: update according to RDB change
49	*
50	* Hydra_Software_Devel/3 11/23/10 2:47p xhuang
51	* SW7552-4: update according to RDB change
52	*
53	* Hydra_Software_Devel/2 10/29/10 4:38p xhuang
54	* SW7552-4:add rfm for 7552
55	*
56	* Hydra_Software_Devel/1 10/28/10 4:53p xhuang
57	* SW7552-4: Add support for 7552
58	*
59	*
60	***************************************************************************/
61	#include "bstd.h"
62	#include "bint_7552.h"
63	#include "bchp_7552.h"
64
65	/* Include interrupt definitions from RDB */
66	#include "bchp_hif_cpu_intr1.h"
67
68	/* Standard L2 stuff */
69	#include "bchp_aio_inth.h"
70	#include "bchp_avd_intr2_0.h"
71	#include "bchp_bsp_control_intr2.h"
72	#include "bchp_bvnb_intr2.h"
73	#include "bchp_bvnf_intr2_0.h"
74	#include "bchp_bvnf_intr2_1.h"
75	#include "bchp_bvnf_intr2_3.h"
76	#include "bchp_bvnf_intr2_4.h"
77	#include "bchp_bvnf_intr2_5.h"
78	#include "bchp_bvnm_intr2_0.h"
79	#include "bchp_hdmi_tx_intr2.h"
80	#include "bchp_hif_spi_intr2.h"
81	#include "bchp_hif_intr2.h"
82	#include "bchp_memc_l2_0.h"
83	#include "bchp_raaga_dsp_inth.h"
84	#include "bchp_raaga_dsp_fw_inth.h"
85	#include "bchp_sm_l2.h"
86	#include "bchp_sun_l2.h"
87	#include "bchp_aon_l2.h"
88	#include "bchp_aon_pm_l2.h"
89	#include "bchp_video_enc_intr2.h"
90	#include "bchp_mcif_intr2.h"
91	#include "bchp_m2mc_top_l2.h"
92	#include "bchp_clkgen_intr2.h"
93	#include "bchp_upg_aux_aon_intr2.h"
94	#include "bchp_thd_intr2.h"
95	#include "bchp_thd_intr2b.h"
96	#include "bchp_ufe_misc.h"
97	#include "bchp_ds_topm.h"
98	#include "bchp_rfm_l2.h"
99
100	/* XPT */
101	#include "bchp_xpt_fe.h"
102	#include "bchp_xpt_bus_if.h"
103	#include "bchp_xpt_dpcr0.h"
104	#include "bchp_xpt_dpcr1.h"
105	#include "bchp_xpt_dpcr2.h"
106	#include "bchp_xpt_dpcr3.h"
107	#include "bchp_xpt_pb0.h"
108	#include "bchp_xpt_pb1.h"
109	#include "bchp_xpt_pb2.h"
110	#include "bchp_xpt_pb3.h"
111	#include "bchp_xpt_rave.h"
112	#include "bchp_xpt_msg.h"
113	#include "bchp_xpt_pcroffset.h"
114	#include "bchp_xpt_wakeup.h"
115	#include "bchp_xpt_full_pid_parser.h"
116
117	/* UARTs, keypad, I2C */
118	#include "bchp_irq0.h"
119	#include "bchp_irq0_aon.h"
120	#include "bchp_upg_aux_aon_intr2.h"
121
122	/* Smartcard interrupts. */
123	#include "bchp_scirq0.h"
124
125	/* Timer */
126	#include "bchp_timer.h"
127
128	BDBG_MODULE(interruptinterface_7552);
129
130	#define BINT_P_STD_STATUS 0x00
131	#define BINT_P_STD_SET 0x04
132	#define BINT_P_STD_CLEAR 0x08
133	#define BINT_P_STD_MASK_STATUS 0x0C
134	#define BINT_P_STD_MASK_SET 0x10
135	#define BINT_P_STD_MASK_CLEAR 0x14
136
137
138	#define BINT_P_STANDARD_L2_CASES \
139	case BCHP_AIO_INTH_R5F_STATUS: \
140	case BCHP_AVD_INTR2_0_CPU_STATUS: \
141	case BCHP_BSP_CONTROL_INTR2_CPU_STATUS: \
142	case BCHP_BVNB_INTR2_CPU_STATUS: \
143	case BCHP_BVNF_INTR2_0_R5F_STATUS: \
144	case BCHP_BVNF_INTR2_1_R5F_STATUS: \
145	case BCHP_BVNF_INTR2_3_AVD0_STATUS: \
146	case BCHP_BVNF_INTR2_4_AVD0_STATUS: \
147	case BCHP_BVNF_INTR2_5_R5F_STATUS: \
148	case BCHP_BVNM_INTR2_0_R5F_STATUS: \
149	case BCHP_M2MC_TOP_L2_CPU_STATUS: \
150	case BCHP_HIF_INTR2_CPU_STATUS: \
151	case BCHP_HDMI_TX_INTR2_CPU_STATUS: \
152	case BCHP_MEMC_L2_0_R5F_STATUS: \
153	case BCHP_RAAGA_DSP_INTH_HOST_STATUS: \
154	case BCHP_RAAGA_DSP_FW_INTH_HOST_STATUS: \
155	case BCHP_SM_L2_CPU_STATUS: \
156	case BCHP_SUN_L2_CPU_STATUS: \
157	case BCHP_AON_L2_CPU_STATUS: \
158	case BCHP_AON_PM_L2_CPU_STATUS: \
159	case BCHP_VIDEO_ENC_INTR2_CPU_STATUS: \
160	case BCHP_MCIF_INTR2_CPU_STATUS: \
161	case BCHP_CLKGEN_INTR2_CPU_STATUS: \
162	case BCHP_UPG_AUX_AON_INTR2_CPU_STATUS: \
163	case BCHP_UFE_MISC_INTR2_STATUS: \
164
165	#define BINT_P_THD_L2_CASES \
166	case BCHP_THD_INTR2_CPU_STATUS: \
167	case BCHP_THD_INTR2B_CPU_STATUS: \
168
169	#define BINT_P_DS_L2_CASES \
170	case BCHP_DS_TOPM_L2_IRQSTS: \
171
172	#define BINT_P_IRQ0_CASES \
173	case BCHP_IRQ0_IRQEN:
174
175	#define BINT_P_IRQ0_ENABLE 0
176	#define BINT_P_IRQ0_STATUS 4
177
178
179	#define BINT_P_IRQ0_AON_CASES \
180	case BCHP_IRQ0_AON_IRQEN:
181
182	#define BINT_P_IRQ0_AON_ENABLE 0
183	#define BINT_P_IRQ0_AON_STATUS 4
184
185
186	#define BINT_P_XPT_STATUS 0x00
187	#define BINT_P_XPT_ENABLE 0x04
188
189	#define BINT_P_XPT_STATUS_CASES \
190	case BCHP_XPT_BUS_IF_INTR_STATUS_REG: \
191	case BCHP_XPT_BUS_IF_INTR_STATUS2_REG: \
192	case BCHP_XPT_BUS_IF_INTR_STATUS3_REG: \
193	case BCHP_XPT_BUS_IF_INTR_STATUS4_REG: \
194	case BCHP_XPT_BUS_IF_INTR_STATUS5_REG: \
195	case BCHP_XPT_PB0_INTR: \
196	case BCHP_XPT_PB1_INTR: \
197	case BCHP_XPT_PB2_INTR: \
198	case BCHP_XPT_PB3_INTR: \
199	case BCHP_XPT_FE_INTR_STATUS0_REG: \
200	case BCHP_XPT_FE_INTR_STATUS1_REG: \
201	case BCHP_XPT_DPCR0_INTR_STATUS_REG: \
202	case BCHP_XPT_DPCR1_INTR_STATUS_REG: \
203	case BCHP_XPT_DPCR2_INTR_STATUS_REG: \
204	case BCHP_XPT_DPCR3_INTR_STATUS_REG: \
205	case BCHP_XPT_FULL_PID_PARSER_IBP_PCC_INTR_STATUS_REG: \
206	case BCHP_XPT_FULL_PID_PARSER_PBP_PCC_INTR_STATUS_REG: \
207	case BCHP_XPT_FULL_PID_PARSER_IBP_SCC_INTR_STATUS_REG: \
208	case BCHP_XPT_FULL_PID_PARSER_PBP_SCC_INTR_STATUS_REG: \
209	case BCHP_XPT_FULL_PID_PARSER_IBP_PSG_PROTOCOL_INTR_STATUS_REG: \
210	case BCHP_XPT_FULL_PID_PARSER_PBP_PSG_PROTOCOL_INTR_STATUS_REG: \
211	case BCHP_XPT_FULL_PID_PARSER_IBP_TRANSPORT_ERROR_INTR_STATUS_REG: \
212	case BCHP_XPT_FULL_PID_PARSER_PBP_TRANSPORT_ERROR_INTR_STATUS_REG: \
213	case BCHP_XPT_WAKEUP_INTR_STATUS_REG:
214
215
216	#define BINT_P_PCROFFSET_CASES \
217	case BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS: \
218	case BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS: \
219	case BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS: \
220	case BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS:
221
222	#define BINT_P_PCROFFSET_STATUS 0x00
223	#define BINT_P_PCROFFSET_ENABLE 0x04
224
225	/* There is no constant address mapping from RAVE status to RAVE enable registers. */
226	#define BINT_P_RAVE_STATUS 0x00
227
228	#define BINT_P_XPT_RAVE_CASES \
229	case BCHP_XPT_RAVE_INT_CX0: \
230	case BCHP_XPT_RAVE_INT_CX1: \
231	case BCHP_XPT_RAVE_INT_CX2: \
232	case BCHP_XPT_RAVE_INT_CX3: \
233	case BCHP_XPT_RAVE_INT_CX4: \
234	case BCHP_XPT_RAVE_INT_CX5: \
235	case BCHP_XPT_RAVE_INT_CX6: \
236	case BCHP_XPT_RAVE_INT_CX7: \
237	case BCHP_XPT_RAVE_INT_CX8: \
238	case BCHP_XPT_RAVE_INT_CX9: \
239	case BCHP_XPT_RAVE_INT_CX10: \
240	case BCHP_XPT_RAVE_INT_CX11: \
241	case BCHP_XPT_RAVE_INT_CX12: \
242	case BCHP_XPT_RAVE_INT_CX13: \
243	case BCHP_XPT_RAVE_INT_CX14: \
244	case BCHP_XPT_RAVE_INT_CX15: \
245	case BCHP_XPT_RAVE_INT_CX16: \
246	case BCHP_XPT_RAVE_INT_CX17: \
247	case BCHP_XPT_RAVE_INT_CX18: \
248	case BCHP_XPT_RAVE_INT_CX19: \
249	case BCHP_XPT_RAVE_INT_CX20: \
250	case BCHP_XPT_RAVE_INT_CX21: \
251	case BCHP_XPT_RAVE_INT_CX22: \
252	case BCHP_XPT_RAVE_INT_CX23:
253
254	#define BINT_P_XPT_BUF_STATUS 0x00
255	#define BINT_P_XPT_BUF_ENABLE 0x10
256
257	#define BINT_P_XPT_BUF_CASES \
258	case BCHP_XPT_MSG_BUF_OVFL_INTR_00_31: \
259	case BCHP_XPT_MSG_BUF_OVFL_INTR_32_63: \
260	case BCHP_XPT_MSG_BUF_OVFL_INTR_64_95: \
261	case BCHP_XPT_MSG_BUF_OVFL_INTR_96_127: \
262	case BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31: \
263	case BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63: \
264	case BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95: \
265	case BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127:
266
267	#define BINT_P_XPT_MSG_ERR_STATUS ( 0x00 )
268	#define BINT_P_XPT_MSG_ERR_ENABLE ( 0x04 )
269	#define BINT_P_XPT_MSG_ERR_CASES \
270	case BCHP_XPT_MSG_DAT_ERR_INTR:
271
272	#define BINT_P_RFM_STATUS 0x00
273	#define BINT_P_RFM_ENABLE 0x04
274	#define BINT_P_RFM_CLEAR 0x08
275	#define BINT_P_RFM_MASK_STATUS 0x0c
276	#define BINT_P_RFM_CASE \
277	case BCHP_RFM_L2_CPU_STATUS:
278
279	/* BINT_P_UPGSC_ENABLE was defined as -4 for BCHP_SCIRQ0_SCIRQSTAT.
280	* Since we are using BCHP_SCIRQ0_SCIRQEN, it is not needed but
281	* to minimize the change, it is kept and set to 0
282	*/
283	#define BINT_P_UPGSC_ENABLE (0)
284
285	#define BINT_P_UPGSC_CASES \
286	case BCHP_SCIRQ0_SCIRQEN:
287
288	#define BINT_P_TIMER_STATUS 0x00
289	#define BINT_P_TIMER_MASK 0x04
290
291	#define BINT_P_TIMER_CASES \
292	case BCHP_TIMER_TIMER_IS:
293
294	#define BINT_P_STAT_TIMER_TICKS_PER_USEC 27
295
296	static void BINT_P_7552_SetInt( BREG_Handle regHandle, uint32_t baseAddr, int shift );
297	static void BINT_P_7552_ClearInt( BREG_Handle regHandle, uint32_t baseAddr, int shift );
298	static void BINT_P_7552_SetMask( BREG_Handle regHandle, uint32_t baseAddr, int shift );
299	static void BINT_P_7552_ClearMask( BREG_Handle regHandle, uint32_t baseAddr, int shift );
300	static uint32_t BINT_P_7552_ReadMask( BREG_Handle regHandle, uint32_t baseAddr );
301	static uint32_t BINT_P_7552_ReadStatus( BREG_Handle regHandle, uint32_t baseAddr );
302	static uint32_t GetRaveIntEnableOffset( uint32_t BaseAddr );
303
304	static const BINT_P_IntMap bint_7552[] =
305	{
306	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT, BCHP_AIO_INTH_R5F_STATUS, 0, "AIO"},
307	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT, BCHP_BSP_CONTROL_INTR2_CPU_STATUS, 0, "BSP"},
308	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT, BCHP_BVNB_INTR2_CPU_STATUS, 0, "BVNB_0"},
309	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT, BCHP_BVNF_INTR2_0_R5F_STATUS, 0, "BVNF_0"},
310	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT, BCHP_BVNF_INTR2_1_R5F_STATUS, 0, "BVNF_1"},
311	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT, BCHP_BVNF_INTR2_5_R5F_STATUS, 0, "BVNF_3"}, /* BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_5_SHIFT */
312	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT, BCHP_BVNM_INTR2_0_R5F_STATUS, 0, "BVNM"},
313	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT, BCHP_CLKGEN_INTR2_CPU_STATUS, 0, "CLKGEN"},
314	/* EXT_IRQ_0_CPU_INTR - EXT_IRQ_14_CPU_INTR is not mapped */
315	/* GENET_0_A_CPU_INTR, GENET_0_B_CPU_INTR is not mapped */
316	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT, BCHP_M2MC_TOP_L2_CPU_STATUS, 0, "M2MC"},
317	{ BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT, BCHP_HDMI_TX_INTR2_CPU_STATUS, 0, "HDMI_TX"},
318	/* HIF_CPU_INTR is not mapped */
319	/* HIF_SPI_CPU_INTR is not mapped */
320
321	/* IPI0_CPU_INTR, IPI1_CPU_INTR is not mapped */
322	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT + 32, BCHP_MEMC_L2_0_R5F_STATUS, 0, "MEMC0"},
323	/* NMI_PIN_CPU_INTR is not mapped */
324	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT + 32, BCHP_RAAGA_DSP_INTH_HOST_STATUS, 0, "RAAGA_CPU"},
325	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT + 32, BCHP_RAAGA_DSP_FW_INTH_HOST_STATUS, 0, "RAAGA_FW"},
326	/* UPG_MC_CPU_INTR, UHF1_CPU_INTR is not mapped */
327	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT + 32, BCHP_SM_L2_CPU_STATUS, 0, "SM"},
328	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT + 32, BCHP_SUN_L2_CPU_STATUS, 0, "SUN"},
329	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT + 32, BCHP_AON_L2_CPU_STATUS, 0, "SYS_AON"},
330	/BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT + 32, BCHP_AON_PM_L2_CPU_STATUS, 0, "SYS_PM"},/
331	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT + 32, BCHP_UPG_AUX_AON_INTR2_CPU_STATUS, 0, "UPG_AUX_AON"},
332	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT + 32, BCHP_IRQ0_IRQEN, 0xF8FFFFFF, "UPG_BSC"},
333	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT + 32, BCHP_IRQ0_AON_IRQEN, 0xF7FFFFFF, "UPG_BSC_AON"},
334	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT + 32, BCHP_IRQ0_IRQEN, 0xFFFFFC00, "UPG_MAIN"},
335	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT + 32, BCHP_IRQ0_AON_IRQEN, 0xFFFFFC00, "UPG_MAIN_AON"},
336	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT + 32, BCHP_SCIRQ0_SCIRQEN, 0, "UPG_SC"},
337	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT + 32, BCHP_IRQ0_AON_IRQEN, 0xFFEFFFFF, "UPG_SPI"},
338	{ BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT + 32, BCHP_TIMER_TIMER_IS, 0, "UPG_TMR"},
339	/* UPG_UART0_CPU_INTR, UPG_UART1_CPU_INTR, UPG_UART2_CPU_INTR is not mapped */
340	/* USB0_BRIDGE_CPU_INTR, USB0_EHCI_0_CPU_INTR, USB0_EHCI_1_CPU_INTR, USB0_OHCI_0_CPU_INTR,
341	USB0_OHCI_1_CPU_INTR, USB1_BRIDGE_CPU_INTR, USB1_EHCI_0_CPU_INTR, USB1_EHCI_1_CPU_INTR
342	USB1_OHCI_0_CPU_INTR, USB1_OHCI_1_CPU_INTR is not mapped */
343
344	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT + 64, BCHP_VIDEO_ENC_INTR2_CPU_STATUS, 0, "VEC"},
345	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FE_INTR_STATUS0_REG, 0, "XPT_FE_STATUS0"},
346	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FE_INTR_STATUS1_REG, 0, "XPT_FE_STATUS1"},
347	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_IBP_PCC_INTR_STATUS_REG, 0, "XPT_IBP_PCC"},
348	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_PBP_PCC_INTR_STATUS_REG, 0, "XPT_PBP_PCC"},
349	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_IBP_SCC_INTR_STATUS_REG, 0, "XPT_IBP_SCC"},
350	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_PBP_SCC_INTR_STATUS_REG, 0, "XPT_PBP_SCC"},
351	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_IBP_PSG_PROTOCOL_INTR_STATUS_REG, 0, "XPT_IBP_PSG"},
352	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_PBP_PSG_PROTOCOL_INTR_STATUS_REG, 0, "XPT_PBP_PSG"},
353	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_IBP_TRANSPORT_ERROR_INTR_STATUS_REG, 0, "XPT_IBP_TRANSPORT_ERROR"},
354	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT + 64, BCHP_XPT_FULL_PID_PARSER_PBP_TRANSPORT_ERROR_INTR_STATUS_REG, 0, "XPT_PBP_TRANSPORT_ERROR"},
355	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31, BINT_DONT_PROCESS_L2,"XPT_MSG_0"},
356	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63, BINT_DONT_PROCESS_L2,"XPT_MSG_1"},
357	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95, BINT_DONT_PROCESS_L2,"XPT_MSG_2"},
358	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127, BINT_DONT_PROCESS_L2,"XPT_MSG_3"},
359	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_DAT_ERR_INTR, 0, "XPT_MSG_ERR"},
360	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_OVFL_INTR_00_31, BINT_DONT_PROCESS_L2,"XPT_OVFL_0"},
361	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_OVFL_INTR_32_63, BINT_DONT_PROCESS_L2,"XPT_OVFL_1"},
362	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_OVFL_INTR_64_95, BINT_DONT_PROCESS_L2,"XPT_OVFL_2"},
363	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT + 64, BCHP_XPT_MSG_BUF_OVFL_INTR_96_127, BINT_DONT_PROCESS_L2,"XPT_OVFL_3"},
364	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_DPCR0_INTR_STATUS_REG, 0, "XPT_DPCR0"},
365	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_DPCR1_INTR_STATUS_REG, 0, "XPT_DPCR1"},
366	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_DPCR2_INTR_STATUS_REG, 0, "XPT_DPCR2"},
367	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_DPCR3_INTR_STATUS_REG, 0, "XPT_DPCR3"},
368	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS, 0, "XPT_PCROFF0"},
369	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS, 0, "XPT_PCROFF1"},
370	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS, 0, "XPT_PCROFF2"},
371	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT + 64, BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS, 0, "XPT_PCROFF3"},
372	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX0, 0, "RAV_CX0"},
373	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX1, 0, "RAV_CX1"},
374	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX2, 0, "RAV_CX2"},
375	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX3, 0, "RAV_CX3"},
376	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX4, 0, "RAV_CX4"},
377	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX5, 0, "RAV_CX5"},
378	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX6, 0, "RAV_CX6"},
379	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX7, 0, "RAV_CX7"},
380	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX8, 0, "RAV_CX8"},
381	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX9, 0, "RAV_CX9"},
382	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX10, 0, "RAV_CX10"},
383	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX11, 0, "RAV_CX11"},
384	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX12, 0, "RAV_CX12"},
385	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX13, 0, "RAV_CX13"},
386	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX14, 0, "RAV_CX14"},
387	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX15, 0, "RAV_CX15"},
388	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX16, 0, "RAV_CX16"},
389	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX17, 0, "RAV_CX17"},
390	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX18, 0, "RAV_CX18"},
391	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX19, 0, "RAV_CX19"},
392	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX20, 0, "RAV_CX20"},
393	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX21, 0, "RAV_CX21"},
394	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX22, 0, "RAV_CX22"},
395	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_CX23, 0, "RAV_CX23"},
396	/* { BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT + 64, BCHP_XPT_RAVE_INT_MISC, 0, "RAV_MISC"},*/
397	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_BUS_IF_INTR_STATUS_REG, 0, "XPT"},
398	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_BUS_IF_INTR_STATUS2_REG, 0, "XPT2"},
399	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_BUS_IF_INTR_STATUS3_REG, 0, "XPT3"},
400	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_BUS_IF_INTR_STATUS4_REG, 0, "XPT4"},
401	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_BUS_IF_INTR_STATUS5_REG, 0, "XPT5"},
402	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_PB0_INTR, 0, "XPT_PB0"},
403	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_PB1_INTR, 0, "XPT_PB1"},
404	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_PB2_INTR, 0, "XPT_PB2"},
405	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_PB3_INTR, 0, "XPT_PB3"},
406	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT + 64, BCHP_XPT_WAKEUP_INTR_STATUS_REG, 0, "XPT_WAKEUP"},
407	/* SDIO0_0_CPU_INTR is not mapped */
408	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT + 64, BCHP_AVD_INTR2_0_CPU_STATUS, 0, "AVD0"},
409	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_SHIFT + 64, BCHP_RFM_L2_CPU_STATUS, 0, "RFM"},
410	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_THD_A_CPU_INTR_SHIFT + 64, BCHP_THD_INTR2_CPU_STATUS, 0, "THD_A"},
411	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_THD_B_CPU_INTR_SHIFT + 64, BCHP_THD_INTR2B_CPU_STATUS, 0, "THD_B"},
412	/{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UFE_CPU_INTR_SHIFT + 64, BCHP_UFE_MISC_INTR2_STATUS, 0, "UFE"}, /
413	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS_0_CPU_INTR_SHIFT + 64, BCHP_DS_TOPM_L2_IRQSTS, 0, "DS_0"},
414	{ BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_SHIFT + 64, BCHP_MCIF_INTR2_CPU_STATUS, 0, "UPG_AUX"},
415	{ -1, 0, 0, NULL}
416	};
417
418	static const BINT_Settings bint_7552Settings =
419	{
420	BINT_P_7552_SetInt,
421	BINT_P_7552_ClearInt,
422	BINT_P_7552_SetMask,
423	BINT_P_7552_ClearMask,
424	BINT_P_7552_ReadMask,
425	BINT_P_7552_ReadStatus,
426	bint_7552,
427	"7552"
428	};
429
430	static void BINT_P_7552_SetInt( BREG_Handle regHandle, uint32_t baseAddr, int shift )
431	{
432	uint16_t ulChipID = BCHP_GetChipID();
433
434	switch( baseAddr )
435	{
436	BINT_P_STANDARD_L2_CASES
437	BREG_Write32( regHandle, baseAddr + BINT_P_STD_SET, 1ul<<shift);
438	break;
439	BINT_P_THD_L2_CASES
440	if((ulChipID == 0x7531) \|\| (ulChipID == 0x7532) \|\|
441	(ulChipID == 0x7541) \|\| (ulChipID == 0x7542) \|\|
442	(ulChipID == 0x7551) \|\| (ulChipID == 0x7552) \|\|
443	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592))
444	{
445	BREG_Write32( regHandle, baseAddr + BINT_P_STD_SET, 1ul<<shift);
446	}
447	break;
448	BINT_P_DS_L2_CASES
449	if((ulChipID == 0x7581) \|\| (ulChipID == 0x7582) \|\|
450	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592) \|\|
451	(ulChipID == 0x7574))
452	{
453	BREG_Write32( regHandle, baseAddr + BINT_P_STD_SET, 1ul<<shift);
454	}
455	break;
456	default:
457	/* Only standard L2 interrupts support setting of interrupts */
458	break;
459	}
460	}
461
462	static void BINT_P_7552_ClearInt( BREG_Handle regHandle, uint32_t baseAddr, int shift )
463	{
464	uint16_t ulChipID = BCHP_GetChipID();
465
466	BDBG_MSG(("ClearInt %#x:%d", baseAddr, shift));
467	switch( baseAddr )
468	{
469	BINT_P_STANDARD_L2_CASES
470	BREG_Write32( regHandle, baseAddr + BINT_P_STD_CLEAR, 1ul<<shift);
471	break;
472	BINT_P_THD_L2_CASES
473	if((ulChipID == 0x7531) \|\| (ulChipID == 0x7532) \|\|
474	(ulChipID == 0x7541) \|\| (ulChipID == 0x7542) \|\|
475	(ulChipID == 0x7551) \|\| (ulChipID == 0x7552) \|\|
476	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592))
477	{
478	BREG_Write32( regHandle, baseAddr + BINT_P_STD_CLEAR, 1ul<<shift);
479	}
480	break;
481	BINT_P_DS_L2_CASES
482	if((ulChipID == 0x7581) \|\| (ulChipID == 0x7582) \|\|
483	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592) \|\|
484	(ulChipID == 0x7574))
485	{
486	BREG_Write32( regHandle, baseAddr + BINT_P_STD_CLEAR, 1ul<<shift);
487	}
488	break;
489	BINT_P_XPT_STATUS_CASES
490	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_STATUS, ~(1ul<<shift));
491	break;
492	BINT_P_XPT_RAVE_CASES
493	BREG_Write32( regHandle, baseAddr + BINT_P_RAVE_STATUS, (1ul<<shift));
494	break;
495	BINT_P_XPT_BUF_CASES
496	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_BUF_STATUS, ~(1ul<<shift));
497	break;
498	BINT_P_TIMER_CASES
499	BREG_Write32( regHandle, baseAddr + BINT_P_TIMER_STATUS, 1ul<<shift);
500	break;
501	BINT_P_UPGSC_CASES
502	BINT_P_IRQ0_CASES
503	BINT_P_IRQ0_AON_CASES
504	/* Has to cleared at the source */
505	break;
506	BINT_P_XPT_MSG_ERR_CASES
507	/* Write 0 to clear the int bit. Writing 1's are ingored. */
508	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_STATUS, ~( 1ul << shift ) );
509	break;
510	BINT_P_PCROFFSET_CASES
511	/* Write 0 to clear the int bit. Writing 1's are ingored. */
512	BREG_Write32( regHandle, baseAddr + BINT_P_PCROFFSET_STATUS, ~( 1ul << shift ) );
513	break;
514	BINT_P_RFM_CASE
515	if((ulChipID == 0x7532) \|\| (ulChipID == 0x7542) \|\|
516	(ulChipID == 0x7552) \|\| (ulChipID == 0x7562) \|\|
517	(ulChipID == 0x7574) \|\| (ulChipID == 0x7582) \|\|
518	(ulChipID == 0x7592))
519	{
520	BREG_Write32( regHandle, baseAddr + BINT_P_RFM_CLEAR, 1ul<<shift);
521	}
522	break;
523	default:
524	/* Other types of interrupts do not support clearing of interrupts (condition must be cleared) */
525	break;
526	}
527	}
528
529	static void BINT_P_7552_SetMask( BREG_Handle regHandle, uint32_t baseAddr, int shift )
530	{
531	uint32_t intEnable;
532
533	uint32_t RaveEnReg = 0;
534	uint16_t ulChipID = BCHP_GetChipID();
535
536	BDBG_MSG(("SetMask %#x:%d", baseAddr, shift));
537
538	switch( baseAddr )
539	{
540	BINT_P_STANDARD_L2_CASES
541	BREG_Write32( regHandle, baseAddr + BINT_P_STD_MASK_SET, 1ul<<shift);
542	break;
543	BINT_P_THD_L2_CASES
544	if((ulChipID == 0x7531) \|\| (ulChipID == 0x7532) \|\|
545	(ulChipID == 0x7541) \|\| (ulChipID == 0x7542) \|\|
546	(ulChipID == 0x7551) \|\| (ulChipID == 0x7552) \|\|
547	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592))
548	{
549	BREG_Write32( regHandle, baseAddr + BINT_P_STD_MASK_SET, 1ul<<shift);
550	}
551	break;
552	BINT_P_DS_L2_CASES
553	if((ulChipID == 0x7581) \|\| (ulChipID == 0x7582) \|\|
554	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592) \|\|
555	(ulChipID == 0x7574))
556	{
557	BREG_Write32( regHandle, baseAddr + BINT_P_STD_MASK_SET, 1ul<<shift);
558	}
559	break;
560	BINT_P_XPT_STATUS_CASES
561	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_XPT_ENABLE);
562	intEnable &= ~(1ul<<shift);
563	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_ENABLE, intEnable);
564	break;
565	BINT_P_XPT_RAVE_CASES
566	RaveEnReg = GetRaveIntEnableOffset( baseAddr );
567	intEnable = BREG_Read32( regHandle, RaveEnReg );
568	intEnable &= ~(1ul<<shift);
569	BREG_Write32( regHandle, RaveEnReg, intEnable);
570	break;
571	BINT_P_XPT_BUF_CASES
572	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_XPT_BUF_ENABLE);
573	intEnable &= ~(1ul<<shift);
574	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_BUF_ENABLE, intEnable);
575	break;
576	BINT_P_TIMER_CASES
577	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_TIMER_MASK);
578	intEnable &= ~(1ul<<shift);
579	BREG_Write32( regHandle, baseAddr + BINT_P_TIMER_MASK, intEnable);
580	break;
581	BINT_P_IRQ0_CASES
582	/* we need to keep uart a/b interrupts enabled */
583	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_ENABLE);
584	intEnable &= ~(1ul<<shift);
585	BREG_Write32( regHandle, baseAddr + BINT_P_IRQ0_ENABLE, intEnable);
586	break;
587	BINT_P_IRQ0_AON_CASES
588	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_AON_ENABLE);
589	intEnable &= ~(1ul<<shift);
590	BREG_Write32( regHandle, baseAddr + BINT_P_IRQ0_AON_ENABLE, intEnable);
591	break;
592	BINT_P_UPGSC_CASES
593	/* TODO: The linux kernel may also use this interrupt register, so we must disable interrupts */
594	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_UPGSC_ENABLE );
595	intEnable &= ~(1ul<<shift);
596	BREG_Write32( regHandle, baseAddr + BINT_P_UPGSC_ENABLE, intEnable );
597	break;
598
599	BINT_P_XPT_MSG_ERR_CASES
600	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_ENABLE );
601	intEnable &= ~( 1ul << shift );
602	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_ENABLE, intEnable);
603	break;
604
605	BINT_P_PCROFFSET_CASES
606	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_PCROFFSET_ENABLE );
607	intEnable &= ~( 1ul << shift );
608	BREG_Write32( regHandle, baseAddr + BINT_P_PCROFFSET_ENABLE, intEnable);
609	break;
610	BINT_P_RFM_CASE
611	if((ulChipID == 0x7532) \|\| (ulChipID == 0x7542) \|\|
612	(ulChipID == 0x7552) \|\| (ulChipID == 0x7562) \|\|
613	(ulChipID == 0x7574) \|\| (ulChipID == 0x7582) \|\|
614	(ulChipID == 0x7592))
615	{
616	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_RFM_ENABLE );
617	intEnable &= ~( 1ul << shift );
618	BREG_Write32( regHandle, baseAddr + BINT_P_RFM_ENABLE, intEnable);
619	}
620	break;
621	default:
622	/* Unhandled interrupt base address */
623	BDBG_ASSERT( false );
624	break;
625	}
626	}
627
628	static void BINT_P_7552_ClearMask( BREG_Handle regHandle, uint32_t baseAddr, int shift )
629	{
630	uint32_t intEnable;
631
632	uint32_t RaveEnReg = 0;
633	uint16_t ulChipID = BCHP_GetChipID();
634
635	BDBG_MSG(("ClearMask %#x:%d", baseAddr, shift));
636	switch( baseAddr )
637	{
638	BINT_P_STANDARD_L2_CASES
639	BREG_Write32( regHandle, baseAddr + BINT_P_STD_MASK_CLEAR, 1ul<<shift);
640	break;
641	BINT_P_THD_L2_CASES
642	if((ulChipID == 0x7531) \|\| (ulChipID == 0x7532) \|\|
643	(ulChipID == 0x7541) \|\| (ulChipID == 0x7542) \|\|
644	(ulChipID == 0x7551) \|\| (ulChipID == 0x7552) \|\|
645	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592))
646	{
647	BREG_Write32( regHandle, baseAddr + BINT_P_STD_MASK_CLEAR, 1ul<<shift);
648	}
649	break;
650	BINT_P_DS_L2_CASES
651	if((ulChipID == 0x7581) \|\| (ulChipID == 0x7582) \|\|
652	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592) \|\|
653	(ulChipID == 0x7574))
654	{
655	BREG_Write32( regHandle, baseAddr + BINT_P_STD_MASK_CLEAR, 1ul<<shift);
656	}
657	break;
658	BINT_P_XPT_STATUS_CASES
659	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_XPT_ENABLE);
660	intEnable \|= 1ul<<shift;
661	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_ENABLE, intEnable);
662	break;
663	BINT_P_XPT_RAVE_CASES
664	RaveEnReg = GetRaveIntEnableOffset( baseAddr );
665	intEnable = BREG_Read32( regHandle, RaveEnReg );
666	intEnable \|= (1ul<<shift);
667	BREG_Write32( regHandle, RaveEnReg, intEnable);
668	break;
669	BINT_P_XPT_BUF_CASES
670	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_XPT_BUF_ENABLE);
671	intEnable \|= 1ul<<shift;
672	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_BUF_ENABLE, intEnable);
673	break;
674	BINT_P_IRQ0_CASES
675	/* we need to keep uart a/b interrupts enabled */
676	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_ENABLE);
677	intEnable \|= (1ul<<shift);
678	BREG_Write32( regHandle, baseAddr + BINT_P_IRQ0_ENABLE, intEnable );
679	break;
680	BINT_P_IRQ0_AON_CASES
681	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_AON_ENABLE);
682	intEnable \|= (1ul<<shift);
683	BREG_Write32( regHandle, baseAddr + BINT_P_IRQ0_AON_ENABLE, intEnable );
684	break;
685	BINT_P_UPGSC_CASES
686	/*
687	The BCHP_IRQ0_IRQSTAT_uarta_irq_MASK is a special bit that is actually a L1 mask. Therefore
688	we should never be touching this bit in the L2 interrupt manager.
689	*/
690	BDBG_ASSERT( shift != BCHP_IRQ0_IRQSTAT_uairq_SHIFT && shift != BCHP_IRQ0_IRQSTAT_ubirq_SHIFT );
691
692	/* TODO: The linux kernel may also use this interrupt register, so we must disable interrupts */
693	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_UPGSC_ENABLE );
694	intEnable \|= 1ul<<shift;
695	BREG_Write32( regHandle, baseAddr + BINT_P_UPGSC_ENABLE, intEnable );
696	break;
697	BINT_P_TIMER_CASES
698	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_TIMER_MASK );
699	intEnable \|= (1ul<<shift);
700	BREG_Write32( regHandle, baseAddr + BINT_P_TIMER_MASK, intEnable );
701	break;
702
703	BINT_P_XPT_MSG_ERR_CASES
704	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_ENABLE );
705	intEnable \|= ( 1ul << shift );
706	BREG_Write32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_ENABLE, intEnable);
707	break;
708
709	BINT_P_PCROFFSET_CASES
710	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_PCROFFSET_ENABLE );
711	intEnable \|= ( 1ul << shift );
712	BREG_Write32( regHandle, baseAddr + BINT_P_PCROFFSET_ENABLE, intEnable);
713	break;
714
715	BINT_P_RFM_CASE
716	if((ulChipID == 0x7532) \|\| (ulChipID == 0x7542) \|\|
717	(ulChipID == 0x7552) \|\| (ulChipID == 0x7562) \|\|
718	(ulChipID == 0x7574) \|\| (ulChipID == 0x7582) \|\|
719	(ulChipID == 0x7592))
720	{
721	intEnable = BREG_Read32( regHandle, baseAddr + BINT_P_RFM_ENABLE );
722	intEnable \|= ( 1ul << shift );
723	BREG_Write32( regHandle, baseAddr + BINT_P_RFM_ENABLE, intEnable);
724	}
725	break;
726	default:
727	/* Unhandled interrupt base address */
728	BDBG_ASSERT( false );
729	break;
730	}
731	}
732
733	static uint32_t BINT_P_7552_ReadMask( BREG_Handle regHandle, uint32_t baseAddr )
734	{
735	uint32_t RaveEnReg = 0;
736	uint16_t ulChipID = BCHP_GetChipID();
737
738	BDBG_MSG(("ReadMask %#x", baseAddr));
739	switch( baseAddr )
740	{
741	BINT_P_STANDARD_L2_CASES
742	return BREG_Read32(regHandle, baseAddr + BINT_P_STD_MASK_STATUS);
743	BINT_P_THD_L2_CASES
744	if((ulChipID == 0x7531) \|\| (ulChipID == 0x7532) \|\|
745	(ulChipID == 0x7541) \|\| (ulChipID == 0x7542) \|\|
746	(ulChipID == 0x7551) \|\| (ulChipID == 0x7552) \|\|
747	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592))
748	{
749	return BREG_Read32(regHandle, baseAddr + BINT_P_STD_MASK_STATUS);
750	}
751	else
752	return 0;
753	BINT_P_DS_L2_CASES
754	if((ulChipID == 0x7581) \|\| (ulChipID == 0x7582) \|\|
755	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592) \|\|
756	(ulChipID == 0x7574))
757	{
758	return BREG_Read32(regHandle, baseAddr + BINT_P_STD_MASK_STATUS);
759	}
760	else
761	return 0;
762	BINT_P_XPT_STATUS_CASES
763	return ~BREG_Read32( regHandle, baseAddr + BINT_P_XPT_ENABLE );
764	BINT_P_XPT_RAVE_CASES
765	RaveEnReg = GetRaveIntEnableOffset( baseAddr );
766	return ~BREG_Read32( regHandle, RaveEnReg );
767	BINT_P_XPT_BUF_CASES
768	return ~BREG_Read32( regHandle, baseAddr + BINT_P_XPT_BUF_ENABLE );
769	BINT_P_TIMER_CASES
770	return ~BREG_Read32( regHandle, baseAddr + BINT_P_TIMER_MASK );
771	BINT_P_IRQ0_CASES
772	return BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_ENABLE );
773	BINT_P_IRQ0_AON_CASES
774	return BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_AON_ENABLE );
775	BINT_P_UPGSC_CASES
776	/*
777	The BCHP_IRQ0_IRQSTAT_uXrta_irq_MASK is a special bit that is actually a L1 mask. Therefore
778	we always want to ignore it in the L2 interrupt manager
779	*/
780	return ~(BREG_Read32( regHandle, baseAddr + BINT_P_UPGSC_ENABLE ));
781
782	BINT_P_XPT_MSG_ERR_CASES
783	return ~BREG_Read32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_ENABLE );
784
785	BINT_P_PCROFFSET_CASES
786	return ~BREG_Read32( regHandle, baseAddr + BINT_P_PCROFFSET_ENABLE );
787	BINT_P_RFM_CASE
788	if((ulChipID == 0x7532) \|\| (ulChipID == 0x7542) \|\|
789	(ulChipID == 0x7552) \|\| (ulChipID == 0x7562) \|\|
790	(ulChipID == 0x7574) \|\| (ulChipID == 0x7582) \|\|
791	(ulChipID == 0x7592))
792	{
793	return BREG_Read32(regHandle, baseAddr + BINT_P_RFM_MASK_STATUS);
794	}
795	else
796	return 0;
797	default:
798	/* Unhandled interrupt base address */
799	BDBG_ASSERT( false );
800	return 0;
801	}
802	}
803
804	static uint32_t BINT_P_7552_ReadStatus( BREG_Handle regHandle, uint32_t baseAddr )
805	{
806	uint16_t ulChipID = BCHP_GetChipID();
807
808	BDBG_MSG(("ReadStatus %#x", baseAddr));
809	switch( baseAddr )
810	{
811	BINT_P_STANDARD_L2_CASES
812	return BREG_Read32(regHandle, baseAddr + BINT_P_STD_STATUS);
813	BINT_P_THD_L2_CASES
814	if((ulChipID == 0x7531) \|\| (ulChipID == 0x7532) \|\|
815	(ulChipID == 0x7541) \|\| (ulChipID == 0x7542) \|\|
816	(ulChipID == 0x7551) \|\| (ulChipID == 0x7552) \|\|
817	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592))
818	{
819	return BREG_Read32(regHandle, baseAddr + BINT_P_STD_STATUS);
820	}
821	else
822	return 0;
823	BINT_P_DS_L2_CASES
824	if((ulChipID == 0x7581) \|\| (ulChipID == 0x7582) \|\|
825	(ulChipID == 0x7591) \|\| (ulChipID == 0x7592) \|\|
826	(ulChipID == 0x7574))
827	{
828	return BREG_Read32(regHandle, baseAddr + BINT_P_STD_STATUS);
829	}
830	else
831	return 0;
832	BINT_P_XPT_STATUS_CASES
833	return BREG_Read32( regHandle, baseAddr + BINT_P_XPT_STATUS );
834	BINT_P_XPT_RAVE_CASES
835	return BREG_Read32( regHandle, baseAddr + BINT_P_RAVE_STATUS );
836	BINT_P_XPT_BUF_CASES
837	return BREG_Read32( regHandle, baseAddr + BINT_P_XPT_BUF_STATUS );
838	BINT_P_TIMER_CASES
839	return BREG_Read32( regHandle, baseAddr + BINT_P_TIMER_STATUS );
840	BINT_P_IRQ0_CASES
841	/* we need to keep uart a/b interrupts enabled, and mask them for application */
842	return (BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_STATUS )) ;
843	BINT_P_IRQ0_AON_CASES
844	return BREG_Read32( regHandle, baseAddr + BINT_P_IRQ0_AON_STATUS );
845	BINT_P_UPGSC_CASES
846	/*
847	The BCHP_IRQ0_IRQSTAT_uarta_irq_MASK is a special bit that is actually a L1 mask. Therefore
848	we always want to ignore it in the L2 interrupt manager
849	*/
850	return BREG_Read32( regHandle, baseAddr + BINT_P_UPGSC_ENABLE ) & ~(BCHP_IRQ0_IRQSTAT_uairq_MASK\|BCHP_IRQ0_IRQSTAT_ubirq_MASK);
851
852	BINT_P_XPT_MSG_ERR_CASES
853	return BREG_Read32( regHandle, baseAddr + BINT_P_XPT_MSG_ERR_STATUS );
854
855	BINT_P_PCROFFSET_CASES
856	return BREG_Read32( regHandle, baseAddr + BINT_P_PCROFFSET_STATUS );
857
858	BINT_P_RFM_CASE
859	if((ulChipID == 0x7532) \|\| (ulChipID == 0x7542) \|\|
860	(ulChipID == 0x7552) \|\| (ulChipID == 0x7562) \|\|
861	(ulChipID == 0x7574) \|\| (ulChipID == 0x7582) \|\|
862	(ulChipID == 0x7592))
863	{
864	return BREG_Read32(regHandle, baseAddr + BINT_P_RFM_STATUS);
865	}
866	else
867	return 0;
868
869	default:
870	/* Unhandled interrupt base address */
871	BDBG_ASSERT( false );
872	return 0;
873	}
874	}
875
876	const BINT_Settings *BINT_7552_GetSettings( void )
877	{
878	return &bint_7552Settings;
879	}
880
881
882	static uint32_t GetRaveIntEnableOffset(
883	uint32_t BaseAddr
884	)
885	{
886	uint32_t EnableAddr = 0;
887
888	switch( BaseAddr )
889	{
890	case BCHP_XPT_RAVE_INT_CX0: EnableAddr = BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES; break;
891	case BCHP_XPT_RAVE_INT_CX1: EnableAddr = BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES; break;
892	case BCHP_XPT_RAVE_INT_CX2: EnableAddr = BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES; break;
893	case BCHP_XPT_RAVE_INT_CX3: EnableAddr = BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES; break;
894	case BCHP_XPT_RAVE_INT_CX4: EnableAddr = BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES; break;
895	case BCHP_XPT_RAVE_INT_CX5: EnableAddr = BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES; break;
896	case BCHP_XPT_RAVE_INT_CX6: EnableAddr = BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES; break;
897	case BCHP_XPT_RAVE_INT_CX7: EnableAddr = BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES; break;
898	case BCHP_XPT_RAVE_INT_CX8: EnableAddr = BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES; break;
899	case BCHP_XPT_RAVE_INT_CX9: EnableAddr = BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES; break;
900	case BCHP_XPT_RAVE_INT_CX10: EnableAddr = BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES; break;
901	case BCHP_XPT_RAVE_INT_CX11: EnableAddr = BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES; break;
902	case BCHP_XPT_RAVE_INT_CX12: EnableAddr = BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES; break;
903	case BCHP_XPT_RAVE_INT_CX13: EnableAddr = BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES; break;
904	case BCHP_XPT_RAVE_INT_CX14: EnableAddr = BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES; break;
905	case BCHP_XPT_RAVE_INT_CX15: EnableAddr = BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES; break;
906	case BCHP_XPT_RAVE_INT_CX16: EnableAddr = BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES; break;
907	case BCHP_XPT_RAVE_INT_CX17: EnableAddr = BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES; break;
908	case BCHP_XPT_RAVE_INT_CX18: EnableAddr = BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES; break;
909	case BCHP_XPT_RAVE_INT_CX19: EnableAddr = BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES; break;
910	case BCHP_XPT_RAVE_INT_CX20: EnableAddr = BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES; break;
911	case BCHP_XPT_RAVE_INT_CX21: EnableAddr = BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES; break;
912	case BCHP_XPT_RAVE_INT_CX22: EnableAddr = BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES; break;
913	case BCHP_XPT_RAVE_INT_CX23: EnableAddr = BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES; break;
914
915	default:
916	/* Unhandled interrupt base address */
917	BDBG_ASSERT( false );
918	break;
919	}
920
921	return EnableAddr;
922	}
923
924
925	/* End of file */
926

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source: svn/newcon3bcm2_21bu/magnum/basemodules/int/7552/bint_7552.c @ 76

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