| 1 | /*************************************************************************** |
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| 2 | * (c)2005-2012 Broadcom Corporation |
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| 3 | * |
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| 4 | * This program is the proprietary software of Broadcom Corporation and/or its licensors, |
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| 5 | * and may only be used, duplicated, modified or distributed pursuant to the terms and |
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| 6 | * conditions of a separate, written license agreement executed between you and Broadcom |
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| 7 | * (an "Authorized License"). Except as set forth in an Authorized License, Broadcom grants |
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| 8 | * no license (express or implied), right to use, or waiver of any kind with respect to the |
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| 9 | * Software, and Broadcom expressly reserves all rights in and to the Software and all |
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| 10 | * intellectual property rights therein. IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU |
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| 11 | * HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY |
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| 12 | * NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE. |
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| 13 | * |
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| 14 | * Except as expressly set forth in the Authorized License, |
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| 15 | * |
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| 16 | * 1. This program, including its structure, sequence and organization, constitutes the valuable trade |
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| 17 | * secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof, |
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| 18 | * and to use this information only in connection with your use of Broadcom integrated circuit products. |
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| 19 | * |
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| 20 | * 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" |
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| 21 | * AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR |
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| 22 | * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO |
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| 23 | * THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES |
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| 24 | * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, |
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| 25 | * LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION |
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| 26 | * OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF |
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| 27 | * USE OR PERFORMANCE OF THE SOFTWARE. |
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| 28 | * |
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| 29 | * 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS |
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| 30 | * LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR |
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| 31 | * EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR |
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| 32 | * USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF |
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| 33 | * THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT |
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| 34 | * ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE |
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| 35 | * LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF |
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| 36 | * ANY LIMITED REMEDY. |
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| 37 | * |
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| 38 | * $brcm_Workfile: bads_def.h $ |
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| 39 | * $brcm_Revision: 39 $ |
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| 40 | * $brcm_Date: 2/22/12 2:09p $ |
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| 41 | * |
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| 42 | * Module Description: |
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| 43 | * |
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| 44 | * Revision History: |
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| 45 | * |
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| 46 | * $brcm_Log: /AP/ctfe/core/ads/bads_def.h $ |
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| 47 | * |
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| 48 | * 39 2/22/12 2:09p farshidf |
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| 49 | * SW7552-217: Enable Burst mode for DS only for china based on compile |
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| 50 | * flag |
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| 51 | * |
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| 52 | * Fw_Integration_Devel/14 2/22/12 2:08p farshidf |
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| 53 | * SW7552-217: Enable Burst mode for DS only for china based on compile |
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| 54 | * flag |
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| 55 | * |
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| 56 | * Fw_Integration_Devel/AP_V4_0_ADS_DEV/3 2/22/12 2:08p farshidf |
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| 57 | * SW7552-217: Enable Burst mode for DS only for china based on compile |
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| 58 | * flag |
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| 59 | * |
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| 60 | * Fw_Integration_Devel/AP_V4_0_ADS_DEV/2 2/21/12 12:03p cbrooks |
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| 61 | * sw3128-1:disabled Burst Mode for Annex A |
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| 62 | * |
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| 63 | * Fw_Integration_Devel/AP_V4_0_ADS_DEV/1 2/20/12 5:40p cbrooks |
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| 64 | * sw3128-1:Added Burst Noise Enable for Annex A China |
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| 65 | * |
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| 66 | * Fw_Integration_Devel/13 12/15/11 12:23p farshidf |
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| 67 | * SW3461-118: merge to integ |
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| 68 | * |
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| 69 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/7 12/12/11 4:14p cbrooks |
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| 70 | * sw3128-1:added new coeffs for FOI timing loop |
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| 71 | * |
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| 72 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/6 11/21/11 6:55p mpovich |
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| 73 | * SW3128-71: Support for a single, common 3128 chip family F/W binary. |
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| 74 | * |
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| 75 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/SW3128-71/1 11/17/11 6:58p mpovich |
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| 76 | * SW3128-71: Support for common 3128 family chip F/W. |
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| 77 | * |
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| 78 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/5 11/17/11 6:27p mpovich |
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| 79 | * SW3128-1: Revert INIT_BBS_UNUSED_FLAG5 to , |
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| 80 | * BADS_Internal_Params_eDisable. |
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| 81 | * |
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| 82 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/4 10/31/11 10:50a cbrooks |
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| 83 | * sw3128-1:added FOI timing loop |
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| 84 | * |
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| 85 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/3 10/31/11 9:39a thayashi |
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| 86 | * Changed CWC PLL BW |
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| 87 | * |
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| 88 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/2 10/24/11 2:29p cbrooks |
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| 89 | * sw3128-1:made Taks -1.75 MHz AnnexB CWC only for chips with WFE |
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| 90 | * |
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| 91 | * Fw_Integration_Devel/AP_V3_0_ADS_DEV/1 10/21/11 6:16p cbrooks |
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| 92 | * sw3128-1:added Taks -1.75 MHz CWC spur cancellation for AnnexB |
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| 93 | * |
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| 94 | * Fw_Integration_Devel/8 10/12/11 10:40a farshidf |
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| 95 | * SW3128-54: merge to Integ branch |
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| 96 | * |
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| 97 | * Fw_Integration_Devel/AP_V2_0_ADS_DEV/1 10/6/11 11:45a farshidf |
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| 98 | * SW3128-1: add support for 3128 C0 |
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| 99 | * |
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| 100 | * 31 8/17/11 8:00p farshidf |
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| 101 | * SW3461-1: enable INIT_BBS_UNUSED_FLAG6 |
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| 102 | * |
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| 103 | * 30 8/12/11 3:13p farshidf |
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| 104 | * SW3461-1: merge to main |
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| 105 | * |
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| 106 | * Fw_Integration_Devel/6 8/12/11 2:10p farshidf |
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| 107 | * SW3461-1: merge to integ |
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| 108 | * |
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| 109 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/16 7/29/11 11:25a cbrooks |
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| 110 | * sw3128-1:increased stuck fec timeout |
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| 111 | * |
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| 112 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/15 7/28/11 6:44p cbrooks |
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| 113 | * sw3128-1:Added auto reacquision count attemps for each mode |
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| 114 | * |
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| 115 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/14 7/28/11 4:40p cbrooks |
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| 116 | * sw3128-1:minor revisions for clarity |
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| 117 | * |
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| 118 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/13 7/27/11 7:58p cbrooks |
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| 119 | * sw3128-1:disabled acquisition test |
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| 120 | * |
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| 121 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/12 7/25/11 5:49p farshidf |
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| 122 | * SW3128-1: correction chip ID |
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| 123 | * |
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| 124 | * Fw_Integration_Devel/5 7/25/11 5:48p farshidf |
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| 125 | * SW3128-1: correction chip ID |
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| 126 | * |
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| 127 | * 29 7/26/11 6:24p farshidf |
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| 128 | * SW3128-1: remove 7552 callback |
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| 129 | * |
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| 130 | * 28 7/26/11 2:23p farshidf |
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| 131 | * SWDTV-7869: enable the FFT IRQ for 35233 |
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| 132 | * |
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| 133 | * 27 7/25/11 5:48p farshidf |
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| 134 | * SW3128-1: correction of chip ID |
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| 135 | * |
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| 136 | * 26 7/25/11 10:34a farshidf |
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| 137 | * SW3128-1: merge to main |
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| 138 | * |
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| 139 | * Fw_Integration_Devel/4 7/25/11 10:19a farshidf |
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| 140 | * SW3128-1: merge to integ |
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| 141 | * |
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| 142 | * Fw_Integration_Devel/3 7/20/11 9:49a farshidf |
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| 143 | * SW3128-1: B0 support |
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| 144 | * |
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| 145 | * Fw_Integration_Devel/2 7/8/11 11:34a farshidf |
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| 146 | * SW3128-11: merge to integ |
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| 147 | * |
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| 148 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/11 7/22/11 4:51p cbrooks |
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| 149 | * sw3128-1:Added SLow Scan for RFI interference |
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| 150 | * |
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| 151 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/10 7/18/11 6:37p cbrooks |
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| 152 | * sw3128-1:temporarily make slow mode same as fast mode |
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| 153 | * |
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| 154 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/9 7/18/11 6:09p cbrooks |
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| 155 | * sw3128-1:Added Baseband timing loop |
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| 156 | * |
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| 157 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/8 7/18/11 9:59a farshidf |
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| 158 | * SW3128-28: compile fix |
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| 159 | * |
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| 160 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/7 7/15/11 6:27p farshidf |
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| 161 | * SWDTV-7869: fix compile error |
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| 162 | * |
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| 163 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/6 7/15/11 6:23p farshidf |
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| 164 | * SWDTV-7869: add the new flag for B0 chip |
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| 165 | * |
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| 166 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/5 7/15/11 5:40p cbrooks |
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| 167 | * sw3128-1:added slow acquire for RFI support |
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| 168 | * |
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| 169 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/4 7/14/11 5:25p cbrooks |
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| 170 | * sw3128-1:enabled callback in 3461 |
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| 171 | * |
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| 172 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/3 7/1/11 1:10p cbrooks |
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| 173 | * sw3128-1:disabled callback in 3461 |
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| 174 | * |
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| 175 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/2 7/1/11 12:54p cbrooks |
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| 176 | * sw3128-1:added callback for 3461 |
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| 177 | * |
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| 178 | * Fw_Integration_Devel/AP_V0_6_ADS_DEV/1 6/30/11 6:01p cbrooks |
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| 179 | * sw3128-1:added retry capability |
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| 180 | * |
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| 181 | * Fw_Integration_Devel/1 6/29/11 12:38p farshidf |
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| 182 | * SW3461-13: merge to integration branch |
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| 183 | * |
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| 184 | * Fw_Integration_Devel/Ads_Fw_Devel_Rc04/2 6/22/11 6:46p cbrooks |
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| 185 | * sw3128-1:disabled callback for 3461 |
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| 186 | * |
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| 187 | * Fw_Integration_Devel/Ads_Fw_Devel_Rc04/1 6/22/11 5:32p cbrooks |
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| 188 | * sw3128-1:callback spport for 3461 |
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| 189 | * |
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| 190 | * 21 6/9/11 6:15p mpovich |
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| 191 | * SW3461-1: Merge Ver 0.4 Integ. onto main branch. |
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| 192 | * |
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| 193 | * SW_System_4_Integ_Test/4 6/9/11 2:16p mpovich |
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| 194 | * SW3461-1: Rebase with main branch. |
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| 195 | * |
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| 196 | * 20 6/7/11 6:02p farshidf |
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| 197 | * SW3128-1: add 3123 support |
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| 198 | * |
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| 199 | * 19 6/7/11 3:15p farshidf |
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| 200 | * SW3128-1: merge to main |
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| 201 | * |
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| 202 | * SW_System_4_Integ_Test/3 6/7/11 1:50p farshidf |
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| 203 | * SW3128-1: sync up with backend |
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| 204 | * |
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| 205 | * SW_System_4_Integ_Test/2 6/7/11 11:05a farshidf |
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| 206 | * SW3128-1: merge to integration branch |
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| 207 | * |
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| 208 | * Ads_Fw_Devel_3/5 6/7/11 10:56a cbrooks |
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| 209 | * sw3128-1:added3461/ 7552 CWC |
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| 210 | * |
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| 211 | * Ads_Fw_Devel_3/4 6/6/11 7:50p cbrooks |
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| 212 | * sw3128-1:Added 3461 CWC spur |
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| 213 | * |
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| 214 | * Ads_Fw_Devel_3/3 6/1/11 12:08p cbrooks |
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| 215 | * sw3128-1:new defs |
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| 216 | * |
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| 217 | * Ads_Fw_Devel_3/1 5/27/11 12:28p cbrooks |
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| 218 | * sw3128-1:Added IMC and CWC |
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| 219 | * |
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| 220 | * 18 5/18/11 3:43p farshidf |
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| 221 | * SW3128-1: compile fix |
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| 222 | * |
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| 223 | * 17 5/18/11 3:42p farshidf |
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| 224 | * SW3128-1: disable callback for 3461 |
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| 225 | * |
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| 226 | * 16 5/10/11 3:13p farshidf |
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| 227 | * SW3128-1: merge main |
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| 228 | * |
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| 229 | * ADS_3128_3/6 5/7/11 3:53p cbrooks |
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| 230 | * sw3128-1:clean up |
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| 231 | * |
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| 232 | * ADS_3128_3/5 5/7/11 3:47p cbrooks |
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| 233 | * sw3128-1:corrected freq offset |
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| 234 | * |
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| 235 | * ADS_3128_3/4 5/5/11 8:14p cbrooks |
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| 236 | * sw3128-1:Cleanup Code |
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| 237 | * |
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| 238 | * ADS_3128_3/3 5/1/11 3:45p cbrooks |
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| 239 | * sw3128-1:New Code |
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| 240 | * |
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| 241 | * ADS_3128_3/2 5/1/11 3:30p cbrooks |
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| 242 | * sw3128-1:Cleaned up Channel Scan Code |
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| 243 | * |
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| 244 | * ADS_3128_3/1 4/28/11 1:08p cbrooks |
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| 245 | * sw3128-1:New Code for scan |
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| 246 | * |
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| 247 | * 14 4/26/11 6:50p farshidf |
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| 248 | * SW3128-1: merge main |
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| 249 | * |
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| 250 | * ADS_3128_2/5 4/26/11 5:09p farshidf |
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| 251 | * SW3128-1: merge main |
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| 252 | * |
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| 253 | * 13 4/15/11 5:16p farshidf |
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| 254 | * SW3128-1: update from charlie |
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| 255 | * |
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| 256 | * 12 4/15/11 4:39p farshidf |
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| 257 | * SW3128-1: merge main |
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| 258 | * |
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| 259 | * ADS_3128_2/3 4/13/11 5:04p cbrooks |
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| 260 | * sw3128-1:new cwc code |
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| 261 | * |
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| 262 | * ADS_3128_2/2 4/11/11 8:31p cbrooks |
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| 263 | * SW3128-1:Added CWC code |
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| 264 | * |
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| 265 | * ADS_3128_2/1 4/11/11 12:46p cbrooks |
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| 266 | * sw3128-1:New CWC code |
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| 267 | * |
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| 268 | * 11 3/24/11 4:15p farshidf |
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| 269 | * SW3128-1: add support for 3124 |
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| 270 | * |
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| 271 | * 10 3/3/11 11:01a farshidf |
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| 272 | * SW3128-1: clean up |
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| 273 | * |
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| 274 | * 8 2/28/11 5:57p cbrooks |
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| 275 | * sw3128-1:Changed acqwords to internal_params |
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| 276 | * |
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| 277 | * 7 2/9/11 10:50a cbrooks |
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| 278 | * SW3128-1:LIC EST CODE |
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| 279 | * |
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| 280 | * 6 1/31/11 7:50p cbrooks |
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| 281 | * sw3128-1:new code |
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| 282 | * |
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| 283 | * 5 1/30/11 6:35p cbrooks |
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| 284 | * sw3128-1:FFT Code |
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| 285 | * |
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| 286 | * 4 1/28/11 4:00p farshidf |
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| 287 | * SW3461-1: update |
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| 288 | * |
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| 289 | * 3 1/28/11 3:45p farshidf |
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| 290 | * SW3128-1: adapt the files to 3461 |
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| 291 | * |
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| 292 | * 2 1/26/11 4:13p farshidf |
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| 293 | * SW3128-1: clean up |
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| 294 | * |
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| 295 | ***************************************************************************/ |
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| 296 | #ifndef BADS_DEF_H__ |
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| 297 | #define BADS_DEF_H__ |
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| 298 | |
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| 299 | #ifdef __cplusplus |
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| 300 | extern "C" { |
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| 301 | #endif |
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| 302 | |
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| 303 | /*************************************************************************** |
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| 304 | * BADS CORE Defines |
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| 305 | ****************************************************************************/ |
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| 306 | #if (BCHP_VER == BCHP_VER_A0) |
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| 307 | #if ((BCHP_CHIP==7552) || (BCHP_CHIP==35233) || (BCHP_FAMILY==3128) || (BCHP_FAMILY==3461)) |
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| 308 | #define BCHP_DS_CORE_V_9_1 1 |
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| 309 | #endif |
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| 310 | #elif (BCHP_VER == BCHP_VER_B0) |
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| 311 | #if ((BCHP_CHIP==7552) || (BCHP_CHIP==35233) || (BCHP_FAMILY==3128) || (BCHP_FAMILY==3461)) |
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| 312 | #define BCHP_DS_CORE_V_9_2 1 |
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| 313 | #endif |
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| 314 | #elif (BCHP_VER == BCHP_VER_C0) |
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| 315 | #if ((BCHP_FAMILY==3128)) |
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| 316 | #define BCHP_DS_CORE_V_9_3 1 |
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| 317 | #endif |
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| 318 | #else |
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| 319 | #error DS core NOT DEFINED in ADS PI |
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| 320 | #endif |
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| 321 | |
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| 322 | /*************************************************************************** |
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| 323 | * BADS define statements |
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| 324 | ****************************************************************************/ |
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| 325 | #if (BCHP_FAMILY==3128) || (BCHP_FAMILY==3461) || (BCHP_CHIP==7552) |
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| 326 | #define FFT_INTERRUPT 1 |
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| 327 | #else |
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| 328 | #define FFT_INTERRUPT 0 |
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| 329 | #endif |
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| 330 | #define PRINT_DEBUG 0 |
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| 331 | |
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| 332 | #define NUM_FAST_ACQUIRES 1 |
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| 333 | #define NUM_SLOW_ACQUIRES 1 |
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| 334 | |
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| 335 | /*Define number of times to retry if not locked and we are in Auto Acquire mode for different Acquisition Modes*/ |
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| 336 | #define NUM_RETRIES_IF_AUTOACQUIRE_AND_AUTOSELECT 2 |
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| 337 | #define NUM_RETRIES_IF_AUTOACQUIRE_AND_FAST 0 |
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| 338 | #define NUM_RETRIES_IF_AUTOACQUIRE_AND_SLOW 0 |
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| 339 | #define NUM_RETRIES_IF_AUTOACQUIRE_AND_SCAN 0 |
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| 340 | |
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| 341 | #define PRE_NYQUIST_FILTER_BW_1MHZ 60 /*This is in KHz*/ |
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| 342 | #define AGCBI_MAX_VALUE 0x70000000 /*Max AGCB integrator value to show no signal*/ |
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| 343 | |
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| 344 | #define AGC_TIME_SAMPLES 30000 /*Number of F_HS samples for AGC to converge, 15000 = 1 ms for F_HS of 15 MSPS*/ |
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| 345 | |
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| 346 | #define TL_TIME_HIGH_BAUD_SAMPLES 15000 /*Number of baud samples for TL to converge, 5000 = 1 ms for Baud rate of 5 MBAUD*/ |
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| 347 | #define TL_TIME_MED_BAUD_SAMPLES 10000 |
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| 348 | #define TL_TIME_LOW_BAUD_SAMPLES 5000 |
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| 349 | #define CMA_TIME_BLIND1_BAUD_SAMPLES 30000 /*30000*/ |
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| 350 | #define CMA_TIME_BLIND2_BAUD_SAMPLES 20000 /*20000*/ |
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| 351 | #define CMA_TIME_LOCKED1_BAUD_SAMPLES 30000 /*30000*/ |
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| 352 | #define CMA_TIME_LOCKED2_BAUD_SAMPLES 20000 /*20000*/ |
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| 353 | |
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| 354 | #define CMA_TIME_FAST_TRIM_BAUD_SAMPLES 10000 /*10000*/ |
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| 355 | #define LMS_TIME_FAST_TRIM_BAUD_SAMPLES 10000 /*10000*/ |
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| 356 | |
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| 357 | #define CMA_TIME_SLOW_TRIM1_BAUD_SAMPLES 768000 /*Q256/Q128 750000*/ |
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| 358 | #define LMS_TIME_SLOW_TRIM1_BAUD_SAMPLES 256000 /*Q256/Q128 250000*/ |
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| 359 | |
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| 360 | #define CMA_TIME_SLOW_TRIM2_BAUD_SAMPLES 48000 /*Q64/Q32/Q16 750000*/ |
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| 361 | #define LMS_TIME_SLOW_TRIM2_BAUD_SAMPLES 16000 /*Q64/Q32/Q16 250000*/ |
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| 362 | |
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| 363 | |
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| 364 | #define ANNEXA_FEC_LOCK_TIMEOUT 20 /*sync timeout in ms*/ |
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| 365 | #define ANNEXB_FEC_LOCK_TIMEOUT 40 /*sync timeout in ms*/ |
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| 366 | |
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| 367 | #define MAX_PHASE_ERROR 5000 |
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| 368 | |
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| 369 | #define NUM_TIMING_FFTS 3 /*1,2, or 3*/ |
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| 370 | #define NUM_CARRIER_FFTS 3 /*1,2, or 3*/ |
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| 371 | |
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| 372 | #define SNR_LEAKY_AVG 512 |
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| 373 | |
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| 374 | /*Lock Detector Values*/ |
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| 375 | /*Every 1 mS the PI calles the BADS_P_Get_LockStatus function*/ |
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| 376 | /*Lock is declared IF the number of clean blocks detected in since the previous call is >= NUM_CLEAN_BLOCKS_TO_LOCK*/ |
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| 377 | /*if this condition is not met then*/ |
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| 378 | /*Lock is declared if there have NOT been more then NUM_BAD_BLOCK_TO_UNLOCK bad blocks have accumulated*/ |
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| 379 | /*if this condition is not met then*/ |
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| 380 | /*Unlock is declared if there have been more then NUM_BAD_BLOCK_TO_UNLOCK bad blocks have accumulated*/ |
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| 381 | #define NUM_CLEAN_BLOCKS_TO_LOCK 1 |
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| 382 | #define NUM_BAD_BLOCK_TO_UNLOCK 1000 |
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| 383 | #define STUCK_FEC_RESET_COUNT 10 |
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| 384 | |
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| 385 | /*Acquire Parameter Ranges*/ |
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| 386 | #define MAX_CARRIER_RANGE 1000000 |
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| 387 | #define MIN_BAUD_RATE 1000000 |
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| 388 | #define MAX_BAUD_RATE 7300000 |
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| 389 | |
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| 390 | /*Scan Parameter Ranges*/ |
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| 391 | #define MAX_CARRIER_SCAN 1000000 |
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| 392 | #define MIN_BAUD_SCAN 1000000 |
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| 393 | #define MAX_BAUD_SCAN 7300000 |
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| 394 | |
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| 395 | #define Q64_ANNEXB_SYMBOL_RATE 5056941 |
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| 396 | #define MAX_Q64_ANNEXB_SYMBOL_RATE 5081941 |
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| 397 | #define MIN_Q64_ANNEXB_SYMBOL_RATE 5031941 |
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| 398 | |
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| 399 | #define Q256_Q1024_ANNEXB_SYMBOL_RATE 5360537 |
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| 400 | #define MAX_Q256_Q1024_ANNEXB_SYMBOL_RATE 5385537 |
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| 401 | #define MIN_Q256_Q1024_ANNEXB_SYMBOL_RATE 5335537 |
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| 402 | |
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| 403 | /*Set the default IF frequency for the BADS_Local_Params structure*/ |
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| 404 | #define IF_FREQUENCY 0 |
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| 405 | |
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| 406 | |
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| 407 | /*Number of CWC to use in manual mode or what type to use in auto mode, if INIT_BBS_CWC==BADS_Internal_Params_eEnable*/ |
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| 408 | #define CWC_MODE1 2 /*0 disable, 1 for Non-tracking mode (CWC_LFC1 - CWC_LFC4 will be set to 0), 2 for AFC mode, 3 for PLL mode*/ |
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| 409 | #define CWC_MODE2 3 /*the CWC's must be enabled in order, 0 then 1 then 2 etc..*/ |
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| 410 | #define CWC_MODE3 3 |
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| 411 | #define CWC_MODE4 3 |
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| 412 | #define CWC_AFC_ACQ_BW 0x12800320 |
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| 413 | #define CWC_AFC_TRK_BW 0x03200160 |
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| 414 | #define CWC_AFC_MU 2 |
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| 415 | #define CWC_AFC_LEAK 0 |
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| 416 | #define CWC_PLL_ACQ_BW 0x00040064 |
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| 417 | #define CWC_PLL_TRK_BW 0x00040064 |
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| 418 | #define CWC_PLL_MU 2 |
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| 419 | #define CWC_PLL_LEAK 0 |
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| 420 | |
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| 421 | /***************************************************************************************/ |
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| 422 | /*THE CWC HAS SOME STRANGE PROGRAMMING DO NOT CHANGE THE DEFINITIONS BELOW*/ |
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| 423 | /*The chip has a bitwise definition for the AFC/PLL mode but no bitwise RDB representation*/ |
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| 424 | /*CWC_ENA needs to be 15, 14, 12, 8 or 0*/ |
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| 425 | #define CWC_ACQ_LFC1 ((CWC_MODE1 == 3) ? CWC_PLL_ACQ_BW : CWC_AFC_ACQ_BW) |
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| 426 | #define CWC_ACQ_LFC2 ((CWC_MODE2 == 3) ? CWC_PLL_ACQ_BW : CWC_AFC_ACQ_BW) |
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| 427 | #define CWC_ACQ_LFC3 ((CWC_MODE3 == 3) ? CWC_PLL_ACQ_BW : CWC_AFC_ACQ_BW) |
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| 428 | #define CWC_ACQ_LFC4 ((CWC_MODE4 == 3) ? CWC_PLL_ACQ_BW : CWC_AFC_ACQ_BW) |
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| 429 | #define CWC_TRK_LFC1 ((CWC_MODE1 == 3) ? CWC_PLL_TRK_BW : CWC_AFC_TRK_BW) |
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| 430 | #define CWC_TRK_LFC2 ((CWC_MODE2 == 3) ? CWC_PLL_TRK_BW : CWC_AFC_TRK_BW) |
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| 431 | #define CWC_TRK_LFC3 ((CWC_MODE3 == 3) ? CWC_PLL_TRK_BW : CWC_AFC_TRK_BW) |
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| 432 | #define CWC_TRK_LFC4 ((CWC_MODE4 == 3) ? CWC_PLL_TRK_BW : CWC_AFC_TRK_BW) |
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| 433 | #define CWC_MU1 ((CWC_MODE1 == 3) ? CWC_PLL_MU : CWC_AFC_MU) |
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| 434 | #define CWC_MU2 ((CWC_MODE2 == 3) ? CWC_PLL_MU : CWC_AFC_MU) |
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| 435 | #define CWC_MU3 ((CWC_MODE3 == 3) ? CWC_PLL_MU : CWC_AFC_MU) |
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| 436 | #define CWC_MU4 ((CWC_MODE4 == 3) ? CWC_PLL_MU : CWC_AFC_MU) |
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| 437 | #define CWC_LK1 ((CWC_MODE1 == 3) ? CWC_PLL_LEAK : CWC_AFC_LEAK) |
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| 438 | #define CWC_LK2 ((CWC_MODE2 == 3) ? CWC_PLL_LEAK : CWC_AFC_LEAK) |
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| 439 | #define CWC_LK3 ((CWC_MODE3 == 3) ? CWC_PLL_LEAK : CWC_AFC_LEAK) |
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| 440 | #define CWC_LK4 ((CWC_MODE4 == 3) ? CWC_PLL_LEAK : CWC_AFC_LEAK) |
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| 441 | #define MANUAL_CWC_NUM ((CWC_MODE1 != 0) ? 1 : 0) + ((CWC_MODE2 != 0) ? 1 : 0) + ((CWC_MODE3 != 0) ? 1 : 0) + ((CWC_MODE4 != 0) ? 1 : 0) |
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| 442 | #define CWC_PLL ((CWC_MODE1 == 3) ? 1 : 0) | ((CWC_MODE2 == 3) ? 1 : 0)<<1 | ((CWC_MODE3 == 3) ? 1 : 0)<<2 | ((CWC_MODE4 == 3) ? 1 : 0)<<3 |
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| 443 | #define CWC_ENA 15 - (((CWC_MODE1 != 0) ? 1 : 0) | ((CWC_MODE2 != 0) ? 1 : 0)<<1 | ((CWC_MODE3 != 0) ? 1 : 0)<<2 | ((CWC_MODE4 != 0) ? 1 : 0)<<3) |
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| 444 | /***************************************************************************************/ |
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| 445 | |
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| 446 | |
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| 447 | /*Initial Values for the BADS_Internal_Params structure*/ |
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| 448 | /*Warning!! these can be overwritten by BBS*/ |
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| 449 | #define INIT_BBS_RERUN_INIT BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 450 | |
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| 451 | #ifdef BADS_ANNEXA_BURST_SUPPORT |
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| 452 | #define INIT_BBS_ANNEXA_BURST_MODE BADS_Internal_Params_eEnable /*enable Require only for China Annex A*/ |
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| 453 | #else |
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| 454 | #define INIT_BBS_ANNEXA_BURST_MODE BADS_Internal_Params_eDisable |
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| 455 | #endif |
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| 456 | |
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| 457 | #if (BCHP_FAMILY==3128) || (BCHP_FAMILY==3461) || (BCHP_CHIP==7552) |
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| 458 | #define INIT_BBS_CWC BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 459 | #else |
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| 460 | #define INIT_BBS_CWC BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 461 | #endif |
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| 462 | |
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| 463 | #define INIT_BBS_CFL BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 464 | #define INIT_BBS_CIP_CO_JAMLOAD BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 465 | #define INIT_BBS_DDAGC BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 466 | #define INIT_BBS_IMC BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 467 | #define INIT_BBS_IQPHS BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 468 | #define INIT_BBS_IQIMB BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 469 | #define INIT_BBS_SWEEP_SWITCH BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 470 | #define INIT_BBS_SWEEP_NEG2POS_INVERT BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 471 | #define INIT_BBS_ACQUISITION_TEST BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 472 | #define INIT_BBS_TIMING_SCAN BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 473 | #define INIT_BBS_TIMING_SCAN_LOAD BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 474 | #define INIT_BBS_CARRIER_SCAN BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 475 | #define INIT_BBS_CARRIER_SCAN_LOAD BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 476 | #define INIT_BBS_UNUSED_FLAG0 BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 477 | #define INIT_BBS_UNUSED_FLAG1 BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 478 | #define INIT_BBS_UNUSED_FLAG2 BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ |
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| 479 | |
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| 480 | #if (BCHP_FAMILY==3128) |
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| 481 | #define INIT_BBS_UNUSED_FLAG3 BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_VIDEO_CANCELLATION_ANNEX_B: Disable means do not add a CWC at RF Freq - 1.75 MHz, enable means add CWC*/ |
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| 482 | #else |
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| 483 | #define INIT_BBS_UNUSED_FLAG3 BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_VIDEO_CANCELLATION_ANNEX_B: Disable means do not add a CWC at RF Freq - 1.75 MHz, enable means add CWC*/ |
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| 484 | #endif |
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| 485 | |
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| 486 | #define INIT_BBS_UNUSED_FLAG4 BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_DUAL_SCAN: Disable mean one fast scan, Enable for one fast scan then one slow scan*/ |
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| 487 | |
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| 488 | #define INIT_BBS_UNUSED_FLAG5 BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_TIMING_FOI: Disable mean transition tracker, Enable for FOI*/ |
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| 489 | |
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| 490 | #if (BCHP_FAMILY==3128) || (BCHP_FAMILY==3461) || (BCHP_CHIP==7552) |
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| 491 | #define INIT_BBS_UNUSED_FLAG6 BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_CALLBACK_ENABLE: Disable mean no callback function, use callback function*/ |
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| 492 | #else |
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| 493 | #define INIT_BBS_UNUSED_FLAG6 BADS_Internal_Params_eDisable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_CALLBACK_ENABLE: Disable mean no callback function, use callback function*/ |
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| 494 | #endif |
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| 495 | |
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| 496 | #define INIT_BBS_UNUSED_FLAG7 BADS_Internal_Params_eEnable /*BADS_Internal_Params_eDisable or BADS_Internal_Params_eEnable*/ /*used as INIT_BBS_CWC_AUTO: Disable mean manual, Enable for auto*/ |
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| 497 | #define INIT_BBS_ACQUISITION_NUMBER 0 /*uint8_t*/ |
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| 498 | #define INIT_BBS_TIMING_SCAN_EXTRA_BINS 1*256 /*uint16_t, must be in 8.8 format*/ |
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| 499 | #define INIT_BBS_CARRIER_SCAN_EXTRA_BINS 1*256 /*uint16_t, must be in 8.8 format*/ |
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| 500 | #define INIT_BBS_TIMING_SCAN_PERCENT 6*256 /*uint16_t, must be in 8.8 format*/ |
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| 501 | #define INIT_BBS_CARRIER_SCAN_PERCENT 2*256 /*uint16_t, must be in 8.8 format, must be <6.25% or 6.25*256*/ |
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| 502 | #define INIT_BBS_TIMING_SCAN_THRESHOLD 0x3000 /*uint32_t, 17 bits in chip*/ |
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| 503 | #define INIT_BBS_CARRIER_SCAN_THRESHOLD 0x3000 /*uint32_t, 17 bits in chip*/ |
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| 504 | #define INIT_BBS_CWC1_FIN1 2000000 /*int32_t, 24 bit signed in chip*/ |
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| 505 | #define INIT_BBS_CWC2_FIN2 2000000 /*int32_t, 24 bit signed in chip*/ |
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| 506 | #define INIT_BBS_CWC3_FIN3 0 /*int32_t, 24 bit signed in chip*/ |
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| 507 | #define INIT_BBS_CWC4_FIN4 0 /*int32_t, 24 bit signed in chip*/ |
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| 508 | #define INIT_BBS_CWC1_FOFFSET1 0 /*int32_t, 29 bit signed in chip*/ |
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| 509 | #define INIT_BBS_CWC2_FOFFSET2 0 /*int32_t, 29 bit signed in chip*/ |
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| 510 | #define INIT_BBS_CWC3_FOFFSET3 0 /*int32_t, 29 bit signed in chip*/ |
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| 511 | #define INIT_BBS_CWC4_FOFFSET4 0 /*int32_t, 29 bit signed in chip*/ |
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| 512 | #define INIT_BBS_ACQWORD0 0 /*uint32_t*/ |
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| 513 | #define INIT_BBS_ACQWORD1 0 /*uint32_t*/ |
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| 514 | #define INIT_BBS_ACQWORD2 0 /*uint32_t*/ |
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| 515 | #define INIT_BBS_ACQWORD3 0 /*uint32_t*/ |
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| 516 | #define INIT_BBS_ACQWORD4 0 /*uint32_t*/ |
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| 517 | #define INIT_BBS_ACQWORD5 0 /*uint32_t*/ |
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| 518 | #define INIT_BBS_ACQWORD6 0 /*uint32_t*/ /*used by acquisition test */ |
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| 519 | #define INIT_BBS_ACQWORD7 0 /*uint32_t*/ /*used by acquisition test */ |
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| 520 | |
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| 521 | #ifdef __cplusplus |
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| 522 | } |
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| 523 | #endif |
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| 524 | |
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| 525 | #endif |
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