| 1 | /*************************************************************************** |
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| 2 | * Copyright (c) 2006-2012, Broadcom Corporation |
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| 3 | * All Rights Reserved |
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| 4 | * Confidential Property of Broadcom Corporation |
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| 5 | * |
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| 6 | * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
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| 7 | * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
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| 8 | * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
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| 9 | * |
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| 10 | * $brcm_Workfile: bape_chip_priv.h $ |
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| 11 | * $brcm_Revision: Hydra_Software_Devel/43 $ |
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| 12 | * $brcm_Date: 3/5/12 9:22a $ |
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| 13 | * |
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| 14 | * Module Description: Audio Decoder Interface |
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| 15 | * |
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| 16 | * Revision History: |
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| 17 | * |
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| 18 | * $brcm_Log: /magnum/portinginterface/ape/7422/bape_chip_priv.h $ |
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| 19 | * |
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| 20 | * Hydra_Software_Devel/43 3/5/12 9:22a jgarrett |
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| 21 | * SW7425-2455: Removing ADC and RF Inputs |
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| 22 | * |
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| 23 | * Hydra_Software_Devel/42 1/18/12 11:21a gskerl |
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| 24 | * SW7429-18: Removed erroneous #error when there are no HDMI or SPDIF |
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| 25 | * inputs. |
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| 26 | * |
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| 27 | * Hydra_Software_Devel/41 1/17/12 6:31p gskerl |
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| 28 | * SW7429-18: Added conditional definitions for |
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| 29 | * BAPE_CHIP_SPDIF_INPUT_TYPE_IS_LEGACY and |
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| 30 | * BAPE_CHIP_SPDIF_INPUT_TYPE_IS_IOPIN. |
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| 31 | * |
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| 32 | * Hydra_Software_Devel/40 1/13/12 3:28p gskerl |
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| 33 | * SW7429-18: Added BAPE_CHIP_MAI_INPUT_TYPE_IS_xxx macros |
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| 34 | * |
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| 35 | * Hydra_Software_Devel/39 12/5/11 7:02p gskerl |
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| 36 | * SW7429-18: Define sample rate converter type... either |
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| 37 | * BAPE_CHIP_SRC_TYPE_IS_LEGACY or BAPE_CHIP_SRC_TYPE_IS_IIR. |
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| 38 | * |
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| 39 | * Hydra_Software_Devel/39 12/5/11 7:02p gskerl |
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| 40 | * SW7429-18: Define sample rate converter type... either |
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| 41 | * BAPE_CHIP_SRC_TYPE_IS_LEGACY or BAPE_CHIP_SRC_TYPE_IS_IIR. |
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| 42 | * |
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| 43 | * Hydra_Software_Devel/39 12/5/11 6:50p gskerl |
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| 44 | * SW7429-18: Define sample rate converter type... either |
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| 45 | * BAPE_CHIP_SRC_TYPE_IS_LEGACY or BAPE_CHIP_SRC_TYPE_IS_IIR. |
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| 46 | * |
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| 47 | * Hydra_Software_Devel/38 12/1/11 6:40p gskerl |
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| 48 | * SW7429-18: Only define BAPE_CHIP_MAX_SRC_COEFF_CHUNKS when it's |
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| 49 | * dependencies are defined. |
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| 50 | * |
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| 51 | * Hydra_Software_Devel/37 12/1/11 3:43p jgarrett |
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| 52 | * SW7429-18: Correcting STC address selection for 7429 |
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| 53 | * |
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| 54 | * Hydra_Software_Devel/36 11/30/11 6:28p jgarrett |
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| 55 | * SW7429-18: Revising coefficient numbers for 7429 |
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| 56 | * |
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| 57 | * Hydra_Software_Devel/35 11/30/11 4:26p jgarrett |
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| 58 | * SW7429-18: Adding stubs for SPDIF/MAI inputs on 7429 |
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| 59 | * |
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| 60 | * Hydra_Software_Devel/34 11/29/11 12:03p gskerl |
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| 61 | * SW7429-18: Fixed compile warning (and bug) #ifdef --> #if defined. |
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| 62 | * |
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| 63 | * Hydra_Software_Devel/33 11/28/11 6:32p gskerl |
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| 64 | * SW7429-18: Added check for |
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| 65 | * BCHP_AUD_MISC_SEROUT_SEL_HDMI_RX_ARC_ENABLE_MASK to decide if |
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| 66 | * BAPE_CHIP_MAX_AUDIO_RETURN_CHANNELS should be defined |
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| 67 | * |
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| 68 | * Hydra_Software_Devel/32 11/14/11 3:22p gskerl |
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| 69 | * SW7429-18: Merging 7429 changes back to main branch. |
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| 70 | * |
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| 71 | * Hydra_Software_Devel/SW7429-18/7 11/4/11 4:42p jgarrett |
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| 72 | * SW7429-18: Adding SPDIF Output for 7429 |
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| 73 | * |
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| 74 | * Hydra_Software_Devel/SW7429-18/6 10/27/11 3:21p jgarrett |
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| 75 | * SW7429-18: Adding I2S Output for 7429 |
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| 76 | * |
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| 77 | * Hydra_Software_Devel/SW7429-18/5 10/26/11 12:44p jgarrett |
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| 78 | * SW7429-18: Merging latest changes from main branch |
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| 79 | * |
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| 80 | * Hydra_Software_Devel/SW7429-18/4 10/26/11 11:43a jgarrett |
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| 81 | * SW7429-18: Adding I2S Input for 7429 |
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| 82 | * |
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| 83 | * Hydra_Software_Devel/SW7429-18/3 10/25/11 5:34p jgarrett |
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| 84 | * SW7429-18: Adding HDMI output support for 7429 |
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| 85 | * |
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| 86 | * Hydra_Software_Devel/SW7429-18/2 10/25/11 10:15a jgarrett |
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| 87 | * SW7429-18: Adding NCO support for 7429 |
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| 88 | * |
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| 89 | * Hydra_Software_Devel/SW7429-18/1 10/21/11 6:29p jgarrett |
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| 90 | * SW7429-18: Initial compileable version for 7429 |
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| 91 | * |
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| 92 | * Hydra_Software_Devel/31 10/19/11 4:56p jgarrett |
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| 93 | * SW7231-321: Fixed clockgen mux for 7231 B0 |
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| 94 | * |
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| 95 | * Hydra_Software_Devel/30 9/2/11 3:53p sgadara |
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| 96 | * SWDTV-6627: [35233] Refine the SRC coefficient memory allocation |
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| 97 | * |
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| 98 | * Hydra_Software_Devel/29 8/26/11 9:50p sgadara |
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| 99 | * SWDTV-6627: [35233] Add Equalizer support |
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| 100 | * |
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| 101 | * Hydra_Software_Devel/28 8/12/11 4:18p venkatr |
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| 102 | * SWDTV-6584 : [35233] ADC input code cleanup |
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| 103 | * |
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| 104 | * Hydra_Software_Devel/27 8/11/11 1:16p jgarrett |
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| 105 | * SWDTV-6584: Making includes of audadc and spdif_rcvr register headers |
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| 106 | * conditional on presence of the required blocks |
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| 107 | * |
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| 108 | * Hydra_Software_Devel/26 8/10/11 9:28a venkatr |
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| 109 | * SWDTV-6584 : [35233] Add ADC Input for APE |
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| 110 | * |
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| 111 | * Hydra_Software_Devel/25 7/8/11 6:38p jgarrett |
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| 112 | * SWDTV-6760: Adding I2sMultiOutput |
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| 113 | * |
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| 114 | * Hydra_Software_Devel/24 7/8/11 4:32p gskerl |
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| 115 | * SW7552-72: Added support for NCO/Mclkgen audio clock sources |
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| 116 | * |
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| 117 | * Hydra_Software_Devel/23 6/9/11 3:40p gskerl |
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| 118 | * SW7552-37: Set BAPE_CHIP_MAX_RFMODS based on RDB defs |
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| 119 | * |
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| 120 | * Hydra_Software_Devel/22 5/31/11 6:37p jgarrett |
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| 121 | * SW7425-406: Adding initial DSP mixer code |
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| 122 | * |
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| 123 | * Hydra_Software_Devel/21 5/12/11 12:11p gskerl |
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| 124 | * SW7422-354: Fixed to support APE compilation on 35230 |
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| 125 | * |
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| 126 | * Hydra_Software_Devel/20 5/3/11 7:00p gskerl |
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| 127 | * SW7422-354: First attempt at adding support for the audio return |
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| 128 | * channel |
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| 129 | * |
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| 130 | * Hydra_Software_Devel/19 4/18/11 10:13p gskerl |
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| 131 | * SW7425-364: Added BAPE_Pll_EnableExternalMclk() API to APE, then called |
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| 132 | * it from NEXUS_AudioModule_EnableExternalMclk() |
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| 133 | * |
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| 134 | * Hydra_Software_Devel/18 4/16/11 12:15p jgarrett |
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| 135 | * SW7425-371: Removing tab characters |
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| 136 | * |
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| 137 | * Hydra_Software_Devel/17 4/11/11 5:54p jgarrett |
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| 138 | * SWDTV-6305: Adding ADC/RF Inputs for DTV |
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| 139 | * |
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| 140 | * Hydra_Software_Devel/16 4/6/11 1:24a jgarrett |
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| 141 | * SW35330-35: Merge to main branch |
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| 142 | * |
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| 143 | * Hydra_Software_Devel/SW35330-35/3 4/6/11 11:15a jgarrett |
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| 144 | * SW35330-35: Adding 35233 |
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| 145 | * |
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| 146 | * Hydra_Software_Devel/SW35330-35/2 4/5/11 7:13p jgarrett |
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| 147 | * SW35330-35: PCM Playback working on 35230 |
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| 148 | * |
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| 149 | * Hydra_Software_Devel/SW35330-35/1 4/5/11 12:50p jgarrett |
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| 150 | * SW35330-35: FMM Abstraction refactoring to support DTV |
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| 151 | * |
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| 152 | * Hydra_Software_Devel/15 4/5/11 6:53p gskerl |
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| 153 | * SW7552-28: Updated comment. |
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| 154 | * |
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| 155 | * Hydra_Software_Devel/14 3/24/11 7:55p gskerl |
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| 156 | * SW7422-146: Improved audio reference clock selection logic to handle |
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| 157 | * RDB differences for the 7231 |
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| 158 | * |
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| 159 | * Hydra_Software_Devel/13 3/24/11 10:28a jgarrett |
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| 160 | * SW7422-364: Fixing compilation errors on systems without HDMI or SPDIF |
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| 161 | * input |
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| 162 | * |
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| 163 | * Hydra_Software_Devel/12 3/23/11 11:03a piyushg |
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| 164 | * SW7422-146: Make MAX_HDMI and MAX_SDPIF recvr marcos independent of |
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| 165 | * BCHP_74xx macros |
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| 166 | * |
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| 167 | * Hydra_Software_Devel/11 3/10/11 7:03p jgarrett |
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| 168 | * SW7422-146: Refactored DFIFO code, added support for input capture from |
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| 169 | * compressed/multichannel |
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| 170 | * |
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| 171 | * Hydra_Software_Devel/10 3/9/11 4:47p piyushg |
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| 172 | * SW7422-146: Initial checkin for HDMI and SPDIF inout ports. |
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| 173 | * |
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| 174 | * Hydra_Software_Devel/9 2/28/11 1:55p gskerl |
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| 175 | * SW7422-146: Increased BAPE_CHIP_MAX_DACS from 1 to 2. |
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| 176 | * |
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| 177 | * Hydra_Software_Devel/8 2/28/11 1:28p jgarrett |
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| 178 | * SW7422-146: Filter graph reworked to remove mixer dependencies |
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| 179 | * |
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| 180 | * Hydra_Software_Devel/7 2/28/11 12:22p gskerl |
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| 181 | * SW7422-146: Changed BAPE_CHIP_MAX_RFMODS from 1 to 0 (because the 7422 |
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| 182 | * doesn't have any RF mods). |
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| 183 | * |
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| 184 | * Hydra_Software_Devel/6 2/9/11 5:28p gskerl |
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| 185 | * SW7422-146:Added "#define BAPE_BASE_PLL_TO_FS_RATIO 256" which |
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| 186 | * defines ratio of |
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| 187 | * the PLL's channel 0 frequency to the "base" sample rate. |
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| 188 | * |
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| 189 | * Hydra_Software_Devel/5 2/4/11 12:43p gskerl |
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| 190 | * SW7422-146:Modified the counting of I2S outputs so that it will handle |
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| 191 | * 7422/7425 I2S register names. |
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| 192 | * |
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| 193 | * Hydra_Software_Devel/4 1/19/11 2:58p jgarrett |
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| 194 | * SW7422-146: Initial decode/passthrough of ac3 |
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| 195 | * |
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| 196 | * Hydra_Software_Devel/3 1/6/11 2:33p jgarrett |
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| 197 | * SW7422-146: Adding initial input capture API |
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| 198 | * |
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| 199 | * Hydra_Software_Devel/2 12/17/10 3:58p jgarrett |
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| 200 | * SW7422-146: Nexus APE integration on 7422 |
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| 201 | * |
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| 202 | * Hydra_Software_Devel/1 12/16/10 4:05p jgarrett |
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| 203 | * SW7422-146: Initial compilable APE for 7422 |
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| 204 | ***************************************************************************/ |
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| 205 | |
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| 206 | #ifndef BAPE_CHIP_PRIV_H_ |
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| 207 | #define BAPE_CHIP_PRIV_H_ |
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| 208 | |
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| 209 | #include "bchp_common.h" |
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| 210 | #include "bchp_aud_fmm_bf_ctrl.h" |
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| 211 | #include "bchp_aud_fmm_dp_ctrl0.h" |
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| 212 | #include "bchp_aud_fmm_src_ctrl0.h" |
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| 213 | #if defined BCHP_AUD_FMM_OP_CTRL_REG_START |
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| 214 | /* Older-style RDB only */ |
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| 215 | #include "bchp_aud_fmm_op_ctrl.h" |
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| 216 | #include "bchp_aud_fmm_iop_ctrl.h" |
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| 217 | #endif |
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| 218 | #if defined BCHP_AUD_FMM_OP_MCLKGEN_REG_START |
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| 219 | #include "bchp_aud_fmm_op_mclkgen.h" |
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| 220 | #endif /* defined BCHP_AUD_FMM_OP_MCLKGEN_REG_START */ |
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| 221 | |
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| 222 | #ifdef BCHP_AIO_MISC_REG_START |
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| 223 | #include "bchp_aio_misc.h" |
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| 224 | #include "bchp_aud_fmm_misc.h" |
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| 225 | #else |
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| 226 | #include "bchp_aud_misc.h" |
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| 227 | #endif |
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| 228 | |
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| 229 | #ifdef BCHP_AUD_FMM_IOP_MISC_REG_START |
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| 230 | #include "bchp_aud_fmm_iop_misc.h" |
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| 231 | #endif |
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| 232 | |
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| 233 | #define BAPE_CHIP_MAX_DECODERS (BAPE_CHIP_MAX_SFIFOS) |
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| 234 | #define BAPE_CHIP_MAX_PLAYBACKS (BAPE_CHIP_MAX_SFIFOS) |
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| 235 | #define BAPE_CHIP_MAX_INPUT_CAPTURES (BAPE_CHIP_MAX_DFIFOS) |
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| 236 | #define BAPE_CHIP_MAX_DSP_MIXERS (1) /* Allow 1 DSP mixer */ |
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| 237 | #define BAPE_CHIP_MAX_DSP_TASKS (3+BAPE_CHIP_MAX_DSP_MIXERS) /* 3 decoders + 1 FW Mixer */ |
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| 238 | |
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| 239 | /* Max STCs */ |
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| 240 | #ifdef BCHP_AUD_FMM_MISC_STC_UPPERi_ARRAY_END |
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| 241 | /* Legacy RDB */ |
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| 242 | #define BAPE_CHIP_MAX_STCS (BCHP_AUD_FMM_MISC_STC_UPPERi_ARRAY_END) |
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| 243 | #ifdef BCHP_AUD_FMM_MISC_STC_LOWERi_ARRAY_BASE |
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| 244 | #define BAPE_CHIP_GET_STC_ADDRESS(idx) (BCHP_AUD_FMM_MISC_STC_LOWERi_ARRAY_BASE + ((BCHP_AUD_FMM_MISC_STC_LOWERi_ARRAY_ELEMENT_SIZE/8)*(idx))) |
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| 245 | #else |
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| 246 | #define BAPE_CHIP_GET_STC_ADDRESS(idx) (BCHP_AUD_FMM_MISC_STC_UPPERi_ARRAY_BASE + ((BCHP_AUD_FMM_MISC_STC_UPPERi_ARRAY_ELEMENT_SIZE/8)*(idx))) |
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| 247 | #endif |
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| 248 | #else |
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| 249 | /* 7429 style RDB */ |
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| 250 | #define BAPE_CHIP_MAX_STCS (BCHP_AUD_MISC_STC_UPPERi_ARRAY_END) |
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| 251 | |
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| 252 | #ifdef BCHP_AUD_MISC_STC_LOWERi_ARRAY_BASE |
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| 253 | #define BAPE_CHIP_GET_STC_ADDRESS(idx) (BCHP_AUD_MISC_STC_LOWERi_ARRAY_BASE + ((BCHP_AUD_MISC_STC_LOWERi_ARRAY_ELEMENT_SIZE/8)*(idx))) |
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| 254 | #else |
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| 255 | #define BAPE_CHIP_GET_STC_ADDRESS(idx) (BCHP_AUD_MISC_STC_UPPERi_ARRAY_BASE + ((BCHP_AUD_MISC_STC_UPPERi_ARRAY_ELEMENT_SIZE/8)*(idx))) |
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| 256 | #endif |
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| 257 | #endif |
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| 258 | |
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| 259 | /* Check for DACs */ |
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| 260 | #if defined BCHP_HIFIDAC_CTRL2_REG_START || defined BCHP_HIFIDAC_CTRL_2_REG_START |
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| 261 | #define BAPE_CHIP_MAX_DACS (3) |
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| 262 | #elif defined BCHP_HIFIDAC_CTRL1_REG_START || defined BCHP_HIFIDAC_CTRL_1_REG_START |
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| 263 | #define BAPE_CHIP_MAX_DACS (2) |
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| 264 | #elif defined BCHP_HIFIDAC_CTRL0_REG_START || defined BCHP_HIFIDAC_CTRL_0_REG_START |
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| 265 | #define BAPE_CHIP_MAX_DACS (1) |
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| 266 | #endif |
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| 267 | |
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| 268 | /* Check for the number of I2S outputs... */ |
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| 269 | #if defined BCHP_AUD_FMM_OP_CTRL_I2SS1_CFG || defined BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_START |
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| 270 | #define BAPE_CHIP_MAX_I2S_OUTPUTS (2) |
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| 271 | #elif defined BCHP_AUD_FMM_OP_CTRL_I2SS0_CFG || defined BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START |
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| 272 | #define BAPE_CHIP_MAX_I2S_OUTPUTS (1) |
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| 273 | /* There must not be any I2S outputs */ |
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| 274 | #else |
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| 275 | #define BAPE_CHIP_MAX_I2S_OUTPUTS (0) |
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| 276 | #endif |
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| 277 | |
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| 278 | /* Check for I2S Multi Outputs */ |
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| 279 | #define BAPE_CHIP_MAX_I2S_MULTI_OUTPUTS (0) |
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| 280 | |
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| 281 | /* Check for I2S Inputs */ |
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| 282 | #if defined BCHP_AUD_FMM_IOP_CTRL_I2SIN_CFG1 || defined BCHP_AUD_FMM_IOP_IN_I2S_STEREO_1_REG_START |
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| 283 | #define BAPE_CHIP_MAX_I2S_INPUTS (2) |
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| 284 | #elif defined BCHP_AUD_FMM_IOP_CTRL_I2SIN_CFG0 || defined BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START |
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| 285 | #define BAPE_CHIP_MAX_I2S_INPUTS (1) |
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| 286 | #else |
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| 287 | #define BAPE_CHIP_MAX_I2S_INPUTS (0) |
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| 288 | #endif |
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| 289 | |
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| 290 | /* MAI Inputs */ |
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| 291 | #if defined BCHP_HDMI_RCVR_CTRL_REG_START |
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| 292 | #define BAPE_CHIP_MAX_MAI_INPUTS (1) |
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| 293 | #define BAPE_CHIP_MAI_INPUT_TYPE_IS_LEGACY 1 /* 1=>true: This is a Legacy (7422/7425) type of MAI/HDMI input */ |
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| 294 | #elif defined BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START |
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| 295 | #define BAPE_CHIP_MAX_MAI_INPUTS (1) |
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| 296 | #define BAPE_CHIP_MAI_INPUT_TYPE_IS_IOPIN 1 /* 1=>true: This is a newer (IOP IN) (7429) type of MAI/HDMI input */ |
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| 297 | #endif |
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| 298 | |
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| 299 | /* SPDIF Inputs */ |
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| 300 | #if defined BCHP_SPDIF_RCVR_CTRL_REG_START |
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| 301 | #define BAPE_CHIP_MAX_SPDIF_INPUTS (1) |
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| 302 | #define BAPE_CHIP_SPDIF_INPUT_TYPE_IS_LEGACY 1 /* 1=>true: This is a Legacy (7422/7425) type of SPDIF input */ |
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| 303 | #elif defined BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START |
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| 304 | #define BAPE_CHIP_MAX_SPDIF_INPUTS (1) |
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| 305 | #define BAPE_CHIP_SPDIF_INPUT_TYPE_IS_IOPIN 1 /* 1=>true: This is a newer (IOP IN) (7429) type of SPDIF input */ |
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| 306 | #endif |
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| 307 | |
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| 308 | #if defined BCHP_RFM_SYSCLK_REG_START |
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| 309 | #define BAPE_CHIP_MAX_RFMODS (1) |
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| 310 | #else |
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| 311 | #define BAPE_CHIP_MAX_RFMODS (0) |
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| 312 | #endif |
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| 313 | |
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| 314 | #if defined BCHP_AUD_FMM_OP_CTRL_SPDIF_CFG_0 || defined BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START |
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| 315 | #define BAPE_CHIP_MAX_SPDIF_OUTPUTS (1) |
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| 316 | #endif |
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| 317 | |
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| 318 | #if defined BCHP_AUD_FMM_OP_CTRL_MAI_FORMAT || defined BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START |
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| 319 | #define BAPE_CHIP_MAX_MAI_OUTPUTS (1) |
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| 320 | #endif |
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| 321 | |
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| 322 | #if defined BCHP_AUD_FMM_MISC_SEROUT_SEL_SPDIF_OUT_1_ENABLE_MASK || defined BCHP_AUD_MISC_SEROUT_SEL_HDMI_RX_ARC_ENABLE_MASK |
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| 323 | #define BAPE_CHIP_MAX_AUDIO_RETURN_CHANNELS (1) |
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| 324 | #endif |
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| 325 | |
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| 326 | #define BAPE_CHIP_MAX_OUTPUT_CAPTURES (BAPE_CHIP_MAX_LOOPBACKS) |
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| 327 | |
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| 328 | /* PLL Details */ |
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| 329 | #if defined BCHP_AUD_FMM_PLL2_REG_START || defined BCHP_AUD_FMM_IOP_PLL_2_REG_START |
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| 330 | #define BAPE_CHIP_MAX_PLLS (3) |
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| 331 | #elif defined BCHP_AUD_FMM_PLL1_REG_START || defined BCHP_AUD_FMM_IOP_PLL_1_REG_START |
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| 332 | #define BAPE_CHIP_MAX_PLLS (2) |
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| 333 | #elif defined BCHP_AUD_FMM_PLL0_REG_START || defined BCHP_AUD_FMM_IOP_PLL_0_REG_START |
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| 334 | #define BAPE_CHIP_MAX_PLLS (1) |
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| 335 | #else |
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| 336 | /* No PLLs */ |
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| 337 | #define BAPE_CHIP_MAX_PLLS (0) |
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| 338 | #endif |
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| 339 | |
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| 340 | /* NCO Details */ |
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| 341 | #if defined BCHP_AUD_FMM_OP_MCLKGEN_MCLK_GEN_2_CONTROL || defined BCHP_AUD_FMM_IOP_NCO_2_REG_START |
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| 342 | #define BAPE_CHIP_MAX_NCOS (3) |
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| 343 | #elif defined BCHP_AUD_FMM_OP_MCLKGEN_MCLK_GEN_1_CONTROL || defined BCHP_AUD_FMM_IOP_NCO_1_REG_START |
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| 344 | #define BAPE_CHIP_MAX_NCOS (2) |
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| 345 | #elif defined BCHP_AUD_FMM_OP_MCLKGEN_MCLK_GEN_0_CONTROL || defined BCHP_AUD_FMM_IOP_NCO_0_REG_START |
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| 346 | #define BAPE_CHIP_MAX_NCOS (1) |
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| 347 | #else |
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| 348 | /* No NCOs */ |
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| 349 | #endif |
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| 350 | |
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| 351 | #define BAPE_BASE_PLL_TO_FS_RATIO 256 /* PLL channel 0 runs at 256 * "base" Fs */ |
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| 352 | |
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| 353 | /* SFIFO Details */ |
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| 354 | #define BAPE_CHIP_MAX_SFIFOS (BCHP_AUD_FMM_BF_CTRL_SOURCECH_CFGi_ARRAY_END+1) |
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| 355 | |
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| 356 | /* DFIFO Details */ |
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| 357 | #ifdef BCHP_AUD_FMM_BF_CTRL_DESTCH_CFG0 |
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| 358 | #define BAPE_CHIP_MAX_DFIFOS (1) /* Required because the RDB defs change with only one channel */ |
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| 359 | #else |
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| 360 | #define BAPE_CHIP_MAX_DFIFOS (BCHP_AUD_FMM_BF_CTRL_DESTCH_CFGi_ARRAY_END+1) |
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| 361 | #endif |
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| 362 | #if defined(BCHP_AUD_FMM_BF_CTRL_DESTCH_CFG0_CAPTURE_MODE_SHIFT) || defined(BCHP_AUD_FMM_BF_CTRL_DESTCH_CFGi_CAPTURE_MODE_SHIFT) |
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| 363 | #define BAPE_CHIP_DFIFO_SUPPORTS_16BIT_CAPTURE 1 |
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| 364 | #endif |
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| 365 | |
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| 366 | /* SRC Details */ |
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| 367 | #define BAPE_CHIP_MAX_SRCS (BCHP_AUD_FMM_SRC_CTRL0_STRM_CFGi_ARRAY_END+1) |
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| 368 | |
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| 369 | #if defined BCHP_AUD_FMM_SRC_CTRL0_COEFFi_ARRAY_BASE |
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| 370 | #define BAPE_CHIP_SRC_TYPE_IS_IIR 1 /* 1=>true: This is an IIR-type of SRC */ |
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| 371 | #if BCHP_AUD_FMM_SRC_CTRL0_COEFFi_ARRAY_END == 487 |
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| 372 | /* SRC Coefficient Memory */ |
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| 373 | #define BAPE_CHIP_P_SRC_IIR_CHUNK_BASE 0 |
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| 374 | #define BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS 11 |
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| 375 | #define BAPE_CHIP_P_SRC_IIR_CHUNK_END (BAPE_CHIP_P_SRC_IIR_CHUNK_BASE + BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS - 1) |
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| 376 | #define BAPE_CHIP_P_MAX_IIR_FILTERS_PER_SRC 8 |
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| 377 | #define BAPE_CHIP_P_MAX_IIR_COEFF_PER_SRC (5 * BAPE_CHIP_P_MAX_IIR_FILTERS_PER_SRC) |
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| 378 | #define BAPE_CHIP_P_MAX_SRC_IIR_COEFF_PER_CHUNK BAPE_CHIP_P_MAX_IIR_COEFF_PER_SRC |
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| 379 | #define BAPE_CHIP_P_TOTAL_SRC_IIR_COEFF (BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS * BAPE_CHIP_P_MAX_SRC_IIR_COEFF_PER_CHUNK) |
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| 380 | |
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| 381 | #define BAPE_CHIP_P_SRC_LIN_CHUNK_BASE (BAPE_CHIP_P_SRC_IIR_CHUNK_END + 1) |
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| 382 | #define BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS 16 |
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| 383 | #define BAPE_CHIP_P_SRC_LIN_CHUNK_END (BAPE_CHIP_P_SRC_LIN_CHUNK_BASE + BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS - 1) |
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| 384 | #define BAPE_CHIP_P_NUM_LIN_COEFF_PER_SRC 3 |
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| 385 | #define BAPE_CHIP_P_NUM_LIN_COEFF_PER_CHUNK BAPE_CHIP_P_NUM_LIN_COEFF_PER_SRC |
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| 386 | #define BAPE_CHIP_P_TOTAL_LIN_COEFF (BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS * BAPE_CHIP_P_NUM_LIN_COEFF_PER_CHUNK) |
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| 387 | #define BAPE_CHIP_MAX_SRC_COEFF_CHUNKS (BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS + BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS) |
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| 388 | |
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| 389 | #elif BCHP_AUD_FMM_SRC_CTRL0_COEFFi_ARRAY_END == 231 |
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| 390 | #define BAPE_CHIP_P_SRC_IIR_CHUNK_BASE 0 |
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| 391 | #define BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS 4 |
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| 392 | #define BAPE_CHIP_P_SRC_IIR_CHUNK_END (BAPE_CHIP_P_SRC_IIR_CHUNK_BASE + BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS - 1) |
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| 393 | #define BAPE_CHIP_P_MAX_IIR_FILTERS_PER_SRC 8 |
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| 394 | #define BAPE_CHIP_P_MAX_IIR_COEFF_PER_SRC (5 * BAPE_CHIP_P_MAX_IIR_FILTERS_PER_SRC) |
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| 395 | #define BAPE_CHIP_P_MAX_SRC_IIR_COEFF_PER_CHUNK BAPE_CHIP_P_MAX_IIR_COEFF_PER_SRC |
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| 396 | #define BAPE_CHIP_P_TOTAL_SRC_IIR_COEFF (BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS * BAPE_CHIP_P_MAX_SRC_IIR_COEFF_PER_CHUNK) |
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| 397 | |
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| 398 | #define BAPE_CHIP_P_SRC_LIN_CHUNK_BASE (BAPE_CHIP_P_SRC_IIR_CHUNK_END + 1) |
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| 399 | #define BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS 16 |
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| 400 | #define BAPE_CHIP_P_SRC_LIN_CHUNK_END (BAPE_CHIP_P_SRC_LIN_CHUNK_BASE + BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS - 1) |
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| 401 | #define BAPE_CHIP_P_NUM_LIN_COEFF_PER_SRC 3 |
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| 402 | #define BAPE_CHIP_P_NUM_LIN_COEFF_PER_CHUNK BAPE_CHIP_P_NUM_LIN_COEFF_PER_SRC |
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| 403 | #define BAPE_CHIP_P_TOTAL_LIN_COEFF (BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS * BAPE_CHIP_P_NUM_LIN_COEFF_PER_CHUNK) |
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| 404 | #define BAPE_CHIP_MAX_SRC_COEFF_CHUNKS (BAPE_CHIP_P_MAX_SRC_IIR_CHUNKS + BAPE_CHIP_P_MAX_SRC_LIN_CHUNKS) |
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| 405 | #else |
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| 406 | #error unsupported number of SRC coefficients |
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| 407 | #endif |
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| 408 | #elif defined BCHP_AUD_FMM_SRC_CTRL0_COEFF2X_i_ARRAY_BASE |
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| 409 | #define BAPE_CHIP_SRC_TYPE_IS_LEGACY 1 /* 1=>true: This is an legacy type of SRC */ |
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| 410 | #else |
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| 411 | #error "Unknown Sample Rate Converter type" |
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| 412 | #endif |
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| 413 | |
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| 414 | /* Mixer Details */ |
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| 415 | #if BCHP_CHIP == 7408 |
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| 416 | #define BAPE_CHIP_MAX_MIXERS (6) /* On the 7408, this is 6, others have more -- This must match the HW for coefficient loading. */ |
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| 417 | #define BAPE_CHIP_MAX_MIXER_INPUTS (4) /* On the 7408, only four inputs are supported per mixer. Most other chips is 8. */ |
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| 418 | #else |
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| 419 | #if defined BCHP_AUD_FMM_DP_CTRL0_MIXER_CONFIGi_ARRAY_END |
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| 420 | /* 7429-style chips define both of these using RDB arrays */ |
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| 421 | #define BAPE_CHIP_MAX_MIXERS (BCHP_AUD_FMM_DP_CTRL0_MIXER_CONFIGi_ARRAY_END+1) |
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| 422 | #define BAPE_CHIP_MAX_MIXER_INPUTS (BCHP_AUD_FMM_DP_CTRL0_MIXER0_INPUT_CONFIGi_ARRAY_END+1) |
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| 423 | #elif defined BCHP_AUD_FMM_DP_CTRL0_MIXER11_CONFIG |
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| 424 | /* 7425-style mixer block */ |
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| 425 | #define BAPE_CHIP_MAX_MIXERS (12) |
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| 426 | #define BAPE_CHIP_MAX_MIXER_INPUTS (8) |
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| 427 | #else |
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| 428 | /* Legacy 8-mixer block */ |
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| 429 | #define BAPE_CHIP_MAX_MIXERS (8) |
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| 430 | #define BAPE_CHIP_MAX_MIXER_INPUTS (8) |
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| 431 | #endif |
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| 432 | #endif |
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| 433 | #define BAPE_CHIP_MAX_MIXER_OUTPUTS (2) |
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| 434 | #define BAPE_CHIP_MAX_MIXER_PLAYBACKS (1+BCHP_AUD_FMM_DP_CTRL0_PB_FCI_IDi_ARRAY_END-BCHP_AUD_FMM_DP_CTRL0_PB_FCI_IDi_ARRAY_START) |
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| 435 | |
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| 436 | /* Dummysinks */ |
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| 437 | #ifdef BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START |
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| 438 | #include "bchp_aud_fmm_iop_dummysink_0.h" |
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| 439 | #define BAPE_CHIP_MAX_DUMMYSINKS (BCHP_AUD_FMM_IOP_DUMMYSINK_0_STREAM_CFG_0_i_ARRAY_END+1) |
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| 440 | #else |
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| 441 | #define BAPE_CHIP_MAX_DUMMYSINKS (4) |
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| 442 | #endif |
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| 443 | |
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| 444 | /* Loopbacks */ |
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| 445 | #if BCHP_AUD_FMM_IOP_CTRL_LOOPBACK_CFG0 |
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| 446 | #define BAPE_CHIP_MAX_LOOPBACKS (1) /* On the 7408, this is 1, others have more */ |
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| 447 | #elif defined BCHP_AUD_FMM_IOP_CTRL_LOOPBACK_CFG |
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| 448 | #define BAPE_CHIP_MAX_LOOPBACKS (4) |
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| 449 | #elif defined BCHP_AUD_FMM_IOP_CTRL_LOOPBACK_CFGi_ARRAY_END |
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| 450 | #define BAPE_CHIP_MAX_LOOPBACKS (BCHP_AUD_FMM_IOP_CTRL_LOOPBACK_CFGi_ARRAY_END+1) |
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| 451 | #elif defined BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START |
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| 452 | #include "bchp_aud_fmm_iop_loopback_0.h" |
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| 453 | #define BAPE_CHIP_MAX_LOOPBACKS (BCHP_AUD_FMM_IOP_LOOPBACK_0_STREAM_CFG_i_ARRAY_END+1) |
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| 454 | #endif |
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| 455 | |
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| 456 | #ifdef BCHP_AUD_FMM_OP_CTRL_MCLK_CFG_FSi_ARRAY_END |
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| 457 | /* FS Timing Sources */ |
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| 458 | #define BAPE_CHIP_MAX_FS (BCHP_AUD_FMM_OP_CTRL_MCLK_CFG_FSi_ARRAY_END+1) |
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| 459 | #endif |
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| 460 | |
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| 461 | /* External MCLK Outputs */ |
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| 462 | #if defined BCHP_AUD_FMM_OP_CTRL_MCLK_CFG_EXTi_ARRAY_END |
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| 463 | #define BAPE_CHIP_MAX_EXT_MCLKS (BCHP_AUD_FMM_OP_CTRL_MCLK_CFG_EXTi_ARRAY_END+1) |
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| 464 | #elif defined BCHP_AUD_FMM_IOP_MISC_MCLK_CFG_i_ARRAY_END |
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| 465 | #define BAPE_CHIP_MAX_EXT_MCLKS (BCHP_AUD_FMM_IOP_MISC_MCLK_CFG_i_ARRAY_END+1) |
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| 466 | #endif |
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| 467 | |
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| 468 | #define BAPE_CHIP_MAX_OUTPUT_PORTS (BCHP_SHIFT(AUD_FMM_OP_CTRL_ENABLE_STATUS, reserved0)) /* Total output ports */ |
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| 469 | |
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| 470 | #if defined BCHP_AUD_FMM_BF_CTRL_ADAPTRATE_CFGi_ARRAY_END |
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| 471 | #define BAPE_CHIP_MAX_ADAPTRATE_CONTROLLERS (BCHP_AUD_FMM_BF_CTRL_ADAPTRATE_CFGi_ARRAY_END+1) |
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| 472 | #elif defined BCHP_AUD_FMM_BF_CTRL_ADAPTRATE_7_CFG |
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| 473 | #define BAPE_CHIP_MAX_ADAPTRATE_CONTROLLERS (8) /* New chips provide 8 controllers */ |
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| 474 | #else |
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| 475 | #define BAPE_CHIP_MAX_ADAPTRATE_CONTROLLERS (4) /* Legacy chips only provided 4 controllers */ |
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| 476 | #endif |
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| 477 | |
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| 478 | #ifdef BCHP_AUD_FMM_IOP_CTRL_REG_START |
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| 479 | #define BAPE_CHIP_MAX_IOP_STREAMS (BAPE_CHIP_MAX_OUTPUT_PORTS + BAPE_CHIP_MAX_LOOPBACKS + BAPE_CHIP_MAX_DUMMYSINKS) |
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| 480 | #else |
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| 481 | /* The "stream" concept went away on newer chips like 7429 */ |
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| 482 | #define BAPE_CHIP_MAX_IOP_STREAMS 0 |
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| 483 | #endif |
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| 484 | |
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| 485 | #define BAPE_CHIP_DEFAULT_NUM_COMPRESSED_BUFFERS (2) /* For AC3+ passthrough we need one for SPDIF out (AC3) and one for HDMI (AC3+) */ |
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| 486 | #define BAPE_CHIP_DEFAULT_NUM_PCM_BUFFERS (4) /* 5.1 + one stereo */ |
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| 487 | #define BAPE_CHIP_MAX_PATH_DELAY (128) |
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| 488 | #define BAPE_CHIP_BYTES_PER_PCM_SAMPLE (4) |
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| 489 | #define BAPE_CHIP_BYTES_PER_PCM_SAMPLE_PAIR (2*BAPE_CHIP_BYTES_PER_PCM_SAMPLE) |
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| 490 | #define BAPE_CHIP_BYTES_PER_COMPRESSED_SAMPLE (2) |
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| 491 | #define BAPE_CHIP_INTERLEAVE_DSP_SAMPLES (0) |
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| 492 | |
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| 493 | #define BAPE_CHIP_MAX_SFIFO_GROUPS (BAPE_CHIP_MAX_SFIFOS) |
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| 494 | #define BAPE_CHIP_MAX_DFIFO_GROUPS (BAPE_CHIP_MAX_DFIFOS) |
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| 495 | #define BAPE_CHIP_MAX_SRC_GROUPS (BAPE_CHIP_MAX_SRCS) |
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| 496 | #define BAPE_CHIP_MAX_MIXER_GROUPS (BAPE_CHIP_MAX_MIXERS) |
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| 497 | #define BAPE_CHIP_MAX_LOOPBACK_GROUPS (BAPE_CHIP_MAX_LOOPBACKS) |
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| 498 | #define BAPE_CHIP_MAX_DUMMYSINK_GROUPS (BAPE_CHIP_MAX_DUMMYSINKS) |
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| 499 | |
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| 500 | /* And finally, here are some things that aren't in the RDB */ |
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| 501 | |
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| 502 | /* Define values for the PLL_AUDIO<n>_REFERENCE_CLOCK fields of the |
|---|
| 503 | * CLKGEN_INTERNAL_MUX_SELECT register |
|---|
| 504 | */ |
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| 505 | #ifdef BCHP_CLKGEN_INTERNAL_MUX_SELECT |
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| 506 | #if (BCHP_CHIP==7231 && BCHP_VER == BCHP_VER_A0) |
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| 507 | #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_Fixed 1 |
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| 508 | #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_Vcxo0 0 |
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| 509 | #else /* for others (7422, 7425, 7344, 7346, 7358) */ |
|---|
| 510 | #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_Fixed 0 |
|---|
| 511 | #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_Vcxo0 1 |
|---|
| 512 | #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_Vcxo1 2 |
|---|
| 513 | #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_Vcxo2 3 |
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| 514 | #endif |
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| 515 | #endif |
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| 516 | |
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| 517 | #endif /* #ifndef BAPE_CHIP_PRIV_H_ */ |
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| 518 | |
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