source: svn/newcon3bcm2_21bu/magnum/portinginterface/dma/7552/bdma_mem_priv.h

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1/***************************************************************************
2 *     Copyright (c) 2003-2011, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bdma_mem_priv.h $
11 * $brcm_Revision: Hydra_Software_Devel/7 $
12 * $brcm_Date: 5/2/11 1:30p $
13 *
14 * Module Description:
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/portinginterface/dma/7400/bdma_mem_priv.h $
19 *
20 * Hydra_Software_Devel/7   5/2/11 1:30p vanessah
21 * SWDTV-6186: 35233 DMA support
22 *
23 * Hydra_Software_Devel/6   3/21/11 6:47p vanessah
24 * SW7420-1431: Large descriptor list subset support
25 *
26 * Hydra_Software_Devel/5   1/18/11 4:54p cdisc
27 * SW35125-56: adding 35125 BCHP precompile lines and removing 35125 stub
28 * functions
29 *
30 * Hydra_Software_Devel/4   6/18/10 2:43p cdisc
31 * SW35230-352: M2M and partial key ladder support (adjusting
32 * BDMA_P_MEM_KEY_SIZE for 35230 only)
33 *
34 * Hydra_Software_Devel/3   10/3/08 5:29p syang
35 * PR 34606: support 41 key slots for 7405 B0
36 *
37 * Hydra_Software_Devel/2   7/11/08 3:45p syang
38 * PR 43729:  rm code for old crypto hw arch
39 *
40 * Hydra_Software_Devel/1   7/11/08 1:15p syang
41 * PR 43729: break from the old 7038
42 *
43 * Hydra_Software_Devel/28   12/7/07 6:55p syang
44 * PR 34606:  fix compile warning
45 *
46 * Hydra_Software_Devel/27   12/7/07 6:38p syang
47 * PR 34606: move SetCrypto to Tran level from Engine level for better
48 * sharing by threads of the same progress
49 *
50 * Hydra_Software_Devel/26   12/7/07 4:09p syang
51 * PR 34606: rewrite more than half of code to support hw sharing for
52 * kernel and user-mode sides
53 *
54 * Hydra_Software_Devel/25   10/15/07 3:37p syang
55 * PR 35947: add "_isr" to call back func name
56 *
57 * Hydra_Software_Devel/24   3/19/07 4:18p syang
58 * PR 28171: prepare to add sharf support
59 *
60 * Hydra_Software_Devel/23   3/16/07 3:22p syang
61 * PR 28173: add scatter-gather support
62 *
63 * Hydra_Software_Devel/22   3/16/07 12:50p syang
64 * PR 28173: add dynamic link support (not turn on yet)
65 *
66 * Hydra_Software_Devel/20   3/7/07 4:26p tdo
67 * PR 26224:  Add support for 2nd MEM DMA for 7400B0
68 *
69 * Hydra_Software_Devel/19   2/5/07 4:42p syang
70 * PR 23354: allow mem addr in mem_1; cleanup cip specific code section
71 * macro usage
72 *
73 * Hydra_Software_Devel/18   1/18/07 4:01p syang
74 * PR 16059: update BDMA_P_MEM_ADDR_MASK for 7401 according to request
75 * from Michael Phillips
76 *
77 * Hydra_Software_Devel/17   1/8/07 12:53p tdo
78 * PR 26224:  Add second DMA MEM engine support for 7400 B0
79 *
80 * Hydra_Software_Devel/16   10/3/06 4:00p syang
81 * PR 24634: replace critical section with private mutex for
82 * mem/pci_dma_handle create/destroy.
83 *
84 * Hydra_Software_Devel/15   3/23/06 12:42p syang
85 * PR 19670: added support for 7438
86 *
87 * Hydra_Software_Devel/14   2/3/06 4:51p syang
88 * PR 19425: allow mem addr bigger than (1<<28)
89 *
90 * Hydra_Software_Devel/13   7/14/05 5:11p syang
91 * PR 16059: updated 7401 crypto configure
92 *
93 * Hydra_Software_Devel/12   7/8/05 3:48p nissen
94 * PR 15575: Added BDMA_Mem_Transfer() entry point function to do memory
95 * transfers with less function call overhead.
96 *
97 * Hydra_Software_Devel/11   5/18/05 9:51p nissen
98 * PR 14516: Added support for setting ENC_DEC_INIT and removed word
99 * alignment check of TRANSFER_SIZE.
100 *
101 * Hydra_Software_Devel/10   5/18/05 9:07p nissen
102 * PR 15312: Added support for big endian memory transfers.
103 *
104 * Hydra_Software_Devel/9   5/24/04 5:59p jasonh
105 * PR 11189: Merge down from B0 to main-line
106 *
107 * Hydra_Software_Devel/Refsw_Devel_7038_B0/1   5/6/04 2:23p syang
108 * PR 10685:  In order to support new crypt features of B0, changed DesSel
109 * to CryptAlg,  expanded Key sel, added MODE_SEL and ENC_DEC_INIT
110 * setting (changed to use mode 1, mode 0 is not used again),
111 *
112 * Hydra_Software_Devel/8   2/4/04 3:01p syang
113 * PR 9608: 1). added init for hMemDma / hPciDma of Channel, hDma of
114 * MemDma / PciDma and hChannel of Queue; 2). split CallBackFunc type def
115 * to mem and pci versions; 3). fixed typo in TranHandle def; 4).leave
116 * critical section before calling BINT func; 5). fixed a bug with
117 * nextDesc in Desc info setting; 6). use wake to start dma as in sleep
118 * mode; 7). corrected typo in the asserts of Queue_CreateTran.
119 *
120 * Hydra_Software_Devel/7   10/23/03 6:17p syang
121 * to make linux comipler silent
122 *
123 * Hydra_Software_Devel/6   10/23/03 4:20p syang
124 * adjusted sub-module implementaion overview
125 *
126 * Hydra_Software_Devel/5   10/23/03 3:15p syang
127 * added real pci dma implementation
128 *
129 * Hydra_Software_Devel/4   10/23/03 11:07a syang
130 * first time checking after resolving comipling errors
131 *
132 * Hydra_Software_Devel/3   10/15/03 3:04p syang
133 * updated to use TranHandle, rather than TranId
134 *
135 * Hydra_Software_Devel/2   10/10/03 4:10p syang
136 * updated BDMA_Mem_Context
137 *
138 * Hydra_Software_Devel/1   9/25/03 6:44p syang
139 * init version, from scratch
140 *
141 ***************************************************************************/
142#ifndef BDMA_MEM_PRIV_H__
143#define BDMA_MEM_PRIV_H__
144
145#include "bdma_priv.h"
146#include "bdma_queue.h"
147#ifdef BDMA_P_SUPPORT_SHARF_DMA_ENGINE
148#include "bdma_mem_sharf_priv.h"
149#endif
150
151#ifdef __cplusplus
152extern "C" {
153#endif
154
155
156/***************************************************************************
157 * {private}
158
159 * Implementation Overview:
160 *
161 * The implementation uses a private queue module, to manage the active
162 * transfers. The queue module is shared by both memory DMA and PCI DMA.
163 * It manages the queue entry assigning, freeing, and the transfer status.
164 * Refer to queue module overview for more info.
165 *
166 * Memory DMA sub-module code should never refer to the member of queue
167 * module directly, however it needs to know the def of struct
168 * BDMA_P_QueueEntry.
169 *
170 * By abstracting out the queue module, the readabilty, maintainabilty, and
171 * extendabilty (such as to IO DMA) are much improved. Code size is also
172 * improved.
173 ****************************************************************************/
174
175#define BDMA_P_MEM_GET_CONTEXT(handle, context) \
176        BDMA_P_GENERIC_GET_CONTEXT((handle), (context), BDMA_P_Mem_Context)
177
178#define BDMA_P_MEM_SET_BLACK_MAGIC(handle) \
179        BDMA_P_GENERIC_SET_BLACK_MAGIC((handle), BDMA_P_Mem_Context)
180
181#define BDMA_P_MEM_DESTROY_CONTEXT(struct_ptr) \
182        BDMA_P_GENERIC_DESTROY_CONTEXT(struct_ptr, BDMA_P_Mem_Context) 
183
184#if (BDMA_P_SUPPORT_MEM_DMA_41_KEY_SLOTS)
185#define BDMA_P_MEM_KEY_SLOT_MAX               41
186#else
187#define BDMA_P_MEM_KEY_SLOT_MAX               15
188#endif 
189
190#if ((BCHP_CHIP == 35230) || (BCHP_CHIP == 35125) || (BCHP_CHIP == 35233))
191#define BDMA_P_MEM_KEY_SIZE                   8
192#else
193#define BDMA_P_MEM_KEY_SIZE                   6
194#endif
195
196#define BDMA_P_MEM_MAX_BLOCK_SIZE             (0x1000000 -1)  /* 16 MBytes */   
197       
198/***************************************************************************
199 * Memory Tran Handle
200 */
201typedef struct BDMA_P_Mem_TranContext
202{
203        BDMA_P_QueueEntry  QueueEntry;
204       
205} BDMA_P_Mem_TranContext;
206
207
208/***************************************************************************
209 * Memory Dma Context
210 */
211typedef struct BDMA_P_Mem_Context
212{
213        uint32_t   ulBlackMagic;   /* Black magic for handle validation */
214
215        /* created from this handle */
216        BDMA_Handle    hDma;
217
218        /* engine id */
219        BDMA_MemDmaEngine eEngine;
220
221        /* register offset */
222        uint32_t       ulRegOffset;
223
224        /* configures */
225        BDMA_Endian     eReadEndian;/* endian read mode */
226        BDMA_SwapMode   eSwapMode;  /* swap mode */
227        BDMA_CryptMode  eCryptMode;
228        uint32_t        ulKeySlot;
229        bool            bSgEnable;
230        bool            bCryptoSetInEngine;
231        bool            bCryptoSetInTran;
232       
233        /* tran entry queue */
234        BDMA_P_QueueHandle  hQueue;
235       
236        /* interrupt call back handle */
237        BINT_CallbackHandle  hCallBack; 
238
239#ifdef BDMA_P_SUPPORT_SHARF_DMA_ENGINE
240        BDMA_P_Mem_Sharf_Handle  hSharf;
241#endif
242       
243} BDMA_P_Mem_Context;
244
245
246/***************************************************************************
247 *
248 * Utility functions used by BDMA
249 *
250 ***************************************************************************/
251/*--------------------------------------------------------------------------
252 * To be called by BDMA API func before taking real action, to get dma mutex
253 * WITH block, ideally for user mode
254 */
255BERR_Code BDMA_P_Mem_AcquireMutex(
256        BDMA_Mem_Handle          hMemDma,
257        BKNI_MutexHandle        *phMutex );
258
259
260/***************************************************************************
261 *
262 * API support functions
263 *
264 ***************************************************************************/
265
266/*--------------------------------------------------------------------------
267 */
268BERR_Code BDMA_P_Mem_GetMemDmaPtrFromTran_isr(
269        BDMA_P_QueueEntry *    pTran,
270        BDMA_P_Mem_Context **  ppMemDma );
271
272/***************************************************************************
273 *
274 */
275BERR_Code BDMA_P_Mem_Init(
276        BDMA_P_Mem_Context  * pMemDma,
277        const BDMA_Mem_Settings *pSettings,
278        uint32_t              ulL2IntrBintId );
279
280/***************************************************************************
281 *
282 */
283BERR_Code BDMA_P_Mem_UnInit(
284        BDMA_P_Mem_Context  * pMemDma );
285
286/***************************************************************************
287 *
288 */
289BERR_Code BDMA_P_Mem_Create(
290        BDMA_Handle           hDma,
291        BDMA_MemDmaEngine     eEngine,
292        const BDMA_Mem_Settings *pSettings,
293        BDMA_Mem_Handle *     phMemDma );
294
295/***************************************************************************
296 *
297 */
298BERR_Code BDMA_P_Mem_Destroy(
299        BDMA_Mem_Handle          hMemDma );
300
301/***************************************************************************
302 *
303 */
304BERR_Code BDMA_P_Mem_SetSwapMode_isr(
305        BDMA_Mem_Handle          hMemDma,
306        BDMA_SwapMode            eSwapMode );
307
308/***************************************************************************
309 *
310 */
311BERR_Code BDMA_P_Mem_SetByteSwapMode_isr(
312        BDMA_Mem_Handle          hMemDma,
313        BDMA_Endian              eReadEndian,
314        BDMA_SwapMode            eSwapMode );
315
316BERR_Code BDMA_P_Mem_Tran_SetCrypto_isr(
317        BDMA_Mem_Tran_Handle     hTran,
318        BDMA_CryptMode           eCryptMode,
319        uint32_t                 ulKeySlot,
320        bool                     bSgEnable );
321
322/***************************************************************************
323 * obsolete
324 */
325BERR_Code BDMA_P_Mem_SetCrypto_isr(
326        BDMA_Mem_Handle          hMemDma,
327        BDMA_CryptMode           eCryptMode,   
328        uint32_t                 ulKeySlot,
329        bool                     bSgEnable );
330
331/***************************************************************************
332 *
333 */
334BERR_Code BDMA_P_Mem_Tran_Create_isr(
335        BDMA_Mem_Handle          hMemDma,
336        uint32_t                 ulNumBlocks,
337        bool                     bCachedDesc,
338        BDMA_Mem_Tran_Handle  *  phTran );
339
340/***************************************************************************
341 *
342 */
343BERR_Code BDMA_P_Mem_Tran_SetDmaBlockInfo_isr(
344        BDMA_Mem_Tran_Handle     hTran,
345        uint32_t                 ulBlockId,
346        uint32_t                 ulDstBusAddr,
347        uint32_t                 ulSrcBusAddr,
348        uint32_t                 ulBlockSize,
349        bool                     bCryptInit );
350
351/***************************************************************************
352 * To be called to mark / unmark the block as scatter-gather start /end point
353 * validated against the current engine state.
354 */
355BERR_Code BDMA_P_Mem_Tran_SetSgStartEnd_isr(
356        BDMA_Mem_Tran_Handle     hTran,
357        uint32_t                 ulBlockId,
358        bool                     bSgStart,
359        bool                     bSgEnd );
360
361/***************************************************************************
362 * To be called by both BDMA_P_Mem_Tran_Start and
363 * BDMA_P_Mem_Tran_StartAndCallBack, BDMA_P_Mem_Tran_Start should pass NULL
364 * for pCallBackFunc_isr and pUserCallBackParam
365 */
366BERR_Code BDMA_P_Mem_Tran_Start_isr(
367        BDMA_Mem_Tran_Handle     hTran,
368        uint32_t                 ulNumActBlocks,
369        BDMA_Mem_CallbackFunc    pCallBackFunc_isr,
370        void *                   pUserCallBackParam );
371
372/***************************************************************************
373 * To be called by both BDMA_Mem_Tran_StartDmaSubset and
374 * BDMA_Mem_Tran_StartDmaSubsetAndCallBack.
375 */
376
377BERR_Code BDMA_P_Mem_Tran_StartSubset_isr(
378        BDMA_Mem_Tran_Handle     hTran,
379        uint32_t                 ulFirstBlock,
380        uint32_t                 ulNumActBlocks,
381        BDMA_Mem_CallbackFunc    pCallBackFunc_isr,
382        void *                   pUserCallBackParam );
383
384/***************************************************************************
385 */
386BERR_Code BDMA_P_Mem_Transfer_isr(
387        BDMA_Mem_Tran_Handle     hTran,
388        uint32_t                 ulBlockId,
389        uint32_t                 ulDstBusAddr,
390        uint32_t                 ulSrcBusAddr,
391        uint32_t                 ulBlockSize,
392        bool                     bCryptInit,
393        BDMA_Mem_CallbackFunc    pCallBackFunc_isr,
394        void *                   pUserCallBackParam );
395
396/***************************************************************************
397 * To be called by BDMA_Mem_Tran_GetStatus.
398 */
399BERR_Code BDMA_P_Mem_Tran_GetStatus_isr(
400        BDMA_Mem_Tran_Handle     hTran,
401        BDMA_TranStatus *        peTranStatus );
402
403/***************************************************************************
404 * To be called by BDMA_Mem_Tran_Destroy. It free the queue entries occupied
405 * this Tran
406 */
407BERR_Code BDMA_P_Mem_Tran_Destroy_isr(
408        BDMA_Mem_Tran_Handle     hTran );
409
410
411/***************************************************************************
412 * To be called by BDMA_Mem_Tran_Reset. It resets the Tran into its
413 * initially created state
414 */
415BERR_Code BDMA_P_Mem_Tran_Reset_isr(
416        BDMA_Mem_Tran_Handle     hTran );
417
418
419#ifdef __cplusplus
420}
421#endif
422
423#endif /* #ifndef BDMA_MEM_PRIV_H__ */
424
425/* end of file */
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