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bgio_pin_priv.c

Last change on this file was 76, checked in by megakiss, 10 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2011, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bgio_pin_priv.c $
11	* $brcm_Revision: Hydra_Software_Devel/83 $
12	* $brcm_Date: 12/5/11 5:02p $
13	*
14	* Module Description:
15	*
16	*
17	* Revision History:
18	* $brcm_Log: /magnum/portinginterface/gio/7425/bgio_pin_priv.c $
19	*
20	* Hydra_Software_Devel/83 12/5/11 5:02p tdo
21	* SW7552-90: Set AON GPIO as push-pull type through bgio PI
22	*
23	* Hydra_Software_Devel/82 10/24/11 5:21p tdo
24	* SW7552-90: Set AON GPIO as push-pull type through bgio PI
25	*
26	* Hydra_Software_Devel/81 6/16/11 5:58p tdo
27	* SWDTV-7592: add BDBG_OBJECT_ASSERT for BGIO.
28	*
29	* Hydra_Software_Devel/80 6/16/11 11:26a tdo
30	* SWDTV-7292: Re-org GIO code
31	*
32	* Hydra_Software_Devel/79 6/13/11 2:38p tdo
33	* SWDTV-7292: Add Magnum PI GIO to 35233
34	*
35	* Hydra_Software_Devel/78 6/7/11 1:21p tdo
36	* SWDTV-7292: Add Magnum PI GIO to 35233
37	*
38	* Hydra_Software_Devel/77 6/1/11 4:03p syang
39	* SW7401-4472: change interrupt config order as requested.
40	*
41	* Hydra_Software_Devel/76 5/2/11 5:05p franli
42	* SWDTV-6889:Add board specific configure in vdc test
43	*
44	* Hydra_Software_Devel/75 4/13/11 6:54p tdo
45	* SW7425-112: Add GIO support for 7425 B0 chip
46	*
47	* Hydra_Software_Devel/75 4/13/11 6:15p tdo
48	* SW7425-112: Add GIO support for 7425 B0 chip
49	*
50	* Hydra_Software_Devel/74 3/29/11 12:02p pblanco
51	* SW35125-43: Fix compiler warning for 35125.
52	*
53	* Hydra_Software_Devel/73 3/21/11 5:43p jhaberf
54	* SWDTV-6095: Added dummy placeholder for 35233 DTV chip
55	*
56	* Hydra_Software_Devel/72 3/21/11 3:47p jhaberf
57	* SW35330-13: Added support for 35233 DTV chip
58	*
59	* Hydra_Software_Devel/71 12/23/10 1:23p zhang
60	* SW35125-43: Added 35125 defines and fixed pin creation bug.
61	*
62	* Hydra_Software_Devel/70 12/6/10 4:08p jhaberf
63	* SW35230-1: Added 35125 to the build
64	*
65	* Hydra_Software_Devel/69 12/2/10 2:38p tdo
66	* SWBLURAY-23686: Add GIO PortingInterface support for Blast (7640) chip
67	*
68	* Hydra_Software_Devel/68 11/23/10 11:29a jrubio
69	* SW7344-9: update 7346
70	*
71	* Hydra_Software_Devel/67 11/17/10 9:02a tdo
72	* SW7231-11: Add GIO PI support for 7231/7344/7346
73	*
74	* Hydra_Software_Devel/66 11/3/10 6:14p xhuang
75	* SW7358-3: sync with RDB change
76	*
77	* Hydra_Software_Devel/65 11/1/10 5:00p xhuang
78	* SW7552-4: Add 7552 support
79	*
80	* Hydra_Software_Devel/64 9/8/10 4:33p xhuang
81	* SW7358-3: update according to RDB change
82	*
83	* Hydra_Software_Devel/63 8/30/10 3:23p tdo
84	* SW7425-22: Add GIO PI support for 7425
85	*
86	* Hydra_Software_Devel/62 8/30/10 3:18p tdo
87	* SW7425-22: Add GIO PI support for 7425
88	*
89	* Hydra_Software_Devel/61 8/12/10 12:59p tdo
90	* SW7358-6: Add support for 7358
91	*
92	* Hydra_Software_Devel/SW7358-6/1 8/12/10 2:48p xhuang
93	* SW7358-6: Add support for 7358 in gio
94	*
95	* Hydra_Software_Devel/60 7/28/10 10:23p tdo
96	* SWBLURAY-21288: Add support for real gpio pins (not pin muxed) for
97	* Quick (7631) chip
98	*
99	* Hydra_Software_Devel/59 6/29/10 3:23p tdo
100	* SWBLURAY-21288: Need GIO PI updated for Quick (7631) chip
101	*
102	* Hydra_Software_Devel/58 6/24/10 7:07p vanessah
103	* SW7422-12: Naming convention problem for the registers.
104	*
105	* Hydra_Software_Devel/56 6/22/10 11:40a vanessah
106	* SW7422-12: To support appframework. Missing files added:
107	* magnum\portinginterface\pwr rockford\appframework\src\board\97422 To
108	* do list: 1. in framework_board.c, more initialization to be done. 2.
109	* More registers mapping, like clock generation as well as
110	* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL etc
111	*
112	* Hydra_Software_Devel/55 1/5/10 1:02p jhaberf
113	* SW35230-1: Check in of file on behalf of Srinivasa M.P. Reddy in order
114	* to get 35230 RAP PI compiling
115	*
116	* Hydra_Software_Devel/54 11/19/09 11:14a tdo
117	* SW7468-23: Create GIO PI for 7468
118	*
119	* Hydra_Software_Devel/53 11/18/09 11:35p tdo
120	* SW7408-22: Add GIO PI support for 7408
121	*
122	* Hydra_Software_Devel/52 9/1/09 2:37p yuxiaz
123	* SW7550-28: Add GIO pinmux support for 7125.
124	*
125	* Hydra_Software_Devel/51 9/1/09 11:11a tdo
126	* SW7550-28: Add GIO pinmux support for 7550
127	*
128	* Hydra_Software_Devel/50 8/28/09 3:07p yuxiaz
129	* SW7550-28: Add GIO pinmux support for 7550.
130	*
131	* Hydra_Software_Devel/49 8/27/09 6:29p tdo
132	* SW7630-15: Bringup of portinginterface "gio" for Grain (7630) and 7342
133	*
134	* Hydra_Software_Devel/48 6/17/09 4:34p tdo
135	* PR55763: Fix gpio_52 for 7340
136	*
137	* Hydra_Software_Devel/47 6/11/09 9:30p tdo
138	* PR55763: Port Magnum gio module to 97340 chipset
139	*
140	* Hydra_Software_Devel/46 4/27/09 11:07a jhaberf
141	* PR53796: Updating gio build to support BCM35130 DTV chip.
142	*
143	* Hydra_Software_Devel/45 3/24/09 4:11p tdo
144	* PR52975: Fix compiling error
145	*
146	* Hydra_Software_Devel/44 3/23/09 10:01p tdo
147	* PR52975: BGIO PI support for 7635 "Dune" chip
148	*
149	* Hydra_Software_Devel/43 1/27/09 8:37p tdo
150	* PR51627: add VDC 7336 PI support
151	*
152	* Hydra_Software_Devel/42 9/10/08 7:50p tdo
153	* PR46763: Add GIO PI support for 7420
154	*
155	* Hydra_Software_Devel/41 9/9/08 2:01p tdo
156	* PR46701: Add support for GIO for 3548B0
157	*
158	* Hydra_Software_Devel/40 7/7/08 6:09p tdo
159	* PR44530: BGIO support for 7601
160	*
161	* Hydra_Software_Devel/39 7/7/08 6:06p tdo
162	* PR44530: BGIO support for 7601
163	*
164	* Hydra_Software_Devel/38 6/30/08 2:06p tdo
165	* PR44360: Remove FORWARD_NULL Coverity Defect
166	*
167	* Hydra_Software_Devel/37 6/10/08 1:17p tdo
168	* PR41941: Basic GIO PI support for 7335B0
169	*
170	* Hydra_Software_Devel/36 4/30/08 6:59p tdo
171	* PR34956: gpio pin name change for 7325
172	*
173	* Hydra_Software_Devel/35 4/8/08 5:47p tdo
174	* PR41205: Add _isr functions to avoid deadlock
175	*
176	* Hydra_Software_Devel/34 3/5/08 12:31p tdo
177	* PR39459: Basic GIO PI support for 3556
178	*
179	* Hydra_Software_Devel/33 2/27/08 11:54a tdo
180	* PR34956: Re-organize GPIO pin mux and add 3548 support.
181	*
182	* Hydra_Software_Devel/32 2/14/08 6:25p pntruong
183	* PR34956: Added stub to compile for 3548.
184	*
185	* Hydra_Software_Devel/31 11/20/07 10:53p tdo
186	* PR36883: Add gio PI suppport for 7335
187	*
188	* Hydra_Software_Devel/30 10/15/07 2:29p yuxiaz
189	* PR36114: Added GIO support for 7325.
190	*
191	* Hydra_Software_Devel/29 9/13/07 4:12p syang
192	* PR 30391, PR 32351: clean up OpenDrain pin data set records when it is
193	* destroied or changed to diff type
194	*
195	* Hydra_Software_Devel/28 9/12/07 6:35p syang
196	* PR 30391, PR 32351: guard reg read and modify by kni critical section
197	*
198	* Hydra_Software_Devel/27 9/12/07 5:58p syang
199	* PR 30391, PR 32351: BGIO only init for the pin created by BGIO to avoid
200	* overriding configures by other sw entity; BGIO read from HW reg (no more
201	* sw buffering);
202	*
203	* Hydra_Software_Devel/26 5/18/07 3:25p syang
204	* PR 31356: add gpio PI support for 7440 B0
205	*
206	* Hydra_Software_Devel/25 5/18/07 10:47a yuxiaz
207	* PR30839: Added 7405 support in GIO.
208	*
209	* Hydra_Software_Devel/24 12/29/06 11:31a syang
210	* PR 25750: add 7403 and 7400 B0 support
211	*
212	* Hydra_Software_Devel/23 10/4/06 3:14p syang
213	* PR 23355: fixed a typo in 3563 pin mux entry
214	*
215	* Hydra_Software_Devel/22 10/4/06 12:01p syang
216	* PR 23536: update pin mux in sun_top_ctrl for 7440
217	*
218	* Hydra_Software_Devel/21 7/21/06 11:27a syang
219	* PR 22789: added support for gio control set *_EXT_HI and more pins with
220	* control set *_EXT, added suuport for 7118, 3563 and 7440
221	*
222	* Hydra_Software_Devel/20 6/21/06 6:41p syang
223	* PR 16058: added 7401 B0 support
224	*
225	* Hydra_Software_Devel/19 3/23/06 2:27p syang
226	* PR 19670: added support for 7438 A0
227	*
228	* Hydra_Software_Devel/18 2/3/06 5:01p syang
229	* PR 19425: added 7400 support
230	*
231	* Hydra_Software_Devel/17 7/14/05 5:05p syang
232	* PR 16058: added 7401 support
233	*
234	* Hydra_Software_Devel/16 6/24/05 10:08a syang
235	* PR 14720: added C1 support
236	*
237	* Hydra_Software_Devel/15 5/13/05 12:59p syang
238	* PR 14720: added 7038 B2 and C1 support
239	*
240	* Hydra_Software_Devel/14 4/20/05 12:55p syang
241	* PR 14421: be able to compile for 3560 now
242	*
243	* Hydra_Software_Devel/13 3/18/05 6:30p syang
244	* PR 14421: updated SUN_TOP_CTRL_* registers for 3560
245	*
246	* Hydra_Software_Devel/12 3/16/05 12:31p syang
247	* PR 14421: added support for 3560
248	*
249	* Hydra_Software_Devel/11 2/1/05 3:49p jasonh
250	* PR 14009: Fixed chip revision detection.
251	*
252	* Hydra_Software_Devel/10 1/25/05 4:50p syang
253	* PR 1344: fixed the mis-using of BVDC_P macro
254	*
255	* Hydra_Software_Devel/9 1/25/05 10:14a syang
256	* PR 1344: corrected the gpio pin order in s_aPinMux[]
257	*
258	* Hydra_Software_Devel/8 1/24/05 7:27p syang
259	* PR 1344: added C0 support
260	*
261	* Hydra_Software_Devel/7 7/27/04 11:21a syang
262	* PR 10548: changed to use BCHP_MASK and BCHP_SHIFT
263	*
264	* Hydra_Software_Devel/6 5/24/04 5:07p jasonh
265	* PR 11189: Merge down from B0 to main-line
266	*
267	* Hydra_Software_Devel/Refsw_Devel_7038_B0/3 5/7/04 5:02p syang
268	* PR 10097: added RST register setting to block interrupt firing when it
269	* is meant to be disabled
270	*
271	* Hydra_Software_Devel/Refsw_Devel_7038_B0/2 4/28/04 11:10a syang
272	* PR 10097: write 1 and then 0 to interrupt clear bit
273	*
274	* Hydra_Software_Devel/Refsw_Devel_7038_B0/1 4/20/04 2:28p syang
275	* PR 10687: updated sun_top_ctrl registers to B0
276	*
277	* Hydra_Software_Devel/4 3/15/04 6:28p syang
278	* PR 10097: fixed a comparing problem in BGIO_P_Pin_SetType
279	*
280	* Hydra_Software_Devel/3 2/24/04 7:20p syang
281	* PR 9785: more api function implementations are added
282	*
283	* Hydra_Software_Devel/2 2/20/04 4:53p syang
284	* PR 9785: check in before clearcase upgrade world wise
285	*
286	* Hydra_Software_Devel/1 2/20/04 11:23a syang
287	* PR 9785: init version
288	*
289	***************************************************************************/
290
291	#include "bgio_pin_priv.h"
292	#include "bgio_priv.h"
293	#include "berr.h"
294	#include "bkni.h"
295	#include "bchp_gio.h"
296	#include "bchp_sun_top_ctrl.h"
297	#include "bchp_common.h"
298	#ifdef BCHP_AON_PIN_CTRL_REG_START
299	#include "bchp_aon_pin_ctrl.h"
300	#endif
301	#include "bkni.h"
302
303	BDBG_MODULE(BGIO);
304	BDBG_OBJECT_ID(BGIO_PIN);
305
306	/***************************************************************************
307	*
308	* Utility functions
309	*
310	***************************************************************************/
311	static BERR_Code BGIO_P_Pin_ClearOpenDrainSet(
312	BGIO_Handle hGpio,
313	BGIO_PinId ePinId )
314	{
315	BERR_Code eResult = BERR_SUCCESS;
316	uint32_t ulRegOffset, ulBitOffset;
317	uint32_t ulRegIndex = 0;
318
319	BDBG_OBJECT_ASSERT(hGpio, BGIO);
320	BDBG_ASSERT( BGIO_PinId_eInvalid > ePinId );
321
322	/* read the HW register and modify it for this setting */
323	eResult = BGIO_P_CalcPinRegAndBit( ePinId, BCHP_GIO_DATA_LO,
324	&ulRegOffset, &ulBitOffset );
325	BDBG_ASSERT( BERR_SUCCESS == eResult );
326
327	if (BERR_SUCCESS == eResult )
328	{
329	ulRegIndex = ulRegOffset / 4;
330	hGpio->aulOpenDrainSet[ulRegIndex] &= (~ BGIO_P_BIT_MASK(ulBitOffset));
331	}
332
333	return eResult;
334	}
335
336
337	/***************************************************************************
338	*
339	* API support functions
340	*
341	***************************************************************************/
342
343
344	#define BGIO_P_PIN_MUX_SEL_GPIO 0
345	/***************************************************************************
346	*
347	*/
348	BERR_Code BGIO_P_Pin_Create(
349	BGIO_Handle hGpio,
350	BGIO_PinId ePinId,
351	BGIO_Pin_Handle * phPin )
352	{
353	BERR_Code eResult = BERR_SUCCESS;
354	BGIO_P_Pin_Context * pPin = NULL;
355	const BGIO_P_PinMux * pPinMux;
356	BREG_Handle hRegister;
357	uint32_t ulRegValue;
358
359	if ( NULL != phPin )
360	*phPin = NULL;
361
362	BDBG_OBJECT_ASSERT(hGpio, BGIO);
363	pPinMux = BGIO_P_GetPinMux(ePinId);
364	if ((NULL == phPin) \|\|
365	(BGIO_PinId_eInvalid <= ePinId) \|\|
366	(pPinMux->ulReg == BGIO_P_NULL_REG) )
367	{
368	return BERR_TRACE(BERR_INVALID_PARAMETER);
369	}
370
371	/* GPIO pin can not share among two apps */
372	if ( NULL != BGIO_P_GetPinHandle(hGpio, ePinId) )
373	{
374	return BERR_TRACE(BERR_INVALID_PARAMETER);
375	}
376
377	/* allocate pin gio sub-module's context */
378	pPin = (BGIO_P_Pin_Context *)BKNI_Malloc( sizeof(BGIO_P_Pin_Context) );
379	if ( NULL == pPin )
380	{
381	return BERR_TRACE(BERR_OUT_OF_SYSTEM_MEMORY);
382	}
383	BKNI_Memset((void*)pPin, 0x0, sizeof(BGIO_P_Pin_Context));
384	BDBG_OBJECT_SET(pPin, BGIO_PIN);
385
386	if(pPinMux->ulReg != BGIO_P_GIO_REG)
387	{
388	/* set pin mux to make the pin work as GPIO pin */
389	hRegister = BGIO_P_GetRegisterHandle( hGpio );
390	BKNI_EnterCriticalSection();
391	ulRegValue = BREG_Read32(hRegister, pPinMux->ulReg) &
392	~ pPinMux->ulBitMask;
393	ulRegValue \|= pPinMux->ulValue;
394	BREG_Write32( hRegister, pPinMux->ulReg, ulRegValue );
395	BKNI_LeaveCriticalSection();
396	}
397
398	/* init pin sub-module's main context */
399	BGIO_P_PIN_SET_BLACK_MAGIC( pPin );
400	pPin->hGpio = hGpio;
401	pPin->ePinId = ePinId;
402
403	eResult = BGIO_P_Pin_SetType( pPin, BGIO_PinType_eInput, false );
404	BDBG_ASSERT( BERR_SUCCESS == eResult );
405	eResult = BGIO_P_Pin_SetIntrMode( pPin, BGIO_IntrMode_eDisabled, false );
406	BDBG_ASSERT( BERR_SUCCESS == eResult );
407	eResult = BGIO_P_Pin_ClearIntrStatus( pPin, false );
408	BDBG_ASSERT( BERR_SUCCESS == eResult );
409
410	/* connect pin gio sub-module to gio module's main context */
411	eResult = BGIO_P_AddPinToList( hGpio, pPin );
412
413	*phPin = pPin;
414	return eResult;
415	}
416
417	/***************************************************************************
418	*
419	*/
420	BERR_Code BGIO_P_Pin_Destroy(
421	BGIO_Pin_Handle hPin )
422	{
423	BERR_Code eResult = BERR_SUCCESS;
424	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
425
426	/* block the pin's driving and interrupt,
427	* important for other pins' Pin_SetValue later */
428	eResult = BGIO_P_Pin_SetType( hPin, BGIO_PinType_eInput, false );
429	BDBG_ASSERT( BERR_SUCCESS == eResult );
430	eResult = BGIO_P_Pin_SetIntrMode( hPin, BGIO_IntrMode_eDisabled, false );
431	BDBG_ASSERT( BERR_SUCCESS == eResult );
432	eResult = BGIO_P_Pin_ClearOpenDrainSet(hPin->hGpio, hPin->ePinId);
433	BDBG_ASSERT( BERR_SUCCESS == eResult );
434
435	/* remove pin handle from the pin list in gio module's main context */
436	eResult = BGIO_P_RemovePinFromList( hPin->hGpio, hPin );
437	BDBG_ASSERT( BERR_SUCCESS == eResult );
438
439	BDBG_OBJECT_DESTROY(hPin, BGIO_PIN);
440	BKNI_Free((void*)hPin);
441	return eResult;
442	}
443
444	/***************************************************************************
445	*
446	*/
447	#define BGIO_P_PUSH_PULL BGIO_PinValue_e0
448	#define BGIO_P_OPEN_DRAIN BGIO_PinValue_e1
449	#define BGIO_P_OUTPUT BGIO_PinValue_e0
450	#define BGIO_P_INPUT_ONLY BGIO_PinValue_e1
451
452	BERR_Code BGIO_P_Pin_SetType(
453	BGIO_Pin_Handle hPin,
454	BGIO_PinType ePinType,
455	bool bInIsr )
456	{
457	BERR_Code eResult = BERR_SUCCESS;
458	BGIO_PinValue eValIoDir, eValOdEn;
459
460	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
461	if (BGIO_PinType_eInvalid <= ePinType)
462	{
463	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
464	return eResult;
465	}
466
467	/* calc reg values */
468	switch ( ePinType )
469	{
470	case BGIO_PinType_eInput:
471	eValIoDir = BGIO_P_INPUT_ONLY;
472	eValOdEn = BGIO_P_PUSH_PULL;
473	break;
474	case BGIO_PinType_ePushPull:
475	/* special GPIO pins can not work as push-pull type */
476	if((BGIO_PinId_eSgpio00 <= hPin->ePinId && hPin->ePinId < BGIO_PinId_eAgpio00) \|\|
477	(BGIO_PinId_eAsgpio00 <= hPin->ePinId))
478	{
479	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
480	return eResult;
481	}
482	eValIoDir = BGIO_P_OUTPUT;
483	eValOdEn = BGIO_P_PUSH_PULL;
484	break;
485	case BGIO_PinType_eOpenDrain:
486	eValIoDir = BGIO_P_OUTPUT;
487	eValOdEn = BGIO_P_OPEN_DRAIN;
488	break;
489	default:
490	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
491	return eResult;
492	}
493	hPin->ePinType = ePinType;
494
495	/* modify hGpio's register value records for this pin and write HW reg */
496	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
497	BCHP_GIO_IODIR_LO, eValIoDir, bInIsr );
498	BDBG_ASSERT( BERR_SUCCESS == eResult );
499	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
500	BCHP_GIO_ODEN_LO, eValOdEn, bInIsr );
501	BDBG_ASSERT( BERR_SUCCESS == eResult );
502
503	/* TODO: init value for push-pull XXX ??? */
504	if ( BGIO_PinType_eOpenDrain == ePinType )
505	eResult = BGIO_P_Pin_SetValue( hPin, BGIO_PinValue_e1, bInIsr ); /* release */
506	else
507	eResult = BGIO_P_Pin_ClearOpenDrainSet(hPin->hGpio, hPin->ePinId);
508	BDBG_ASSERT( BERR_SUCCESS == eResult );
509	return eResult;
510	}
511
512	/***************************************************************************
513	*
514	*/
515	BERR_Code BGIO_P_Pin_GetValue(
516	BGIO_Pin_Handle hPin,
517	BGIO_PinValue * pePinValue )
518	{
519	BERR_Code eResult = BERR_SUCCESS;
520	BGIO_PinValue ePinValue = BGIO_PinValue_eInvalid;
521
522	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
523	if (NULL == pePinValue)
524	{
525	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
526	return eResult;
527	}
528
529	/* read the pin value from HW reg */
530	eResult = BGIO_P_ReadPinRegBit( hPin->hGpio, hPin->ePinId, BCHP_GIO_DATA_LO,
531	&ePinValue );
532	BDBG_ASSERT( BERR_SUCCESS == eResult );
533	*pePinValue = ePinValue;
534	return eResult;
535	}
536
537	/***************************************************************************
538	*
539	*/
540	BERR_Code BGIO_P_Pin_SetValue(
541	BGIO_Pin_Handle hPin,
542	BGIO_PinValue ePinValue,
543	bool bInIsr )
544	{
545	BERR_Code eResult = BERR_SUCCESS;
546
547	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
548	if (BGIO_PinValue_eInvalid <= ePinValue)
549	{
550	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
551	return eResult;
552	}
553
554	/* modify hGpio's register value records for this pin and write HW reg */
555	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
556	BCHP_GIO_DATA_LO, ePinValue, bInIsr );
557	BDBG_ASSERT( BERR_SUCCESS == eResult );
558	return eResult;
559	}
560
561	/***************************************************************************
562	*
563	*/
564	#define BGIO_P_INTR_RESET BGIO_PinValue_e0 /* reset to work normal */
565	#define BGIO_P_INTR_CLEAR BGIO_PinValue_e1 /* clear and block */
566	#define BGIO_P_INTR_DISABLE BGIO_PinValue_e0
567	#define BGIO_P_INTR_ENABLE BGIO_PinValue_e1
568	#define BGIO_P_INTR_FALL_EDGE BGIO_PinValue_e0
569	#define BGIO_P_INTR_RISE_EDGE BGIO_PinValue_e1
570	#define BGIO_P_INTR_ONE_EDGE BGIO_PinValue_e0
571	#define BGIO_P_INTR_BOTH_EDGE BGIO_PinValue_e1
572	#if (BCHP_CHIP != 7038) && (BCHP_CHIP != 7438)
573	#define BGIO_P_INTR_EDGE BGIO_PinValue_e0
574	#define BGIO_P_INTR_LEVEL BGIO_PinValue_e1
575	#define BGIO_P_INTR_0 BGIO_PinValue_e0
576	#define BGIO_P_INTR_1 BGIO_PinValue_e1
577	#endif
578
579	BERR_Code BGIO_P_Pin_SetIntrMode(
580	BGIO_Pin_Handle hPin,
581	BGIO_IntrMode eIntrMode,
582	bool bInIsr )
583	{
584	BERR_Code eResult = BERR_SUCCESS;
585	BGIO_PinValue eIntrEna, eEdgeSel, eEdgeInsen;
586	#if (BCHP_CHIP != 7038) && (BCHP_CHIP != 7438)
587	BGIO_PinValue eLvlEdge;
588	#endif
589
590	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
591	if (BGIO_IntrMode_eInvalid <= eIntrMode)
592	{
593	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
594	return eResult;
595	}
596
597	/* calc reg values */
598	eEdgeInsen = BGIO_P_INTR_ONE_EDGE;
599	#if (BCHP_CHIP != 7038) && (BCHP_CHIP != 7438)
600	eLvlEdge = BGIO_P_INTR_EDGE;
601	#endif
602	switch ( eIntrMode )
603	{
604	case BGIO_IntrMode_eDisabled:
605	eIntrEna = BGIO_P_INTR_DISABLE;
606	eEdgeSel = BGIO_P_INTR_FALL_EDGE;
607	break;
608	case BGIO_IntrMode_e0To1:
609	eIntrEna = BGIO_P_INTR_ENABLE;
610	eEdgeSel = BGIO_P_INTR_RISE_EDGE;
611	break;
612	case BGIO_IntrMode_e1To0:
613	eIntrEna = BGIO_P_INTR_ENABLE;
614	eEdgeSel = BGIO_P_INTR_FALL_EDGE;
615	break;
616	case BGIO_IntrMode_e0To1_Or_1To0:
617	eIntrEna = BGIO_P_INTR_ENABLE;
618	eEdgeSel = BGIO_P_INTR_FALL_EDGE;
619	eEdgeInsen = BGIO_P_INTR_BOTH_EDGE;
620	break;
621	#if (BCHP_CHIP != 7038) && (BCHP_CHIP != 7438)
622	case BGIO_IntrMode_e0:
623	eIntrEna = BGIO_P_INTR_ENABLE;
624	eLvlEdge = BGIO_P_INTR_LEVEL;
625	eEdgeSel = BGIO_P_INTR_0;
626	break;
627	case BGIO_IntrMode_e1:
628	eIntrEna = BGIO_P_INTR_ENABLE;
629	eLvlEdge = BGIO_P_INTR_LEVEL;
630	eEdgeSel = BGIO_P_INTR_1;
631	break;
632	#endif
633	default:
634	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
635	return eResult;
636	}
637	hPin->eIntrMode = eIntrMode;
638
639	/* modify hGpio's register value records for this pin and write HW reg */
640	#if (BCHP_CHIP == 7038) \|\| (BCHP_CHIP==7438)
641	/* Both MASK and RESET in RST are needed to really enable interrupt */
642	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
643	BCHP_GIO_RST_LO, BGIO_P_INTR_CLEAR, bInIsr );
644	BDBG_ASSERT( BERR_SUCCESS == eResult ); /* clear and block for 7038 */
645	if ( BGIO_IntrMode_eDisabled != eIntrMode )
646	{
647	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
648	BCHP_GIO_RST_LO, BGIO_P_INTR_RESET, bInIsr );
649	BDBG_ASSERT( BERR_SUCCESS == eResult ); /* reset to work normal */
650	}
651	#else
652	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
653	BCHP_GIO_STAT_LO, BGIO_P_INTR_CLEAR, bInIsr );
654	BDBG_ASSERT( BERR_SUCCESS == eResult ); /* clear and work normal */
655	#endif
656	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
657	BCHP_GIO_EC_LO, eEdgeSel, bInIsr );
658	BDBG_ASSERT( BERR_SUCCESS == eResult );
659	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
660	BCHP_GIO_EI_LO, eEdgeInsen, bInIsr );
661	BDBG_ASSERT( BERR_SUCCESS == eResult );
662	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
663	BCHP_GIO_MASK_LO, eIntrEna, bInIsr );
664	BDBG_ASSERT( BERR_SUCCESS == eResult );
665
666	return eResult;
667	}
668
669	/***************************************************************************
670	*
671	*/
672	BERR_Code BGIO_P_Pin_ClearIntrStatus(
673	BGIO_Pin_Handle hPin,
674	bool bInIsr )
675	{
676	BERR_Code eResult = BERR_SUCCESS;
677	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
678
679	#if (BCHP_CHIP == 7038) \|\| (BCHP_CHIP==7438)
680	/* modify hGpio's register value records for this pin and write HW reg
681	* needs to write a "1" and a "0" to the clear bit to clear the
682	* interrupt status and to set ready for new interrupt for the pin */
683	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
684	BCHP_GIO_RST_LO, BGIO_PinValue_e1, bInIsr );
685	BDBG_ASSERT( BERR_SUCCESS == eResult );
686	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
687	BCHP_GIO_RST_LO, BGIO_PinValue_e0, bInIsr );
688	BDBG_ASSERT( BERR_SUCCESS == eResult );
689	#else
690	if ( (BGIO_IntrMode_e0 != hPin->eIntrMode) &&
691	(BGIO_IntrMode_e1 != hPin->eIntrMode) )
692	{
693	eResult = BGIO_P_WritePinRegBit( hPin->hGpio, hPin->ePinId, hPin->ePinType,
694	BCHP_GIO_STAT_LO, BGIO_PinValue_e1, bInIsr );
695	}
696	else
697	{
698	BDBG_ERR(("Level trigered intr must be cleared by changing pin value"));
699	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
700	}
701	#endif
702	return eResult;
703	}
704
705	/***************************************************************************
706	*
707	*/
708	BERR_Code BGIO_P_Pin_GetIntrStatus(
709	BGIO_Pin_Handle hPin,
710	bool * pbFire )
711	{
712	BERR_Code eResult = BERR_SUCCESS;
713	BGIO_PinValue ePinValue = BGIO_PinValue_eInvalid;
714
715	BDBG_OBJECT_ASSERT(hPin, BGIO_PIN);
716	if (NULL == pbFire)
717	{
718	eResult = BERR_TRACE(BERR_INVALID_PARAMETER);
719	return eResult;
720	}
721
722	/* read the pin value from HW reg */
723	eResult = BGIO_P_ReadPinRegBit( hPin->hGpio, hPin->ePinId,
724	BCHP_GIO_STAT_LO, &ePinValue );
725	BDBG_ASSERT( BERR_SUCCESS == eResult );
726
727	*pbFire = (BGIO_PinValue_e1 == ePinValue);
728	return eResult;
729	}
730
731
732	/* End of File */
733

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source: svn/newcon3bcm2_21bu/magnum/portinginterface/gio/7552/bgio_pin_priv.c

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