source: svn/newcon3bcm2_21bu/magnum/portinginterface/hdm/7552/bhdm_config.h

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1/***************************************************************************
2 *     Copyright (c) 2003-2012, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bhdm_config.h $
11 * $brcm_Revision: Hydra_Software_Devel/94 $
12 * $brcm_Date: 3/9/12 6:52p $
13 *
14 * Module Description:
15 *
16 * Revision History:
17 *
18 * $brcm_Log: /magnum/portinginterface/hdm/7038/bhdm_config.h $
19 *
20 * Hydra_Software_Devel/94   3/9/12 6:52p vle
21 * SW7435-44: Update HDMI_TX_PHY channel swap settings for all 40nm
22 * platforms. Future platforms relies on the default values
23 *
24 * Hydra_Software_Devel/93   3/1/12 11:29a vle
25 * SW7435-44: Update HDMI_TX_PHY channel_swap settings for 7435
26 *
27 * Hydra_Software_Devel/92   2/13/12 11:39a vle
28 * SW7360-9: Add dual HPD support for 7360
29 *
30 * Hydra_Software_Devel/91   1/20/12 4:29p vle
31 * SW7360-9: Add support for 7360
32 *
33 * Hydra_Software_Devel/90   1/19/12 2:34p rgreen
34 * SW7125-1146: Enable TMDS at open to fix interrupt issue; Get RSEN
35 * setting at isr vs event time; Add debug configurations for RSEN amd
36 * TMDS settings
37 *
38 * Hydra_Software_Devel/89   1/6/12 2:59p vle
39 * SW7435-11: Add support for 7435
40 *
41 * Hydra_Software_Devel/88   1/4/12 3:31p rgreen
42 * SW7405-5004: Add Source Product Description (SPD) debug option
43 *
44 * Hydra_Software_Devel/87   12/12/11 2:12p rgreen
45 * SW7552-157: Fix 7552 build; remove references to unused
46 * BHDM_CONFIG_40NM_REV2_SUPPORT
47 *
48 * Hydra_Software_Devel/86   11/23/11 1:17p rgreen
49 * SW7425-1140: Merge to mainline
50 *
51 * Hydra_Software_Devel/SW7425-1140/1   11/22/11 5:48p vle
52 * SW7425-1140: Add BHDM_CONFIG_CEC_LEGACY_SUPPORT for backward compatible
53 * for CEC legacy platforms.
54 *
55 * Hydra_Software_Devel/85   11/14/11 3:33p rgreen
56 * SW7425-1710: Update BHDM_CONFIG macro usage.  Describe specific
57 * functionality vs chip process
58 *
59 * Hydra_Software_Devel/84   11/14/11 2:15p rgreen
60 * SW7425-1710: Update BHDM_CONFIG macro usage.  Describe specific
61 * functionality vs chip process
62 *
63 * Hydra_Software_Devel/83   11/4/11 4:08p rgreen
64 * SW7125-1128,SW7125-1138:  Use register based General Control Packet
65 * only when attached receiver supports Deep Color
66 *
67 * Hydra_Software_Devel/82   10/28/11 2:26p mward
68 * SW7435-11: Add 7435.
69 *
70 * Hydra_Software_Devel/81   10/12/11 3:30p vle
71 * SW7429-5: Add support for 7429 - Take 2
72 *
73 * Hydra_Software_Devel/80   10/11/11 4:50p vle
74 * SW7429-5: Add support for 7429.
75 *
76 * Hydra_Software_Devel/79   9/7/11 10:40a vle
77 * SW7422-114: Only 40nm platforms should be using register based GCP for
78 * AVMute
79 *
80 * Hydra_Software_Devel/78   8/17/11 6:37p vle
81 * SW7231-322: Add support for 7231B0
82 *
83 * Hydra_Software_Devel/77   7/1/11 10:47a vle
84 * SW7422-458: merge bdvd changes to mainline
85 *
86 * Hydra_Software_Devel/bdvd_v4.0/1   6/28/11 2:13p rbshah
87 * SWBLURAY-26245:[ see Broadcom Issue Tracking JIRA for more info ]
88 *
89 * Hydra_Software_Devel/76   6/17/11 5:58p vle
90 * SW7231-147: Tweak Pre-emphasis settings for some 40nm A0 platforms to
91 * fix HDMI eye diagram issue in 1080p 8bit color depth - Take 2: For A0
92 * only
93 *
94 * Hydra_Software_Devel/75   6/17/11 1:42p vle
95 * SW7405-5358, SW7405-5312: Separate 3D support from EDID parser to allow
96 * easier back port
97 *
98 * Hydra_Software_Devel/74   6/13/11 6:07p vle
99 * SW7231-147: Tweak Pre-emphasis settings for some 40nm A0 platforms to
100 * fix HDMI eye diagram issue in 1080p 8bit color depth
101 *
102 * Hydra_Software_Devel/73   4/8/11 3:25p rgreen
103 * SW7405-3994: Disable debug messages for HDMI 1.4a (VSI format messages)
104 *
105 * Hydra_Software_Devel/72   2/10/11 7:43p vle
106 * SW7550-672: Fix GCP packet handlings for 65nm platforms with HDMI 1.3
107 * support.
108 *
109 * Hydra_Software_Devel/71   12/27/10 3:18p pntruong
110 * SW7231-10, SW7231-16: Bringup hdmi output.
111 *
112 * Hydra_Software_Devel/71   12/27/10 3:17p pntruong
113 * SW7231-10, SW7231-16: Bringup hdmi output.
114 *
115 * Hydra_Software_Devel/70   12/22/10 11:40a vle
116 * SW7344-11: Configure HDMI_TX_PHY.CHANNEL_SWAP for 40nm platforms. Not
117 * all chips can use the default values.
118 *
119 * Hydra_Software_Devel/69   12/21/10 4:47p vle
120 * SWBLURAY-23688: Add support for 7640
121 *
122 * Hydra_Software_Devel/68   11/19/10 4:10p vle
123 * SW7344-11: Add support for 7344 / 7346
124 *
125 * Hydra_Software_Devel/67   11/5/10 5:17p vle
126 * SW7552-12: Add support for 7552
127 *
128 * Hydra_Software_Devel/66   11/5/10 3:32p vle
129 * SW7231-10: Add support for 7231
130 *
131 * Hydra_Software_Devel/65   9/29/10 4:15p vle
132 * SW7422-23: Add 7422 support
133 *
134 * Hydra_Software_Devel/64   9/28/10 7:19p vle
135 * SW7422-23: Refactor HDMI code to isolate platform dependent code
136 * furthermore. Add support for 7422 and other 40nm platforms.
137 *
138 * Hydra_Software_Devel/63   6/22/10 6:57p vle
139 * SW7405-3994: Add support to parse all Shorthand and additional 3D
140 * Timing/Structure support indication in HDMI 1.4a
141 *
142 * Hydra_Software_Devel/62   5/11/10 7:14p vle
143 * SW7405-3994: Add VSDB debug config
144 *
145 * Hydra_Software_Devel/61   4/12/10 3:27p vle
146 * SW7405-3997: Enable VSI debug message by default.
147 *
148 * Hydra_Software_Devel/60   2/23/10 12:49a vle
149 * SW7420-579: Refactor HDMI PI.
150 *
151 * Hydra_Software_Devel/17   1/7/10 5:12p vle
152 * SW7420-536: Add method to use RAM packets to generate GCP Packets for
153 * various platforms.
154 *
155 * Hydra_Software_Devel/16   1/6/10 4:38p vle
156 * SW3548-2670: Centralize all CEC timing configurations
157 *
158 * Hydra_Software_Devel/15   12/8/09 7:27p vle
159 * SW7468-18: Add support for 7208
160 *
161 * Hydra_Software_Devel/14   11/20/09 11:51a vle
162 * SW7408-14, SW7468-18: Add support for 7408 and 7468
163 *
164 * Hydra_Software_Devel/13   9/11/09 11:26a vle
165 * SW7550-12: Add support for 7550
166 *
167 * Hydra_Software_Devel/12   9/1/09 2:00p vle
168 * SW7630-17: Add support for Grain 7630
169 *
170 * Hydra_Software_Devel/11   8/26/09 9:17p vle
171 * SW7125-9: Add support for 7125
172 *
173 * Hydra_Software_Devel/10   8/4/09 4:36p vle
174 * PR55220, PR55228: Add support for 7340, 7342
175 *
176 * Hydra_Software_Devel/PR55545/1   7/24/09 11:39a mward
177 * PR57053: Add 7125 for bring-up.
178 *
179 * Hydra_Software_Devel/9   7/22/09 7:35p vle
180 * PR56776: Prevent HDCP An Timeout
181 *
182 * Hydra_Software_Devel/8   6/25/09 3:04p vle
183 * PR56132, PR48151:
184 * Add support for Get HDMI Vendor Specific Info Frame
185 * Correct channel assignment for PCM 5.1
186 *
187 * Hydra_Software_Devel/7   6/23/09 3:42p vle
188 * PR55933: Update for 7601/7635
189 *
190 * Hydra_Software_Devel/6   5/6/09 7:20p vle
191 * PR52978: Add support for 7635
192 *
193 * Hydra_Software_Devel/bdvd_v3.0/1   5/1/09 9:29a rbshah
194 * PR_14471[DVD]:[ see HiDef-DVD bug tracking system for more info ].
195 * Bring HDMI to life. Audio is muted unconditionally all the time to
196 * avoid noisy output (given the chip bug).
197 *
198 * Qucik verification of HDCP and all supported video resolutions.
199 *
200 * Reviewer: Narasimha.
201 *
202 * Hydra_Software_Devel/5   3/24/09 12:27a vle
203 * PR52978: Add support for 7635
204 *
205 * Hydra_Software_Devel/4   3/9/09 3:21p vle
206 * PR50570, PR50918, PR49277, PR49652, PR52873:
207 * Add API to mute/unmute audio, update pixel repitition support, add
208 * SetPixelDataOverride API for transmission of black video. Merge
209 * changes/updates from bdvd_v2.0 to main branch.
210 *
211 * Hydra_Software_Devel/3   3/3/09 8:23p vle
212 * PR50569: Add HW Ri/Pj checking feature. Merged from bdvd branch after
213 * Rajul's testing effort.
214 *
215 * Hydra_Software_Devel/PR44535/bdvd_v2.0/3   1/23/09 10:14a rbshah
216 * PR_10346 [ see HiDef-DVD bug tracking system for more info ].  Checkin
217 * code drop from Anthony Le for Auto Ri,Pj feature in the
218 * 7601B0 (Digital Video PR50569).
219 *
220 * This is disabled by default and will be turned on once it has
221 * been tested and soaked.
222 *
223 * Did verify the A0 build!
224 *
225 * Hydra_Software_Devel/2   10/9/08 5:55p vle
226 * PR45656: Add support for 7420
227 *
228 * Hydra_Software_Devel/1   10/9/08 4:38p vle
229 * PR44535: Merge to main Hydra dev. branch
230 *
231 * Hydra_Software_Devel/PR44535/1   8/6/08 7:47p vle
232 * PR44535: Initial version
233 *
234 ***************************************************************************/
235
236#ifndef BHDM_CONFIG_H__
237#define BHDM_CONFIG_H__
238
239/* HDMI Tx Configuration Options */
240
241/*
242** All HDCP Rx are required to support Short or Fast I2C Reads, where a
243** I2C read without an offset indicates to read data from the default I2C
244** offset of the device.  In the case of the HDCP Rx (0x74), the default
245** offset is 0x08 (Ri).
246**
247** Some early DVI receivers did not  properly implement the Short Read
248** resulting in Authentication errors. 
249** Disable the I2C Short Read here if the STB is having trouble authenticating
250** with an older DVI Rx.  Failures might show the same HDCP R0'  value on each
251** authentication attempt
252*/
253
254#define BHDM_CONFIG_HDCP_RI_SHORT_READ  1
255
256/* enable PLL KICKSTART workaround; useful for IPSTB or excessive jitter streams */
257#if (BCHP_CHIP == 7038) || (BCHP_CHIP == 7401)
258#define BHDM_CONFIG_PLL_KICKSTART_WORKAROUND 1
259#endif
260
261
262/*
263** Time to wait for HDCP An Value to be generated by core
264** the value should be generated within 1 frame
265** default value of 50ms here is about
266*/
267#define BHDM_HDCP_CONFIG_AN_TIMEOUT_MS 50
268
269#define BHDM_CONFIG_HDMI_3D_SUPPORT 1
270
271/* available debug options; enables BDBG_MSGs etc.  */
272#define BHDM_CONFIG_DEBUG_HDMI_PACKETS 0
273#define BHDM_CONFIG_DEBUG_GCP_PACKET_USAGE 0
274#define BHDM_CONFIG_DEBUG_AVI_INFOFRAME 0
275#define BHDM_CONFIG_DEBUG_AUDIO_INFOFRAME 0
276#define BHDM_CONFIG_DEBUG_VENDOR_SPECIFIC_INFOFRAME 0
277#define BHDM_CONFIG_DEBUG_SPD_INFOFRAME 0
278#define BHDM_CONFIG_DEBUG_FIFO 0
279#define BHDM_CONFIG_DEBUG_HDCP_BCAPS 0
280#define BHDM_CONFIG_DEBUG_EDID_VSDB 0
281#define BHDM_CONFIG_DEBUG_EDID_3DSTRUCT 0
282#define BHDM_CONFIG_DEBUG_EDID_3DMASK 0
283
284
285#define BHDM_CONFIG_DEBUG_EDID_PROCESSING 0
286
287#define BHDM_CONFIG_REPEATER_SIMULATION_TEST 0
288#define BHDM_CONFIG_LINK_INTEGRITY_FAILURE_SIMULATION 0
289
290#define BHDM_CONFIG_DEBUG_PJ_CHECKING 0
291
292#define BHDM_CONFIG_DEBUG_TMDS 0
293#define BHDM_CONFIG_DEBUG_RSEN 0
294
295
296
297/******************************************************************/
298/* chip revision specific configuration - DO NOT MODIFY ANY BELOW */
299/******************************************************************/
300
301
302/***************************************
303        BHDM_CONFIG_DVO_SUPPORT
304        - compile for HDMI Transmitter Core
305*/
306#define BHDM_CONFIG_TX 1
307
308#if ((BCHP_CHIP == 7400) && (BCHP_VER >= BCHP_VER_B0)) \
309||   (BCHP_CHIP == 7405) || (BCHP_CHIP == 7325) || (BCHP_CHIP == 7335) \
310||   (BCHP_CHIP == 7336) || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) \
311||   (BCHP_CHIP == 7420) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
312||   (BCHP_CHIP == 7208) || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) \
313||   (BCHP_CHIP == 7601) || (BCHP_CHIP == 7630) \
314||   (BCHP_CHIP == 7635)
315#define BHDM_CONFIG_65NM_SUPPORT 1
316#endif
317
318
319
320/* *NEW* */
321#if ((BCHP_CHIP == 7422) || (BCHP_CHIP == 7425) || (BCHP_CHIP == 7231) \
322||   (BCHP_CHIP == 7358) || (BCHP_CHIP == 7344) || (BCHP_CHIP == 7346) \
323||   (BCHP_CHIP == 7552) || (BCHP_CHIP == 7640) \
324||   (BCHP_CHIP == 7429) || (BCHP_CHIP == 7435) || (BCHP_CHIP == 7360))
325
326#define BHDM_CONFIG_40NM_SUPPORT 1
327#define BHDM_CONFIG_SCHEDULER_REV_2 1
328#define BHDM_CONFIG_HDCP_ADVANCED_HW_AUTO_RI_PJ_SUPPORT 1
329
330#else
331
332#define BHDM_CONFIG_CEC_LEGACY_SUPPORT 1
333#endif
334
335
336#if (((BCHP_CHIP == 7422) || (BCHP_CHIP == 7425) || (BCHP_CHIP == 7231) \
337||    (BCHP_CHIP == 7358) || (BCHP_CHIP == 7344) || (BCHP_CHIP == 7346) \
338||    (BCHP_CHIP == 7640)) \
339&&    (BCHP_VER < BCHP_VER_B0)) \
340|| (BCHP_CHIP == 7552)
341
342#define BHDM_CONFIG_SINGLE_CEC_INTERRUPT  1
343#endif
344
345
346#if ((BCHP_VER >= BCHP_VER_B0) \
347&&    ((BCHP_CHIP == 7422) || (BCHP_CHIP == 7425) || (BCHP_CHIP == 7231) \
348||     (BCHP_CHIP == 7358) || (BCHP_CHIP == 7344) || (BCHP_CHIP == 7346) \
349||     (BCHP_CHIP == 7640))) \
350|| (BCHP_CHIP == 7429) || (BCHP_CHIP == 7435) || (BCHP_CHIP == 7360)
351#define BHDM_CONFIG_DUAL_CEC_TXRX_INTERRUPT 1
352#define BHDM_CONFIG_PIXEL_OVERRIDE_UPDATE 1
353#define BHDM_CONFIG_CLOCK_STOP_SUPPORT 1
354#endif
355
356
357#if (BCHP_CHIP == 7435) || (BCHP_CHIP == 7436) || (BCHP_CHIP == 7360)
358#define BHDM_CONFIG_DUAL_HPD_SUPPORT 1
359#endif
360
361
362 /* 7231, 7358 and 7552 requires swapping of the HDMI_TX_PHY channel settings
363        The default values/settings do not work */
364#if (BCHP_CHIP == 7231) || (BCHP_CHIP == 7358) || (BCHP_CHIP == 7552)           
365#define BHDM_CONFIG_SWAP_DEFAULT_PHY_CHANNELS 1
366
367#if (BCHP_CHIP == 7358) || (BCHP_CHIP == 7552)
368#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_INV 0
369#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_INV 0
370#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_INV 0
371#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_INV 0
372
373#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL 2
374#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL 3
375#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL 0
376#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL 1
377#else
378#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_INV 0
379#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_INV 0
380#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_INV 0
381#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_INV 0
382
383#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL 3
384#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL 2
385#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL 1
386#define BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL 0
387#endif
388#endif
389
390
391#if BHDM_CONFIG_65NM_SUPPORT \
392||  BHDM_CONFIG_40NM_SUPPORT
393#define BHDM_CONFIG_RECEIVER_SENSE_SUPPORT 1
394#define BHDM_CONFIG_PRE_EMPHASIS_SUPPORT 1
395#endif
396
397
398
399#if (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7125) \
400||  (BCHP_CHIP == 7340) ||  (BCHP_CHIP == 7342) \
401||  (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) || (BCHP_CHIP == 7550) \
402||  (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
403|| BHDM_CONFIG_40NM_SUPPORT
404#define BHDM_CONFIG_HDMI_1_3_SUPPORT 1
405#endif
406
407
408/* check if a Tx Box is using DVO */
409#if !defined(BHDM_CONFIG_DVO_SUPPORT)
410#if BHDM_ENABLE_DVO
411#define BHDM_CONFIG_DVO_SUPPORT 1
412#endif
413#endif
414
415
416/***************************************
417        BHDM_CONFIG_DISABLE_MUX_VSYNC_ON_AVMUTE
418        - disable mux_vsync when using AvMute in case HDCP is enabled
419        - See PR11060
420****************************************/
421#if (BCHP_CHIP == 7038) \
422        && ((BCHP_VER <= BCHP_VER_B1))
423#define BHDM_CONFIG_DISABLE_MUX_VSYNC_ON_AVMUTE 1
424#endif
425
426
427/***************************************
428        BHDM_CONFIG_DISABLE_HDCP_AUTH_REPEATER_DEVCOUNT0
429        - revoke authentication for repeaters with an attached device count of 0
430        - See PR15217
431***************************************/
432#if (BCHP_CHIP == 7038) \
433        && (((BCHP_VER >= BCHP_VER_B0) && (BCHP_VER <= BCHP_VER_B2)) \
434        ||        ((BCHP_VER <= BCHP_VER_C1)))
435
436#define BHDM_CONFIG_DISABLE_HDCP_AUTH_REPEATER_DEVCOUNT0 1
437#endif
438
439
440/***************************************
441        BHDM_CONFIG_DRIVER_AMP_DEFAULT
442****************************************/
443#if (BCHP_CHIP == 7038)
444
445#if BCHP_VER <= BCHP_VER_B2
446#define BHDM_CONFIG_DRIVER_AMP_DEFAULT 6
447
448#elif BCHP_VER >= BCHP_VER_C0
449#define BHDM_CONFIG_DRIVER_AMP_DEFAULT 4
450
451#else
452#error "Unknown 7038 revision; need to specify PREDRIVER_AMP_DEFAULT value"
453#endif
454
455#elif (BCHP_CHIP == 7438) || (BCHP_CHIP == 7440) || (BCHP_CHIP == 7403)
456#define BHDM_CONFIG_DRIVER_AMP_DEFAULT 5
457
458#elif (BCHP_CHIP == 7401)
459#define BHDM_CONFIG_DRIVER_AMP_DEFAULT 4
460
461#elif ((BCHP_CHIP == 7400) && (BCHP_VER >= BCHP_VER_B0)) || (BCHP_CHIP == 7405) \
462        || (BCHP_CHIP == 7325) || (BCHP_CHIP == 7335) || (BCHP_CHIP == 7336)
463#define BHDM_CONFIG_DRIVER_AMP_DEFAULT 3
464
465#elif (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
466   || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
467   || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
468   || BHDM_CONFIG_40NM_SUPPORT
469#define BHDM_CONFIG_DRIVER_AMP_DEFAULT 5
470
471#elif !defined(BHDM_CONFIG_TX)
472        /* not used */
473#else
474#error "New/Unknown chip; no PREDRIVER_AMP_DEFAULT value"
475#endif
476
477
478/***************************************
479        BHDM_CONFIG_DVO_7038BX_VERSION
480
481        changes DVO pins in starting in 7038 C0
482***************************************/
483
484#if (BCHP_CHIP == 7038)
485
486#if (BCHP_VER >=  BCHP_VER_B0) && (BCHP_VER <= BCHP_VER_B2)
487#define BHDM_CONFIG_DVO_7038BX_VERSION 1
488#else
489#define BHDM_CONFIG_DVO_7038CX_VERSION 1
490#endif
491
492#elif (BCHP_CHIP == 7401)
493#define BHDM_CONFIG_DVO_7401_VERSION 1
494#endif
495
496
497/***************************************
498        BHDM_CONFIG_RDB_NAME_FIX
499*/
500
501#if (BCHP_CHIP == 7038) || (BCHP_CHIP == 7438) || (BCHP_CHIP == 3560)
502#define BHDM_CONFIG_RDB_NAME_FIX 1
503#endif
504
505
506/***************************************
507        BHDM_CONFIG_88_2KHZ_AUDIO_SUPPORT
508***************************************/
509#if ((BCHP_CHIP == 7038) && (BCHP_VER >= BCHP_VER_C0))  || (BCHP_CHIP == 7438) \
510        || (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
511        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
512        || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
513        || BHDM_CONFIG_40NM_SUPPORT
514#define BHDM_CONFIG_88_2KHZ_AUDIO_SUPPORT 1
515#endif
516
517
518/***************************************
519        BHDM_CONFIG_96KHZ_AUDIO_SUPPORT
520***************************************/
521#if (BCHP_CHIP == 7438) ||      (BCHP_CHIP == 7440) || (BCHP_CHIP==7400) || (BCHP_CHIP == 7405) \
522        || (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
523        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
524        || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
525        || BHDM_CONFIG_40NM_SUPPORT
526#define BHDM_CONFIG_96KHZ_AUDIO_SUPPORT 1
527#endif
528
529
530/***************************************
531        BHDM_CONFIG_176_4KHZ_AUDIO_SUPPORT
532***************************************/
533#if ((BCHP_CHIP == 7038) && (BCHP_VER >= BCHP_VER_C0))  \
534        || (BCHP_CHIP == 7438) ||  (BCHP_CHIP == 7405) || (BCHP_CHIP == 7400) \
535        || (BCHP_CHIP == 7335) || (BCHP_CHIP == 7336) || ((BCHP_CHIP == 7325) && (BCHP_VER >= BCHP_VER_B0)) \
536        || (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
537        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
538        || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
539        || BHDM_CONFIG_40NM_SUPPORT
540#define BHDM_CONFIG_176_4KHZ_AUDIO_SUPPORT 1
541#endif
542
543
544/***************************************
545        BHDM_CONFIG_192KHZ_AUDIO_SUPPORT
546***************************************/
547#if ((BCHP_CHIP == 7038) && (BCHP_VER >= BCHP_VER_C0))  || (BCHP_CHIP == 7438) \
548        || (BCHP_CHIP == 7440) || (BCHP_CHIP == 7443) || (BCHP_CHIP==7400) || (BCHP_CHIP == 7405) \
549        || (BCHP_CHIP == 7335) || (BCHP_CHIP == 7336) || (BCHP_CHIP == 7325) || (BCHP_CHIP == 7401) \
550        || (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
551        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
552        || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
553        || BHDM_CONFIG_40NM_SUPPORT
554#define BHDM_CONFIG_192KHZ_AUDIO_SUPPORT 1
555#endif
556
557
558/***************************************
559        BHDM_CONFIG_1080P_5060HZ_SUPPORT
560
561        7340/7342/7408/7208 uses dvp_ht_lite core, does not support 1080p/60 & 1080p/50
562***************************************/
563#if (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
564        || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) || (BCHP_CHIP == 7468) \
565        || BHDM_CONFIG_40NM_SUPPORT
566#define BHDM_CONFIG_1080P_5060HZ_SUPPORT 1
567#endif
568
569
570/***************************************
571        BHDM_CONFIG_1366_FORMAT_CHECK
572**************************************/
573#if !((BCHP_CHIP == 7401) || (BCHP_CHIP == 7038))
574#define BHDM_CONFIG_1366_FORMAT_CHECK 1
575#endif
576
577
578#if BHDM_CEC_SUPPORT
579/***************************************
580        BHDM_CONFIG_CEC_DEVICE_TYPE
581**************************************/
582#if (BCHP_CHIP == 7438) || (BCHP_CHIP == 7440) || (BCHP_CHIP == 7601) \
583        || (BCHP_CHIP==7635) || (BCHP_CHIP == 7630) || (BCHP_CHIP == 7640)
584#define BHDM_CONFIG_CEC_DEVICE_TYPE 0x04
585#else
586#define BHDM_CONFIG_CEC_DEVICE_TYPE 0x03
587#endif
588
589
590/***************************************
591        Uninitialized CEC logical address
592**************************************/
593#define BHDM_CONFIG_CEC_UNINITIALIZED_LOGICAL_ADDR 0xFF
594
595
596/***************************************
597        Older platforms use CEC PAD_SW_RESET register
598        7601/7420 and newer platforms no longer use this.
599*/
600#if (BCHP_CHIP == 7038) || (BCHP_CHIP == 7438) || (BCHP_CHIP == 7440) || (BCHP_CHIP==7400) \
601        || (BCHP_CHIP == 7401) || (BCHP_CHIP == 7405) || (BCHP_CHIP == 7335) || (BCHP_CHIP == 7336) \
602        || (BCHP_CHIP == 7325)
603#define BHDM_CONFIG_CEC_USE_PAD_SW_RESET 1
604#endif
605
606
607#endif
608
609
610/***************************************
611        Broadcom Supported audio formats;
612        use to determine support for Audio Formats specified in EDID   
613**************************************/
614#if (BCHP_CHIP == 7401) || (BCHP_CHIP == 7400) || (BCHP_CHIP == 7402) || (BCHP_CHIP == 7403) \
615        || (BCHP_CHIP == 7405) || (BCHP_CHIP == 7325) || (BCHP_CHIP == 7335) || (BCHP_CHIP == 7336) \
616        || (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
617        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) || (BCHP_CHIP == 7550) \
618        || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
619        || BHDM_CONFIG_40NM_SUPPORT
620#define BHDM_CONFIG_AUDIO_SUPPORT_DDP 1
621#endif
622
623
624#if (BCHP_CHIP == 7401) ||      (BCHP_CHIP == 7400) || (BCHP_CHIP == 7402) || (BCHP_CHIP == 7403) \
625        || (BCHP_CHIP == 7405) || (BCHP_CHIP == 7325) || (BCHP_CHIP == 7335) || (BCHP_CHIP == 7336)
626#define BHDM_CONFIG_AUDIO_SUPPORT_WMAPRO 1
627#endif
628
629
630#if  (BCHP_CHIP == 7440) || (BCHP_CHIP == 7601) || (BCHP_CHIP == 7420) || (BCHP_CHIP == 7635) \
631        || (BCHP_CHIP == 7630) || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) || (BCHP_CHIP == 7125) \
632        || (BCHP_CHIP == 7550) || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
633        || BHDM_CONFIG_40NM_SUPPORT
634#define BHDM_CONFIG_AUDIO_SUPPORT_DTSHD 1
635#define BHDM_CONFIG_AUDIO_SUPPORT_MATMLP 1
636#endif
637
638
639/***************************************
640        Force sending ENC_DIS signal from PI
641        if this is not handled by the hardware
642***************************************/
643#if ((BCHP_CHIP==7400) && (BCHP_VER>=BCHP_VER_E0))
644        /* Do not force ENC_DIS/ENC_EN signal */
645#else
646#define BHDM_CONFIG_HDCP_FORCE_ENC_SIGNAL 1
647#endif
648
649
650/***************************************
651        BHDM_CONFIG_AUTO_RI_PJ_CHECK
652***************************************/
653#if ((BCHP_CHIP == 7601) && (BCHP_VER >= BCHP_VER_B0)) \
654        || (BCHP_CHIP == 7420) || (BCHP_CHIP==7125) \
655        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) \
656        || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
657        || (BCHP_CHIP == 7550) || (BCHP_CHIP == 7408) \
658        || (BCHP_CHIP == 7468) || (BCHP_CHIP == 7208) \
659        || BHDM_CONFIG_40NM_SUPPORT
660#define BHDM_CONFIG_HDCP_AUTO_RI_PJ_CHECKING_SUPPORT 1
661#endif
662
663
664/***************************************
665        BHDM_CONFIG_AUDIO_MAI_BUS_DISABLE_SUPPORT
666**************************************/
667#if ((BCHP_CHIP == 7601) && (BCHP_VER >= BCHP_VER_B0)) \
668        || (BCHP_CHIP == 7420) || (BCHP_CHIP==7125) \
669        || (BCHP_CHIP == 7340) || (BCHP_CHIP == 7342) \
670        || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) \
671        || (BCHP_CHIP == 7550) || (BCHP_CHIP == 7468) \
672        || (BCHP_CHIP == 7408) || (BCHP_CHIP == 7208) \
673        || BHDM_CONFIG_40NM_SUPPORT
674#define BHDM_CONFIG_AUDIO_MAI_BUS_DISABLE_SUPPORT 1
675#endif
676
677
678/***************************************
679        BHDM_CONFIG_REGISTER_GCP_FOR_AV_MUTE
680        use Register based General Control Packet (GCP)
681        vs RAM Packet based General Control Packet
682***************************************/
683#if BHDM_CONFIG_40NM_SUPPORT
684#define BHDM_CONFIG_REGISTER_GCP_FOR_AV_MUTE 1
685#endif
686
687
688/***************************************
689        BHDM_CONFIG_BLURAY_PLATFORMS
690***************************************/
691#if (BCHP_CHIP == 7601) || (BCHP_CHIP == 7635) || (BCHP_CHIP == 7630) || (BCHP_CHIP == 7640)
692#define BHDM_CONFIG_BLURAY_PLATFORMS
693#endif
694
695
696/*****************************************
697        PRE-EMPHASIS Settings to work around bad PLL in some 40nm
698        A0 platforms. This hardware     issue is fixed in December 2010
699******************************************/
700#if (((BCHP_CHIP == 7422) || (BCHP_CHIP == 7425) || (BCHP_CHIP == 7231) \
701        || (BCHP_CHIP == 7344) || (BCHP_CHIP == 7346) || (BCHP_CHIP == 7640)) \
702        && (BCHP_VER < BCHP_VER_A1))
703#define BHDM_CONFIG_40NM_PREEMP_WORKAROUND      1
704#endif
705
706
707/***************************************
708        BHDM_CONFIG_AUDIO_MAI_BUS_CHANNEL_MAP_1TO1
709***************************************/
710#ifdef BHDM_CONFIG_BLURAY_PLATFORMS
711#define BHDM_CONFIG_AUDIO_MAI_BUS_CHANNEL_MAP_1TO1 1
712#endif
713
714
715#endif /* BHDM_CONFIG_H__ */
716
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