source: svn/newcon3bcm2_21bu/magnum/portinginterface/thd/7552/bthd_acq_dvbt.c

Last change on this file was 76, checked in by megakiss, 10 years ago

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1/******************************************************************************
2*     (c)2010-2012 Broadcom Corporation
3* 
4*  This program is the proprietary software of Broadcom Corporation and/or its licensors,
5*  and may only be used, duplicated, modified or distributed pursuant to the terms and
6*  conditions of a separate, written license agreement executed between you and Broadcom
7*  (an "Authorized License").  Except as set forth in an Authorized License, Broadcom grants
8*  no license (express or implied), right to use, or waiver of any kind with respect to the
9*  Software, and Broadcom expressly reserves all rights in and to the Software and all
10*  intellectual property rights therein.  IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11*  HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12*  NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE. 
13*   
14*  Except as expressly set forth in the Authorized License,
15*   
16*  1.     This program, including its structure, sequence and organization, constitutes the valuable trade
17*  secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof,
18*  and to use this information only in connection with your use of Broadcom integrated circuit products.
19*   
20*  2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
21*  AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR
22*  WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
23*  THE SOFTWARE.  BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES
24*  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE,
25*  LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION
26*  OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF
27*  USE OR PERFORMANCE OF THE SOFTWARE.
28* 
29*  3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS
30*  LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR
31*  EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR
32*  USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF
33*  THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT
34*  ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE
35*  LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF
36*  ANY LIMITED REMEDY.
37*
38 *****************************************************************************/
39/***************************************************************************
40*     (c)2005-2012 Broadcom Corporation
41* 
42*
43* $brcm_Workfile: bthd_acq_dvbt.c $
44* $brcm_Revision: 32 $
45* $brcm_Date: 3/23/12 12:44p $
46*
47* [File Description:]
48*
49* Revision History:
50*
51* $brcm_Log: /AP/ctfe/core/thd/bthd_acq_dvbt.c $
52*
53* 32   3/23/12 12:44p farshidf
54* SW3128-125: FW version 4.6
55*
56* Fw_Integration_Devel/14   3/23/12 12:44p farshidf
57* SW3128-125: FW version 4.6
58*
59* Fw_Integration_Devel/AP_V4_0_THD_DEV/3   3/13/12 3:32p farshidf
60* SW3462-6: merge to dev
61*
62* Fw_Integration_Devel/AP_V4_0_THD_DEV/SW3462-6/1   2/29/12 5:26p farshidf
63* SW3461-165 : Chip version clean up & fix tuner for 3462
64*
65* Fw_Integration_Devel/AP_V4_0_THD_DEV/1   2/16/12 5:34p hfu
66* SW3461-149: Make sure THD go to THD_State_CheckLock state to avoid
67*  missing RS SYNC.
68*
69* 29   2/9/12 3:01p farshidf
70* SW7552-205: remove warning
71*
72* 28   1/25/12 4:11p farshidf
73* SW3461-110: merge to integ/main
74*
75* Fw_Integration_Devel/11   1/25/12 4:10p farshidf
76* SW3461-110: merge to integ/main
77*
78* Fw_Integration_Devel/AP_V3_0_THD_DEV/12   1/24/12 3:33p mpovich
79* SW3461-110:  Modify THD acquisition logic to abort during various
80*  stages if expected events (flagged by register reads) do not occur
81*  within expected timeframe.
82*
83* Fw_Integration_Devel/AP_V3_0_THD_DEV/11   1/24/12 3:26p mpovich
84* SW3461-110:  Modify THD acquisition logic to abort during various
85*  stages if expected events (flagged by register reads) do not occur
86*  within expected timeframe.
87*
88* Fw_Integration_Devel/AP_V3_0_THD_DEV/10   1/6/12 1:54p farshidf
89* SW3461-40: merge to Dev branch
90*
91* Fw_Integration_Devel/AP_V3_0_THD_DEV/SW3461-40/5   12/29/11 2:53p mpovich
92* SW3461-40: Rebase with DEV branch.
93*
94* Fw_Integration_Devel/AP_V3_0_THD_DEV/9   12/21/11 2:49p farshidf
95* SW7552-170: merge to dev
96*
97* 26   12/21/11 2:33p farshidf
98* SW7552-170:remove warning
99*
100* 25   12/15/11 2:14p farshidf
101* SW3461-118: merge to main
102*
103* Fw_Integration_Devel/9   12/15/11 12:24p farshidf
104* SW3461-118: merge to integ
105*
106* Fw_Integration_Devel/AP_V3_0_THD_DEV/8   12/7/11 11:37a hfu
107*  SW3461-88: Turn off impulsive noise canceller bypass when ImpulseMode
108*  is auto.
109*
110* Fw_Integration_Devel/AP_V3_0_THD_DEV/7   11/3/11 3:08p hfu
111* SW3461-73: Change FW min_scale from 1.5  to 1.125 in P_DvbtSetFwFtt().
112*
113* Fw_Integration_Devel/AP_V3_0_THD_DEV/SW3461-40/4   11/1/11 2:45p mpovich
114* SW3461-40: Rebase with devel. branch.
115*
116* Fw_Integration_Devel/AP_V3_0_THD_DEV/6   10/28/11 12:12p farshidf
117* SW3461-75: Move to new IRQ handling
118*
119* Fw_Integration_Devel/AP_V3_0_THD_DEV/5   10/27/11 5:32p jputnam
120* SW3461-73: Improve acquisition probability by: (1) Add FW_REF_RST in
121*  P_AcquireTrack() to match deployed 7550 firmware, (2) Change FW
122*  min_scale from 1.125 to 1.5 in P_DvbtSetFwFtt(), and (3) Enable FW
123*  slip during acquisition in  P_DvbtSetFwFtt() (disabled later in
124*  tracking)
125*
126* Fw_Integration_Devel/AP_V3_0_THD_DEV/SW3461-40/3   10/27/11 2:33p mpovich
127* SW3461-40: Abort-Early for THD acquire (Initial
128*  concept/implementation).
129*
130* Fw_Integration_Devel/AP_V3_0_THD_DEV/SW3461-40/2   10/27/11 11:32a mpovich
131* SW3461-40: Abort-Early for THD acquire (Initial
132*  concept/implementation).
133*
134* Fw_Integration_Devel/AP_V3_0_THD_DEV/SW3461-40/1   10/24/11 10:02p mpovich
135* SW3461-40: Abort-Early for THD acquire (Initial
136*  concept/implementation).
137*
138* Fw_Integration_Devel/AP_V3_0_THD_DEV/4   10/19/11 6:29p hfu
139* SW3461-65: BER in BBS jumps after 3 minutes for DVB-T.  Code change to
140*  prevent 32-bit variable overflow during the VitBer calculation. So the
141*  VitBer will be correct until total number of packets counter reaches
142*  its limit.
143*
144* Fw_Integration_Devel/AP_V3_0_THD_DEV/3   10/14/11 12:32a farshidf
145* SW3461-64: merge warning fix
146*
147* 22   10/14/11 12:27a farshidf
148* SW3461-64: fix warning
149*
150* 21   10/13/11 11:52p farshidf
151* SW3461-64: merge to main
152*
153* Fw_Integration_Devel/7   10/13/11 6:57p farshidf
154* SW3461-64: merge to integ
155*
156* Fw_Integration_Devel/AP_V3_0_THD_DEV/2   10/12/11 5:39p hfu
157* SW3461-61. BER changes in DVBT QAM64, 2/3, 2k mode after retune is
158*  performed.   FW fix: 2K mode cci_threshold changed from 0xC to 0xF. In
159*  addition to the adding delay time before DvbtGetNotch() from 32 to 64
160*  for 2K mode which is made in bthd_acq.c
161*
162* Fw_Integration_Devel/AP_V3_0_THD_DEV/1   9/26/11 2:40p mbsingh
163* SW3461-1: Merge from 2.0 dev branch (This is mainly a shift to WPO
164*  algorithm)
165*
166* Fw_Integration_Devel/AP_V2_0_THD_DEV/7   9/21/11 5:39p mbsingh
167* SW3461-1: Fix the regression crash issue due to getting stuck in state
168*  machine
169*
170* Fw_Integration_Devel/AP_V2_0_THD_DEV/6   9/14/11 4:58p mbsingh
171* - Fix function naming
172*
173* Fw_Integration_Devel/AP_V2_0_THD_DEV/5   9/9/11 6:10p mbsingh
174* SW3461-1:  - Removed MAXPEAK stuff
175*
176* Fw_Integration_Devel/AP_V2_0_THD_DEV/4   9/8/11 10:49p mbsingh
177* SW3461-1:  Separated SetFW function cleanly now to make DVBT work for
178*  ISDBT containing chips also.  In initial merged code from THD_FTT_WPO
179*  branch DVBT would work only in non ISDBT chips due to wrong SetFW
180*  function selection
181*
182* Fw_Integration_Devel/AP_V2_0_THD_DEV/3   9/8/11 10:06p mbsingh
183* SW3461-1: Merging from THD_FTT_WPO branch                   -
184*  Architectural change to new FTT algo for acquisition
185*
186* Fw_Integration_Devel/AP_V0_6_THD_DEV/Thd_ftt_wpo/2   8/24/11 10:55a hzou
187* Updated state machine to do FFTTrigger after 1st TPS synch, and only
188*  redo TPS synch is missing 1st peak or having on-the-guard echos
189*
190* Fw_Integration_Devel/AP_V0_6_THD_DEV/Thd_ftt_wpo/1   8/18/11 10:55a hzou
191* Ported change for FTT and WPO
192*
193* Fw_Integration_Devel/6   8/24/11 5:47p farshidf
194* SW7552-60: add the isdb-t constellation
195*
196* Fw_Integration_Devel/AP_V2_0_THD_DEV/2   8/24/11 5:41p farshidf
197* SW7552-60: add the softdecision for isdbt
198*
199* 18   8/24/11 12:33p farshidf
200* SW3461-38: merge to main
201*
202* Fw_Integration_Devel/5   8/24/11 12:07p farshidf
203* SW3461-38: merge to integ
204*
205* Fw_Integration_Devel/AP_V2_0_THD_DEV/1   8/22/11 12:45p jputnam
206* SW3461-1: Added SmartTune
207*
208* Fw_Integration_Devel/4   8/17/11 4:05p farshidf
209* SW3461-1: update the printf
210*
211* 17   8/17/11 4:04p farshidf
212* SW3461-1: update the printf
213*
214* 16   8/12/11 3:14p farshidf
215* SW3461-1: merge to main
216*
217* Fw_Integration_Devel/2   8/12/11 2:11p farshidf
218* SW3461-1: merge to integ
219*
220* Fw_Integration_Devel/AP_V0_6_THD_DEV/2   8/10/11 4:33p farshidf
221* SW3461-1: update the events creation to be able to run T and T2
222*
223* Fw_Integration_Devel/AP_V0_6_THD_DEV/1   8/10/11 3:45p farshidf
224* SW3461-1: update status printf
225*
226* Fw_Integration_Devel/1   6/29/11 12:39p farshidf
227* SW3461-13: merge to integration branch
228*
229* Fw_Integration_Devel/Dvbt_Fw_Devel_Rc05/1   6/15/11 10:42a jchien
230* DVBT_FW_Devel_Rc05: fix a bug in state_Track from code porting
231*
232* 14   6/8/11 6:24p farshidf
233* SW3461-1: merge main
234*
235* Dvb_Fw_Devel_4/1   6/8/11 5:20p farshidf
236* SW3461-1: sync up with backend chip
237*
238* Hydra_Software_Devel/4   6/1/11 11:48a farshidf
239* SW7552-36: clean up
240*
241* Hydra_Software_Devel/3   5/27/11 10:52a farshidf
242* SW7552-36: compiel fix
243*
244* Hydra_Software_Devel/2   5/5/11 12:31p farshidf
245* SWDTV-6857: latest DVB-T code from 3461 label FW_3461_A0_05032011_1344
246*
247* 13   5/3/11 1:36p mpovich
248* SW3461-1: Merge to main of intermediate label, FW_3461_A0_05022011_1100
249*  (05/02/2011 Pace build).
250*
251* DVB_3461_1/10   4/27/11 8:30a jputnam
252* SW3461-1:  Added #define ChangeFFTWindowSeamless for experimentation
253*  with seamless FW switching to improve acquisition time
254*
255* DVB_3461_1/9   4/26/11 9:21p jputnam
256* SW3461-1: Removed code associated with frequency-domain FFT trigger
257*  algorithm.  Development moved to another branch. Removed unconditional
258*  return value of THD_AcquireResult_Lock in AcquireCheckLock() function
259*
260* 12   4/21/11 6:03p farshidf
261* SW3461-1: merge main
262*
263* DVB_3461_1/8   4/21/11 6:02p farshidf
264* SW3461-1: merge main
265*
266* 11   4/21/11 6:01p farshidf
267* SW3461-1: make the files host compatible
268*
269* 10   4/21/11 5:28p farshidf
270* SW3461-1: make it host compatible
271*
272* 9   4/20/11 4:56p farshidf
273* SW3461-1: make it host compatible
274*
275* 8   4/19/11 12:03p farshidf
276* SW3461-1: make host compatible
277*
278* 7   4/11/11 3:50p farshidf
279* SW3461-1: merge main
280*
281* DVB_3461_1/5   4/11/11 9:16a jputnam
282* SW3461-1: Functional CoChannel mode
283*
284* DVB_3461_1/4   4/8/11 11:57a jputnam
285* SW3461-1: Automatic ChannelEstimatorMode functional
286*
287* DVB_3461_1/3   4/7/11 10:59p jputnam
288* SW3461-1: Removed obsolete lock functions.  Reverted state machine so
289*  that SP, TPS, and FEC states are revisited upon FFTWindowMode change.
290*  Force RS_SYNC_LOSS interrupt if P_Acquire returns without locking to
291*  force proper update of lock state.
292*
293* DVB_3461_1/2   4/7/11 9:29p jputnam
294* SW3461-1: Initial version of interrupt-based lock detection
295*
296* DVB_3461_1/1   4/5/11 9:14p jputnam
297* SW3461-1: Revamped P_Lock and P_DvbtLock functions. Added proper Acq
298*  and Ret thresholds for RS lock detectors. Cosmetic clean-up of code
299*  and printfs.
300*
301* 4   3/10/11 8:02p jputnam
302* SW3461-1: Abbreviated debug messages
303*
304* 3   3/8/11 12:39p farshidf
305* SW3461-1: fix teh THD API
306*
307* 2   1/24/11 2:32p farshidf
308* SW3461-1: stop the stream when BCHP_THD_INTR_AP_SET is set to 0x80
309*
310* 1   1/6/11 10:01a jputnam
311* SW3461-1: Separated DVB-T specific functions into dedicated file
312*
313*
314***************************************************************************/
315#include "bstd.h"
316#include "bmth.h"
317#include "bkni.h"
318#include "btmr.h"
319#ifndef LEAP_BASED_CODE
320#include "bthd_3x7x.h"
321#endif
322#include "bchp_thd_core.h"
323#include "bthd_api.h"
324#include "bthd_acq.h"
325#include "bthd_acq_dvbt.h"
326#include "bthd_coef.h"
327
328#include "bchp_thd_intr2.h"
329#include "bchp_thd_intr2b.h"
330#ifdef LEAP_BASED_CODE
331#include "bchp_leap_ctrl.h"
332#include "bthd_irq.h"
333#endif
334
335#ifndef LEAP_BASED_CODE
336BDBG_MODULE(bthd_acq_dvbt);
337#endif
338
339/***************************************************************************
340 * BTHD_P_DvbtSetFWFtt()
341 ***************************************************************************/
342void BTHD_P_DvbtSetFWFtt( BTHD_3x7x_Handle h, 
343                   THD_FFTWindowMode_t FFTWindowMode, 
344                   THD_TransmissionMode_t TransmissionMode, 
345                   THD_GuardInterval_t GuardInterval)
346{
347
348  uint32_t fw=0,fw_search=0,N=bthd_transmission_mode[TransmissionMode];
349  BSTD_UNUSED(FFTWindowMode);
350  BSTD_UNUSED(GuardInterval);
351
352  /* First Peak */
353  fw_search = 0x11202000 | (8 * (N/2048));  /* FFT window min_scale=1.125 (0.5dB),start_index_mode=1,1st peak mode,L=8*N/2048 */
354  /* fw_search = 0x11802000 | (8 * (N/2048)); */  /* FFT window min_scale=1.5,start_index_mode=1,1st peak mode,L=8*N/2048*/
355  /*fw = 0x03214050; */  /* Decrease average beta from 2^(-7) to 2^(-6) for freq-domain trigger position algorithm for faster convergence time */
356  fw = 0x03214051; /* Decrease average beta from 2^(-7) to 2^(-6) for freq-domain trigger position algorithm for faster convergence time, enable slip */
357
358  /* Disable expanded search mode for GI=1/4 due to acquisition instability */
359  /* if (GuardInterval == 3) */
360  fw = fw & 0xfcffffff;
361
362#ifdef FASTACQ
363  fw = (fw & 0xffff00ff) | 0x00002000;
364#endif
365  BREG_Write32(h->hRegister,  BCHP_THD_CORE_FW,fw );
366  BREG_Write32(h->hRegister,  BCHP_THD_CORE_FW_SEARCH,fw_search);
367  BREG_Write32(h->hRegister,  BCHP_THD_CORE_FW_OFFSET,0x00000010 );  /* FFT window offset=16 */
368  BREG_Write32(h->hRegister,  BCHP_THD_CORE_FW_SPAN,0x00000200 );      /* FFT window span scale = 0.25 */
369}
370
371
372/******************************************************************************
373 * BTHD_P_GetDvbtSoftDecisionBuf()
374 ******************************************************************************/
375BERR_Code BTHD_P_GetDvbtSoftDecisionBuf(BTHD_3x7x_Handle h,  /* [in] BTHD handle */
376    int16_t nbrToGet,                 /* [in] Number values to get */
377    int16_t *pI,                      /* [out] Ptr to array to store output I soft decision */
378    int16_t *pQ,                      /* [out] Ptr to array to store output Q soft decision */
379    int16_t *nbrGotten                /* [out] Number of values gotten/read */
380    )
381{
382
383  uint32_t val, tps;
384  uint8_t idx=0;
385  uint32_t N = bthd_transmission_mode[BREG_ReadField(h->hRegister, THD_CORE_TPS_OV, TRANS_MODE )];
386  uint32_t GuardInterval = BREG_ReadField(h->hRegister, THD_CORE_TPS_OV, GUARD);
387  BSTD_UNUSED(nbrGotten);
388  BSTD_UNUSED(nbrToGet);
389 
390  tps = BREG_Read32(h->hRegister, BCHP_THD_CORE_TPS);
391  tps &= BCHP_THD_CORE_TPS_QAM_MASK;
392  tps >>= BCHP_THD_CORE_TPS_QAM_SHIFT;
393 
394  while (idx < 30) {
395    val = BREG_Read32(h->hRegister, BCHP_THD_CORE_SOFT_READ_DATA);
396    pI[idx] = (int16_t)((val & 0xFFFC0000) >> (14+tps));
397    pQ[idx] = (int16_t)((val & 0x0003fFF0) >> tps);
398    idx++;
399    BTHD_P_OSleep(h,1,N,GuardInterval);
400  }
401
402  return BERR_SUCCESS;
403}
404/***************************************************************************
405 * BTHD_P_DvbtSetMode()
406 ***************************************************************************/
407void BTHD_P_DvbtSetMode( BTHD_3x7x_Handle h, 
408                         THD_TransmissionMode_t TransmissionMode, 
409                         THD_GuardInterval_t GuardInterval, 
410                         THD_Qam_t Qam, 
411                         THD_CodeRate_t CodeRateHP, 
412                         THD_CodeRate_t CodeRateLP, 
413                         THD_DvbtHierarchy_t Hierarchy)
414{
415  uint32_t  tps;
416  tps = (Qam << 4) | (Hierarchy << 8) | (CodeRateHP << 12) | (CodeRateLP << 16) | (GuardInterval << 20) | (TransmissionMode << 24) | (1U << 31);
417  BREG_Write32(h->hRegister, BCHP_THD_CORE_TPS_OV, tps );
418}
419
420/***************************************************************************
421 * BTHD_P_DvbtSetTPS()
422 ***************************************************************************/
423BTHD_RESULT BTHD_P_DvbtSetTPS( BTHD_3x7x_Handle h, 
424                               THD_TransmissionMode_t TransmissionMode, 
425                               THD_GuardInterval_t GuardInterval)
426{
427  BTHD_RESULT return_val = THD_AcquireResult_InitLockState;
428  uint32_t tps,N=bthd_transmission_mode[TransmissionMode];
429  BERR_Code eEventWaitResult;
430
431  BREG_WriteField(h->hRegister, THD_CORE_RST, TPS_RST, 1 ); /* Force TPS reset */
432  BREG_WriteField(h->hRegister, THD_CORE_RST, TPS_RST, 0 ); /* Release TPS reset */
433
434  if (h->pAcquireParam->DvbtAcquireParam.TPSMode == THD_DvbtTPSMode_Manual) {
435    BREG_WriteField(h->hRegister, THD_CORE_TPS_OV, QAM, h->pAcquireParam->DvbtAcquireParam.Qam);
436    BREG_WriteField(h->hRegister, THD_CORE_TPS_OV, HIERARCHY, h->pAcquireParam->DvbtAcquireParam.Hierarchy);
437    BREG_WriteField(h->hRegister, THD_CORE_TPS_OV, CRATE_HP,  h->pAcquireParam->DvbtAcquireParam.CodeRateHP);
438    BREG_WriteField(h->hRegister, THD_CORE_TPS_OV, CRATE_LP,  h->pAcquireParam->DvbtAcquireParam.CodeRateLP);
439  } else {
440#if (BTHD_P_BCHP_THD_CORE_VER == BTHD_P_BCHP_CORE_V_4_0)
441        if (BKNI_CreateEvent(&(h->hTpsSyncEvent)) != BERR_SUCCESS)
442                BDBG_ERR(("Not enough event for hTpsSyncEvent"));
443#endif
444    BINT_EnableCallback( h->hTpsSyncCallback);
445     eEventWaitResult = BTHD_P_WaitForEventOrAbort(h, h->hTpsSyncEvent, 150);
446     /* eEventWaitResult success: return_val, Failure: THD_AcquireResult_NoTPSLock, or,
447     * THD_AcquireResult_AbortedEarly if "Acquire Aborted Early" Event took place */
448     return_val = BTHD_P_MapWaitForEventResult_To_THD_AcqResult(eEventWaitResult, return_val, THD_AcquireResult_NoTPSLock);
449
450
451        BINT_DisableCallback( h->hTpsSyncCallback);
452#if (BTHD_P_BCHP_THD_CORE_VER == BTHD_P_BCHP_CORE_V_4_0)
453        BKNI_DestroyEvent(h->hTpsSyncEvent);
454#endif
455    if (return_val != THD_AcquireResult_NoTPSLock && return_val != THD_AcquireResult_AbortedEarly) {
456      eEventWaitResult = BTHD_P_OSleep(h,1,N,GuardInterval);
457      tps = BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS );
458      tps = (BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS_OV) & 0xfff00000) | (tps & 0x000fffff);
459      BREG_Write32(h->hRegister,  BCHP_THD_CORE_TPS_OV, tps );
460      if ( eEventWaitResult == BTHD_ERR_ACQUIRE_ABORTED ) {
461        return_val = THD_AcquireResult_AbortedEarly;
462      }
463    }
464  }
465  return return_val;
466}
467
468/***************************************************************************
469 * BTHD_P_DvbtSetOI()
470 ***************************************************************************/
471void BTHD_P_DvbtSetOI( BTHD_3x7x_Handle h )
472{
473  const bthd_oi_cw_t *cw;
474  uint32_t tps;
475  THD_GuardInterval_t GuardInterval;
476  THD_Qam_t Qam;
477  THD_DvbtHierarchy_t Hierarchy;
478  THD_CodeRate_t CodeRateLP, CodeRateHP, CodeRate;
479
480  tps = BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS_OV );
481  GuardInterval = (tps >> 20) & 0x3;
482  Qam = (tps >> 4) & 0x3;
483  Hierarchy  = (tps >> 8) & 0x3;
484  CodeRateHP = (tps >> 12) & 0x7;
485  CodeRateLP = (tps >> 16) & 0x7;
486
487  if ( h->pAcquireParam->DvbtAcquireParam.PriorityMode == THD_DvbtPriorityMode_High) {
488    CodeRate = CodeRateHP;
489    if (Hierarchy)
490      Qam = THD_Qam_Qpsk;
491  } else {
492    CodeRate = CodeRateHP;
493    if (Hierarchy)
494      Qam -= 1;
495  }
496 
497  cw = &bthd_oi_table[GuardInterval][Qam][CodeRate];
498  BREG_Write32(h->hRegister,  BCHP_THD_CORE_OI_N, cw->n );
499  BREG_Write32(h->hRegister,  BCHP_THD_CORE_OI_D, cw->d );
500}
501
502/***************************************************************************
503 * BTHD_P_DvbtSetEq()
504 ***************************************************************************/
505void BTHD_P_DvbtSetEq( BTHD_3x7x_Handle h, 
506                       THD_CoChannelMode_t CoChannelMode)
507{
508  uint32_t format_ov,exp_offset=0,tps;
509  THD_Qam_t Qam;
510  THD_DvbtHierarchy_t Hierarchy;
511  THD_TransmissionMode_t TransmissionMode;
512
513  const uint8_t format_ov_table_cci_off[][3] = {{0xd,0xe,0xe},
514                                                 {0xd,0xe,0xe},
515                                                 {0xd,0xe,0xf},
516                                                 {0xd,0xe,0xf}};
517  const uint8_t format_ov_table_cci_on [][3] = {{0xb,0xb,0xb},
518                                                 {0xb,0xb,0xb},
519                                                 {0xb,0xe,0xf},
520                                                 {0xb,0xe,0xf}};
521  const uint32_t exp_offset_table_cci_off[][3] = {{0x000,0x3f0,0x3f0},
522                                                   {0x000,0x3f8,0x3f8},
523                                                   {0x000,0x3f4,0x3f4}};
524  const uint32_t exp_offset_table_cci_on [][3] = {{0x000,0x000,0x000},
525                                                   {0x000,0x000,0x000},
526                                                   {0x000,0x000,0x000}};
527
528  tps = BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS_OV );
529  TransmissionMode = (tps >> 24) & 0x3;
530  Qam = (tps >> 4) & 0x3;
531  Hierarchy  = (tps >> 8) & 0x3;
532
533  if (CoChannelMode == THD_CoChannelMode_None) {
534    format_ov  = format_ov_table_cci_off[Hierarchy][Qam];
535    exp_offset = exp_offset_table_cci_off[TransmissionMode][Qam];
536  } else {
537    format_ov  = format_ov_table_cci_on[Hierarchy][Qam];
538    exp_offset = exp_offset_table_cci_on[TransmissionMode][Qam];
539  }
540
541  BREG_WriteField(h->hRegister, THD_CORE_EQ, EXP_USE_FORMAT_OV, format_ov );
542  BREG_WriteField(h->hRegister, THD_CORE_EQ, EXP_OFFSET, exp_offset );     
543}
544
545
546/***************************************************************************
547 * BTHD_P_DvbtSetViterbi()
548 ***************************************************************************/
549void BTHD_P_DvbtSetViterbi( BTHD_3x7x_Handle h, 
550                            THD_CodeRate_t CodeRateHP, 
551                            THD_CodeRate_t CodeRateLP)
552{
553  uint32_t Dly;
554  THD_CodeRate_t CodeRate;
555  const uint32_t DlyTable[] = {0x000,0x110,0x208,0x310,0x518};
556
557  if (h->pAcquireParam->DvbtAcquireParam.PriorityMode == THD_DvbtPriorityMode_High)
558    CodeRate = CodeRateHP;
559  else
560    CodeRate = CodeRateLP;
561  Dly = DlyTable[CodeRate];
562
563  BREG_Write32(h->hRegister,  BCHP_THD_CORE_VIT_OVS,Dly );        /* Viterbi overwrite sync mode delay */
564  BREG_Write32(h->hRegister,  BCHP_THD_CORE_VIT,0x00000607 );     /* Viterbi overwrite sync mode enabled */
565}
566
567/***************************************************************************
568 * BTHD_P_DvbtSetFEC()
569 ***************************************************************************/
570BTHD_RESULT BTHD_P_DvbtSetFEC( BTHD_3x7x_Handle h )
571{
572
573  BTHD_RESULT return_val = THD_AcquireResult_InitLockState;
574  uint32_t tps;
575  THD_CodeRate_t CodeRateLP, CodeRateHP;
576  BERR_Code eEventWaitResult;
577
578  tps = BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS_OV );
579  CodeRateHP = (tps >> 12) & 0x7;
580  CodeRateLP = (tps >> 16) & 0x7;
581
582  if ( h->pAcquireParam->DvbtAcquireParam.PriorityMode == THD_DvbtPriorityMode_High)
583          BREG_WriteField(h->hRegister, THD_CORE_FEC, HP, 1);
584  else
585          BREG_WriteField(h->hRegister, THD_CORE_FEC, HP, 0);
586  BREG_Write32(h->hRegister,  BCHP_THD_CORE_FEC_SYNC,0x07021f1e ); /* FEC sync allow 2 bad headers out of 8 */
587  BTHD_P_DvbtSetEq(h, THD_CoChannelMode_None);
588  BTHD_P_DvbtSetViterbi(h, CodeRateHP, CodeRateLP);
589  BREG_WriteField(h->hRegister, THD_CORE_FEC, SYNC_MODE, 1 );
590  BREG_WriteField(h->hRegister, THD_CORE_RST, FEC_RST, 0 ); 
591  BREG_WriteField(h->hRegister, THD_CORE_RST, RS_RST, 0 );
592#if (BTHD_P_BCHP_THD_CORE_VER == BTHD_P_BCHP_CORE_V_4_0)
593  if (BKNI_CreateEvent(&(h->hFecSyncEvent)) != BERR_SUCCESS)
594                BDBG_ERR(("Not enough event for hFecSyncEvent"));
595#endif
596  BINT_EnableCallback( h->hFecSyncCallback);
597
598  eEventWaitResult = BTHD_P_WaitForEventOrAbort(h, h->hFecSyncEvent, 100);
599  /* eEventWaitResult success: return_val, Failure: THD_AcquireResult_NoFECLock, or,
600  * THD_AcquireResult_AbortedEarly if "Acquire Aborted Early" Event took place */
601  return_val = BTHD_P_MapWaitForEventResult_To_THD_AcqResult(eEventWaitResult, return_val, THD_AcquireResult_NoFECLock);
602
603
604  BINT_DisableCallback( h->hFecSyncCallback);
605#if (BTHD_P_BCHP_THD_CORE_VER == BTHD_P_BCHP_CORE_V_4_0)
606  BKNI_DestroyEvent(h->hFecSyncEvent);
607#endif
608  return return_val;
609}
610/***************************************************************************
611 * BTHD_P_DvbtGetNotch()
612 ***************************************************************************/
613BTHD_RESULT BTHD_P_DvbtGetNotch( BTHD_3x7x_Handle h, 
614                                 THD_TransmissionMode_t TransmissionMode)
615{ 
616  uint32_t iteration=0, start=0,idx,value,cur_exp,min_exp=0,mean_exp,min_idx,NumCoChannelFound = 0, cci_threshold;
617  bool CoChannelPresent = false;
618
619  /* Determine whether analog TV CCI is present using snooper.
620     Look for the presence of any 2 of the video, color, or audio carriers. 
621     This 2-out-of-3 criterion allows differentiation between true analog TV CCI
622     and spurs which often occur around sensitivity. If this criterion is too
623     strict, consider using a 1-out-of-3 criterion for input power levels above
624     sensitivity and this 2-out-of-3 criterion for input power levels near sensitivity */
625  iteration = 0;
626  while ((iteration < 3) && !CoChannelPresent) {
627    switch (iteration) {
628    case 0: if (TransmissionMode == THD_TransmissionMode_2k) start=000; else start = 0561; break;  /* Video carrier */
629    case 1: if (TransmissionMode == THD_TransmissionMode_2k) start=936; else start = 5280; break;  /* Color carrier */
630    case 2: if (TransmissionMode == THD_TransmissionMode_2k) start=936; else start = 6048; break;  /* Audio carrier */
631    }
632    BREG_Write32(h->hRegister,  BCHP_THD_CORE_CE_RECORD_CFG,0x07030000 + start );  /* CE snooper capture exponents, snapshot mode, step=3 */
633
634    /* while (!BREG_ReadField(h->hRegister,  THD_CORE_CE_RECORD_CFG, DONE)); */
635        if ( ! BTHD_P_Wait_CE_Recording_Status_Done(h, 1000) ) { /* units are in msec */
636          BDBG_MSG(("BTHD_P_DvbtGetNotch timeout waiting for THD_CORE_CE_RECORD_CFG DONE"));
637          goto BTHD_P_DvbtGetNotch_Abort;
638        }
639    BREG_Write32(h->hRegister,  BCHP_THD_CORE_CE_READ_INDEX,0x00000000 );
640    for (idx=0; idx<256; idx++) {
641      value = BREG_Read32(h->hRegister,  BCHP_THD_CORE_CE_READ_DATA );
642      cur_exp = (value & 0x0000fc00) >> 10;
643      if ((idx == 0) || (cur_exp < min_exp)) { /* Compute min, smaller noise exponent -> larger noise */
644        min_exp = cur_exp;
645        min_idx = idx;
646      }
647    }
648    mean_exp = (value & 0x000003f0) >> 4;
649   
650    if (TransmissionMode == THD_TransmissionMode_2k)
651        cci_threshold = 0x0f;
652    else
653        cci_threshold = 0x0c;
654       
655       
656    if (mean_exp > (min_exp + cci_threshold))           /* CCI present if min_exp-mean_exp > cci_threshold */
657        NumCoChannelFound++;
658    if (NumCoChannelFound > 1)
659        {CoChannelPresent = true;}
660   
661    iteration++;
662  }
663  /* Normal-Exit */
664  goto BTHD_P_DvbtGetNotch_Exit;
665 
666  /* Abort-Exit */
667BTHD_P_DvbtGetNotch_Abort:
668  CoChannelPresent = false;
669  goto BTHD_P_DvbtGetNotch_Exit;
670 
671BTHD_P_DvbtGetNotch_Exit:
672  return CoChannelPresent;
673}
674
675/***************************************************************************
676 * BTHD_P_DvbtSetICE ()
677 ***************************************************************************/
678BTHD_RESULT BTHD_P_DvbtSetICE( BTHD_3x7x_Handle h, 
679                               THD_TransmissionMode_t TransmissionMode,
680                               THD_GuardInterval_t GuardInterval)
681{
682  int n,k;
683  uint32_t ice[16],ice_val[16],ice_cnt[16],ice_found,ice_val_max,ice_cnt_max,ice_index_max;
684  uint32_t ice_cnt_best=0,ice_val_best=0,ice_index_best=0,spinv_best=0;
685  uint32_t N=bthd_transmission_mode[TransmissionMode];
686  uint32_t iteration;
687  int32_t  cl_int, cl_fcw;
688
689  /* Collect ICE values with carrier loop frozen */
690  BREG_WriteField(h->hRegister, THD_CORE_FRZ, CL_FRZ, 1);
691  cl_int = BREG_Read32(h->hRegister,  BCHP_THD_CORE_CL_INT); 
692  cl_fcw = BREG_Read32(h->hRegister,  BCHP_THD_CORE_CL_FCW);
693         
694  for (iteration=0; iteration<2; iteration++) {
695    BREG_WriteField(h->hRegister, THD_CORE_FRZ, CP_CINT_FRZ, 0 );
696    BTHD_P_OSleep(h,3,N,GuardInterval);
697    for (n=0; n<16; n++) {
698      ice[n] = BREG_ReadField(h->hRegister,  THD_CORE_CL_IEST, INT);
699      ice_val[n] = 0;
700      ice_cnt[n] = 0;
701      BTHD_P_OSleep(h,1,N,GuardInterval);
702      /* BDBG_MSG(("BTHD_P_DvbtSetICE:\tICE = 0x%08x",ice[n]); */
703    }
704
705    /* Identify unique ICE values and count number-of-occurrences of each */
706    ice_val[0] = ice[0];
707    ice_cnt[0] = 1;
708    for (n=1; n<16; n++) {
709      ice_found = 0;
710      for (k=0; k<n; k++) {
711              if (ice[n] == ice_val[k]) {  /* found, increment the count */
712                ice_cnt[k] = ice_cnt[k]+1;
713                ice_found = 1;       
714              }
715      }
716      if (!ice_found) {              /* not found, add it to the table */
717              ice_val[k] = ice[n];
718              ice_cnt[k] = 1;
719      }
720    }
721
722    /* Determine value which occurs most often */ 
723    ice_val_max = ice_val[0];
724    ice_cnt_max = ice_cnt[0];
725    ice_index_max = 0;
726    for (n=1; n<16; n++) {
727      if (ice_cnt[n] > ice_cnt_max) {
728              ice_val_max = ice_val[n];
729              ice_cnt_max = ice_cnt[n];
730              ice_index_max = n;
731      }
732    }
733    /* BDBG_MSG(("BTHD_P_DvbtSetICE:\tIC Offset = %d, ICE Max = 0x%08x (%d occurences)", carrier_off, ice_val[ice_index_max],ice_cnt_max); */
734
735    /* Keep track of the best result for comparison */
736    if (ice_cnt_max > ice_cnt_best) {
737      ice_cnt_best   =  ice_cnt_max;
738      ice_val_best   =  ice_val_max;
739      ice_index_best =  ice_index_max;
740      spinv_best     =  iteration;
741    }
742
743    /* Check for valid ICE and exit */
744    if ( ice_cnt_max >= THD_ICESpectrumInversionThreshold )
745      break;
746 
747    /* Try spectral inversion on second iteration */
748    /* BDBG_MSG(("BTHD_P_DvbtSetICE:\tTrying spectral inversion")); */
749    if (h->pInternalAcquireParam->FrontEndMode == THD_FrontEndMode_Baseband) {
750      BREG_WriteField(h->hRegister, THD_CORE_FE, NEGATE_Q, 1);
751    } else {
752      /*  Negate carrier fcw and integrator */ 
753      BREG_Write32(h->hRegister,  BCHP_THD_CORE_CL_FCW, (cl_fcw ^ 0xffffffff) + 1U);
754      BREG_Write32(h->hRegister,  BCHP_THD_CORE_CL_INT, (cl_int ^ 0xffffffff) + 1U);   
755    }
756
757    /* Freeze and wait 10 symbols */
758    BREG_WriteField(h->hRegister, THD_CORE_FRZ, CP_CINT_FRZ, 1 );             /*  Freeze integer carrier estimator*/
759    BTHD_P_OSleep(h,10,N,GuardInterval);
760  }
761
762  /* Reset CL_INT back to initial value (allowing for spectral inversion) */
763  if (iteration)
764    BREG_Write32(h->hRegister, BCHP_THD_CORE_CL_INT, (cl_int ^ 0xffffffff) + 1U);
765  else
766    BREG_Write32(h->hRegister,  BCHP_THD_CORE_CL_INT, cl_int);
767
768  /* Uninvert signal if needed. 
769     This can happen if spectral inversion was tested but noninverted spectrum yielded a better ICE */
770  if (iteration && !spinv_best) {
771    if (h->pInternalAcquireParam->FrontEndMode == THD_FrontEndMode_Baseband) {
772      BREG_WriteField(h->hRegister, THD_CORE_FE, NEGATE_Q, 0);
773    } else {
774      BREG_Write32(h->hRegister,  BCHP_THD_CORE_CL_FCW, cl_fcw);
775      BREG_Write32(h->hRegister,  BCHP_THD_CORE_CL_INT, cl_int);
776    }
777  }
778  if (spinv_best)
779    BDBG_MSG(("\tSpectral Inversion Detected"));
780 
781  /* Detection flag for suspect ICE result */
782  if (ice_cnt_best < 6) {
783    /* BDBG_WRN(("BTHD_P_DvbtSetICE:\tLow ICE Count Detected")); */
784    h->pStatus->LowICECount = 1;
785  }
786  else {
787    h->pStatus->LowICECount = 0;
788  }
789
790  BREG_WriteField(h->hRegister, THD_CORE_FRZ, CP_CINT_FRZ, 1 );
791  BTHD_P_OSleep(h,1,N,GuardInterval);
792
793  /* BDBG_MSG(("BTHD_P_DvbtSetICE:\tICE Max = 0x%08x (%d occurences)",ice_val_best,ice_cnt_best)); */
794  return(ice_val_best);
795}
796
797/***************************************************************************
798 * BTHD_P_DvbtSetFrame()
799 ***************************************************************************/
800void BTHD_P_DvbtSetFrame( BTHD_3x7x_Handle h )
801{
802  uint32_t tps;
803  uint32_t fsize;
804  unsigned D;
805  unsigned Q;
806  unsigned R;
807  uint32_t num;
808  uint32_t den;
809  uint32_t bw;
810
811  /* Extract the guard interval, QAM mode, and code rate from the TPS value */
812  tps = BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS_OV );
813  D = (1U << (5-((tps >> 20) & 0x3)));
814  Q = (tps >> 4)  & 0x3;
815  R = bthd_rate_denominator_table[ (tps >> 12) & 0x7 ];
816
817  /* Handle errors in TPS.*/
818  if (Q == 3) /* Handle invalid QAM.*/
819    Q = 0;  /* Arbitrary QAM.*/
820
821  /* Calculate the frame size */
822  bw = bthd_bandwidth[h->pAcquireParam->CommonAcquireParam.Bandwidth];
823  num = 281250 * bw * D * (Q + 1) * (R - 1); 
824  den = 272 * (D + 1) * R;
825  fsize = (num + (den >> 1)) / den;
826
827  BREG_Write32(h->hRegister,  BCHP_THD_CORE_FSIZE, (uint32_t)fsize );
828  /* BDBG_MSG(("BTHD_P_DvbtSetFrame:\tFSIZE  = 0x%08x", fsize);  */
829}
830
831/***************************************************************************
832 * BTHD_P_DvbtStatus()
833 ***************************************************************************/
834void BTHD_P_DvbtStatus( BTHD_3x7x_Handle h ) 
835{
836  uint32_t value,value2,CERC,CBERC,NBERC,UBERC,TBERC,NFERC,UFERC,TFERC,eq_snr;
837  uint32_t scale, sft_scale;
838  int32_t tmp;
839  uint32_t pouthi, poutlo, poutlo2, utmp;
840
841  const uint8_t scale_table[] = { 29, 27, 25, 29 }; /* Support invalid QAM.*/
842  const uint8_t sft_scale_table[][4] = \
843  {
844    {  2,  2,  2,  2 },
845    { 10, 10, 20, 52 },
846    { 42, 42, 60, 108},
847    {  2,  2,  2,  2 } 
848  };
849
850  /* Determine transmission parameters */
851  value = BREG_Read32(h->hRegister,  BCHP_THD_CORE_TPS_OV);
852  h->pStatus->DvbtStatus.CodeRateLP   = (value >> 16) & 0x7;
853  h->pStatus->DvbtStatus.CodeRateHP   = (value >> 12) & 0x7;
854  h->pStatus->DvbtStatus.Interleaving = (value >> 10) & 0x1;
855  h->pStatus->DvbtStatus.Hierarchy    = (value >> 8)  & 0x3;
856  h->pStatus->DvbtStatus.Qam          = (value >> 4)  & 0x3;
857  h->pStatus->DvbtStatus.CellID       = BREG_ReadField(h->hRegister, THD_CORE_TPS_CELL_ID, CELL_ID );
858
859  /* Determine stream priority */
860  if (BREG_ReadField(h->hRegister, THD_CORE_FEC, HP ))
861    h->pStatus->DvbtStatus.Priority = THD_DvbtPriorityMode_High;
862  else
863    h->pStatus->DvbtStatus.Priority = THD_DvbtPriorityMode_Low; 
864 
865  /* Compute data SNR */
866  eq_snr = BREG_Read32(h->hRegister, BCHP_THD_CORE_EQ_SNR);
867  if (eq_snr >> (8+2)) {
868    scale     = scale_table[h->pStatus->DvbtStatus.Qam];
869    sft_scale = sft_scale_table[h->pStatus->DvbtStatus.Qam][h->pStatus->DvbtStatus.Hierarchy];
870
871    /* Take 10*log10(value2/256.0) to obtain value in dB */
872    tmp = (sft_scale << (scale-2))/(eq_snr >> (8+2));
873    /* 256*10*log10(1/256) = -6165, application then takes SNR_p/256 for SNR in dB */ 
874    h->pStatus->DvbtStatus.SNRData = BMTH_2560log10(tmp) - 6165;
875  }
876
877  /* Compute pre-Viterbi BER */
878  value  = BREG_Read32(h->hRegister,  BCHP_THD_CORE_VIT_RCNT );
879  value2 = BREG_Read32(h->hRegister,  BCHP_THD_CORE_VIT_RERR );
880  if (value2)
881  {
882    /* h->pStatus->PreVitBER = (((value * 2147483648) / value2) >> 16);  */         
883    BMTH_HILO_64TO64_Mul(0, value, 0, 0x80000000, &pouthi, &poutlo);
884    BMTH_HILO_64TO64_Div32(pouthi, poutlo, value2, &utmp, &poutlo2);
885    h->pStatus->DvbtStatus.PreVitBER = utmp; /* Application takes x/(2^31) to obtain error rate */
886  }
887
888  /* Read hardware error counters */
889  BREG_WriteField(h->hRegister, THD_CORE_FEC, CAPERC, 1 ); 
890
891  CERC  = BREG_Read32(h->hRegister,  BCHP_THD_CORE_RS_CERC );
892  NBERC = BREG_Read32(h->hRegister,  BCHP_THD_CORE_RS_NBERC );
893  CBERC = BREG_Read32(h->hRegister,  BCHP_THD_CORE_RS_CBERC );
894  UBERC = BREG_Read32(h->hRegister,  BCHP_THD_CORE_RS_UBERC );
895  NFERC = BREG_Read32(h->hRegister,  BCHP_THD_CORE_NFERC );
896  UFERC = BREG_Read32(h->hRegister,  BCHP_THD_CORE_UFERC );
897  TBERC = NBERC + CBERC + UBERC;
898  TFERC = NFERC + UFERC; 
899
900  BREG_WriteField(h->hRegister, THD_CORE_FEC, CAPERC, 0 ); 
901
902  /* Update software error counters */
903  h->pStatus->DvbtStatus.TS_CERC  = h->pStatus->DvbtStatus.TS_CERC_ref  + CERC;
904  h->pStatus->DvbtStatus.TS_NBERC = h->pStatus->DvbtStatus.TS_NBERC_ref + NBERC;
905  h->pStatus->DvbtStatus.TS_CBERC = h->pStatus->DvbtStatus.TS_CBERC_ref + CBERC;
906  h->pStatus->DvbtStatus.TS_UBERC = h->pStatus->DvbtStatus.TS_UBERC_ref + UBERC;
907  h->pStatus->DvbtStatus.TS_TBERC = h->pStatus->DvbtStatus.TS_TBERC_ref + TBERC;
908  h->pStatus->DvbtStatus.TS_NFERC = h->pStatus->DvbtStatus.TS_NFERC_ref + NFERC;
909  h->pStatus->DvbtStatus.TS_UFERC = h->pStatus->DvbtStatus.TS_UFERC_ref + UFERC;
910  h->pStatus->DvbtStatus.TS_TFERC = h->pStatus->DvbtStatus.TS_TFERC_ref + TFERC;
911
912  /* Reset hardware error counters every 10 one-second frames */
913  if (TFERC >= THD_StatusFramesForReset) {
914    BTHD_P_ResetStatusHW(h);
915   
916    h->pStatus->DvbtStatus.TS_CERC_ref  = h->pStatus->DvbtStatus.TS_CERC;
917    h->pStatus->DvbtStatus.TS_NBERC_ref = h->pStatus->DvbtStatus.TS_NBERC;
918    h->pStatus->DvbtStatus.TS_CBERC_ref = h->pStatus->DvbtStatus.TS_CBERC;
919    h->pStatus->DvbtStatus.TS_UBERC_ref = h->pStatus->DvbtStatus.TS_UBERC;
920    h->pStatus->DvbtStatus.TS_TBERC_ref = h->pStatus->DvbtStatus.TS_TBERC;
921    h->pStatus->DvbtStatus.TS_NFERC_ref = h->pStatus->DvbtStatus.TS_NFERC;
922    h->pStatus->DvbtStatus.TS_UFERC_ref = h->pStatus->DvbtStatus.TS_UFERC;
923    h->pStatus->DvbtStatus.TS_TFERC_ref = h->pStatus->DvbtStatus.TS_TFERC;
924  } 
925
926  /* Compute Viterbi BER and TS PER */
927  if (h->pStatus->DvbtStatus.TS_TBERC) {
928    /* h->pStatus->TS_PER = (h->pStatus->TS_UBERC * (1ULL<<31)) / h->pStatus->TS_TBERC; */
929    BMTH_HILO_32TO64_Mul(0x80000000, (h->pStatus->DvbtStatus.TS_UBERC), &pouthi, &poutlo);
930    BMTH_HILO_64TO64_Div32(pouthi, poutlo, (h->pStatus->DvbtStatus.TS_TBERC), &pouthi, &h->pStatus->DvbtStatus.TS_PER );
931    /* h->pStatus->VitBER = (h->pStatus->TS_CERC * (1ULL<<31)) / (h->pStatus->TS_TBERC * 8 * 188ULL); */
932    BMTH_HILO_32TO64_Mul(0x80000000, (h->pStatus->DvbtStatus.TS_CERC), &pouthi, &poutlo);
933    /*BMTH_HILO_64TO64_Div32(pouthi, poutlo, (h->pStatus->DvbtStatus.TS_TBERC * 8 * 188), &pouthi, &h->pStatus->DvbtStatus.VitBER );*/
934    BMTH_HILO_64TO64_Div32(pouthi, poutlo, (8 * 188), &pouthi, &poutlo );
935    BMTH_HILO_64TO64_Div32(pouthi, poutlo, (h->pStatus->DvbtStatus.TS_TBERC), &pouthi, &h->pStatus->DvbtStatus.VitBER );
936  }
937  if (h->pStatus->DvbtStatus.TS_TFERC){
938    /* h->pStatus->TS_ESR = ((100ULL * h->pStatus->TS_UFERC) / h->pStatus->TS_TFERC); */
939    BMTH_HILO_32TO64_Mul(0x10000000, (h->pStatus->DvbtStatus.TS_UFERC), &pouthi, &poutlo);
940    BMTH_HILO_64TO64_Div32(pouthi, poutlo, (h->pStatus->DvbtStatus.TS_TFERC), &pouthi, &h->pStatus->DvbtStatus.TS_ESR );
941  }
942}
943
944/***************************************************************************
945 * BTHD_P_DvbtResetStatus()
946 ***************************************************************************/
947void BTHD_P_DvbtResetStatus( BTHD_3x7x_Handle h )
948{
949  h->pStatus->DvbtStatus.TS_CERC      = 0;
950  h->pStatus->DvbtStatus.TS_CBERC     = 0;
951  h->pStatus->DvbtStatus.TS_UBERC     = 0; 
952  h->pStatus->DvbtStatus.TS_NBERC     = 0;
953  h->pStatus->DvbtStatus.TS_TBERC     = 0;
954  h->pStatus->DvbtStatus.TS_UFERC     = 0; 
955  h->pStatus->DvbtStatus.TS_NFERC     = 0;
956  h->pStatus->DvbtStatus.TS_TFERC     = 0;
957
958  h->pStatus->DvbtStatus.TS_CERC_ref  = 0;
959  h->pStatus->DvbtStatus.TS_CBERC_ref = 0;
960  h->pStatus->DvbtStatus.TS_UBERC_ref = 0; 
961  h->pStatus->DvbtStatus.TS_NBERC_ref = 0;
962  h->pStatus->DvbtStatus.TS_TBERC_ref = 0;
963  h->pStatus->DvbtStatus.TS_UFERC_ref = 0; 
964  h->pStatus->DvbtStatus.TS_NFERC_ref = 0;
965  h->pStatus->DvbtStatus.TS_TFERC_ref = 0;
966
967  h->pStatus->DvbtStatus.PreVitBER    = 0;
968  h->pStatus->DvbtStatus.VitBER       = 0;
969  h->pStatus->DvbtStatus.TS_PER       = 0;
970  h->pStatus->DvbtStatus.TS_ESR       = 0;
971}
972
973/***************************************************************************
974 * BTHD_P_DvbtAcquire()
975 ***************************************************************************/
976BTHD_RESULT BTHD_P_DvbtAcquire( BTHD_3x7x_Handle h )
977{
978  BTHD_RESULT return_val=THD_AcquireResult_InitLockState;
979
980  THD_FFTWindowMode_t FFTWindowMode=THD_FFTWindowMode_InSpan;
981  THD_ChannelEstimatorMode_t ChannelEstimatorMode=THD_ChannelEstimatorMode_Fixed, ChannelEstimatorModeList[2];
982  THD_State_t NextState=THD_State_Init, LastState=THD_State_Init, State=THD_State_Init;
983  bool Done=false, acqProfileValid[16];
984  uint32_t retries=0, ChannelEstimatorRetries, fscntInit=0xffffffff, acqProfile[16], k;
985  uint32_t TPSRetries=0, AllowedTPSRetries=1;
986  char     *acqProfileString[16];
987
988  /* Initialize Candidate Channel Estimator Modes */
989  ChannelEstimatorModeList[0] = THD_ChannelEstimatorMode_Fixed;
990  ChannelEstimatorModeList[1] = THD_ChannelEstimatorMode_Pedestrian;
991  if (h->pInternalAcquireParam->ChannelEstimatorMode == THD_ChannelEstimatorMode_Auto) {
992    ChannelEstimatorMode = ChannelEstimatorModeList[0];
993    ChannelEstimatorRetries = 1;
994  } else {
995    ChannelEstimatorModeList[0] = h->pInternalAcquireParam->ChannelEstimatorMode;
996    ChannelEstimatorRetries = 0;
997  }
998
999  /* Use Fscnt for acquisition time profiling */
1000  BREG_Write32(h->hRegister, BCHP_THD_CORE_FSCNT,fscntInit);
1001
1002  acqProfileString[THD_State_Init] = "Init";
1003  acqProfileString[THD_State_SP] = "SP";
1004  acqProfileString[THD_State_FFTTrigger] = "FFTTrigger"; 
1005  acqProfileString[THD_State_TPS] = "TPS";
1006  acqProfileString[THD_State_FEC] = "FEC";
1007  acqProfileString[THD_State_Track] = "Track";
1008  acqProfileString[THD_State_CheckLock] = "CheckLock";
1009  acqProfileString[THD_State_ChangeChannelEstimator] = "ChangeChannelEstimator";
1010  acqProfileString[THD_State_Done] = "Done";
1011  for (k=0; k<16; k++)
1012    acqProfileValid[k] = false;
1013
1014  /* State Machine */
1015  while (!Done) {
1016    switch(State) {
1017
1018    case THD_State_Init:
1019      BDBG_MSG(("\tTHD Init"));
1020      h->pInternalAcquireParam->AllowRsSyncEvent = true;
1021      return_val = BTHD_P_AcquireInit(h,FFTWindowMode);
1022      if ((return_val == THD_AcquireResult_NoSignal) || (return_val == THD_AcquireResult_NoFFTLock) || (return_val == THD_AcquireResult_AbortedEarly))
1023              NextState = THD_State_Done;
1024      else
1025              NextState = THD_State_SP;
1026      break;
1027
1028    case THD_State_SP:
1029      BDBG_MSG(("\tTHD SP"));
1030      return_val = BTHD_P_AcquireSP(h);
1031      if ((return_val == THD_AcquireResult_NoSPLock) || (return_val == THD_AcquireResult_AbortedEarly))
1032              NextState = THD_State_Done;
1033      else
1034          NextState = THD_State_TPS;
1035      break;
1036
1037    case THD_State_TPS:
1038      BDBG_MSG(("\tTHD TPS"));
1039      return_val = BTHD_P_AcquireTPS(h);
1040      if (return_val == THD_AcquireResult_AbortedEarly) {
1041          NextState = THD_State_Done;
1042      } else if (TPSRetries < AllowedTPSRetries) {
1043              NextState = THD_State_FFTTrigger;
1044          TPSRetries++;
1045      }
1046      else {
1047        if (return_val == THD_AcquireResult_NoTPSLock)
1048                NextState = THD_State_Done;
1049        else
1050                NextState = THD_State_FEC;
1051      }
1052      break;
1053
1054    case THD_State_FFTTrigger:
1055      BDBG_MSG(("\tTHD FFTTrigger"));
1056      return_val = BTHD_P_AcquireFFTTrigger(h);
1057      if (return_val == THD_AcquireResult_NoSPLock)
1058        BDBG_MSG(("\tTHD FFTTrigger obtained NO SPLock"));
1059      if (return_val == THD_AcquireResult_AbortedEarly) {
1060          NextState = THD_State_Done;
1061      }
1062      else {
1063        if (h->pStatus->FFTTriggerMissed || h->pStatus->FFTTriggerOnGuard)
1064          NextState  = THD_State_TPS; 
1065        else
1066              NextState  = THD_State_FEC; 
1067      }
1068      break;
1069
1070    case THD_State_FEC:
1071      BDBG_MSG(("\tTHD FEC"));
1072      return_val = BTHD_P_AcquireFEC(h,(retries==0));
1073      if ((return_val == THD_AcquireResult_NoFECLock) || (return_val == THD_AcquireResult_AbortedEarly)) {
1074              NextState = THD_State_Done;
1075      } else {
1076              NextState = THD_State_Track;
1077              retries = 0;
1078      }
1079      break;
1080
1081    case THD_State_Track:
1082      BDBG_MSG(("\tTHD Track"));
1083      ChannelEstimatorMode = ChannelEstimatorModeList[retries];
1084      return_val = BTHD_P_AcquireTrack(h,FFTWindowMode,ChannelEstimatorMode);
1085      if (return_val == THD_AcquireResult_AbortedEarly) {
1086          NextState = THD_State_Done;
1087      }
1088      else {
1089              NextState = THD_State_CheckLock;
1090      } 
1091     
1092      /*Turn off impulsive noise canceller bypass when ImpulseMode is auto*/
1093      if (h->pInternalAcquireParam->ImpulseMode == THD_ImpulseMode_Auto)
1094        BREG_WriteField(h->hRegister, THD_CORE_BYP, IMPE_BYP, 0);
1095      else
1096        BREG_WriteField(h->hRegister, THD_CORE_BYP, IMPE_BYP, 1);
1097       
1098      break;
1099
1100    case THD_State_CheckLock:
1101      BDBG_MSG(("\tTHD CheckLock"));
1102      return_val = BTHD_P_AcquireCheckLock(h);
1103      if (return_val == THD_AcquireResult_NoFECLock) {
1104              if (retries < ChannelEstimatorRetries) {
1105                retries++;
1106                NextState = THD_State_ChangeChannelEstimator;
1107              } else
1108                NextState = THD_State_Done;
1109      } else
1110              NextState = THD_State_Done;
1111      break;
1112
1113    case THD_State_ChangeChannelEstimator:
1114      BDBG_MSG(("\tTHD ChangeChannelestimator"));
1115      ChannelEstimatorMode = ChannelEstimatorModeList[retries];
1116      return_val = BTHD_P_AcquireChangeChannelEstimator(h,ChannelEstimatorMode);
1117      if (return_val == THD_AcquireResult_AbortedEarly) {
1118        NextState = THD_State_Done;
1119      }
1120      else {
1121        NextState = THD_State_CheckLock;
1122      }
1123      break;
1124
1125    case THD_State_Done:
1126      BDBG_MSG(("\tTHD Done"));
1127      h->pInternalAcquireParam->AllowRsSyncEvent = false;
1128      BKNI_ResetEvent(h->hRsSyncEvent);     
1129      Done = true;
1130#ifdef EMULATION_ENABLE
1131          BREG_Write32(h->hRegister,  BCHP_THD_INTR_AP_SET, 0x00000080 );
1132#endif
1133      break;
1134
1135        default:
1136          BDBG_MSG(("\tNOT SUPPORTED MODE"));
1137          break;
1138    }
1139
1140    acqProfile[State] = BREG_Read32(h->hRegister, BCHP_THD_CORE_FSCNT);
1141    acqProfileValid[State] = true;
1142
1143    if (!Done)
1144      LastState=State;
1145    State=NextState;
1146  }
1147
1148  /* Update status structure with auto-detected modes */
1149  h->pStatus->ChannelEstimatorMode = ChannelEstimatorMode;
1150  h->pStatus->FFTWindowMode = FFTWindowMode;
1151
1152  /* Report acquisition time */
1153  h->pStatus->AcquisitionTime = (fscntInit - acqProfile[LastState])/(h->pInternalAcquireParam->SampleFreq/1000);
1154  /*BDBG_MSG(("\tAcquisition Time = %d msec",h->pStatus->AcquisitionTime));  */
1155 
1156  for (k=0; k<16; k++)
1157    if (acqProfileValid[k])
1158      BDBG_MSG(("\t\t%d msec: %s", (fscntInit - acqProfile[k])/(h->pInternalAcquireParam->SampleFreq/1000), acqProfileString[k]));
1159 
1160  /* Reset the Abort-Early request */
1161  BTHD_P_AbortAcquireReset(h);
1162
1163  return(return_val);
1164}
1165
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