| 1 | /****************************************************************************** |
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| 2 | * (c)2010-2011 Broadcom Corporation |
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| 3 | * |
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| 4 | * This program is the proprietary software of Broadcom Corporation and/or its licensors, |
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| 5 | * and may only be used, duplicated, modified or distributed pursuant to the terms and |
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| 6 | * conditions of a separate, written license agreement executed between you and Broadcom |
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| 7 | * (an "Authorized License"). Except as set forth in an Authorized License, Broadcom grants |
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| 8 | * no license (express or implied), right to use, or waiver of any kind with respect to the |
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| 9 | * Software, and Broadcom expressly reserves all rights in and to the Software and all |
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| 10 | * intellectual property rights therein. IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU |
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| 11 | * HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY |
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| 12 | * NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE. |
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| 13 | * |
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| 14 | * Except as expressly set forth in the Authorized License, |
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| 15 | * |
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| 16 | * 1. This program, including its structure, sequence and organization, constitutes the valuable trade |
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| 17 | * secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof, |
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| 18 | * and to use this information only in connection with your use of Broadcom integrated circuit products. |
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| 19 | * |
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| 20 | * 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" |
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| 21 | * AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR |
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| 22 | * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO |
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| 23 | * THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES |
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| 24 | * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, |
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| 25 | * LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION |
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| 26 | * OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF |
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| 27 | * USE OR PERFORMANCE OF THE SOFTWARE. |
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| 28 | * |
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| 29 | * 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS |
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| 30 | * LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR |
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| 31 | * EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR |
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| 32 | * USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF |
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| 33 | * THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT |
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| 34 | * ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE |
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| 35 | * LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF |
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| 36 | * ANY LIMITED REMEDY. |
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| 37 | * |
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| 38 | * $brcm_Workfile: btnr_global_clk.h $ |
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| 39 | * $brcm_Revision: 19 $ |
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| 40 | * $brcm_Date: 12/8/11 3:15p $ |
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| 41 | * |
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| 42 | * Module Description: |
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| 43 | * |
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| 44 | * Revision History: |
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| 45 | * |
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| 46 | * $brcm_Log: /AP/ctfe/core/tnr/btnr_global_clk.h $ |
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| 47 | * |
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| 48 | * 19 12/8/11 3:15p shchang |
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| 49 | * SW3461-1: set REFPLL_FREQ_SEL to 1 |
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| 50 | * |
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| 51 | * 18 11/4/11 4:11p farshidf |
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| 52 | * SW3461-82: merge to main |
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| 53 | * |
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| 54 | * Fw_Integration_Devel/5 11/4/11 11:38a farshidf |
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| 55 | * SW3461-82: merge to integ |
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| 56 | * |
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| 57 | * Fw_Integration_Devel/AP_V3_0_TNR_DEV/1 10/24/11 5:02p cbrooks |
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| 58 | * sw3461-1:Added 0 Hz CWC |
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| 59 | * |
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| 60 | * 17 8/12/11 3:15p farshidf |
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| 61 | * SW3461-1: merge to main |
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| 62 | * |
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| 63 | * Fw_Integration_Devel/3 8/12/11 2:11p farshidf |
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| 64 | * SW3461-1: merge to integ |
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| 65 | * |
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| 66 | * Fw_Integration_Devel/AP_V0_6_TNR_DEV/4 7/27/11 7:05p cbrooks |
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| 67 | * sw3461-1:removed frequency dependent gain offsets |
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| 68 | * |
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| 69 | * Fw_Integration_Devel/AP_V0_6_TNR_DEV/3 7/27/11 4:19p cbrooks |
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| 70 | * sw3461-1:added 540 MHz cwc |
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| 71 | * |
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| 72 | * Fw_Integration_Devel/AP_V0_6_TNR_DEV/2 7/14/11 5:21p cbrooks |
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| 73 | * sw3461-1:added callback support for gains |
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| 74 | * |
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| 75 | * Fw_Integration_Devel/AP_V0_6_TNR_DEV/1 7/1/11 3:19p cbrooks |
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| 76 | * sw3461-1:added callback support |
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| 77 | * |
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| 78 | * Fw_Integration_Devel/1 6/29/11 12:39p farshidf |
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| 79 | * SW3461-13: merge to integration branch |
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| 80 | * |
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| 81 | * Fw_Integration_Devel/Tnr_Fw_Devel_Rc05/1 6/20/11 3:06p cbrooks |
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| 82 | * sw3461-1:Added GAIN_OFFSET for channel power |
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| 83 | * |
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| 84 | * 14 6/12/11 11:01a farshidf |
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| 85 | * SW3461-1: remove warning for 7552 |
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| 86 | * |
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| 87 | * 13 6/12/11 10:57a farshidf |
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| 88 | * SW3461-1: remove warning for 7552 |
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| 89 | * |
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| 90 | * 12 6/9/11 6:39p mpovich |
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| 91 | * SW3461-1: Merge Ver 0.4 Integ. onto main branch. |
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| 92 | * |
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| 93 | * SW_System_4_Integ_Test/1 6/9/11 12:26p mpovich |
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| 94 | * SW3461-1: Integrate latest from all devel. branches. Convert end of |
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| 95 | * line comments per coding standard. |
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| 96 | * |
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| 97 | * Tnr_Fw_Devel_4/1 6/6/11 7:48p cbrooks |
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| 98 | * sw3461-1:Added Spur Table |
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| 99 | * |
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| 100 | * 11 5/20/11 6:42a mpovich |
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| 101 | * SW3461-1: rename UFE (BUFE) module to TNR (BTNR). |
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| 102 | * |
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| 103 | * TNR_3461_1/1 5/19/11 5:12p mpovich |
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| 104 | * SW3461-1: Change BUFE module prefix to BTNR |
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| 105 | * |
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| 106 | * 10 5/3/11 1:39p mpovich |
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| 107 | * SW3461-1: Merge to main of intermediate label, FW_3461_A0_05022011_1100 |
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| 108 | * (05/02/2011 Pace build). |
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| 109 | * |
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| 110 | * TNR_3461_1/3 4/26/11 8:40p cbrooks |
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| 111 | * sw3461-1:added spur table |
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| 112 | * |
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| 113 | * 9 4/26/11 8:22p farshidf |
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| 114 | * SW3461-1: add spur table |
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| 115 | * |
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| 116 | * 8 3/25/11 6:31p mpovich |
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| 117 | * SW3128-1: Merge latest from TNR branch to main branch. |
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| 118 | * |
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| 119 | * TNR_3461_1/2 3/24/11 11:53a jputnam |
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| 120 | * SW3461-1: Change TNR clock to 540MHz for cable mode |
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| 121 | * |
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| 122 | * 7 3/18/11 4:11p farshidf |
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| 123 | * SW3461-1: merge main |
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| 124 | * |
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| 125 | * TNR_3461_1/1 3/16/11 8:42p cbrooks |
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| 126 | * sw3461-1:added MIPS timer |
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| 127 | * |
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| 128 | * 6 3/10/11 5:07p cbrooks |
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| 129 | * sw3461-1:new code |
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| 130 | * |
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| 131 | * 5 3/9/11 7:21p cbrooks |
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| 132 | * sw3461-1:Addef TNR programming code |
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| 133 | * |
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| 134 | * 4 3/8/11 8:25p cbrooks |
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| 135 | * sw3461-1:new code |
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| 136 | * |
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| 137 | * 3 3/8/11 2:42p cbrooks |
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| 138 | * sw3461-1:new code |
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| 139 | * |
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| 140 | * 2 3/7/11 9:10p cbrooks |
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| 141 | * sw3128-1:new code |
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| 142 | * |
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| 143 | * 1 2/2/11 9:49p farshidf |
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| 144 | * SW3461-1: new file |
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| 145 | * |
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| 146 | * 1 1/26/11 4:24p farshidf |
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| 147 | * SW3128-1: new file |
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| 148 | * |
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| 149 | *****************************************************************************/ |
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| 150 | |
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| 151 | #ifndef _BTNR_GLOBAL_CLK_H__ |
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| 152 | #define _BTNR_GLOBAL_CLK_H__ |
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| 153 | |
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| 154 | #ifdef __cplusplus |
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| 155 | extern "C" { |
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| 156 | #endif |
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| 157 | |
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| 158 | /*The following offsets need to be set board to board, this set was done with the BCM93461DC1_01*/ |
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| 159 | /*Gain offsets for board to get channel power, values are offsets in db*256*/ |
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| 160 | #define GAIN_OFFSET 20*256 /*Calibrate at 500 MHz and 0 dbmv*/ |
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| 161 | |
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| 162 | |
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| 163 | #define MIPS_TIMER 108000000 |
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| 164 | |
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| 165 | #define REF_FREQ 54000000UL |
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| 166 | |
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| 167 | /*Choose 1 REFPLL Rate*/ |
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| 168 | /*0 for 1080000000, 1 for 1350000000*/ |
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| 169 | #define REFPLL_FREQ_SEL 1 |
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| 170 | |
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| 171 | /*Assumes REF_FREQ = 54000000 and that |
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| 172 | *BTNR_P_TunerInit() makes the #define true*/ |
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| 173 | #if (REFPLL_FREQ_SEL == 0) |
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| 174 | #define REFPLL_FREQ 1080000000UL |
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| 175 | #endif |
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| 176 | #if (REFPLL_FREQ_SEL == 1) |
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| 177 | #define REFPLL_FREQ 1350000000UL |
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| 178 | #endif |
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| 179 | |
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| 180 | /*It is assumed that the BTNR_P_TunerInit() |
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| 181 | * and BTNR_P_Program_CIC_HB_SAW() |
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| 182 | *makes the following #defines true */ |
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| 183 | #define TERR_PHYPLL1_FREQ 2700000000UL |
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| 184 | #define TERR_PHYPLL2_FREQ 1350000000UL |
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| 185 | #define TERR_PHYPLL3_FREQ 225000000UL |
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| 186 | #define TERR_PHYPLL4_FREQ 100000000UL |
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| 187 | #define TERR_PHYPLL5_FREQ 10546875UL |
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| 188 | #define TERR_PHYPLL6_FREQ 540000000UL |
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| 189 | #define F_TER 54000000UL |
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| 190 | #define CABLE_PHYPLL1_FREQ 2632500000UL |
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| 191 | #define CABLE_PHYPLL2_FREQ 1316250000UL |
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| 192 | #define CABLE_PHYPLL3_FREQ 219375000UL |
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| 193 | #define CABLE_PHYPLL4_FREQ 97500000UL |
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| 194 | #define CABLE_PHYPLL5_FREQ 10283203UL |
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| 195 | #define CABLE_PHYPLL6_FREQ 540000000UL /* 526500000UL */ |
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| 196 | #define F_HS 15000000UL /* 14625000UL */ |
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| 197 | #define F_1S 30000000UL /* 29250000UL */ |
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| 198 | |
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| 199 | |
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| 200 | #define REF_FREQ_D128 421875 |
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| 201 | #define DPM_FREQ_MAX 1012600000 |
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| 202 | #define DPM_FREQ_MIN 31640625 |
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| 203 | |
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| 204 | #ifdef LEAP_BASED_CODE |
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| 205 | #define SPUR_TBL_SIZE 11 |
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| 206 | static uint32_t SPUR_TBL[SPUR_TBL_SIZE] = |
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| 207 | { |
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| 208 | 0, 54000000, 675000000, 99900000, 432000000, |
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| 209 | 810000000, 864000000, 486000000, 594000000, |
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| 210 | 648000000, 540000000 |
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| 211 | }; |
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| 212 | #endif |
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| 213 | #ifdef __cplusplus |
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| 214 | } |
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| 215 | #endif |
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| 216 | |
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| 217 | #endif |
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| 218 | |
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| 219 | |
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