source: svn/newcon3bcm2_21bu/magnum/portinginterface/tnr/7552ob/btnr_ob_init.c

Last change on this file was 76, checked in by megakiss, 10 years ago

1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
  • Property svn:executable set to *
File size: 6.3 KB
Line 
1/*************************************************************************
2*     (c)2005-2011 Broadcom Corporation
3*
4*  This program is the proprietary software of Broadcom Corporation and/or its licensors,
5*  and may only be used, duplicated, modified or distributed pursuant to the terms and
6*  conditions of a separate, written license agreement executed between you and Broadcom
7*  (an "Authorized License").  Except as set forth in an Authorized License, Broadcom grants
8*  no license (express or implied), right to use, or waiver of any kind with respect to the
9*  Software, and Broadcom expressly reserves all rights in and to the Software and all
10*  intellectual property rights therein.  IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11*  HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12*  NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE.
13*
14* $brcm_Workfile: btnr_ob_init.c $
15* $brcm_Revision: Hydra_Software_Devel/5 $
16* $brcm_Date: 12/14/11 2:48p $
17*
18* [File Description:]
19*
20* Revision History:
21*
22 * $brcm_Log: /magnum/portinginterface/tnr/7552ob/btnr_ob_init.c $
23 *
24 * Hydra_Software_Devel/5   12/14/11 2:48p farshidf
25 * SW7552-170: remove the tuner power hard code values
26 *
27 * Hydra_Software_Devel/4   12/13/11 5:49p farshidf
28 * SW7552-170: temp code to get it working
29 *
30 * Hydra_Software_Devel/3   12/9/11 3:11p farshidf
31 * SW7552-170: fix compile issue
32 *
33 * Hydra_Software_Devel/2   12/9/11 12:01p farshidf
34 * SW7552-170: update the uFE init
35 *
36*
37***************************************************************************/
38#include "bstd.h"
39#include "bkni.h"
40#include "bmth.h"
41#include "btmr.h"
42#include "btnr.h"
43#include "bdbg.h"
44#include "btnr_priv.h"
45#include "btnr_ob_3x7x_priv.h"
46#include "bchp_ufe_oob.h"
47#include "bchp_ufe_misc.h"
48#include "bchp_ufe_saw_oob.h"
49#include "btnr_ob_struct.h"
50#include "bchp_obadc.h"
51
52#include "btnr_ob_init.h"
53#include "btnr_ob_tune.h"
54
55#ifndef LEAP_BASED_CODE
56BDBG_MODULE(btnr_ob_init);
57#define POWER2_31 2147483648UL
58#define POWER2_16 65536
59#define LOG10_POWER2_9_X5120 13871
60#define Twos_Complement32(x) ((uint32_t)((x ^ 0xFFFFFFFF) + 1))
61#endif
62
63#define BCHP_UFE_MISC_CTRL_CLKGEN_DATA_RESET_SHIFT     BCHP_UFE_MISC_CTRL_DATA_RESET_SHIFT
64#define BCHP_UFE_MISC_CTRL_CLKGEN_DATA_RESET_MASK  (BCHP_UFE_MISC_CTRL_DATA_RESET_MASK | BCHP_UFE_MISC_CTRL_CLKGEN_RESET_MASK)
65
66#define OOB_PHYPLL6_FREQ  540000000UL /* 526500000UL */
67
68
69
70/******************************************************************************
71*  BTNR_P_TnrInit
72******************************************************************************/
73BERR_Code BTNR_Ob_P_TnrInit(BTNR_Ob_3x7x_Handle hTnr, uint32_t RfFreq)
74{
75       
76        BREG_WriteField(hTnr->hRegister, OBADC_CNTL3, PWRUP, 1);
77        BREG_WriteField(hTnr->hRegister, OBADC_CNTL3, RSTB, 0);
78        BREG_WriteField(hTnr->hRegister, OBADC_CNTL3, RSTB, 1);
79
80        BTNR_Ob_P_Program_TNR(hTnr, RfFreq);
81        return BERR_SUCCESS;
82}
83
84
85/******************************************************************************
86*  BTNR_Ob_P_Program_Back_DDFS()
87******************************************************************************/
88void BTNR_Ob_P_Program_Back_DDFS(BTNR_Ob_3x7x_Handle hTnr, uint32_t RfFreq)
89{
90
91        uint32_t ulMultA, ulMultB, ulNrmHi, ulNrmLo, ulDivisor;
92
93        ulMultA = 2*(uint32_t)RfFreq;
94        ulMultB = POWER2_31;
95        ulDivisor = OOB_PHYPLL6_FREQ;
96        BMTH_HILO_32TO64_Mul(ulMultA, ulMultB, &ulNrmHi, &ulNrmLo);
97        BMTH_HILO_64TO64_Div32(ulNrmHi, ulNrmLo, ulDivisor, &ulNrmHi, &ulNrmLo);
98
99        /*Write FCW value*/
100BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_FMIX_FCW, Twos_Complement32(ulNrmLo));
101
102
103}
104
105/******************************************************************************
106*  BTNR_Ob_P_Program_TNR()
107******************************************************************************/
108void BTNR_Ob_P_Program_TNR(BTNR_Ob_3x7x_Handle hTnr, uint32_t RfFreq)
109{
110        uint8_t  CoeffSet, Index;
111
112          BDBG_MSG(("BTNR_Ob_P_Program_TNR"));
113
114         
115        if (BREG_ReadField(hTnr->hRegister, UFE_MISC_CTRL, CLKGEN_DATA_RESET) != BCHP_UFE_MISC_CTRL_CLKGEN_DATA_RESET_MASK)
116                BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, CLKGEN_DATA_RESET, 0x0); /* clear data/clkgen reset*/
117        /*HRC is bypassed*/
118        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_CTRL,                        0x001B0024);
119        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_BYP,                         0x00001004);
120                  BDBG_MSG(("BTNR_Ob_P_Program_TNR 1"));
121        BTNR_Ob_P_Program_Back_DDFS(hTnr, RfFreq);
122
123        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_RST,             0xC0000FFF );        /* reset the clock gen after BYP/CIC programming*/
124        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_RST,             0x40000FFF );        /* clear clock gen reset, but hold datapath reset*/
125        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_DCO_CTRL,        0x00000008 );
126        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC1,            0x0000000D );
127        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC2,            0x0000000B );
128        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC3,            0x00000009 );
129        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC1_THRESH,     0x00033333 );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
130        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC2_THRESH,     0x00033333 );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
131        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC3_THRESH,     0x00033333 );        /* 15dB back-off dec2hex(num2tc(10^(-15/10),2,21,0))*/
132        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_IQIMB_AMP_CTRL,  0x00000007 );
133        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_IQIMB_PHS_CTRL,  0x00000007 );
134
135        for (CoeffSet=0, Index=0;Index<BTNR_OB_SAW_COEFF_SIZE;Index++)
136        BREG_Write32(hTnr->hRegister, BCHP_UFE_SAW_OOB_COEFF0+(4*Index), BTNR_Ob_SAW_Table[CoeffSet][Index]);
137
138
139        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC1_LF,         0x06000000 );
140        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC2_LF,         0x02000000 );
141        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_AGC3_LF,         0x20000000 );
142        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_IQIMB_AMP_LF,    0x00000000 );
143        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_IQIMB_PHS_LF,    0x00000000 );
144        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_FRZ,             0x00000000 );
145        BREG_WriteField(hTnr->hRegister, UFE_OOB_CTRL, VID_QUANT,   0x4);
146
147        BREG_Write32(hTnr->hRegister, BCHP_UFE_OOB_RST,             0x00000000 );        /* clear any remaining data reset*/
148        BREG_WriteField(hTnr->hRegister, UFE_MISC_OOB_CTRL, RESET, 0x1);
149        BREG_WriteField(hTnr->hRegister, UFE_MISC_OOB_CTRL, RESET, 0x0);
150        BREG_WriteField(hTnr->hRegister, UFE_MISC_CTRL, BYP_HRC,        1 );   
151
152}
153
154
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