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bvbi_cgmse.c

Last change on this file was 76, checked in by megakiss, 10 years ago
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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_cgmse.c $
11	* $brcm_Revision: Hydra_Software_Devel/19 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_cgmse.c $
19	*
20	* Hydra_Software_Devel/19 2/20/12 2:53p darnstein
21	* SW7425-2434: more detail in error messages.
22	*
23	* Hydra_Software_Devel/18 2/20/12 12:55p darnstein
24	* SW7425-2434: when an unsupported video format is entered, the BDBG
25	* error message should be informative.
26	*
27	* Hydra_Software_Devel/17 3/24/11 4:08p darnstein
28	* SW7420-1693: For 480P video with VEC double rate (54 MHz sampling) CGMS
29	* rise times need to change.
30	*
31	* Hydra_Software_Devel/16 3/22/11 12:57p darnstein
32	* SW7420-1693: CGMS for 480P video needs to take "VEC double rate
33	* sampling" into account.
34	*
35	* Hydra_Software_Devel/15 1/20/11 4:37p darnstein
36	* SW7335-1139: CGMS-B header was bit-backwards.
37	*
38	* Hydra_Software_Devel/14 3/10/10 5:04p darnstein
39	* SW7420-598: implement Lin's settings for CGMS-A and CGMS-B. Only
40	* applies to chips with orthogonal VEC.
41	*
42	* Hydra_Software_Devel/13 3/3/10 8:07p darnstein
43	* SW7420-598: Adjust #ifdefs that select capabilities CGMS-B, CGMS-Bd.
44	*
45	* Hydra_Software_Devel/12 3/3/10 2:45p darnstein
46	* SW7420-598: Implement Lin Ma's recommendations for tuning. This is a
47	* port of a similar check-in made to the 7400 branch.
48	*
49	* Hydra_Software_Devel/10 2/22/10 5:50p darnstein
50	* SW7420-539: back out the line number adjustment for 1080I CGMS. New VEC
51	* IT microcode makes this unnecessary.
52	*
53	* Hydra_Software_Devel/9 2/22/10 5:22p darnstein
54	* SW7335-666: port over changes from 7335 work. Tuning for 480P, etc.
55	*
56	* Hydra_Software_Devel/8 1/18/10 5:32p darnstein
57	* SW7420-548: New register settings from Lin Ma for 480P, CGMS-Bd.
58	*
59	* Hydra_Software_Devel/8 1/18/10 5:30p darnstein
60	* SW7420-548: New register settings from Lin Ma for 480P, CGMS-Bd.
61	*
62	* Hydra_Software_Devel/6 11/11/09 6:39p darnstein
63	* SW3556-848: newer chipsets have BIT_ORDER option for CGMS-A encoding.
64	*
65	* Hydra_Software_Devel/5 3/27/09 7:43p darnstein
66	* PR53635: Remove internal ConfigForOthers code. It is obsolete, and it
67	* was causing a problem (this PR).
68	*
69	* Hydra_Software_Devel/4 2/9/09 8:25p darnstein
70	* PR45819: no choice of CRC method in 7420-Ax? Might have to revisit
71	* this.
72	*
73	* Hydra_Software_Devel/3 2/9/09 7:58p darnstein
74	* PR45819: minor update for 7420 and CGMSAE core: version numbers.
75	*
76	* Hydra_Software_Devel/2 12/4/08 6:06p darnstein
77	* PR45819: 7420 software will now compile, but not link.
78	*
79	* Hydra_Software_Devel/1 12/3/08 8:01p darnstein
80	* PR45819:
81	*
82	***************************************************************************/
83
84	#include "bstd.h" /* standard types */
85	#include "bdbg.h" /* Dbglib */
86	#include "bkni.h" /* For critical sections */
87	#include "bvbi.h" /* VBI processing, this module. */
88	#include "bvbi_priv.h" /* VBI internal data structures */
89	#include "bavc_hdmi.h"
90
91	#if (BVBI_P_NUM_CGMSAE >= 1)
92	#include "bchp_cgmsae_0.h" /* RDB info for primary CGMSE core */
93	#endif
94	#if (BVBI_P_NUM_CGMSAE >= 2)
95	#include "bchp_cgmsae_1.h" /* RDB info for secondary CGMSE core */
96	#endif
97	#if (BVBI_P_NUM_CGMSAE >= 3)
98	#include "bchp_cgmsae_2.h" /* RDB info for tertiary CGMSE core */
99	#endif
100
101	BDBG_MODULE(BVBI);
102
103	/***************************************************************************
104	* Forward declarations of static (private) functions
105	***************************************************************************/
106
107	static uint32_t P_GetCoreOffset (bool is656, uint8_t hwCoreIndex);
108	#ifdef P_CGMS_SOFTWARE_CRC
109	static uint32_t P_CalculateCRC (uint32_t ulData);
110	#endif
111
112
113	/***************************************************************************
114	* Implementation of supporting CGMS functions that are not in API
115	***************************************************************************/
116
117	void BVBI_P_CGMS_Enc_Init (BREG_Handle hReg, bool is656, uint8_t hwCoreIndex)
118	{
119	BDBG_ENTER(BVBI_P_CGMS_Enc_Init);
120
121	BVBI_P_VIE_SoftReset (hReg, is656, hwCoreIndex, BVBI_P_SELECT_CGMSA);
122
123	BDBG_LEAVE(BVBI_P_CGMS_Enc_Init);
124	}
125
126	BERR_Code BVBI_P_CGMSA_Enc_Program (
127	BREG_Handle hReg,
128	bool is656,
129	uint8_t hwCoreIndex,
130	bool bActive,
131	BFMT_VideoFmt eVideoFormat,
132	BAVC_HDMI_PixelRepetition ePixRep)
133	{
134	/*
135	Programming note: the implementation here assumes that the bitfield layout
136	within registers is the same for all CGMS encoder cores in the chip.
137
138	If a chip is built that has multiple CGMS encoder cores that are not
139	identical, then this routine will have to be redesigned.
140	*/
141	uint32_t ulCoreOffset;
142	uint32_t ulTop_FormatReg;
143	uint32_t ulBot_FormatReg;
144	uint32_t ulTop_ControlReg;
145	uint32_t ulBot_ControlReg;
146
147	uint32_t rise_time;
148	uint32_t gain;
149	uint32_t pulse_width;
150	uint32_t init_delay;
151	uint32_t top_line;
152	uint32_t bot_line;
153	uint32_t line_start;
154	uint32_t enable_top;
155	uint32_t enable_bot;
156
157	BERR_Code eErr = BERR_SUCCESS;
158
159	BDBG_ENTER(BVBI_P_CGMSA_Enc_Program);
160	BSTD_UNUSED (ePixRep);
161
162	/* Figure out which encoder core to use */
163	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
164	if (ulCoreOffset == 0xFFFFFFFF)
165	{
166	/* This should never happen! This parameter was checked by
167	BVBI_Encode_Create() */
168	BDBG_LEAVE(BVBI_P_CGMSA_Enc_Program);
169	return BERR_TRACE(BERR_INVALID_PARAMETER);
170	}
171
172	/* Determine some tuning parameters according to video standard */
173	switch (eVideoFormat)
174	{
175	case BFMT_VideoFmt_eNTSC:
176	case BFMT_VideoFmt_eNTSC_J:
177	rise_time = BCHP_CGMSAE_0_Top_Control_RISE_TIME_MED;
178	gain = 0x62;
179	pulse_width = 0x1E3;
180	init_delay = 0x55;
181	top_line = 20;
182	bot_line = 283 - 256;
183	line_start = BCHP_CGMSAE_0_Bot_Control_VBI_START_LINE256;
184	#ifdef P_CGMS_SOFTWARE_CRC
185	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
186	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
187	#else
188	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
189	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
190	#endif
191	break;
192
193	case BFMT_VideoFmt_e1080i:
194	case BFMT_VideoFmt_e1080i_50Hz:
195	rise_time = BCHP_CGMSAE_0_Top_Control_RISE_TIME_FAST;
196	gain = 0x67;
197	pulse_width = 0x268;
198	init_delay = 0xAF;
199	top_line = 19;
200	bot_line = 582 - 544;
201	line_start = BCHP_CGMSAE_0_Bot_Control_VBI_START_LINE544;
202	#ifdef P_CGMS_SOFTWARE_CRC
203	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
204	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
205	#else
206	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
207	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
208	#endif
209	break;
210
211	case BFMT_VideoFmt_e720p:
212	case BFMT_VideoFmt_e720p_50Hz:
213	rise_time = BCHP_CGMSAE_0_Top_Control_RISE_TIME_FAST;
214	gain = 0x67;
215	pulse_width = 0x1D0;
216	init_delay = 0xB;
217	top_line = 24;
218	bot_line = 0;
219	line_start = 0;
220	#ifdef P_CGMS_SOFTWARE_CRC
221	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
222	#else
223	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
224	#endif
225	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
226	break;
227
228	case BFMT_VideoFmt_e576p_50Hz:
229	/* TODO: tune these settings */
230	rise_time = 1;
231	gain = 0x62;
232	pulse_width = 0x86;
233	init_delay = 0x26;
234	top_line = 43;
235	bot_line = 0;
236	line_start = 0;
237	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
238	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
239	break;
240
241	case BFMT_VideoFmt_e480p:
242	/* VEC is operating at double rate (54 MHz sampling) */
243	rise_time = BCHP_CGMSAE_0_Top_Control_RISE_TIME_MED;
244	gain = 0x67;
245	pulse_width = 0x1A0;
246	init_delay = 0x3E;
247	top_line = 41;
248	bot_line = 0;
249	line_start = 0;
250	#ifdef P_CGMS_SOFTWARE_CRC
251	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
252	#else
253	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
254	#endif
255	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
256	break;
257
258	default:
259	/* Shut up with the compiler warnings */
260	rise_time = 0;
261	gain = 0x0;
262	pulse_width = 0;
263	init_delay = 0;
264	top_line = 0;
265	bot_line = 0;
266	line_start = 0;
267	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
268	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
269	if (bActive)
270	{
271	BDBG_ERR(("BVBI_CGMSE: video format %d not supported",
272	eVideoFormat));
273	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
274	}
275	break;
276	}
277
278	BKNI_EnterCriticalSection();
279
280	/* Read control registers */
281	ulTop_ControlReg =
282	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Top_Control + ulCoreOffset );
283	ulBot_ControlReg =
284	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Bot_Control + ulCoreOffset );
285
286	/* If enabling encoding */
287	if (bActive)
288	{
289	/* Fill in the control registers */
290	ulTop_ControlReg &= ~(
291	BCHP_MASK ( CGMSAE_0_Top_Control, RISE_TIME ) \|
292	BCHP_MASK ( CGMSAE_0_Top_Control, GAIN ) \|
293	BCHP_MASK ( CGMSAE_0_Top_Control, RAW_COUNT ) \|
294	BCHP_MASK ( CGMSAE_0_Top_Control, VBI_LINE ) \|
295	#if defined(BVBI_P_CGMSAE_VER1) \|\| defined(BVBI_P_CGMSAE_VER3) \|\| \
296	defined(BVBI_P_CGMSAE_VER5)
297	BCHP_MASK ( CGMSAE_0_Top_Control, BIT_ORDER ) \|
298	#endif
299	BCHP_MASK ( CGMSAE_0_Top_Control, ENABLE ) );
300	ulTop_ControlReg \|= (
301	BCHP_FIELD_DATA ( CGMSAE_0_Top_Control, RISE_TIME, rise_time ) \|
302	BCHP_FIELD_DATA ( CGMSAE_0_Top_Control, GAIN, gain ) \|
303	BCHP_FIELD_DATA ( CGMSAE_0_Top_Control, RAW_COUNT, 21 ) \|
304	BCHP_FIELD_DATA ( CGMSAE_0_Top_Control, VBI_LINE, top_line ) \|
305	#if defined(BVBI_P_CGMSAE_VER1) \|\| defined(BVBI_P_CGMSAE_VER3) \|\| \
306	defined(BVBI_P_CGMSAE_VER5)
307	BCHP_FIELD_ENUM ( CGMSAE_0_Top_Control, BIT_ORDER, LSB_FIRST ) \|
308	#endif
309	BCHP_FIELD_DATA ( CGMSAE_0_Top_Control, ENABLE, enable_top ) );
310	ulBot_ControlReg &= ~(
311	BCHP_MASK ( CGMSAE_0_Bot_Control, GAIN ) \|
312	BCHP_MASK ( CGMSAE_0_Bot_Control, RAW_COUNT ) \|
313	BCHP_MASK ( CGMSAE_0_Bot_Control, VBI_LINE ) \|
314	BCHP_MASK ( CGMSAE_0_Bot_Control, VBI_START ) \|
315	#if defined(BVBI_P_CGMSAE_VER1) \|\| defined(BVBI_P_CGMSAE_VER3) \|\| \
316	defined(BVBI_P_CGMSAE_VER5)
317	BCHP_MASK ( CGMSAE_0_Bot_Control, BIT_ORDER ) \|
318	#endif
319	BCHP_MASK ( CGMSAE_0_Bot_Control, ENABLE ) );
320	ulBot_ControlReg \|= (
321	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Control, GAIN, gain ) \|
322	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Control, RAW_COUNT, 21 ) \|
323	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Control, VBI_LINE, bot_line ) \|
324	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Control, VBI_START,line_start ) \|
325	#if defined(BVBI_P_CGMSAE_VER1) \|\| defined(BVBI_P_CGMSAE_VER3) \|\| \
326	defined(BVBI_P_CGMSAE_VER5)
327	BCHP_FIELD_ENUM ( CGMSAE_0_Bot_Control, BIT_ORDER, LSB_FIRST ) \|
328	#endif
329	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Control, ENABLE, enable_bot ) );
330
331	/* Program the format registers */
332	ulTop_FormatReg =
333	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Top_Format + ulCoreOffset );
334	ulTop_FormatReg &= ~(
335	BCHP_MASK ( CGMSAE_0_Top_Format, PULSE_WIDTH ) \|
336	BCHP_MASK ( CGMSAE_0_Top_Format, INIT_DELAY ) );
337	ulTop_FormatReg \|= (
338	BCHP_FIELD_DATA ( CGMSAE_0_Top_Format, PULSE_WIDTH,
339	pulse_width ) \|
340	BCHP_FIELD_DATA ( CGMSAE_0_Top_Format, INIT_DELAY,
341	init_delay ) );
342	BREG_Write32 (
343	hReg, BCHP_CGMSAE_0_Top_Format + ulCoreOffset, ulTop_FormatReg );
344	ulBot_FormatReg =
345	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Bot_Format + ulCoreOffset );
346	ulBot_FormatReg &= ~(
347	BCHP_MASK ( CGMSAE_0_Bot_Format, PULSE_WIDTH ) \|
348	BCHP_MASK ( CGMSAE_0_Bot_Format, INIT_DELAY ) );
349	ulBot_FormatReg \|= (
350	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Format, PULSE_WIDTH,
351	pulse_width ) \|
352	BCHP_FIELD_DATA ( CGMSAE_0_Bot_Format, INIT_DELAY,
353	init_delay ) );
354	BREG_Write32 (
355	hReg, BCHP_CGMSAE_0_Bot_Format + ulCoreOffset, ulBot_FormatReg );
356	}
357	else /* Disable encoding */
358	{
359	ulTop_ControlReg &=
360	~BCHP_MASK ( CGMSAE_0_Top_Control, ENABLE );
361	ulTop_ControlReg \|=
362	BCHP_FIELD_ENUM ( CGMSAE_0_Top_Control, ENABLE, DISABLED );
363	ulBot_ControlReg &=
364	~BCHP_MASK ( CGMSAE_0_Bot_Control, ENABLE );
365	ulBot_ControlReg \|=
366	BCHP_FIELD_ENUM ( CGMSAE_0_Bot_Control, ENABLE, DISABLED );
367	}
368
369	/* Write the finished control register values */
370	BREG_Write32 (
371	hReg, BCHP_CGMSAE_0_Top_Control + ulCoreOffset, ulTop_ControlReg );
372	BREG_Write32 (
373	hReg, BCHP_CGMSAE_0_Bot_Control + ulCoreOffset, ulBot_ControlReg );
374
375	BKNI_LeaveCriticalSection();
376
377	BDBG_LEAVE(BVBI_P_CGMSA_Enc_Program);
378	return eErr;
379	}
380
381	uint32_t BVBI_P_CGMSA_Encode_Data_isr (
382	BREG_Handle hReg,
383	bool is656,
384	uint8_t hwCoreIndex,
385	BAVC_Polarity polarity,
386	uint32_t ulData)
387	{
388	uint32_t ulCoreOffset;
389	uint32_t ulErrInfo = 0;
390
391	/* Debug code
392	static uint32_t debugcounter = 0;
393	++debugcounter;
394	*/
395
396	BDBG_ENTER(BVBI_P_CGMSA_Encode_Data_isr);
397
398	/* Get register offset */
399	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
400	if (ulCoreOffset == 0xFFFFFFFF)
401	{
402	/* Should never happen */
403	BDBG_LEAVE(BVBI_P_CGMSA_Encode_Data_isr);
404	return 0xFFFFFFFF;
405	}
406
407	/* If top field */
408	if ((polarity == BAVC_Polarity_eTopField) \|\|
409	(polarity == BAVC_Polarity_eFrame ) )
410	{
411	/* Write new register value */
412	BREG_Write32 (
413	hReg, BCHP_CGMSAE_0_Top_Data + ulCoreOffset, ulData );
414
415	/* Debug code
416	if ((debugcounter > 200) && (debugcounter <= 220))
417	printf ("Wrote %08x to top field\n", ulData);
418	*/
419	}
420	else /* polarity == BAVC_Polarity_eBotField */
421	{
422	/* Write new register value */
423	BREG_Write32 (
424	hReg, BCHP_CGMSAE_0_Bot_Data + ulCoreOffset, ulData );
425
426	/* Debug code
427	if ((debugcounter > 200) && (debugcounter <= 220))
428	printf ("Wrote %08x to bottom field\n", ulData);
429	*/
430	}
431
432	BDBG_LEAVE(BVBI_P_CGMSA_Encode_Data_isr);
433	return ulErrInfo;
434	}
435
436	/***************************************************************************
437	*
438	*/
439	BERR_Code BVBI_P_CGMSA_Encode_Enable_isr (
440	BREG_Handle hReg,
441	bool is656,
442	uint8_t hwCoreIndex,
443	BFMT_VideoFmt eVideoFormat,
444	bool bEnable)
445	{
446	uint32_t ulCoreOffset;
447	uint32_t ulControlReg;
448	uint32_t enable_top;
449	uint32_t enable_bot;
450
451	BDBG_ENTER(BVBI_P_CGMSA_Encode_Enable_isr);
452
453	/* Figure out which encoder core to use */
454	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
455	if (ulCoreOffset == 0xFFFFFFFF)
456	{
457	/* This should never happen! This parameter was checked by
458	BVBI_Encode_Create() */
459	BDBG_LEAVE(BVBI_P_CGMSA_Encode_Enable_isr);
460	BDBG_ERR(("Invalid parameter\n"));
461	return BERR_TRACE(BERR_INVALID_PARAMETER);
462	}
463
464	/* Determine a tuning parameter according to video standard */
465	switch (eVideoFormat)
466	{
467	case BFMT_VideoFmt_eNTSC:
468	case BFMT_VideoFmt_eNTSC_J:
469	#ifdef P_CGMS_SOFTWARE_CRC
470	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
471	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
472	#else
473	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
474	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
475	#endif
476	break;
477
478	case BFMT_VideoFmt_e1080i:
479	#ifdef P_CGMS_SOFTWARE_CRC
480	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
481	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
482	#else
483	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
484	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
485	#endif
486	break;
487
488	case BFMT_VideoFmt_e1080i_50Hz:
489	#ifdef P_CGMS_SOFTWARE_CRC
490	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
491	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
492	#else
493	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
494	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
495	#endif
496	break;
497
498	case BFMT_VideoFmt_e720p:
499	#ifdef P_CGMS_SOFTWARE_CRC
500	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
501	#else
502	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
503	#endif
504	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
505	break;
506
507	case BFMT_VideoFmt_e720p_50Hz:
508	#ifdef P_CGMS_SOFTWARE_CRC
509	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
510	#else
511	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
512	#endif
513	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
514	break;
515
516	case BFMT_VideoFmt_e480p:
517	#ifdef P_CGMS_SOFTWARE_CRC
518	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
519	#else
520	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_CGMSA;
521	#endif
522	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
523	break;
524
525	case BFMT_VideoFmt_e576p_50Hz:
526	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_RAW_DATA;
527	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
528	break;
529
530	default:
531	/* Shut up with the compiler warning */
532	enable_top = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
533	enable_bot = BCHP_CGMSAE_0_Bot_Control_ENABLE_DISABLED;
534	if (bEnable)
535	{
536	BDBG_ERR(("BVBI_CGMSE: video format %d not supported",
537	eVideoFormat));
538	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
539	}
540	break;
541	}
542
543	ulControlReg =
544	BREG_Read32 (hReg, BCHP_CGMSAE_0_Top_Control + ulCoreOffset);
545	ulControlReg &=
546	~BCHP_MASK (CGMSAE_0_Top_Control, ENABLE);
547	if (bEnable)
548	{
549	ulControlReg \|=
550	BCHP_FIELD_DATA (CGMSAE_0_Top_Control, ENABLE, enable_top);
551	}
552	else
553	{
554	ulControlReg \|=
555	BCHP_FIELD_ENUM (CGMSAE_0_Top_Control, ENABLE, DISABLED);
556	}
557	BREG_Write32 (hReg, BCHP_CGMSAE_0_Top_Control + ulCoreOffset, ulControlReg);
558
559	ulControlReg =
560	BREG_Read32 (hReg, BCHP_CGMSAE_0_Bot_Control + ulCoreOffset);
561	ulControlReg &=
562	~BCHP_MASK (CGMSAE_0_Bot_Control, ENABLE);
563	if (bEnable)
564	{
565	ulControlReg \|=
566	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control, ENABLE, enable_bot);
567	}
568	else
569	{
570	ulControlReg \|=
571	BCHP_FIELD_ENUM (CGMSAE_0_Bot_Control, ENABLE, DISABLED);
572	}
573	BREG_Write32 (
574	hReg, BCHP_CGMSAE_0_Bot_Control + ulCoreOffset, ulControlReg);
575
576	BDBG_LEAVE(BVBI_P_CGMSA_Encode_Enable_isr);
577	return BERR_SUCCESS;
578	}
579
580	#if defined(BVBI_P_CGMSAE_VER2) \|\| defined(BVBI_P_CGMSAE_VER3) \|\| \
581	defined(BVBI_P_CGMSAE_VER5) / { /
582
583	/***************************************************************************
584	*
585	*/
586	uint32_t BVBI_P_CGMSB_Encode_Data_isr (
587	BREG_Handle hReg,
588	bool is656,
589	uint8_t hwCoreIndex,
590	BAVC_Polarity polarity,
591	BVBI_CGMSB_Datum cgmsbDatum )
592	{
593	uint32_t ulCoreOffset;
594	uint32_t ulUpdate;
595	uint32_t ulErrInfo = 0;
596
597	BDBG_ENTER(BVBI_P_CGMSB_Encode_Data_isr);
598
599	/* Get register offset */
600	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
601	if (ulCoreOffset == 0xFFFFFFFF)
602	{
603	/* Should never happen */
604	BDBG_LEAVE(BVBI_P_CGMSB_Encode_Data_isr);
605	return 0xFFFFFFFF;
606	}
607
608	/* If top field */
609	if ((polarity == BAVC_Polarity_eTopField) \|\|
610	(polarity == BAVC_Polarity_eFrame ) )
611	{
612	/* Write new register values */
613	BREG_Write32 (
614	hReg, BCHP_CGMSAE_0_Top_Data_B0 + ulCoreOffset, cgmsbDatum[0] );
615	BREG_Write32 (
616	hReg, BCHP_CGMSAE_0_Top_Data_B1 + ulCoreOffset, cgmsbDatum[1] );
617	BREG_Write32 (
618	hReg, BCHP_CGMSAE_0_Top_Data_B2 + ulCoreOffset, cgmsbDatum[2] );
619	BREG_Write32 (
620	hReg, BCHP_CGMSAE_0_Top_Data_B3 + ulCoreOffset, cgmsbDatum[3] );
621	BREG_Write32 (
622	hReg, BCHP_CGMSAE_0_Top_Data_B4 + ulCoreOffset, cgmsbDatum[4] );
623	ulUpdate = BCHP_FIELD_DATA (CGMSAE_0_Reg_updt, TOP, 1);
624	}
625	else /* polarity == BAVC_Polarity_eBotField */
626	{
627	/* Write new register values */
628	BREG_Write32 (
629	hReg, BCHP_CGMSAE_0_Bot_Data_B0 + ulCoreOffset, cgmsbDatum[0] );
630	BREG_Write32 (
631	hReg, BCHP_CGMSAE_0_Bot_Data_B1 + ulCoreOffset, cgmsbDatum[1] );
632	BREG_Write32 (
633	hReg, BCHP_CGMSAE_0_Bot_Data_B2 + ulCoreOffset, cgmsbDatum[2] );
634	BREG_Write32 (
635	hReg, BCHP_CGMSAE_0_Bot_Data_B3 + ulCoreOffset, cgmsbDatum[3] );
636	BREG_Write32 (
637	hReg, BCHP_CGMSAE_0_Bot_Data_B4 + ulCoreOffset, cgmsbDatum[4] );
638	ulUpdate = BCHP_FIELD_DATA (CGMSAE_0_Reg_updt, BOT, 1);
639	}
640
641	/* Tell hardware we are done */
642	BREG_Write32 (hReg, BCHP_CGMSAE_0_Reg_updt + ulCoreOffset, ulUpdate);
643
644	BDBG_LEAVE(BVBI_P_CGMSB_Encode_Data_isr);
645	return ulErrInfo;
646	}
647
648
649	/***************************************************************************
650	*
651	*/
652	BERR_Code BVBI_P_CGMSB_Enc_Program (
653	BREG_Handle hReg,
654	bool is656,
655	uint8_t hwCoreIndex,
656	bool bActive,
657	BFMT_VideoFmt eVideoFormat,
658	BAVC_HDMI_PixelRepetition ePixRep,
659	bool bCea805dStyle)
660	{
661	/*
662	Programming note: the implementation here assumes that the bitfield layout
663	within registers is the same for all CGMS encoder cores in the chip.
664
665	If a chip is built that has multiple CGMS encoder cores that are not
666	identical, then this routine will have to be redesigned.
667	*/
668	uint32_t ulCoreOffset;
669	uint32_t ulTop_FormatReg;
670	uint32_t ulBot_FormatReg;
671	uint32_t ulTop_ControlReg;
672	uint32_t ulBot_ControlReg;
673
674	uint32_t rise_time;
675	uint32_t gain;
676	uint32_t pulse_width;
677	uint32_t init_delay;
678	uint32_t top_line;
679	uint32_t bot_line;
680	uint32_t line_start;
681	uint32_t enable_top;
682	uint32_t enable_bot;
683	#if !defined(BVBI_P_CGMSAE_VER4)
684	uint32_t bit_order;
685	#endif
686	#if !defined(BVBI_P_CGMSAE_VER2)
687	uint32_t crc_meth;
688	#endif
689
690	BERR_Code eErr = BERR_SUCCESS;
691
692	BDBG_ENTER(BVBI_P_CGMSB_Enc_Program);
693	BSTD_UNUSED (ePixRep);
694
695	#if defined(BVBI_P_CGMSAE_VER2)
696	BSTD_UNUSED (bCea805dStyle);
697	#endif
698
699	/* Figure out which encoder core to use */
700	ulCoreOffset = P_GetCoreOffset (is656, hwCoreIndex);
701	if (ulCoreOffset == 0xFFFFFFFF)
702	{
703	/* This should never happen! This parameter was checked by
704	BVBI_Encode_Create() */
705	BDBG_LEAVE(BVBI_P_CGMSB_Enc_Program);
706	return BERR_TRACE(BERR_INVALID_PARAMETER);
707	}
708
709	/* Determine some tuning parameters according to video standard */
710	switch (eVideoFormat)
711	{
712	case BFMT_VideoFmt_eNTSC:
713	case BFMT_VideoFmt_eNTSC_J:
714	rise_time = BCHP_CGMSAE_0_Top_Control_B_RISE_TIME_MED;
715	gain = 0x62;
716	pulse_width = 0x1E3;
717	init_delay = 0x55;
718	top_line = 20;
719	bot_line = 283 - 256;
720	line_start = BCHP_CGMSAE_0_Bot_Control_B_VBI_START_LINE256;
721	#ifdef P_CGMS_SOFTWARE_CRC
722	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_RAW_DATA;
723	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_RAW_DATA;
724	#else
725	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_CGMSA;
726	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_CGMSA;
727	#endif
728	break;
729
730	case BFMT_VideoFmt_e1080i:
731	case BFMT_VideoFmt_e1080i_50Hz:
732	rise_time = 2;
733	gain = 0x5F;
734	pulse_width = 0x54;
735	init_delay = 0xAF;
736	top_line = 18;
737	bot_line = 581 - 544;
738	line_start = BCHP_CGMSAE_0_Bot_Control_B_VBI_START_LINE544;
739	#ifdef P_CGMS_SOFTWARE_CRC
740	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_RAW_DATA;
741	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_RAW_DATA;
742	#else
743	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_CGMSA;
744	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_CGMSA;
745	#endif
746	break;
747
748	case BFMT_VideoFmt_e720p:
749	case BFMT_VideoFmt_e720p_50Hz:
750	rise_time = BCHP_CGMSAE_0_Top_Control_B_RISE_TIME_FAST_37;
751	gain = 0x68;
752	pulse_width = 0x47;
753	init_delay = 0x10;
754	top_line = 23;
755	bot_line = 0;
756	line_start = 0;
757	#ifdef P_CGMS_SOFTWARE_CRC
758	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_RAW_DATA;
759	#else
760	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_CGMSA;
761	#endif
762	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_DISABLED;
763	break;
764
765	case BFMT_VideoFmt_e576p_50Hz:
766	/* TODO: tune these settings */
767	rise_time = 1;
768	gain = 0x62;
769	pulse_width = 0x86;
770	init_delay = 0x26;
771	top_line = 43;
772	bot_line = 0;
773	line_start = 0;
774	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_RAW_DATA;
775	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_DISABLED;
776	break;
777
778	case BFMT_VideoFmt_e480p:
779	/* VEC is operating at double rate (54 MHz) */
780	rise_time = BCHP_CGMSAE_0_Top_Control_B_RISE_TIME_MED_37;
781	gain = 0x62;
782	pulse_width = 0x40;
783	init_delay = 0x4C;
784	top_line = 40;
785	bot_line = 0;
786	line_start = 0;
787	#ifdef P_CGMS_SOFTWARE_CRC
788	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_RAW_DATA;
789	#else
790	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_CGMSA;
791	#endif
792	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_DISABLED;
793	break;
794
795	default:
796	/* Shut up with the compiler warnings */
797	rise_time = 0;
798	gain = 0x0;
799	pulse_width = 0;
800	init_delay = 0;
801	top_line = 0;
802	bot_line = 0;
803	line_start = 0;
804	enable_top = BCHP_CGMSAE_0_Top_Control_B_ENABLE_DISABLED;
805	enable_bot = BCHP_CGMSAE_0_Bot_Control_B_ENABLE_DISABLED;
806	if (bActive)
807	{
808	BDBG_ERR(("BVBI_CGMSE: video format %d not supported",
809	eVideoFormat));
810	return BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
811	}
812	break;
813	}
814
815	/* Make the choice defined in CEA-805-D */
816	#if defined(BVBI_P_CGMSAE_VER3) \|\| defined(BVBI_P_CGMSAE_VER5)/ { /
817	/* Being careful */
818	#if BCHP_CGMSAE_0_Top_Control_BIT_ORDER_MSB_FIRST != \
819	BCHP_CGMSAE_0_Bot_Control_BIT_ORDER_MSB_FIRST
820	#error Programming error
821	#endif
822	#if BCHP_CGMSAE_0_Top_Control_BIT_ORDER_LSB_FIRST != \
823	BCHP_CGMSAE_0_Bot_Control_BIT_ORDER_LSB_FIRST
824	#error Programming error
825	#endif
826	#endif / } /
827	#if BCHP_CGMSAE_0_Top_Control_B_CRC_METHOD_METHOD1 != \
828	BCHP_CGMSAE_0_Bot_Control_B_CRC_METHOD_METHOD1
829	#error Programming error
830	#endif
831	#if BCHP_CGMSAE_0_Top_Control_B_CRC_METHOD_METHOD2 != \
832	BCHP_CGMSAE_0_Bot_Control_B_CRC_METHOD_METHOD2
833	#error Programming error
834	#endif
835	if (bCea805dStyle)
836	{
837	crc_meth = BCHP_CGMSAE_0_Top_Control_B_CRC_METHOD_METHOD2;
838	}
839	else
840	{
841	crc_meth = BCHP_CGMSAE_0_Top_Control_B_CRC_METHOD_METHOD1;
842	}
843	#if !defined(BVBI_P_CGMSAE_VER4)
844	bit_order = BCHP_CGMSAE_0_Top_Control_BIT_ORDER_MSB_FIRST;
845	#endif
846
847	BKNI_EnterCriticalSection();
848
849	/* Read control registers */
850	ulTop_ControlReg =
851	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Top_Control_B + ulCoreOffset );
852	ulBot_ControlReg =
853	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Bot_Control_B + ulCoreOffset );
854
855	/* If enabling encoding */
856	if (bActive)
857	{
858	/* Fill in the control registers */
859	ulTop_ControlReg &= ~(
860	BCHP_MASK (CGMSAE_0_Top_Control_B, RISE_TIME ) \|
861	BCHP_MASK (CGMSAE_0_Top_Control_B, GAIN ) \|
862	BCHP_MASK (CGMSAE_0_Top_Control_B, RAW_COUNT ) \|
863	BCHP_MASK (CGMSAE_0_Top_Control_B, VBI_LINE ) \|
864	#if !defined(BVBI_P_CGMSAE_VER4)
865	BCHP_MASK (CGMSAE_0_Top_Control_B, BIT_ORDER ) \|
866	#endif
867	#if !defined(BVBI_P_CGMSAE_VER4)
868	BCHP_MASK (CGMSAE_0_Top_Control_B, CRC_METHOD ) \|
869	#endif
870	BCHP_MASK (CGMSAE_0_Top_Control_B, ENABLE ) );
871	ulTop_ControlReg \|= (
872	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, RISE_TIME, rise_time) \|
873	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, GAIN, gain) \|
874	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, RAW_COUNT, 21) \|
875	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, VBI_LINE, top_line) \|
876	#if !defined(BVBI_P_CGMSAE_VER4)
877	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, BIT_ORDER, bit_order) \|
878	#endif
879	#if !defined(BVBI_P_CGMSAE_VER4)
880	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, CRC_METHOD, crc_meth) \|
881	#endif
882	BCHP_FIELD_DATA (CGMSAE_0_Top_Control_B, ENABLE, enable_top) );
883	ulBot_ControlReg &= ~(
884	BCHP_MASK (CGMSAE_0_Bot_Control_B, GAIN ) \|
885	BCHP_MASK (CGMSAE_0_Bot_Control_B, RAW_COUNT ) \|
886	BCHP_MASK (CGMSAE_0_Bot_Control_B, VBI_LINE ) \|
887	BCHP_MASK (CGMSAE_0_Bot_Control_B, VBI_START ) \|
888	#if !defined(BVBI_P_CGMSAE_VER4)
889	BCHP_MASK (CGMSAE_0_Bot_Control_B, BIT_ORDER ) \|
890	#endif
891	#if !defined(BVBI_P_CGMSAE_VER4)
892	BCHP_MASK (CGMSAE_0_Bot_Control_B, CRC_METHOD ) \|
893	#endif
894	BCHP_MASK (CGMSAE_0_Bot_Control_B, ENABLE ) );
895	ulBot_ControlReg \|= (
896	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, GAIN, gain) \|
897	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, RAW_COUNT, 21) \|
898	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, VBI_LINE, bot_line) \|
899	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, VBI_START,line_start) \|
900	#if !defined(BVBI_P_CGMSAE_VER4)
901	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, BIT_ORDER, bit_order) \|
902	#endif
903	#if !defined(BVBI_P_CGMSAE_VER4)
904	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, CRC_METHOD, crc_meth) \|
905	#endif
906	BCHP_FIELD_DATA (CGMSAE_0_Bot_Control_B, ENABLE, enable_bot) );
907
908	/* Program the format registers */
909	ulTop_FormatReg =
910	BREG_Read32 ( hReg, BCHP_CGMSAE_0_Top_Format_B + ulCoreOffset);
911	ulTop_FormatReg &= ~(
912	BCHP_MASK (CGMSAE_0_Top_Format_B, HEADER ) \|
913	BCHP_MASK (CGMSAE_0_Top_Format_B, PULSE_WIDTH ) \|
914	BCHP_MASK (CGMSAE_0_Top_Format_B, INIT_DELAY ) );
915	ulTop_FormatReg \|= (
916	BCHP_FIELD_DATA (CGMSAE_0_Top_Format_B, HEADER, 0x32) \|
917	BCHP_FIELD_DATA (CGMSAE_0_Top_Format_B, PULSE_WIDTH,
918	pulse_width ) \|
919	BCHP_FIELD_DATA (CGMSAE_0_Top_Format_B, INIT_DELAY,
920	init_delay ) );
921	BREG_Write32 (
922	hReg, BCHP_CGMSAE_0_Top_Format_B + ulCoreOffset,
923	ulTop_FormatReg);
924	ulBot_FormatReg =
925	BREG_Read32 (hReg, BCHP_CGMSAE_0_Bot_Format_B + ulCoreOffset);
926	ulBot_FormatReg &= ~(
927	BCHP_MASK (CGMSAE_0_Bot_Format_B, HEADER ) \|
928	BCHP_MASK (CGMSAE_0_Bot_Format_B, PULSE_WIDTH ) \|
929	BCHP_MASK (CGMSAE_0_Bot_Format_B, INIT_DELAY ) );
930	ulBot_FormatReg \|= (
931	BCHP_FIELD_DATA (CGMSAE_0_Bot_Format_B, HEADER, 0x32) \|
932	BCHP_FIELD_DATA (CGMSAE_0_Bot_Format_B, PULSE_WIDTH,
933	pulse_width) \|
934	BCHP_FIELD_DATA (CGMSAE_0_Bot_Format_B, INIT_DELAY,
935	init_delay) );
936	BREG_Write32 (
937	hReg, BCHP_CGMSAE_0_Bot_Format_B + ulCoreOffset,
938	ulBot_FormatReg );
939	}
940	else /* Disable encoding */
941	{
942	ulTop_ControlReg &=
943	~BCHP_MASK (CGMSAE_0_Top_Control_B, ENABLE );
944	ulTop_ControlReg \|=
945	BCHP_FIELD_ENUM (CGMSAE_0_Top_Control_B, ENABLE, DISABLED);
946	ulBot_ControlReg &=
947	~BCHP_MASK (CGMSAE_0_Bot_Control_B, ENABLE );
948	ulBot_ControlReg \|=
949	BCHP_FIELD_ENUM (CGMSAE_0_Bot_Control_B, ENABLE, DISABLED);
950	}
951
952	/* Write the finished control register values */
953	BREG_Write32 (
954	hReg, BCHP_CGMSAE_0_Top_Control_B + ulCoreOffset, ulTop_ControlReg);
955	BREG_Write32 (
956	hReg, BCHP_CGMSAE_0_Bot_Control_B + ulCoreOffset, ulBot_ControlReg);
957
958	BKNI_LeaveCriticalSection();
959
960	BDBG_LEAVE(BVBI_P_CGMSB_Enc_Program);
961	return eErr;
962	}
963
964	#endif / } /
965
966
967	/***************************************************************************
968	* Static (private) functions
969	***************************************************************************/
970
971	/***************************************************************************
972	*
973	*/
974	static uint32_t P_GetCoreOffset (bool is656, uint8_t hwCoreIndex)
975	{
976	uint32_t ulCoreOffset = 0xFFFFFFFF;
977
978	if (is656)
979	{
980	#if (BVBI_P_NUM_CGMSAE_656 >= 1)
981	/* No CGMSA 656 encoder */
982	#endif
983	}
984	else
985	{
986	switch (hwCoreIndex)
987	{
988	#if (BVBI_P_NUM_CGMSAE >= 1)
989	case 0:
990	ulCoreOffset = 0;
991	break;
992	#endif
993	#if (BVBI_P_NUM_CGMSAE >= 2)
994	case 1:
995	ulCoreOffset = (BCHP_CGMSAE_1_RevID - BCHP_CGMSAE_0_RevID);
996	break;
997	#endif
998	#if (BVBI_P_NUM_CGMSAE >= 3)
999	case 2:
1000	ulCoreOffset = (BCHP_CGMSAE_2_RevID - BCHP_CGMSAE_0_RevID);
1001	break;
1002	#endif
1003	default:
1004	break;
1005	}
1006	}
1007
1008	return ulCoreOffset;
1009	}
1010
1011	#ifdef P_CGMS_SOFTWARE_CRC
1012	/*********************************************************************func
1013	* P_CalculateCRC
1014	*
1015	* Calculates the CRC value for CGMS data. This was done due to replace
1016	* the calculation done by hardware.
1017	*
1018	* Tests:
1019	* 0x141 -> CRC of 0x3d
1020	* 0x1c0 -> CRC of 0x0b
1021	* 0x0c1 -> CRC of 0x24
1022	*/
1023	static uint32_t P_CalculateCRC (uint32_t ulData)
1024	{
1025	int i;
1026	uint32_t ulGate;
1027	uint32_t ulCRC = (((uint32_t)1) << 6) - 1; /* initially set to all 1s */
1028	uint32_t ulGatePolynomial;
1029
1030	/* mask out any current CRC */
1031	ulData &= (((uint32_t)1)<<14) - 1;
1032
1033	/* traverse through all data bits */
1034	for (i=0; i<14; ++i)
1035	{
1036	/* calculate 1 bit gate value */
1037	ulGate = ((ulData >> i) ^ (ulCRC)) & 0x1;
1038
1039	/* gate set? */
1040	if (ulGate)
1041	{
1042	/* use polynomial */
1043	ulGatePolynomial = 0x10;
1044
1045	/* gate not set */
1046	} else
1047	{
1048	/* don't use gate polynomial */
1049	ulGatePolynomial = 0x0;
1050	}
1051
1052	/* calculate new CRC */
1053	ulCRC = ((ulCRC >> 1) ^ ulGatePolynomial) \| (ulGate << 5);
1054	}
1055
1056	/* return data with calculated CRC */
1057	return ulData \| (ulCRC << 14);
1058	}
1059	#endif

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source: svn/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_cgmse.c

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