source: svn/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_vie.c

Last change on this file was 76, checked in by megakiss, 10 years ago

1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함
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1
2/***************************************************************************
3 *     Copyright (c) 2003-2011, Broadcom Corporation
4 *     All Rights Reserved
5 *     Confidential Property of Broadcom Corporation
6 *
7 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
8 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
9 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
10 *
11 * $brcm_Workfile: bvbi_vie.c $
12 * $brcm_Revision: Hydra_Software_Devel/23 $
13 * $brcm_Date: 10/28/11 2:41p $
14 *
15 * Module Description:
16 *
17 * Revision History:
18 *
19 * $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_vie.c $
20 *
21 * Hydra_Software_Devel/23   10/28/11 2:41p darnstein
22 * SW7435-14: port to 7435. Same software behavior as for 7425.
23 *
24 * Hydra_Software_Devel/22   9/9/11 7:12p darnstein
25 * SW7429-15: trivial adaptation to 7429 chipset.
26 *
27 * Hydra_Software_Devel/21   6/14/11 2:29p darnstein
28 * SWDTV-7525: back out previous check-in.
29 *
30 * Hydra_Software_Devel/20   6/13/11 4:30p darnstein
31 * SWDTV-7525: trivially add support for 35330 chipset.
32 *
33 * Hydra_Software_Devel/19   4/4/11 4:20p darnstein
34 * SWBLURAY-23702: add support for 7640 chipset.
35 *
36 * Hydra_Software_Devel/18   3/24/11 7:10p darnstein
37 * SWDTV-6195: add references to new 35233 chipset.
38 *
39 * Hydra_Software_Devel/17   11/30/10 2:28p darnstein
40 * SW7231-22: support 7231 chipset in same way as 7344 and 7346.
41 *
42 * Hydra_Software_Devel/16   11/23/10 1:55p darnstein
43 * SW7552-15: port to 7552 chipset. Same code as for 7358.
44 *
45 * Hydra_Software_Devel/15   11/11/10 5:19p darnstein
46 * SW7344-8: first cut at porting BVBI to 7344.
47 *
48 * Hydra_Software_Devel/14   10/12/10 6:38p darnstein
49 * SW7358-16: initial port to 7358-A0.
50 *
51 * Hydra_Software_Devel/13   10/1/10 2:47p darnstein
52 * SW7422-46: Adapt to 7422 and 7425 chipsets.
53 *
54 * Hydra_Software_Devel/10   7/15/10 7:00p darnstein
55 * SW7422-46: very simple updates for 7422 compatibility.
56 *
57 * Hydra_Software_Devel/9   11/24/09 4:34p darnstein
58 * SW35230-16: first cut at 35230 support.
59 *
60 * Hydra_Software_Devel/8   6/24/09 5:39p darnstein
61 * PR56342: BVBI compiles for 7550 chipset now.
62 *
63 * Hydra_Software_Devel/7   6/24/09 4:59p darnstein
64 * PR56290: BVBI now compiles for 7342 chipset.
65 *
66 * Hydra_Software_Devel/6   6/24/09 4:38p darnstein
67 * PR56289: BVBI compiles for 7340 chipset now.
68 *
69 * Hydra_Software_Devel/5   1/9/09 7:17p darnstein
70 * PR45819: In the reset function, I forgot to support the AMOLE core.
71 *
72 * Hydra_Software_Devel/4   12/11/08 4:22p darnstein
73 * PR45819: program VBI_ENC and VEC_CFG cores.
74 *
75 * Hydra_Software_Devel/3   12/5/08 11:21a darnstein
76 * PR45819: these functions compile, but do not work properly.
77 *
78 * Hydra_Software_Devel/2   12/4/08 6:07p darnstein
79 * PR45819: 7420 software will now compile, but not link.
80 *
81 * Hydra_Software_Devel/2   12/3/08 7:58p darnstein
82 * PR45819: New, more modular form of most BVBI source files.
83 *
84 * Hydra_Software_Devel/7   7/17/08 8:45p darnstein
85 * PR44539: compilation now possible for 7601.
86 *
87 * Hydra_Software_Devel/6   6/6/08 5:36p darnstein
88 * PR38956: compile in support for SCTE and AMOL in 93548.
89 *
90 * Hydra_Software_Devel/5   4/28/08 7:49p darnstein
91 * PR38956: CGMS-B encoding ready for bring-up. Need accurate register
92 * settings for tuning.
93 *
94 * Hydra_Software_Devel/4   4/2/08 7:55p darnstein
95 * PR38956: VBI software compiles now.
96 *
97 * Hydra_Software_Devel/3   11/16/07 11:32a darnstein
98 * PR29723: Improve handling of non-existent cores in soft reset service
99 * routine.
100 *
101 * Hydra_Software_Devel/2   9/11/07 5:18p darnstein
102 * PR25708: First release of SCTE encoder software.
103 *
104 * Hydra_Software_Devel/1   12/14/06 7:15p darnstein
105 * PR25990: Programming for the VBI_ENC core.
106 *
107 ***************************************************************************/
108
109#include "bstd.h"                       /* standard types */
110#include "bdbg.h"                       /* Dbglib */
111#include "bvbi.h"                       /* VBI processing, this module. */
112#include "bvbi_priv.h"          /* VBI internal data structures */
113#include "bchp_vec_cfg.h"
114
115BDBG_MODULE(BVBI);
116
117/* Welcome to alias central */
118#if (BCHP_CHIP == 7422) || (BCHP_CHIP == 7425) || (BCHP_CHIP == 7435) || \
119    (BCHP_CHIP == 7344) || (BCHP_CHIP == 7346) || (BCHP_CHIP == 7231) || \
120    (BCHP_CHIP == 7429) || (BCHP_CHIP == 7358) || (BCHP_CHIP == 7552) || \
121        (BCHP_CHIP == 7640) || (BCHP_CHIP == 35233)
122        #define BCHP_VEC_CFG_SW_RESET_CCE_0               BCHP_VEC_CFG_SW_INIT_CCE_0
123        #define BCHP_VEC_CFG_SW_RESET_WSE_0               BCHP_VEC_CFG_SW_INIT_WSE_0
124        #define BCHP_VEC_CFG_SW_RESET_TTE_0               BCHP_VEC_CFG_SW_INIT_TTE_0
125        #define BCHP_VEC_CFG_SW_RESET_GSE_0               BCHP_VEC_CFG_SW_INIT_GSE_0
126        #define BCHP_VEC_CFG_SW_RESET_AMOLE_0           BCHP_VEC_CFG_SW_INIT_AMOLE_0
127        #define BCHP_VEC_CFG_SW_RESET_CGMSAE_0         BCHP_VEC_CFG_SW_INIT_CGMSAE_0
128#endif
129#if (BCHP_CHIP == 7422) || (BCHP_CHIP == 7425) || (BCHP_CHIP == 7435) || \
130    (BCHP_CHIP == 7344) || (BCHP_CHIP == 7346) || (BCHP_CHIP == 7231) || \
131        (BCHP_CHIP == 7429)
132        #define BCHP_VEC_CFG_SW_RESET_CCE_ANCIL_0   BCHP_VEC_CFG_SW_INIT_CCE_ANCIL_0
133        #define BCHP_VEC_CFG_SW_RESET_WSE_ANCIL_0   BCHP_VEC_CFG_SW_INIT_WSE_ANCIL_0
134        #define BCHP_VEC_CFG_SW_RESET_TTE_ANCIL_0   BCHP_VEC_CFG_SW_INIT_TTE_ANCIL_0
135        #define BCHP_VEC_CFG_SW_RESET_GSE_ANCIL_0   BCHP_VEC_CFG_SW_INIT_GSE_ANCIL_0
136        #define BCHP_VEC_CFG_SW_RESET_AMOLE_ANCIL_0 \
137                                                      BCHP_VEC_CFG_SW_INIT_AMOLE_ANCIL_0
138        #define BCHP_VEC_CFG_SW_RESET_ANCI656_ANCIL_0 \
139                                                BCHP_VEC_CFG_SW_INIT_ANCI656_ANCIL_0
140#endif
141
142/* This will make code more legible, in special cases. Like, chipsets that do
143 * not support 656 output.
144 */
145#if (BVBI_P_NUM_CCE_656 == 0)
146#define BCHP_VEC_CFG_SW_RESET_CCE_ANCIL_0 0xFFFFFFFF
147#endif
148#if (BVBI_P_NUM_WSE_656 == 0)
149#define BCHP_VEC_CFG_SW_RESET_WSE_ANCIL_0 0xFFFFFFFF
150#endif
151#if (BVBI_P_NUM_TTE_656 == 0)
152#define BCHP_VEC_CFG_SW_RESET_TTE_ANCIL_0 0xFFFFFFFF
153#endif
154#if (BVBI_P_NUM_GSE_656 == 0)
155#define BCHP_VEC_CFG_SW_RESET_GSE_ANCIL_0 0xFFFFFFFF
156#endif
157#if (BVBI_P_NUM_AMOLE_656 == 0)
158#define BCHP_VEC_CFG_SW_RESET_AMOLE_ANCIL_0 0xFFFFFFFF
159#endif
160
161/***************************************************************************
162* Forward declarations of static (private) functions
163***************************************************************************/
164
165
166/***************************************************************************
167* Implementation of "BVBI_" API functions
168***************************************************************************/
169
170
171/***************************************************************************
172* Implementation of supporting VBI_ENC functions that are not in API
173***************************************************************************/
174
175BERR_Code BVBI_P_VIE_SoftReset (
176        BREG_Handle hReg,
177        bool is656, 
178        uint8_t hwCoreIndex,
179        uint32_t whichStandard)
180{
181        uint32_t ulRegBase;
182        uint32_t ulRegAddr;
183
184        BDBG_ENTER(BVBI_P_VIE_SoftReset);
185
186        switch (whichStandard)
187        {
188        case BVBI_P_SELECT_CC:
189                ulRegBase = 
190                        (is656 ? 
191                                BCHP_VEC_CFG_SW_RESET_CCE_ANCIL_0 : 
192                                BCHP_VEC_CFG_SW_RESET_CCE_0);
193                break;
194#if (BVBI_P_NUM_TTE > 0) || (BVBI_P_NUM_TTE_656 > 0)
195        case BVBI_P_SELECT_TT:
196                ulRegBase = 
197                        (is656 ? 
198                                BCHP_VEC_CFG_SW_RESET_TTE_ANCIL_0 : 
199                                BCHP_VEC_CFG_SW_RESET_TTE_0);
200                break;
201#endif
202        case BVBI_P_SELECT_WSS:
203                ulRegBase = 
204                        (is656 ? 
205                                BCHP_VEC_CFG_SW_RESET_WSE_ANCIL_0 : 
206                                BCHP_VEC_CFG_SW_RESET_WSE_0);
207                break;
208#if (BVBI_P_NUM_GSE > 0) 
209        case BVBI_P_SELECT_GS:
210                ulRegBase = 
211                        (is656 ? 
212                                BCHP_VEC_CFG_SW_RESET_GSE_ANCIL_0 : 
213                                BCHP_VEC_CFG_SW_RESET_GSE_0);
214                break;
215#endif
216#if (BVBI_P_NUM_AMOLE > 0) 
217        case BVBI_P_SELECT_AMOL:
218                ulRegBase = 
219                        (is656 ? 
220                                BCHP_VEC_CFG_SW_RESET_AMOLE_ANCIL_0 : 
221                                BCHP_VEC_CFG_SW_RESET_AMOLE_0);
222                break;
223#endif
224        case BVBI_P_SELECT_CGMSA:
225        case BVBI_P_SELECT_CGMSB:
226                ulRegBase = BCHP_VEC_CFG_SW_RESET_CGMSAE_0;
227                break;
228#if (BVBI_P_NUM_SCTEE > 0) 
229        case BVBI_P_SELECT_SCTE:
230                ulRegBase = BCHP_VEC_CFG_SW_RESET_SCTE_0;
231                break;
232#endif
233        default:
234                /* This should never happen! */
235                ulRegBase = 0xFFFFFFFF;
236                break;
237        }
238
239        /* Take care of errors above */
240        if (ulRegBase == 0xFFFFFFFF)
241        {
242                BDBG_LEAVE(BVBI_P_VIE_SoftReset);
243                return BERR_TRACE(BERR_INVALID_PARAMETER);
244        }
245
246        /* Finally, program the soft reset register */
247        ulRegAddr = ulRegBase + 4 * hwCoreIndex;
248        BREG_Write32 (hReg, ulRegAddr, 0x1);
249        BREG_Write32 (hReg, ulRegAddr, 0x0);
250
251        BDBG_LEAVE(BVBI_P_VIE_SoftReset);
252        return BERR_SUCCESS;
253}
254
255#if (BVBI_P_NUM_ANCI656_656 > 0)
256BERR_Code BVBI_P_VIE_AncilSoftReset (
257        BREG_Handle hReg,
258        uint8_t hwCoreIndex)
259{
260        uint32_t ulRegBase;
261        uint32_t ulRegAddr;
262
263        BDBG_ENTER(BVBI_P_VIE_AncilSoftReset);
264
265        /* Figure out which encoder core to use */
266        ulRegBase = BCHP_VEC_CFG_SW_RESET_ANCI656_ANCIL_0;
267        ulRegAddr = ulRegBase + 4 * hwCoreIndex;
268
269        /* Program the soft reset register */
270        BREG_Write32 (hReg, ulRegAddr, 0x1);
271        BREG_Write32 (hReg, ulRegAddr, 0x0);
272
273        BDBG_LEAVE(BVBI_P_VIE_SoftReset);
274        return BERR_SUCCESS;
275}
276#endif
277
278/***************************************************************************
279* Static (private) functions
280***************************************************************************/
281
282/* End of file */
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