source: svn/newcon3bcm2_21bu/nexus/modules/gpio/7552/src/nexus_gpio_table.c

Last change on this file was 76, checked in by megakiss, 10 years ago

1W 대기전력을 만족시키기 위하여 POWEROFF시 튜너를 Standby 상태로 함

  • Property svn:executable set to *
File size: 28.6 KB
Line 
1/***************************************************************************
2*     (c)2008-2011 Broadcom Corporation
3
4*  This program is the proprietary software of Broadcom Corporation and/or its licensors,
5*  and may only be used, duplicated, modified or distributed pursuant to the terms and
6*  conditions of a separate, written license agreement executed between you and Broadcom
7*  (an "Authorized License").  Except as set forth in an Authorized License, Broadcom grants
8*  no license (express or implied), right to use, or waiver of any kind with respect to the
9*  Software, and Broadcom expressly reserves all rights in and to the Software and all
10*  intellectual property rights therein.  IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11*  HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12*  NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE. 
13*   
14*  Except as expressly set forth in the Authorized License,
15*   
16*  1.     This program, including its structure, sequence and organization, constitutes the valuable trade
17*  secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof,
18*  and to use this information only in connection with your use of Broadcom integrated circuit products.
19*   
20*  2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
21*  AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR
22*  WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
23*  THE SOFTWARE.  BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES
24*  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE,
25*  LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION
26*  OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF
27*  USE OR PERFORMANCE OF THE SOFTWARE.
28
29*  3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS
30*  LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR
31*  EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR
32*  USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF
33*  THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT
34*  ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE
35*  LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF
36*  ANY LIMITED REMEDY.
37 *
38 * $brcm_Workfile: nexus_gpio_table.c $
39 * $brcm_Revision: 4 $
40 * $brcm_Date: 11/25/11 4:12p $
41 *
42 * Module Description:
43 * API Description:
44 *   API name: Gpio
45 *    Specific APIs related to Gpio Control.
46 *
47 * Revision History:
48 *
49 * $brcm_Log: /nexus/modules/gpio/7552/src/nexus_gpio_table.c $
50 *
51 * 4   11/25/11 4:12p xhuang
52 * SW7552-141: updat gpio table for B0
53 *
54 * 3   9/29/11 2:43p xhuang
55 * SW7552-128: correct aon gpio table for dummy register
56 *
57 * 2   8/8/11 1:24p xhuang
58 * SW7552-77: Add DVB-CI support
59 *
60 * 1   2/22/11 4:59p xhuang
61 * SW7552-20: Add gpio for 7552
62 *
63 *
64 ***************************************************************************/
65
66#include "nexus_gpio_module.h"
67#include "bchp_sun_top_ctrl.h"
68#include "bchp_aon_pin_ctrl.h"
69#include "bchp_gio.h"
70#include "bchp_gio_aon.h"
71#include "priv/nexus_core.h"
72
73BDBG_MODULE(nexus_gpio_table);
74
75typedef struct NEXUS_GpioTable
76{
77    uint32_t addr;
78    unsigned mask;
79    unsigned shift;
80} NEXUS_GpioTable;
81
82NEXUS_GpioTable g_gpioTable[NEXUS_NUM_GPIO_PINS] = {
83    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT},
84    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT},
85    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT},
86    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT},
87    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT},
88    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT},
89    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT},
90    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT},
91    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT},
92    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT},
93    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT},
94    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT},
95    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT},
96    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT},
97    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT},
98    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT},
99    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT},
100    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT},
101    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT},
102    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT},
103    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT},
104    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT},
105    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT},
106    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT},
107    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT},
108    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT},
109    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT},
110    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT},
111    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT},
112    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT},
113    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT},
114    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT},
115    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT},
116    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT},
117    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT},
118    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT},
119    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT},
120    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT},
121    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT},
122    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT},
123    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT},
124    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT},
125    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT},
126    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT},
127    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT},
128    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT},
129    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT},
130    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT},
131    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT},
132    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT},
133    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT},
134    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT},
135    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT},
136    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT},
137    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT},
138    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT},
139    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT},
140    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT},
141    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT},
142    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT},
143    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT},
144    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT},
145    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT},
146    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT},
147    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT},
148    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT},
149    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT},
150    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT},
151    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT},
152    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT},
153    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT},
154    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT},
155    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT},
156    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT},
157    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT},
158    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT},
159    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT},
160    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT},
161    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT},
162    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT},
163    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT},
164    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT},
165    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT},
166    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT},
167    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT},
168    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT},
169    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT},
170    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT},
171    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT},
172    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT},
173    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT},
174    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT},
175    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT},
176    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT},
177    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT},
178    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, 0, 0}, /* gpio 95 is dummy */
179    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT},
180    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT},
181    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT},
182    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT},
183    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT},
184    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT},
185    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT},
186    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT},
187    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT},
188    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT},
189    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, 0, 0}, /* gpio 106 is dummy */
190    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT},
191    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT},
192    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT},
193    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT},
194    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT},
195    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT},
196    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT},
197    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT},
198    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT},
199    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT},
200    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT},
201    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT},
202    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT},
203    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT},
204    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT},
205    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT},
206    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT},
207    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT},
208};
209
210NEXUS_GpioTable g_sgpioTable[NEXUS_NUM_SGPIO_PINS] = {
211#if BCHP_VER >= BCHP_VER_B0     
212    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT},
213    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT},
214    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT},
215    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT},
216#else
217    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_SHIFT},
218    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_SHIFT},
219    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT},
220    {BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT},
221#endif   
222};
223
224NEXUS_GpioTable g_aonGpioTable[NEXUS_NUM_AON_GPIO_PINS] = {
225    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT},
226    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT},
227    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, 0, 0},    /* aon gpio 02 is dummy */
228    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT},
229    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT},
230    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT},
231   
232    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT},
233    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT},
234    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT},
235    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT},
236    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT},
237    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT},
238    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT},
239    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT},
240   
241    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT},
242    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT},
243    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT},
244    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT},
245    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT},
246    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT},
247    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT},   
248};
249
250NEXUS_GpioTable g_aonSgpioTable[NEXUS_NUM_AON_SGPIO_PINS] = {
251    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT},
252    {BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT},
253};
254
255
256/* These functions must be implemented per-chip */
257NEXUS_Error NEXUS_Gpio_P_GetPinMux(NEXUS_GpioType type, unsigned pin, uint32_t *pAddr, uint32_t *pMask, unsigned *pShift )
258{
259    NEXUS_GpioTable *pEntry=NULL;
260    BDBG_ASSERT(type <= NEXUS_GpioType_eAonSpecial);
261
262    switch (type)
263    {
264        case NEXUS_GpioType_eStandard:
265                if ( pin >= NEXUS_NUM_GPIO_PINS)
266                {
267                return BERR_TRACE(BERR_INVALID_PARAMETER);
268                }
269                pEntry = g_gpioTable+pin;
270            break;
271        case NEXUS_GpioType_eSpecial:
272            if ( pin >= NEXUS_NUM_SGPIO_PINS)
273            {
274                return BERR_TRACE(BERR_INVALID_PARAMETER);
275            }
276                pEntry = g_sgpioTable+pin;
277            break; 
278        case NEXUS_GpioType_eAonStandard:
279            if ( pin >= NEXUS_NUM_AON_GPIO_PINS)
280            {
281                return BERR_TRACE(BERR_INVALID_PARAMETER);
282            }
283                pEntry = g_aonGpioTable+pin;
284            break; 
285        case NEXUS_GpioType_eAonSpecial:
286            if ( pin >= NEXUS_NUM_AON_SGPIO_PINS)
287            {
288                return BERR_TRACE(BERR_INVALID_PARAMETER);
289            }
290                pEntry = g_aonSgpioTable+pin;
291            break; 
292        default:
293            return BERR_TRACE(BERR_INVALID_PARAMETER);
294            break;
295    }
296
297    *pAddr = pEntry->addr;
298    *pMask = pEntry->mask;
299    *pShift = pEntry->shift;
300    return 0;
301}
302
303NEXUS_Error NEXUS_Gpio_P_CheckPinmux(NEXUS_GpioType type, unsigned pin)
304{
305    uint32_t addr, mask, shift, val;
306    NEXUS_Error rc;
307
308    rc = NEXUS_Gpio_P_GetPinMux(type, pin, &addr, &mask, &shift);
309    if (rc) return BERR_TRACE(rc);
310
311    val = BREG_Read32(g_pCoreHandles->reg, addr);
312    /* this code assumes a pinmux value of 0 is GPIO */
313    if ( val & mask ) {
314        /* Pin is not configured as GPIO */
315        BDBG_ERR(("Pin mux register for %u is not properly configured - value %u should be 0",
316                   pin, val>>shift));
317        return BERR_TRACE(BERR_INVALID_PARAMETER);
318    }
319
320    return BERR_SUCCESS;
321}
322
323NEXUS_Error NEXUS_Gpio_P_GetPinData(NEXUS_GpioType type, unsigned pin, uint32_t *pAddress, uint32_t *pShift)
324{
325    BDBG_ASSERT(type <= NEXUS_GpioType_eAonSpecial);
326
327    switch (type)
328    {
329        case NEXUS_GpioType_eStandard:
330                if ( pin < 32 )
331                {
332                /* GPIO Pins 31..0 are in ODEN_LO */
333                *pAddress = BCHP_GIO_ODEN_LO;
334                *pShift = pin;
335                }
336                else if ( pin < 64 )
337                {
338                /* GPIO Pins 63..32 are in ODEN_HI */
339                *pAddress = BCHP_GIO_ODEN_HI;
340                *pShift = pin-32;
341                }
342                else if ( pin < 96 )
343                {
344                /* GPIO Pins 95..64 are in ODEN_EXT, above sgpio bits */
345                *pAddress = BCHP_GIO_ODEN_EXT;
346                *pShift = (pin-64);
347                }
348                else if ( pin < 125 )
349                {
350                /* GPIO Pins 124..96 are in ODEN_EXT_HI */
351                *pAddress = BCHP_GIO_ODEN_EXT_HI;
352                *pShift = (pin-96);
353                }
354                else
355                {
356                return BERR_TRACE(BERR_INVALID_PARAMETER);
357                }
358            break;
359        case NEXUS_GpioType_eSpecial:
360            if ( pin >= NEXUS_NUM_SGPIO_PINS)
361            {
362                return BERR_TRACE(BERR_INVALID_PARAMETER);
363            }
364                else
365                {
366                /* SGPIO Pins 5..0 are in ODEN_EXT */
367                *pAddress = BCHP_GIO_ODEN_EXT;
368                *pShift = pin;
369                }
370            break; 
371        case NEXUS_GpioType_eAonStandard:
372            if ( pin >= NEXUS_NUM_AON_GPIO_PINS)
373            {
374                return BERR_TRACE(BERR_INVALID_PARAMETER);
375            }
376                else
377                {
378                /* AON GPIO Pins 17..0 are in AON_ODEN_LO */
379                *pAddress = BCHP_GIO_AON_ODEN_LO;
380                *pShift = pin;
381                }
382            break; 
383        case NEXUS_GpioType_eAonSpecial:
384            if ( pin >= NEXUS_NUM_AON_SGPIO_PINS)
385            {
386                return BERR_TRACE(BERR_INVALID_PARAMETER);
387            }
388                else
389                {
390                /* AON SGPIO Pins 3..0 are in AON_ODEN_EXT */
391                *pAddress = BCHP_GIO_AON_ODEN_EXT;
392                *pShift = pin;
393                }
394            break; 
395        default:
396            break;
397    }
398
399    return BERR_SUCCESS;
400}
401
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