source: svn/newcon3bcm2_21bu/nexus/platforms/97552/src/bfpga.c

Last change on this file was 76, checked in by megakiss, 10 years ago

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1/***************************************************************************
2 *     Copyright (c) 2002-2009, Broadcom Corporation
3 *     All Rights Reserved
4 *     Confidential Property of Broadcom Corporation
5 *
6 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
8 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9 *
10 * $brcm_Workfile: bfpga.c $
11 * $brcm_Revision: Hydra_Software_Devel/21 $
12 * $brcm_Date: 11/20/09 4:00p $
13 *
14 * Module Description:
15 *
16 * Revision History:
17 *
18 * $brcm_Log: W:/darnstein/snap_mag25/rockford/commondrivers/fpga/97342/bfpga.c $
19 *
20 * Hydra_Software_Devel/21   11/20/09 4:00p darnstein
21 * SW7342-39: add a few asserts for zero pointers. This may help with
22 * debugging.
23 *
24 * Hydra_Software_Devel/20   2/8/08 11:59a vsilyaev
25 * PR 38682: Fixed warning
26 *
27 * Hydra_Software_Devel/19   12/20/06 3:31p erickson
28 * PR25108: add 7403 support
29 *
30 * Hydra_Software_Devel/18   5/12/06 4:37p erickson
31 * PR20219: redesign BFPGA_P_GetAddr, remove hardcoded value
32 *
33 * Hydra_Software_Devel/17   5/12/06 2:47p erickson
34 * PR20219: added PKT4 for 7401/7400
35 *
36 * Hydra_Software_Devel/16   2/3/06 5:09p jgarrett
37 * PR 19250: Updating for 97400, eliminating warnings at startup
38 *
39 * Hydra_Software_Devel/15   12/2/05 4:42p erickson
40 * PR17108: added 7401 specific #ifdef to avoid errors
41 *
42 * Hydra_Software_Devel/14   10/25/05 3:06p dlwin
43 * PR 17809: Added support for handling Stratix FPGA with version 2.x.
44 * 97038B2 ships with 2.3 and higher.
45 *
46 * Hydra_Software_Devel/13   3/22/05 10:29a mphillip
47 * PR14399: Invert the clocks for 3510
48 *
49 * Hydra_Software_Devel/12   3/9/05 7:39p vsilyaev
50 * PR 14402: Fixed clock configuration for 7042 input.
51 *
52 * Hydra_Software_Devel/11   2/7/05 9:34a dlwin
53 * PR 13700: Added default setting for FPGA Ver. 2.0 and up.
54 *
55 * Hydra_Software_Devel/10   1/14/05 12:29p dlwin
56 * PR 13700: Disable resetting for FPGA for 97038C0, if the FPGA is send a
57 * reset command, the I2C bus will lock-up.
58 *
59 * Hydra_Software_Devel/9   1/12/05 2:58p dlwin
60 * PR 13700: Updated to support 97038C0 board, which has the FPGA on I2C
61 * bus instead of EBI.
62 *
63 * Hydra_Software_Devel/8   9/29/04 12:03p marcusk
64 * PR12850: UPdated with support for AVC daughter card setting.
65 *
66 * Hydra_Software_Devel/7   2/6/04 8:07p vsilyaev
67 * PR 9588: Fixed polarity settings for VSB (daughtecards).
68 *
69 * Hydra_Software_Devel/6   2/6/04 8:00p vsilyaev
70 * PR 9588: Fixed polarity for 3510 DS1, DS2, and VSB,
71 *
72 * Hydra_Software_Devel/5   2/6/04 5:32p marcusk
73 * PR9588: Updated to program default polarity values when inputs are
74 * selected.
75 *
76 * Hydra_Software_Devel/4   2/4/04 3:51p marcusk
77 * PR9588: Updated with proper detection of POD and 1394 Ts selects
78 * (documentation was wrong)
79 *
80 * Hydra_Software_Devel/3   2/4/04 2:52p marcusk
81 * PR9588: Updated to use jumper settings when software has not
82 * overwritten output selections
83 *
84 * Hydra_Software_Devel/2   2/4/04 7:57a marcusk
85 * PR9588: Added support for fpga, tested and working.
86 *
87 * Hydra_Software_Devel/1   2/2/04 5:38p marcusk
88 * PR9588: First version (may not compile yet)
89 *
90 ***************************************************************************/
91#include "bstd.h"
92#include "bkni.h"
93#include "bfpga.h"
94
95BDBG_MODULE(fpga);
96
97static const BFPGA_Settings defDevSettings =
98{
99        0x0FFF00,
100        0x0E                            /* 7bit address, unshifted */
101};
102
103#define BOARD_CFG_ADDR                  0x00
104#define FPGA_VER_ADDR                   0x01
105#define STRAP_PINS_ADDR                 0x02
106#define RESETS_ADDR                             0x03
107#define PKT0_CFG_ADDR                   0x04
108
109typedef struct BFPGA_Impl
110{
111        BREG_Handle     hReg;
112        BREG_I2C_Handle hI2CReg;
113        BFPGA_Settings  settings;
114} BFPGA_Impl;
115
116static uint8_t BFPGA_P_Read(
117        BFPGA_Handle hFpga,
118        uint32_t regOffset
119        )
120{
121        uint8_t data;
122
123        if( hFpga->hReg != NULL )
124        {
125                BDBG_ASSERT (hFpga->hReg);
126                data = BREG_Read8(hFpga->hReg, (hFpga->settings.regBase + regOffset));
127        }
128        else
129        {
130                BERR_Code retCode;
131
132                BDBG_ASSERT (hFpga->hI2CReg);
133                retCode = BREG_I2C_Read( hFpga->hI2CReg, hFpga->settings.i2cAddr, regOffset, &data, 1 );
134                BDBG_ASSERT( retCode == BERR_SUCCESS );
135        }
136        return( data );
137}
138
139static void BFPGA_P_Write(
140        BFPGA_Handle hFpga,
141        uint32_t regOffset,
142        uint8_t data
143        )
144{
145        if( hFpga->hReg != NULL )
146        {
147                BREG_Write8(hFpga->hReg, (hFpga->settings.regBase + regOffset), data);
148        }
149        else
150        {
151                BERR_Code retCode;
152
153                retCode = BREG_I2C_Write( hFpga->hI2CReg, hFpga->settings.i2cAddr, regOffset, &data, 1 );
154                BDBG_ASSERT( retCode == BERR_SUCCESS );
155        }
156}
157
158BERR_Code BFPGA_Open(
159        BFPGA_Handle    *phFpga,                        /* [out] returns handle to fpga */
160        BREG_Handle     hReg,                           /* [in] Handle to Memory Mapped register */
161        BREG_I2C_Handle hI2CReg,                        /* [in] I2C Register handle */
162        const BFPGA_Settings *pDefSettings      /* [in] Default settings */
163        )
164{
165        *phFpga = BKNI_Malloc( sizeof(BFPGA_Impl) ); 
166        if( *phFpga == NULL )
167                return BERR_OUT_OF_SYSTEM_MEMORY;
168
169        BKNI_Memset( *phFpga, 0, sizeof(BFPGA_Impl) );
170        (*phFpga)->hReg = hReg;
171        (*phFpga)->hI2CReg = hI2CReg;
172        (*phFpga)->settings = *pDefSettings;
173
174        return BERR_SUCCESS;
175}
176
177void BFPGA_Close(
178        BFPGA_Handle hFpga /* handle to fpga */
179        )
180{
181        BKNI_Free( hFpga );
182}
183
184BERR_Code BFPGA_GetDefaultSettings(
185        BFPGA_Settings *pDefSettings    /* [output] Returns default setting */
186        )
187{
188        BERR_Code retCode = BERR_SUCCESS;
189
190       
191        *pDefSettings = defDevSettings;
192
193        return( retCode );
194}
195
196BERR_Code BFPGA_GetInfo( 
197        BFPGA_Handle hFpga, /* handle to fpga */
198        BFPGA_info *pInfo /* [out] pointer to info structure that will be filled with data */
199        )
200{
201        pInfo->board_cfg = BFPGA_P_Read(hFpga, BOARD_CFG_ADDR);
202        pInfo->fpga_ver = BFPGA_P_Read(hFpga, FPGA_VER_ADDR);
203        pInfo->strap_pins = BFPGA_P_Read(hFpga, STRAP_PINS_ADDR);
204
205        return BERR_SUCCESS;
206}
207
208BERR_Code BFPGA_Reset( 
209        BFPGA_Handle hFpga /* handle to fpga */
210        )
211{
212        uint8_t data = 0x1F;
213
214        /* I2C version of FPGA doesn't support reset correctly */
215        if( hFpga->hReg != NULL )
216        {
217                BFPGA_P_Write(hFpga, RESETS_ADDR, data);
218        }
219
220        return BERR_SUCCESS;
221}
222
223struct BFPGA_P_TsSelectDefault
224{
225        /* BFPGA_TsSelect               tsSelect; */
226        uint8_t                         defaultSetting;
227};
228
229
230/* This table is for Stratix based FPGA V1.x, it exist on 97038B0/B1 boards */
231static const struct BFPGA_P_TsSelectDefault BFPGA_P_Stratix_V1X_TsDefault[] = {
232        { /* BFPGA_TsSelect_eQam_Ds1,   */  0x20 }, 
233        { /* BFPGA_TsSelect_eQam_Oob,   */  0x40 },       
234        { /* BFPGA_TsSelect_eHsx_1,     */  0x00 },       
235        { /* BFPGA_TsSelect_eHsx_2,     */  0x00 },       
236        { /* BFPGA_TsSelect_eEnc_Ts0,   */  0x00 },       
237        { /* BFPGA_TsSelect_e1394,              */  0x00 },
238        { /* BFPGA_TsSelect_eLvds_2,    */  0x40 },       
239        { /* BFPGA_TsSelect_eLvds_1,    */  0x40 },       
240        { /* BFPGA_TsSelect_eQam_Ds2,   */  0x20 },       
241        { /* BFPGA_TsSelect_eEnc_Ts1,   */  0x00 },       
242        { /* BFPGA_TsSelect_ePod,               */  0x00 },         
243        { /* BFPGA_TsSelect_eVsb_1,             */  0x40 },   
244        { /* BFPGA_TsSelect_eVsb_2,             */  0x40 },   
245        { /* BFPGA_TsSelect_eReserved_1,*/      0x00 },         
246        { /* BFPGA_TsSelect_eReserved_2,*/      0x00 },         
247        { /* BFPGA_TsSelect_eDisable,   */      0x00 }           
248};
249
250/* This table is for Stratix based FPGA V2.x, it exist on 97038B2 boards */
251static const struct BFPGA_P_TsSelectDefault BFPGA_P_Stratix_V2X_TsDefault[] = {
252        { /* BFPGA_TsSelect_eQam_Ds1,   */  0x20 }, 
253        { /* BFPGA_TsSelect_eQam_Oob,   */  0x40 },       
254        { /* BFPGA_TsSelect_eHsx_1,     */  0x00 },       
255        { /* BFPGA_TsSelect_eHsx_2,     */  0x00 },       
256        { /* BFPGA_TsSelect_eEnc_Ts0,   */  0x00 },       
257        { /* BFPGA_TsSelect_e1394,              */  0x00 },
258        { /* BFPGA_TsSelect_eLvds_2,    */  0x40 },       
259        { /* BFPGA_TsSelect_eLvds_1,    */  0x40 },       
260        { /* BFPGA_TsSelect_eQam_Ds2,   */  0x20 },       
261        { /* BFPGA_TsSelect_eEnc_Ts1,   */  0x00 },       
262        { /* BFPGA_TsSelect_ePod,               */  0x00 },         
263#if (VSB_CHIP==3510)
264        { /* BFPGA_TsSelect_eVsb_1,             */  0x40 },   
265        { /* BFPGA_TsSelect_eVsb_2,             */  0x40 },   
266#else
267        { /* BFPGA_TsSelect_eVsb_1,             */  0x20 },   
268        { /* BFPGA_TsSelect_eVsb_2,             */  0x20 },   
269#endif
270        { /* BFPGA_TsSelect_eReserved_1,*/      0x00 },         
271        { /* BFPGA_TsSelect_eReserved_2,*/      0x00 },         
272        { /* BFPGA_TsSelect_eDisable,   */      0x00 }           
273};
274
275/* This table is for non-stratix based FPGA V2.x, it exist on 97038Cx, 97401, etc boards */
276static const struct BFPGA_P_TsSelectDefault BFPGA_P_NonStratix_V2X_TsDefault[] = {
277        { /* BFPGA_TsSelect_eQam_Ds1,   */  0x20 }, 
278        { /* BFPGA_TsSelect_eQam_Oob,   */  0x20 },       
279        { /* BFPGA_TsSelect_eHsx_1,     */  0x00 },       
280        { /* BFPGA_TsSelect_eHsx_2,     */  0x00 },       
281        { /* BFPGA_TsSelect_eEnc_Ts0,   */  0x40 },       
282        { /* BFPGA_TsSelect_e1394,              */  0x00 },
283        { /* BFPGA_TsSelect_eLvds_2,    */  0x20 },       
284        { /* BFPGA_TsSelect_eLvds_1,    */  0x20 },       
285        { /* BFPGA_TsSelect_eQam_Ds2,   */  0x20 },       
286        { /* BFPGA_TsSelect_eEnc_Ts1,   */  0x00 },       
287        { /* BFPGA_TsSelect_ePod,               */  0x00 },         
288#if (VSB_CHIP==3510)
289        { /* BFPGA_TsSelect_eVsb_1,             */  0x40 },   
290        { /* BFPGA_TsSelect_eVsb_2,             */  0x40 },   
291#else
292        { /* BFPGA_TsSelect_eVsb_1,             */  0x20 },   
293        { /* BFPGA_TsSelect_eVsb_2,             */  0x20 },   
294#endif
295        { /* BFPGA_TsSelect_eReserved_1,*/      0x00 },         
296        { /* BFPGA_TsSelect_eReserved_2,*/      0x00 },         
297        { /* BFPGA_TsSelect_eDisable,   */      0x00 }           
298};
299
300#if BCHP_CHIP == 7401 || BCHP_CHIP == 7400 || BCHP_CHIP == 7403
301/* PKT4 is available on 97038V4 boards. We have no way to detect version of board. Customers can turn this
302on if they wish. For other boards, default it on. */
303#define B_HAS_PKT4 1
304#endif
305
306static BERR_Code BFPGA_P_GetAddr(BFPGA_OutputSelect outputSelect, uint32_t *addr)
307{
308        if (outputSelect == BFPGA_OutputSelect_ePkt4) {
309        *addr = 0;
310#if B_HAS_PKT4
311                *addr = 0x0B;
312#else
313                return BERR_TRACE(BERR_NOT_SUPPORTED);
314#endif
315        }
316        else {
317                /* here's where the OutputSelect enum maps to an address */
318                *addr = PKT0_CFG_ADDR + outputSelect;
319        }
320        return 0;
321}
322
323BERR_Code BFPGA_SetTsOutput( 
324        BFPGA_Handle hFpga, /* handle to fpga */
325        BFPGA_OutputSelect outputSelect, /* Selects which of the FPGA TS outputs to configure */
326        BFPGA_TsSelect tsSelect /* Selects which stream to send to selected output */
327        )
328{
329        uint8_t data;
330        uint32_t addr;
331       
332        if (BFPGA_P_GetAddr(outputSelect, &addr)) {
333                return BERR_NOT_SUPPORTED;
334        }
335
336#if BCHP_CHIP == 7401 || BCHP_CHIP == 7400 || BCHP_CHIP == 7403
337        /* There is currently only one FPGA type on 97401, so select it without an error message. */
338        data = (BFPGA_P_NonStratix_V2X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
339#else
340        switch( BFPGA_P_Read(hFpga, FPGA_VER_ADDR) & 0xF0 )
341        {
342                case 0x10:
343                        if( hFpga->hReg != NULL )
344                        {
345                                /* Stratix FPGA, controlled over EBI */
346                                data = (BFPGA_P_Stratix_V1X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
347                        }
348                        else
349                        {
350                                /* All non-Stratix FPGA so far support 2.x settings */
351                                data = (BFPGA_P_NonStratix_V2X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
352                        }
353                        break;
354                case 0x20:
355                        if( hFpga->hReg != NULL )
356                        {
357                                /* Stratix FPGA, controlled over EBI */
358                                data = (BFPGA_P_Stratix_V2X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
359                        }
360                        else
361                        {
362                                data = (BFPGA_P_NonStratix_V2X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
363                        }
364                        break;
365                default:
366                        if( hFpga->hReg != NULL )
367                        {
368                                /* Stratix FPGA, controlled over EBI */
369                                BDBG_ERR(("Unknown FPGA version, using Stratix Ver. 2.x settings"));
370                                data = (BFPGA_P_Stratix_V2X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
371                        }
372                        else
373                        {
374                                BDBG_ERR(("Unknown FPGA version, using NonStratix Ver. 2.x settings"));
375                                data = (BFPGA_P_NonStratix_V2X_TsDefault[tsSelect].defaultSetting | (uint8_t)tsSelect);
376                        }
377                        break;
378        }
379#endif
380        BFPGA_P_Write(hFpga, addr, data);
381
382        return BERR_SUCCESS;
383}
384
385struct BFPGA_P_BoardConfig
386{
387        /* BFPGA_OutputSelect outputSelect; */
388        BFPGA_TsSelect TsSelect_JumperOff;
389        BFPGA_TsSelect TsSelect_JumperOn;
390        int BoardConfigBit;
391};
392
393static const struct BFPGA_P_BoardConfig BFPGA_P_gBoardConfig[] = {
394        { /* BFPGA_OutputSelect_ePkt0, */ BFPGA_TsSelect_eQam_Ds1, BFPGA_TsSelect_eQam_Ds1, -1 },
395        { /* BFPGA_OutputSelect_ePkt1, */ BFPGA_TsSelect_eQam_Ds2, BFPGA_TsSelect_eLvds_1,   1 },
396        { /* BFPGA_OutputSelect_ePkt2, */ BFPGA_TsSelect_eHsx_1,   BFPGA_TsSelect_eLvds_2,   2 },
397        { /* BFPGA_OutputSelect_ePkt3, */ BFPGA_TsSelect_eEnc_Ts0, BFPGA_TsSelect_e1394,     3 },
398        { /* BFPGA_OutputSelect_e1394, */ BFPGA_TsSelect_eHsx_1,   BFPGA_TsSelect_eHsx_1,   -2 },
399        { /* BFPGA_OutputSelect_eTest, */ BFPGA_TsSelect_eHsx_2,   BFPGA_TsSelect_eEnc_Ts1,  0 },
400        { /* BFPGA_OutputSelect_ePod,  */ BFPGA_TsSelect_eHsx_1,   BFPGA_TsSelect_eHsx_1,   -2 },
401        { /* BFPGA_OutputSelect_eAvc,  */ BFPGA_TsSelect_eHsx_1,   BFPGA_TsSelect_eHsx_1,   -2 },
402        { /* BFPGA_OutputSelect_ePkt4, */ BFPGA_TsSelect_eVsb_1,   BFPGA_TsSelect_eVsb_1,   -1 },
403};
404       
405BERR_Code BFPGA_GetTsOutput( 
406        BFPGA_Handle hFpga,     /* handle to fpga */
407        BFPGA_OutputSelect outputSelect, /* Selects which of the FPGA TS outputs to configure */
408        BFPGA_TsSelect *p_tsSelect, /* [out] Returns the ts stream that is routed to selected output */
409        bool *p_softwareConfigured /* [out] Returns if the ts stream is configured by software (if not it is configured by the jumper setting) */
410        )
411{
412        uint8_t data;
413        uint32_t addr;
414       
415        if (BFPGA_P_GetAddr(outputSelect, &addr)) {
416                return BERR_NOT_SUPPORTED;
417        }
418
419
420        data = BFPGA_P_Read(hFpga, addr);
421       
422        *p_softwareConfigured = (data&0x80)?false:true;
423        if( *p_softwareConfigured )
424        {
425                *p_tsSelect = (BFPGA_TsSelect)(data & 0x0F);
426        }
427        else
428        {
429                bool jumperState = false;
430                uint8_t board_cfg = BFPGA_P_Read(hFpga, BOARD_CFG_ADDR);
431
432                if( BFPGA_P_gBoardConfig[outputSelect].BoardConfigBit == -2 )
433                {
434                        *p_tsSelect = (BFPGA_TsSelect)(board_cfg&0xF);
435                }
436                else
437                {
438                        if( BFPGA_P_gBoardConfig[outputSelect].BoardConfigBit >= 0 )
439                        {
440                                jumperState = (board_cfg&(1<<BFPGA_P_gBoardConfig[outputSelect].BoardConfigBit))?true:false;
441                        }
442                        *p_tsSelect = jumperState?BFPGA_P_gBoardConfig[outputSelect].TsSelect_JumperOn:BFPGA_P_gBoardConfig[outputSelect].TsSelect_JumperOff;
443                }
444        }
445
446        return BERR_SUCCESS;
447}
448
449BERR_Code BFPGA_SetClockPolarity( 
450        BFPGA_Handle hFpga, /* handle to fpga */
451        BFPGA_OutputSelect outputSelect, /* Selects which of the FPGA TS outputs to configure */
452        BFPGA_ClockPolarity inputClockPolarity, /* Selects the input clock polarity */
453        BFPGA_ClockPolarity outputClockPolarity /* Selects the output clock polarity */
454        )
455{
456        uint8_t data;
457        uint32_t addr;
458       
459        if (BFPGA_P_GetAddr(outputSelect, &addr)) {
460                return BERR_NOT_SUPPORTED;
461        }
462
463
464        data = BFPGA_P_Read(hFpga, addr);
465        data &= 0x9F;
466        data |= (inputClockPolarity?0x40:0x00)|(outputClockPolarity?0x20:0x00);
467        BFPGA_P_Write(hFpga, addr, data);
468
469        return BERR_SUCCESS;
470}
471
472BERR_Code BFPGA_GetClockPolarity( 
473        BFPGA_Handle hFpga, /* handle to fpga */
474        BFPGA_OutputSelect outputSelect, /* Selects which of the FPGA TS outputs to configure */
475        BFPGA_ClockPolarity *p_inputClockPolarity, /* [out] Returns the input clock polarity */
476        BFPGA_ClockPolarity *p_outputClockPolarity /* [out] Returns the output clock polarity */
477        )
478{
479        uint8_t data;
480        uint32_t addr;
481       
482        if (BFPGA_P_GetAddr(outputSelect, &addr)) {
483                return BERR_NOT_SUPPORTED;
484        }
485
486
487        data = BFPGA_P_Read(hFpga, addr);
488        *p_inputClockPolarity = (data&0x40)?BFPGA_ClockPolarity_eNegativeEdge:BFPGA_ClockPolarity_ePositiveEdge;
489        *p_outputClockPolarity = (data&0x20)?BFPGA_ClockPolarity_eNegativeEdge:BFPGA_ClockPolarity_ePositiveEdge;
490
491        return BERR_SUCCESS;
492}
493
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